Multilayer ceramic capacitor

Abstract

Provided is a multilayer ceramic capacitor in which generation of internal structure defects is suppressed while maintaining excellent equivalent series resistance. A dielectric layer (20) of a multilayer ceramic capacitor (1) includes a dielectric having temperature compensation characteristics, a first internal electrode (31) and a second internal electrode (32) include Cu, a first scattered portion (201) including Cu is provided in a region (211) of the dielectric layer (20) near the first internal electrode (31), and a second scattered portion (202) including Cu is provided in a region (212) of the dielectric layer (20) near the second internal electrode (32).

Description

Multilayer ceramic capacitors

[0001] The present invention relates to a multilayer ceramic capacitor.

[0002] As described in Patent Document 1, the mainstream of multilayer ceramic capacitors is generally multilayer ceramic capacitors whose internal electrodes contain Ni as a main component. However, the conventional multilayer ceramic capacitors described in Patent Document 1 and elsewhere do not have sufficient characteristics in the high frequency range to meet the demands of electronic devices such as power amplifier modules.

[0003] In contrast to this, Patent Document 2 discloses a multilayer ceramic capacitor that achieves a high Q value in the high frequency range.

[0004] International Publication No. 2024-142821 Japanese Patent Application Laid-Open No. 2001-338829

[0005] However, a multilayer ceramic capacitor having Cu as the main component of its internal electrodes, as in Patent Document 2, has a lower equivalent series resistance (ESR) than a multilayer ceramic capacitor having Ni as the main component of its internal electrodes, as in Patent Document 1, but the linear expansion coefficient of the internal electrodes is higher. Therefore, the difference in linear expansion coefficient between the dielectric ceramic and the internal electrodes is large. This increases the difference in stress between the Cu-based internal electrodes and the dielectric layers. As a result, there is a risk that structural defects may occur inside the multilayer ceramic capacitor due to external stimuli.

[0006] SUMMARY OF THE INVENTION It is therefore an object of the present invention to provide a multilayer ceramic capacitor in which the generation of internal structural defects is suppressed while maintaining a good equivalent series resistance.

[0007] The multilayer ceramic capacitor of the present invention comprises a laminate including a plurality of stacked dielectric layers and a plurality of first internal electrodes and second internal electrodes, the laminate having main surfaces opposing each other in the stacking direction, side surfaces opposing each other in a width direction perpendicular to the stacking direction, and end surfaces opposing each other in a length direction perpendicular to the stacking direction and the width direction, a first external electrode arranged on the end surfaces and connected to the first internal electrode, and a second external electrode connected to the second internal electrode, the plurality of dielectric layers including a dielectric having temperature compensation characteristics, the first internal electrode and the second internal electrode including Cu, the dielectric layer having first interspersed portions containing Cu in a region adjacent to the first internal electrode, and the dielectric layer having second interspersed portions containing Cu in a region adjacent to the second internal electrode.

[0008] According to the present invention, it is possible to provide a multilayer ceramic capacitor in which the generation of internal structural defects is suppressed while maintaining a good equivalent series resistance.

[0009] FIG. 1 is an external perspective view of a multilayer ceramic capacitor according to a first embodiment of the present disclosure. FIG. 2 is a cross-sectional view taken along line 101-101 in FIG. 1. FIG. 3 is a cross-sectional view taken along line 102-102 in FIG. 1. FIG. 4 is a cross-sectional view taken along line 103-103 in FIG. 1. FIG. 5A is a cross-sectional view in the length direction and the lamination direction of a multilayer ceramic capacitor according to an embodiment of the present disclosure. FIG. 5B is an enlarged view of a boxed area 500 in FIG. 5A. FIG. 6A is a cross-sectional view in the length direction and the width direction of a multilayer ceramic capacitor according to an embodiment of the present disclosure. FIG. 6A is a cross-sectional view in the length direction and the width direction of a multilayer ceramic capacitor according to another example of the embodiment of the present disclosure. FIG. 7 is a table showing evaluation results of comparative examples and examples. FIG. 8A is a cross-sectional view corresponding to FIG. 5A of a modified example of the first embodiment. FIG. 8B is a cross-sectional view corresponding to FIG. 5A of another modified example of the first embodiment. FIG. 8C is a cross-sectional view corresponding to FIG. 5A of another modified example of the first embodiment. FIG. 8D is a cross-sectional view corresponding to FIG. 5A of another modified example of the first embodiment. FIG. 9 is an external perspective view of a multilayer ceramic capacitor according to a second embodiment of the present disclosure. Fig. 10A is a cross-sectional view taken along line 1010-1010 in Fig. 9. Fig. 10B is a view corresponding to the cross-sectional view taken along line 1010-1010 in Fig. 9 of a modified example of the second embodiment. Fig. 10C is a cross-sectional view corresponding to the cross-sectional view taken along line 1010-1010 in Fig. 9 of another modified example of the second embodiment.

[0010] First Embodiment A multilayer ceramic capacitor 1 according to an embodiment of the present disclosure will be described with reference to the drawings. Fig. 1 is an external perspective view of a multilayer ceramic capacitor 1 according to a first embodiment of the present disclosure.

[0011] As shown in Fig. 1, the multilayer ceramic capacitor 1 has a substantially rectangular parallelepiped shape. The multilayer ceramic capacitor 1 includes a laminate 2 and external electrodes. The laminate 2 has a substantially rectangular parallelepiped shape. The external electrodes are disposed at opposite ends of the laminate 2, spaced apart from each other. The external electrodes include a first external electrode 41 and a second external electrode 42.

[0012] The directions in the multilayer ceramic capacitor 1 and the laminate 2 will now be described. Arrow T in FIG. 1 indicates the stacking direction T. Arrow L indicates the length direction L. The length direction L is a direction perpendicular to the stacking direction T. Arrow W indicates the width direction W. The width direction W is a direction perpendicular to the stacking direction T and the length direction L. The stacking direction T, the length direction L, and the width direction W are perpendicular to one another. The arrows T, L, and W indicate the same directions as those described above in figures other than FIG. 1 as well.

[0013] One of the pair of external electrodes is provided at one end in the longitudinal direction L of the laminate 2. The other of the pair of external electrodes is provided at the other end in the longitudinal direction L of the laminate 2. One of the external electrodes is a first external electrode 41. The other external electrode is a second external electrode 42.

[0014] (Laminate) The laminate 2 will be described with reference to Figs. 2, 3, and 4 in addition to Fig. 1. Fig. 2 is a cross-sectional view taken along line 101-101 of Fig. 1. Fig. 3 is a cross-sectional view taken along line 102-102 of Fig. 1. Fig. 4 is a cross-sectional view taken along line 103-103 of Fig. 1. The laminate 2 includes dielectric layers 20 and internal electrodes. The internal electrodes include first internal electrodes 31 and second internal electrodes 32. As shown in Fig. 2, a plurality of dielectric layers 20 and a plurality of internal electrodes are stacked on top of each other.

[0015] The two surfaces of the laminate 2 facing each other in the stacking direction T are called the first main surface 3 and the second main surface 4. The two surfaces of the laminate 2 facing each other in the width direction W are called the first side surface 5 and the second side surface 6. The two surfaces of the laminate 2 facing each other in the length direction L are called the first end surface 7 and the second end surface 8.

[0016] The portion where two surfaces of the laminate 2 intersect is called a ridge portion. The portion where three surfaces of the laminate 2 intersect is called a corner portion. The corners and ridge portions are preferably rounded. Some or all of the main surface, side surface, and end surface may have irregularities formed thereon.

[0017] Line 112 in Fig. 2 indicates the center position in the length direction L of the laminate 2. Line 112 is called the length direction center 112. Line 113 in Fig. 2 indicates the center position in the stacking direction T of the laminate 2. Line 113 is called the stacking direction center 113. Line 111 in Fig. 2 indicates the center position in the width direction W of the laminate 2. Line 111 is called the width direction center 111.

[0018] (Dielectric Layer) The total number of dielectric layers 20 included in the laminate 2 is preferably 2 or more and 101 or less.

[0019] The thickness of the dielectric layer 20 can be observed by measuring the distance between two adjacent first internal electrodes 31 in the stacking direction T or the distance between two adjacent second internal electrodes 32 in the stacking direction T. The thickness of the dielectric layer 20 can be, for example, 1 μm or more and 100 μm or less.

[0020] The dielectric layer 20 is mainly composed of a ceramic material containing at least one of Ca, Sr, Zr, and Ti. Specific examples of the ceramic material include CaZrO. ３ (calcium zirconate) and SrZrO ３ (strontium zirconate), etc. It is particularly preferable that the dielectric layer 20 contains calcium zirconate. However, the material of the dielectric layer 20 is not limited to these.

[0021] The ceramic material forming the dielectric layer 20 may contain all of Ca, Zr, and Ti as its main components. ３ In the formula, ZrO ３ or Ca (Zr ０．９ Ti ０．１ ) O ３ etc. may also be used.

[0022] The ceramic material for forming the dielectric layer 20 is １－ｘ－ｙ , Sr ｘ , Ba ｙ ) ｍ (Zr １－ｚ－α , Ti ｚ , Hf α ) O ３(wherein x is 0 or more and 1 or less, y is 0 or more and 0.4 or less, m is 1.0 or more and 1.1 or less, z is 0 or more and 0.2 or less, and α is 0 or more and 0.3 or less) or BaTi ４ O ９ etc. may also be used.

[0023] Depending on the purpose, additives may be added to the ceramic material forming the dielectric layer 20. Examples of such additives include oxides of rare earth elements such as Mn, Mg, Dy, and Cr, or V, Sm, Eu, Gd, Tb, Ho, Er, Tm, Yb, and Y, or oxides of Co, Ni, Li, B, Na, K, and Si, or glass.

[0024] As described above, in the multilayer ceramic capacitor 1 of this embodiment, the dielectric layers 20 include a dielectric having temperature compensation characteristics. Having temperature compensation characteristics means having a characteristic in which the change in capacitance relative to a change in temperature is small. For example, the change in capacitance is ±30 ppm / °C in the temperature range from −55°C to 125°C.

[0025] The dimensions of the laminate 2 are not particularly limited. The dimension of the laminate 2 in the length direction L can be, for example, 0.2 mm or more and 2.2 mm or less. The preferred dimension of the laminate 2 in the width direction W can be, for example, 0.1 mm or more and 1.5 mm or less. The preferred dimension of the laminate 2 in the stacking direction T can be, for example, 0.1 mm or more and 1.0 mm or less.

[0026] (Internal Electrodes) The internal electrodes will now be described. The internal electrodes include a plurality of first internal electrodes 31 and a plurality of second internal electrodes 32. The first internal electrodes 31 are internal electrodes exposed at the first end face 7. The second internal electrodes 32 are internal electrodes exposed at the second end face 8. Figure 3 shows the first internal electrodes 31.

[0027] The first internal electrode 31 has a first opposing portion 33 and a first lead portion 35. The first opposing portion 33 is a portion that faces the second internal electrode 32. The first lead portion 35 is a portion that is led from the first opposing portion 33 to the first end face 7. The second internal electrode 32 has a second opposing portion 34 and a second lead portion 36. The second opposing portion 34 is a portion that faces the first internal electrode 31. The second lead portion 36 is a portion that is led from the second opposing portion 34 to the second end face 8.

[0028] The shape of the first facing portion 33 is not particularly limited. The shape of the first facing portion 33 is preferably rectangular. The corners of the first facing portion 33 may be rounded or may be obliquely formed (tapered). The shape of the second facing portion 34 is not particularly limited. The shape of the second facing portion 34 is preferably rectangular. The corners of the second facing portion 34 may be rounded or may be obliquely formed (tapered). The taper may have a slope in thickness toward the end.

[0029] The shape of the first lead portion 35 is not particularly limited. The shape of the first lead portion 35 is preferably rectangular. The corners of the first lead portion 35 may be rounded or may be obliquely formed (tapered). The shape of the second lead portion 36 is not particularly limited. The shape of the second lead portion 36 is preferably rectangular. The corners of the second lead portion 36 may be rounded or may be obliquely formed (tapered). The taper may have a slope in thickness toward the end.

[0030] The corner portions are portions located at the corners of the outer shape of the internal electrode when the internal electrode is viewed in cross section in the length direction L and width direction W.

[0031] The width in the width direction W of the first opposing portion 33 and the width in the width direction W of the first lead-out portion 35 may be the same width, or one of the widths may be narrower. The width in the width direction W of the second opposing portion 34 and the width in the width direction W of the second lead-out portion 36 may be the same width, or one of the widths may be narrower.

[0032] The internal electrodes contain at least Cu from among Ni, Cu, Ag, Pd, an alloy of Ag and Pd, and Au, and the main component of the internal electrodes may be Cu.

[0033] The total number of the first internal electrodes 31 and the second internal electrodes 32 can be set to 2 or more and 100 or less.

[0034] The thickness of each of the first internal electrode 31 and the second internal electrode 32 is preferably, for example, about 0.5 μm or more and 3 μm or less.

[0035] (Outer Layer Portion and Inner Layer Portion) The following describes the division of the laminate 2 in the stacking direction T. As shown in Figures 2 and 4, the laminate 2 can be divided into an inner layer portion 10, a first outer layer portion 12, and a second outer layer portion 13 in the stacking direction T.

[0036] The inner layer portion 10 is a portion of the laminate 2 included in the stacking direction T between the position of the internal electrode closest to the first main surface 3 and the position of the internal electrode closest to the second main surface 4 .

[0037] The first outer layer portion 12 is a portion of the laminate 2 included between the first main surface 3 and the position of the internal electrode closest to the first main surface 3 in the stacking direction T. The first outer layer portion 12 is a portion of the laminate 2 included between the inner layer portion 10 and the first main surface 3.

[0038] The second outer layer portion 13 is a portion of the laminate 2 that is included between the second main surface 4 and the position of the internal electrode closest to the second main surface 4 in the stacking direction T. The second outer layer portion 13 is a portion of the laminate 2 that is included between the inner layer portion 10 and the second main surface 4. The first outer layer portion 12 and the second outer layer portion 13 are collectively referred to as the outer layer portions.

[0039] (Core Portion and W Gap) The division of the laminate 2 in the width direction W will be described. As shown in Figures 3 and 4, the laminate 2 can be divided into a core portion 25, a first W gap 15, and a second W gap 16 in the width direction W. The core portion 25 is the portion of the laminate 2 in which internal electrodes are provided in the width direction W. The first W gap 15 is the portion of the laminate 2 between the core portion 25 and the first side surface 5. The second W gap 16 is the portion of the laminate 2 between the core portion 25 and the second side surface 6. The first W gap 15 and the second W gap 16 are collectively referred to as the W gap. No internal electrodes are provided in the W gap. Only a dielectric layer is provided in the W gap. The W gap is also called a side gap.

[0040] (Effective Portion and Ineffective Portion) The division of the core portion 25 in the stacking direction T will be described. As shown in FIG. 4 , the core portion 25 can be divided into an effective portion 26, a first ineffective portion 28, and a second ineffective portion 29 in the stacking direction T. The effective portion 26 is the portion of the core portion 25 in which the first internal electrode 31 or the second internal electrode 32 is arranged in the stacking direction T. The first ineffective portion 28 is the portion of the core portion 25 between the effective portion 26 and the first main surface 3 in the stacking direction T. The second ineffective portion 29 is the portion of the core portion 25 between the effective portion 26 and the second main surface 4 in the stacking direction T. The first ineffective portion 28 and the second ineffective portion 29 are collectively referred to as the ineffective portion. No internal electrodes are provided in the ineffective portions. Only a dielectric layer is provided in the ineffective portions.

[0041] (Opposite Electrode Portion) The portion where the first internal electrode 31 and the second internal electrode 32 overlap is called the opposite electrode portion 38. The opposite electrode portion 38 is the portion where the first opposite portion 33 and the second opposite portion 34 overlap. In the multilayer ceramic capacitor 1, capacitance is formed when the opposite portions of the internal electrodes face each other with the dielectric layer interposed therebetween. In other words, capacitance is formed in the opposite electrode portion 38. This capacitance allows the multilayer ceramic capacitor 1 to exhibit capacitor characteristics.

[0042] (L Gap) The L gap will be described with reference to Figures 2 and 3. In the laminate 2, the portion located between the opposing electrode portion 38 and the end face and including the lead portion of either the first internal electrode 31 or the second internal electrode 32 is called the L gap. The L gap includes a first L gap 18 and a second L gap 19. The first L gap 18 is located between the opposing electrode portion 38 and the first end face 7 and is a portion including the first lead portion 35. The second L gap 19 is located between the opposing electrode portion 38 and the second end face 8 and is a portion including the second lead portion 36.

[0043] (External Electrodes) The external electrodes include a first external electrode 41 and a second external electrode 42. The first external electrode 41 is connected to the first internal electrode 31 and is disposed on the first end face 7. The first external electrode 41 may also be disposed on a portion of the first main surface 3 and a portion of the second main surface 4, as well as a portion of the first side surface 5 and a portion of the second side surface 6. In this embodiment, the first external electrode 41 extends from the first end face 7 to a portion of the first main surface 3 and a portion of the second main surface 4, as well as a portion of the first side surface 5 and a portion of the second side surface 6.

[0044] The second external electrode 42 is connected to the second internal electrode 32 and is disposed on the second end face 8. The second external electrode 42 may also be disposed on a portion of the first main face 3 and a portion of the second main face 4, as well as a portion of the first side face 5 and a portion of the second side face 6. In this embodiment, the second external electrode 42 extends from the second end face 8 to a portion of the first main face 3 and a portion of the second main face 4, as well as a portion of the first side face 5 and a portion of the second side face 6.

[0045] The external electrodes preferably include a base electrode layer and a plating layer. The base electrode layer included in the first external electrode 41 is referred to as a first base electrode layer 51. The base electrode layer included in the second external electrode 42 is referred to as a second base electrode layer 52.

[0046] The plating layer included in the first external electrode 41 is referred to as a first plating layer 61. The plating layer included in the second external electrode 42 is referred to as a second plating layer 62.

[0047] (Base Electrode Layer) The base electrode layer includes at least one selected from a baking layer, a conductive resin layer, a thin film layer, and the like. A case where the base electrode layer is a baking layer will be described. The baking layer includes a glass component and a metal. The glass component of the baking layer includes at least one element selected from, for example, B, Si, Ba, Mg, Al, and Li. The metal of the baking layer includes at least one element selected from, for example, Cu, Ni, Ag, Pd, an Ag—Pd alloy, and Au.

[0048] The baked layer may be formed in multiple layers. The baked layer is formed by applying a conductive paste containing a glass component and a metal to the laminate and baking it. The baked layer may be baked simultaneously with the firing of the internal electrodes and the dielectric layers. It may also be baked after the firing of the internal electrodes. The baked layer may also be baked after the firing of the internal electrodes and the dielectric layers. When the baked layer is baked simultaneously with the firing of the internal electrodes and the dielectric layers, it is preferable to form the baked layer by adding a dielectric material instead of the glass component.

[0049] The thickness in the length direction L at the center position in the stacking direction T of the baked layer located on the first end face 7 and the second end face 8 is preferably, for example, about 3 μm or more and 160 μm or less.

[0050] Furthermore, when a baked layer is provided as a base electrode layer on a portion of the first main surface 3, a portion of the second main surface 4, and a portion of the first side surface 5 and a portion of the second side surface 6, it is preferable that the thickness in the stacking direction T at the center position in the length direction L of the base electrode layer located on the first main surface 3, the second main surface 4, and the first side surface 5 and the second side surface 6 is, for example, approximately 3 μm or more and 40 μm or less.

[0051] (Plating Layer) The first plating layer 61 is disposed so as to cover the first base electrode layer 51. The second plating layer 62 is disposed so as to cover the second base electrode layer 52.

[0052] The material constituting the plating layer includes, for example, at least one selected from Cu, Ni, Sn, Ag, Pd, an Ag—Pd alloy, and Au.

[0053] The plating layer may be formed of multiple layers. In this embodiment, the first plating layer 61 and the second plating layer 62 each include two plating layers. When the plating layer has a two-layer structure, preferably, one layer is a Ni plating layer and the other layer is a Sn plating layer. The Ni plating layer included in the first plating layer 61 is referred to as a first Ni plating layer 63. The Ni plating layer included in the second plating layer 62 is referred to as a second Ni plating layer 64. The Sn plating layer included in the first plating layer 61 is referred to as a first Sn plating layer 65. The Sn plating layer included in the second plating layer 62 is referred to as a second Sn plating layer 66.

[0054] The Ni plating layer prevents the base electrode layer from being eroded by solder when mounting the ceramic electronic component. The Sn plating layer improves the wettability of the solder when mounting the ceramic electronic component, thereby facilitating mounting. For these reasons, it is preferable that the plating layers in contact with the base electrode layer are Ni plating layer and Sn plating layer, in that order. The plating layers may be three or more layers. The main component of the plating layer may be a metal species other than Ni and Sn.

[0055] The preferred thickness of each plating layer is 2 μm or more and 15 μm or less.

[0056] (When no base electrode layer is provided) The external electrode may be formed only with a plating layer, without providing a base electrode layer. A structure in which only a plating layer is provided without providing a base electrode layer will be described. The external electrode does not have a base electrode layer, and the plating layer is formed directly on the surface of the laminate. The internal electrode is directly electrically connected to the plating layer. When the external electrode does not include a base electrode layer, a catalyst may be disposed on the surface of the laminate as a pre-plating treatment, and then the plating layer may be formed.

[0057] The plating layer preferably includes a lower-layer plating electrode formed on the surface of the laminate and an upper-layer plating electrode formed on the surface of the lower-layer plating electrode. The lower-layer plating electrode and the upper-layer plating electrode preferably include at least one metal selected from, for example, Cu, Ni, Sn, Pb, Au, Ag, Pd, Bi, and Zn, or an alloy containing such a metal. The lower-layer plating electrode is preferably formed using Ni, which has solder barrier properties. The upper-layer plating electrode is preferably formed using Sn or Au, which have good solder wettability.

[0058] The lower-layer plated electrode is preferably formed using Cu. The upper-layer plated electrode may be formed as needed, and the external electrode may be composed of only the lower-layer plated electrode. The upper-layer plated electrode may be the outermost layer of the plated layer, or another plated electrode may be formed on the surface of the upper-layer plated electrode.

[0059] The thickness of each plating layer disposed without a base electrode layer is preferably 1 μm or more and 15 μm or less. The plating layer preferably does not contain glass. The metal content per unit volume of the plating layer is preferably 99 volume % or more.

[0060] (Dimensions of Multilayer Ceramic Capacitor) The dimensions of the multilayer ceramic capacitor 1 including the laminate 2 and the external electrodes will be described. The dimension in the length direction L of the multilayer ceramic capacitor 1 can be, for example, 0.2 mm or more and 2.2 mm or less. The preferred dimension in the width direction W of the multilayer ceramic capacitor 1 can be, for example, 0.1 mm or more and 1.5 mm or less. The preferred dimension in the stacking direction T of the multilayer ceramic capacitor 1 can be, for example, 0.1 mm or more and 1.0 mm or less. However, the dimensions of the multilayer ceramic capacitor 1 are not limited to these examples.

[0061] Furthermore, the dimension of the multilayer ceramic capacitor 1 in the length direction L can be greater than the dimension of the multilayer ceramic capacitor 1 in the width direction W and the dimension of the multilayer ceramic capacitor 1 in the lamination direction T.

[0062] The above-described dimensions of the multilayer ceramic capacitor 1 are merely examples. For example, as will be described later in a second embodiment, the dimension of the laminate 2 and the multilayer ceramic capacitor 1 in the length direction L can be made smaller than the dimension of the laminate 2 and the multilayer ceramic capacitor 1 in the width direction W.

[0063] (Interspersed Portions) In the multilayer ceramic capacitor 1 of this embodiment, the dielectric layers 20 have interspersed portions. This will be described with reference to Figures 5A and 5B. Figure 5A is a cross-sectional view of the multilayer ceramic capacitor of this embodiment in the length direction L and lamination direction T. Figure 5B is an enlarged view of a framed area 500 in Figure 5A.

[0064] The interspersed portions are portions whose main component is the same as that of the internal electrodes and whose size is 0.10 μm or more and 0.55 μm or less. In the multilayer ceramic capacitor 1 of this embodiment, the internal electrodes contain Cu. Therefore, the interspersed portions contain Cu.

[0065] 5A and 5B , the interspersed portions include first interspersed portions 201 and second interspersed portions 202. The first interspersed portions 201 are interspersed portions located near the first internal electrodes 31 of the dielectric layer 20. The second interspersed portions 202 are interspersed portions located near the second internal electrodes 32 of the dielectric layer 20. Both the first interspersed portions 201 and the second interspersed portions 202 contain Cu.

[0066] (Region Near Internal Electrode) The region near the internal electrode will be described with reference to Fig. 5B. The region near the internal electrode is called the region near the internal electrode. The region near the internal electrode includes a first region near the internal electrode 211 and a second region near the internal electrode 212. The first region near the internal electrode 211 is the region near the first internal electrode 31. The second region near the internal electrode 212 is the region near the second internal electrode 32.

[0067] The internal electrode neighborhood is a region up to a distance of 45% of the thickness of the dielectric layer 20 from the internal electrode in the stacking direction T. A length TD in Fig. 5B indicates the length in the stacking direction T of the dielectric layer 20 between the first internal electrode 31 and the second internal electrode 32 that are adjacent in the stacking direction T. A length T211 in Fig. 5B indicates the length in the stacking direction T of the first internal electrode neighborhood 211. A length T212 in Fig. 5B indicates the length in the stacking direction T of the second internal electrode neighborhood 212.

[0068] The length T211 is 45% of the length TD. The length T212 is 45% of the length TD.

[0069] The interspersed portions are present at least in the region near the internal electrodes in the dielectric layer 20 of the inner layer portion 10. First interspersed portions 201 are present in the first region near the internal electrodes 211 of the dielectric layer 20. Second interspersed portions 202 are present in the second region near the internal electrodes 212 of the dielectric layer 20.

[0070] The presence of the scattered portions in the dielectric layer 20 can reduce the difference between the linear expansion coefficient of the dielectric layer 20 and the linear expansion coefficient of the internal electrodes. This reduces the difference in shrinkage between the dielectric layer 20 and the internal electrodes during firing. As a result, the residual stress in the dielectric layer 20 after firing is reduced, and the occurrence of structural defects is suppressed.

[0071] Furthermore, in this embodiment, the main component of the internal electrodes is Cu, which results in a good ESR, or equivalent series resistance.

[0072] As described above, the multilayer ceramic capacitor 1 of this embodiment can maintain a good ESR and suppress the occurrence of internal structural defects.

[0073] 5B indicates the distance in the stacking direction T between the first interspersed portion 201 that is farthest from the first internal electrode 31 in the stacking direction T and the first internal electrode 31. The distance Tmax1 is preferably 0.38 μm or more and 1.25 μm or less.

[0074] 5B indicates the distance in the stacking direction T between the second interspersed portions 202 that are farthest from the second internal electrode 32 in the stacking direction T and the second internal electrode 32. The distance Tmax2 is preferably 0.38 μm or more and 1.25 μm or less.

[0075] By setting the maximum distance in the lamination direction T between the interspersed portions and the internal electrodes within a predetermined range, the occurrence of structural defects can be more reliably suppressed.

[0076] It is preferable that the ratio Tmax1 / TD, which is the length TD indicating the thickness of the dielectric layer 20, i.e., the distance between the internal electrodes, and the distance Tmax1 in the stacking direction T between the first interspersed portion 201 that is the furthest from the first internal electrode 31 in the stacking direction T and the first internal electrode 31, is 0.117 or more and 0.400 or less.

[0077] It is preferable that the ratio Tmax2 / TD, which is the length TD indicating the thickness of the dielectric layer 20, i.e., the distance between the internal electrodes, and the distance Tmax2 in the stacking direction T between the second interspersed portion 202 that is the furthest from the second internal electrode 32 in the stacking direction T, is 0.117 or more and 0.400 or less.

[0078] If the ratio is less than 0.117, the linear expansion coefficient of the dielectric layer 20 is not sufficiently large, and therefore the difference in shrinkage between the dielectric layer 20 and the internal electrodes during firing is not sufficiently small, which makes the internal structure more susceptible to defects such as cracks.

[0079] On the other hand, if the ratio exceeds 0.400 μm, the distance between the first interspersed portions 201 and the second interspersed portions 202, the distance between the first interspersed portions 201 and the second internal electrode 32, or the distance between the second interspersed portions 202 and the first internal electrode 31 becomes too small, resulting in a decrease in withstand voltage reliability.

[0080] The interspersed portions contain, for example, Cu, and therefore conduct electricity even if only slightly, and therefore, if the interspersed portions are too close to the internal electrodes, for example, the breakdown voltage (BDV) may decrease.

[0081] From the above, when the ratio is 0.117 μm or more and 0.400 μm or less, the ESR (equivalent series resistance) is good, the occurrence of structural defects is suppressed, and the high temperature load reliability is also good.

[0082] The above-mentioned lengths and distances are measured on a cross section in the length direction L and stacking direction T at the widthwise center 111 of the laminate 2. The same applies to the lengths and distances described below unless otherwise specified.

[0083] (Length Direction Arrangement) The arrangement of the interspersed portions in the length direction L will be described. Distance L11 shown in FIG. 5B indicates the distance in the length direction L between adjacent first interspersed portions 201. Distance L12 shown in FIG. 5B indicates the distance in the length direction L between adjacent second interspersed portions 202. Distance L11 and distance L12 are preferably, for example, about 2 μm. Furthermore, distance L11 and distance L12 can be, for example, the average of the distances between multiple interspersed portions adjacent in the length direction L.

[0084] The length L21 shown in FIG. 5B indicates the length of the first interspersed portions 201 in the length direction L. The length L22 shown in FIG. 5B indicates the length of the second interspersed portions 202 in the length direction L. In a predetermined length range in the length direction L of the internal electrode, such as the entire length of the internal electrode in the length direction L, the sum of the lengths of the portions in which the interspersed portions exist within that length range is preferably, for example, 50% or more. For the first internal electrode 31, the sum of the lengths L21 of the first interspersed portions 201 within that length range is, for example, when the interspersed portions do not overlap in the stacking direction T. For the second internal electrode 32, the sum of the lengths L22 of the second interspersed portions 202 within that length range is, for example, when the interspersed portions do not overlap in the stacking direction T.

[0085] (Distribution of Interspersed Portions in Cross Sections in the Length Direction and the Width Direction) The distribution of interspersed portions in cross sections in the length direction L and the width direction W will be described with reference to Figures 6A and 6B. Figure 6A is a cross-sectional view in the length direction L and the width direction W of a multilayer ceramic capacitor 1 according to an embodiment of the present disclosure. Figure 6B is a cross-sectional view in the length direction L and the width direction W of a multilayer ceramic capacitor according to another example of an embodiment of the present disclosure.

[0086] 6A and 6B are cross-sectional views taken along the center 113 in the stacking direction.

[0087] 6A , first interspersed portions 201 are arranged around the first internal electrode 31. The edge of the first internal electrode 31 facing the first side surface 5 is called the first side surface edge 315. The edge of the first internal electrode 31 facing the second side surface 6 is called the second side surface edge 316. The edge of the first internal electrode 31 facing the second end surface 8 is called the second end surface edge 318. The first interspersed portions 201 are present around all of the edges of the first side surface edge 315, the second side surface edge 316, and the second end surface edge 318.

[0088] Fig. 6B shows a modified example of the first internal electrode 31 shown in Fig. 6A. The first internal electrode 31 shown in Fig. 6A has a rectangular cross section in the length direction L and width direction W. In contrast, the first internal electrode 31 shown in Fig. 6B has a shorter length in the width direction W in the vicinity of the first end face 7.

[0089] As shown in Figure 6B, even if the cross-sectional shape of the first internal electrode 31 in the length direction L and width direction W changes, the first interspersed portions 201 are present around all of the end edges of the first side surface side edge 315, the second side surface side edge 316, and the second end surface side edge 318, just as when the first internal electrode 31 is rectangular.

[0090] 6A and 6B have been described with reference to the first internal electrode 31 and the first interspersed portions 201. The matters described with reference to Fig. 6A and 6B also apply to the second internal electrode 32 and the second interspersed portions 202.

[0091] The evaluation of the comparative example and the example will be described with reference to Figure 7. (Experimental Method) 1. Multilayer ceramic capacitors were manufactured according to the manufacturing method described after sample preparation. The distance between the interspersed portions and the internal electrodes was adjusted by the firing temperature, firing time, and temperature rise / fall rate. The comparative example was manufactured with a firing time longer than any of the examples.

[0092] The dimensions of the multilayer ceramic capacitor were as follows: the length direction L was 0.25 mm, the width direction W was 0.125 mm, and the lamination direction T was 0.125 mm.

[0093] 2. Withstand voltage reliability test The withstand voltage of the multilayer ceramic capacitors manufactured in "1. Sample preparation" was measured. The withstand voltage was measured in a DC-BDV test. The test conditions for the DC-BDV test were as follows: The withstand voltage was measured (DC-BDV test) under conditions of a voltage rise rate of 100 V / sec and a detection current of 10 mA, and the withstand voltage of each sample was measured. Twenty samples were randomly selected for each sample, and the average value of their BDV was used as the withstand voltage value.

[0094] 3. Internal Structure Defect Test The internal structure result test was performed as follows: 1) The cross section in the length direction L and the stacking direction was polished at the center position in the width direction W. This exposed the cross section in the length direction L and the stacking direction T, i.e., the LT cross section. 2) The presence or absence of cracks in the dielectric layer was confirmed using an optical microscope, and the number of samples in which cracks occurred was counted.

[0095] 4. Measurement of the distance between the interspersed portions and the internal electrodes The distance between the interspersed portions and the internal electrodes was measured as follows: 1) The sample polished in "3. Internal structural defect test" was used. That is, the cross section in the length direction L and the lamination direction was polished at the center position in the width direction W. This exposed the LT cross section. 2) Using a scanning electron microscope (SEM), the maximum distance between the first internal electrode and the first interspersed portions, and the maximum distance between the second internal electrode and the second interspersed portions were measured (magnification: 5000x).

[0096] (Experimental Results) The experimental results will be described with reference to Fig. 7. In the following description and Fig. 7, the maximum distance Tmax between the interspersed portions and the internal electrodes refers to the longer of the maximum distance between the first internal electrode and the first interspersed portions and the maximum distance between the second internal electrode and the second interspersed portions, measured in "4. Measurement of the distance between the interspersed portions and the internal electrodes".

[0097] Comparative Example In the comparative example, since there were no scattered portions, internal cracks occurred at a relatively high level.

[0098] Example 1 In Example 1, the maximum distance Tmax between the interspersed portions and the internal electrodes was 0.19 μm. Tmax / TD was 0.077. In Example 1, the incidence of internal structural defects was reduced compared to the comparative example.

[0099] (Examples 2 to 7) In Examples 2 to 7, the maximum distance Tmax between the interspersed portions and the internal electrodes was 0.38 μm or more and 1.36 μm or less. The range of Tmax / TD was 0.117 or more and 0.449 or less. In Examples 2 to 7, the incidence rate of internal structural defects was the best.

[0100] (Example 7) In Example 7, as described above, the maximum distance Tmax between the interspersed portions and the internal electrodes is 1.36 μm. Tmax / TD is 0.449. In Example 7, the incidence rate of internal structural defects was the best. However, in Example 7, the high temperature load reliability was lower than in Examples 1 to 6.

[0101] If the maximum distance Tmax between the interspersed portions and the internal electrodes is less than 0.38 μm and Tmax / TD is less than 0.117, the linear expansion coefficient is not large enough, and it is difficult to reduce the difference in shrinkage with the internal electrodes. As a result, although the incidence of internal structural defects such as cracks decreases, some internal structural defects will still occur.

[0102] If the maximum distance Tmax between the interspersed portions and the internal electrodes exceeds 1.25 μm and Tmax / TD exceeds 0.400, the distance between the first interspersed portions and the second interspersed portions, the distance between the first interspersed portions and the second internal electrodes, or the distance between the second interspersed portions and the first internal electrodes becomes too small, resulting in a certain degree of reduction in withstand voltage reliability.

[0103] In Examples 2 to 6, when the maximum distance Tmax between the interspersed portion and the internal electrode was in the range of 1.25 to 0.38 μm and the range of Tmax / TD was in the range of 0.117 to 0.400, both the reliability against internal structural defects and the high-temperature load reliability were the best, and more preferable results were shown.

[0104] When the maximum distance Tmax between the interspersed portions and the internal electrodes is in the range of 0.38 to 1.25 μm and Tmax / TD is in the range of 0.117 to 0.400, structural defects are suppressed and the withstand voltage reliability is also good.

[0105] (Method for Manufacturing Multilayer Ceramic Capacitor) A method for manufacturing the multilayer ceramic capacitor 1 will be described. Note that the method for manufacturing the multilayer ceramic capacitor 1 is not limited to the method described below.

[0106] A dielectric sheet and a conductive paste for the internal electrodes are prepared. The dielectric sheet and the conductive paste for the internal electrodes contain a binder and a solvent. Known binders and solvents can be used. The dielectric sheet is also called a ceramic green sheet. The conductive paste is also called a paste for the internal electrodes.

[0107] A dielectric sheet on which an internal electrode pattern is formed is prepared. A conductive paste for the internal electrodes is printed on the dielectric sheet in a predetermined pattern, thereby preparing a dielectric sheet on which a first internal electrode pattern is formed and a dielectric sheet on which a second internal electrode pattern is formed. The printing is performed by, for example, screen printing or gravure printing.

[0108] A predetermined number of dielectric sheets not printed with an internal electrode pattern are stacked to form a portion that will become a first outer layer portion. Dielectric sheets printed with a first internal electrode pattern and a second internal electrode pattern are stacked in order on top of that to form a portion that will become an inner layer portion. Furthermore, a predetermined number of dielectric sheets not printed with an internal electrode pattern are stacked on top of the portion that will become an inner layer portion to form a portion that will become a second outer layer portion. In this way, a laminated sheet is produced.

[0109] (Interspersed portions) When printing the paste for the internal electrodes (internal electrode paste) on the ceramic green sheets (dielectric sheets), the internal electrode paste is also printed on the portions that will become the interspersed portions, thereby forming the interspersed portions in the manufactured multilayer ceramic capacitor.

[0110] The method for printing the internal electrode paste is not limited, and examples thereof include screen printing, gravure printing, and inkjet printing. The same applies to printing of the interspersed portions. The internal electrode paste may be printed so that the portions that become the interspersed portions ultimately have a size of 0.10 μm or more and 0.55 μm or less.

[0111] The internal electrode pattern and the interspersed portions may be printed simultaneously or separately. When the internal electrode pattern and the interspersed portions are printed separately, either the internal electrode pattern or the interspersed portions may be printed first.

[0112] The prepared laminated sheet is pressed in the lamination direction by means of a hydrostatic press or the like to prepare a laminated block.

[0113] The laminated block is cut into individual pieces to produce laminated chips. Specifically, the laminated block is cut into individual pieces using a cutting blade to produce pre-fired laminates.

[0114] The laminated chip is fired to produce a laminate. Before firing, the corners and ridges of the laminated chip may be rounded by barrel polishing or the like. The firing temperature is preferably 900°C or higher and 1400°C or lower, depending on the materials of the dielectric and internal electrodes. The above-mentioned barrel polishing or the like can also be performed on the laminated body after firing.

[0115] Next, the external electrodes are formed. First, a conductive paste that will become the base electrode layer is applied to both end surfaces of the laminate 2 to form the base electrode layer. When forming a baked layer as the base electrode layer, a conductive paste containing a glass component and a metal is applied by a method such as dipping, and then a baking process is performed to form the base electrode layer. The baking temperature at this time is preferably 700°C or higher and 900°C or lower.

[0116] Then, a plating layer is formed on the surface of the base electrode layer. A Ni plating layer and a Sn plating layer are formed on the base electrode layer. The Ni plating layer and the Sn plating layer are formed sequentially by, for example, barrel plating. In this manner, a multilayer ceramic capacitor is obtained.

[0117] (Other Manufacturing Methods) Various methods are possible for forming the interspersed portions. In the example of the manufacturing method described above, the internal electrode paste is printed on the portions of the ceramic green sheets that will become the interspersed portions. Other methods for forming the interspersed portions will be described below.

[0118] A method for firing a molded body so as to form interspersed portions in the firing process is described below. A molded body, which is a laminate before firing, is fired to produce a sintered body. The sintered body becomes the laminate of a multilayer ceramic capacitor. Firing converts the ceramic green sheets into dielectric layers and the conductive paste films into internal electrodes. Firing can be performed, for example, in a non-oxidizing atmosphere of nitrogen, water, and hydrogen, at a temperature of 900°C to 1050°C (top temperature) and maintained for 5 to 30 minutes. During firing, the rate of temperature rise and fall is adjusted to 100°C / min to 2000°C / min. More preferably, the rate of temperature rise and fall is adjusted to 150°C / min to 1000°C / min. By performing firing under the above conditions, particularly by adjusting the temperature rise and fall rate to the aforementioned conditions, interspersed portions can be formed after the firing process.

[0119] Specifically, for example, the temperature increase rate is set to 200° C. / min, and the top temperature is set to 1050° C. This allows the interspersed portions to be formed.

[0120] The time required for raising the temperature to the top temperature is preferably 1 minute to 7 minutes.

[0121] (Modification of First Embodiment) A modification of the first embodiment will be described with reference to Figures 8A to 8D. Figures 8A to 8D are cross-sectional views of different modifications of the first embodiment in the length direction L and lamination direction T, respectively. The multilayer ceramic capacitor 1 of the modification differs from the multilayer ceramic capacitor 1 shown in Figure 5A in the configuration of the internal electrodes.

[0122] (Modification shown in FIGS. 8A and 8B) In the modification shown in FIGS. 8A and 8B, a dummy electrode is provided between the tip end of the internal electrode in the length direction L and the end face facing the tip end.

[0123] The tip portion of the first internal electrode 31 on the second end face 8 side in the longitudinal direction L is called the first tip portion 3100. A first dummy electrode 3101 is provided between the first tip portion 3100 and the second end face 8 via the dielectric layer 20. The first dummy electrode 3101 extends in the longitudinal direction L and is connected to the second end face 8. The first dummy electrode 3101 is not connected to the first internal electrode 31.

[0124] The same applies to the second internal electrode 32. The tip portion of the second internal electrode 32 on the first end face 7 side in the longitudinal direction L is called the second tip portion 3200. A second dummy electrode 3202 is provided between the second tip portion 3200 and the first end face 7 with the dielectric layer 20 interposed therebetween. The second dummy electrode 3202 extends in the longitudinal direction L and is connected to the first end face 7. The second dummy electrode 3202 is not connected to the second internal electrode 32.

[0125] Interspersed portions are also arranged in the vicinity of the first dummy electrode 3101 and the second dummy electrode 3202. The interspersed portions arranged in the vicinity of the first dummy electrode 3101 are referred to as first dummy interspersed portions 2011. The interspersed portions arranged in the vicinity of the second dummy electrode 3202 are referred to as second dummy interspersed portions 2022. Like the first interspersed portions 201 and the second interspersed portions 202, the first dummy interspersed portions 2011 and the second dummy interspersed portions 2022 are arranged in the vicinity of the ends of the first dummy electrode 3101 and the second dummy electrode 3202 in the length direction L, the stacking direction T, and the width direction W, respectively.

[0126] 8A and 8B differ in the arrangement of the first internal electrodes 31 and the second internal electrodes 32 in the stacking direction T. In the example shown in Fig. 8A , the first internal electrodes 31 and the second internal electrodes 32 are alternately arranged in the stacking direction T. Accordingly, the first dummy electrodes 3101 and the second dummy electrodes 3202 are also alternately arranged in the stacking direction T, although their positions in the length direction L differ between the second end face 8 side and the first end face 7 side.

[0127] 8B , the first internal electrodes 31 and the second internal electrodes 32 are alternately arranged two by two in the stacking direction T. Accordingly, the first dummy electrodes 3101 and the second dummy electrodes 3202 are also alternately arranged two by two in the stacking direction T, although their positions in the length direction L differ between the second end face 8 side and the first end face 7 side.

[0128] In the multilayer ceramic capacitor 1 shown in Figures 8A and 8B, dummy electrodes are formed between the tip ends in the length direction L of the internal electrodes and the end faces where no electrodes are provided in the multilayer ceramic capacitor 1 shown in Figure 5A. Therefore, in addition to the effect of the arrangement of the interspersed portions described for the multilayer ceramic capacitor 1 shown in Figure 5A, the multilayer ceramic capacitor 1 shown in Figures 8A and 8B suppresses uneven cutting and uneven shapes of the laminated chips when the laminated block is cut into individual pieces to produce laminated chips.

[0129] 8C , the first inner electrode 31 and the second inner electrode 32 do not overlap in the stacking direction T. A dielectric layer 20 is present in the length direction L between the first tip portion 3100 and the second tip portion 3200.

[0130] In the multilayer ceramic capacitor 1 shown in FIG. 8C , in addition to the effect of the arrangement of the interspersed portions described with respect to the multilayer ceramic capacitor 1 shown in FIG. 5A , it is easy to reduce the capacitance of the multilayer ceramic capacitor 1.

[0131] (Modification shown in Fig. 8D) In ​​the modification shown in Fig. 8D, a floating island electrode 300 is provided in addition to the multilayer ceramic capacitor 1 shown in Fig. 8C. The floating island electrode 300 can be a so-called floating electrode. When viewed in the stacking direction T, the floating island electrode 300 partially overlaps with the first inner electrode 31 and the second inner electrode 32.

[0132] The island electrode 300 also has interspersed portions arranged in the vicinity thereof. The interspersed portions arranged in the vicinity of the island electrode 300 are called interspersed island portions 203.

[0133] In the multilayer ceramic capacitor 1 shown in FIG. 8D , in addition to the effect of the arrangement of the interspersed portions described with respect to the multilayer ceramic capacitor 1 shown in FIG. 5A , it is easier to reduce the capacitance of the multilayer ceramic capacitor 1.

[0134] Second Embodiment A multilayer ceramic capacitor 1 according to a second embodiment will be described with reference to FIGS. 9 and 10. In the description of the second embodiment, differences from the first embodiment will be mainly described. Items not specifically described in the second embodiment can be the same as those in the first embodiment.

[0135] 9 is an external perspective view of a multilayer ceramic capacitor 1 according to a second embodiment of the present disclosure. The second embodiment and the first embodiment differ mainly in the size relationship between the length direction L and the width direction W of the multilayer ceramic capacitor 1. In the first embodiment, the size of the multilayer ceramic capacitor 1 in the length direction L is larger than the size of the width direction W. In contrast, in the second embodiment, the size of the multilayer ceramic capacitor 1 in the length direction L is smaller than the size of the width direction W. In other words, the size of the length direction L and the width direction W is reversed between the multilayer ceramic capacitor 1 of the second embodiment and the multilayer ceramic capacitor 1 of the first embodiment.

[0136] The dimensions of the multilayer ceramic capacitor 1 of the second embodiment can be, for example, as follows: the dimension in the length direction L is 0.2 mm or more and 0.6 mm or less, the dimension in the width direction W is 0.4 mm or more and 1 mm or less, and the dimension in the stacking direction T is 0.1 mm or more and 0.9 mm or less.

[0137] The cross-sectional structure of the multilayer ceramic capacitor 1 of the second embodiment will be described with reference to Fig. 10A to Fig. 10C. Fig. 10A is a cross-sectional view taken along line 1010-1010 in Fig. 9. Fig. 10B and Fig. 10C are cross-sectional views corresponding to the cross-sectional view taken along line 1010-1010 in Fig. 9, showing modified examples of the multilayer ceramic capacitor 1 of the second embodiment.

[0138] The configuration of the internal electrodes and the like shown in Fig. 10A is the same as the configuration shown in Fig. 8A for the multilayer ceramic capacitor 1 of the first embodiment. The configuration of the internal electrodes and the like shown in Fig. 10B is the same as the configuration shown in Fig. 8B for the multilayer ceramic capacitor 1 of the first embodiment. The configuration of the internal electrodes and the like shown in Fig. 10C is the same as the configuration shown in Fig. 8C for the multilayer ceramic capacitor 1 of the first embodiment. However, in the multilayer ceramic capacitor 1 shown in Figs. 10A to 10C, the ratio of the dimension in the stacking direction T to the dimension in the length direction L is slightly smaller than in the multilayer ceramic capacitor 1 shown in Figs. 8A to 8C.

[0139] 1 and 9, the multilayer ceramic capacitor 1 of the present disclosure can have various external shapes. For example, the relationship between the dimensions in the length direction L, the width direction W, and the stacking direction T can be set in various ways.

[0140] In particular, by adopting the configuration of the internal electrode layers as shown in Figures 10A to 10C for the multilayer ceramic capacitor 1 of the second embodiment, in addition to the points already described, it is possible to further reduce the ESR (Equivalent Series Resistance), because it is possible to arrange many electrodes with the same potential inside the multilayer ceramic capacitor 1.

[0141] Although the embodiments of the present invention have been described above, the present invention is not limited to the above-described embodiments, and various changes, modifications, and combinations are possible.

[0142] <1> A multilayer ceramic capacitor comprising: a laminate including a plurality of laminated dielectric layers and a plurality of first internal electrodes and second internal electrodes, the laminate having main surfaces opposing each other in a lamination direction, side surfaces opposing each other in a width direction perpendicular to the lamination direction, and end surfaces opposing each other in a length direction perpendicular to the lamination direction and the width direction; a first external electrode disposed on the end surfaces and connected to the first internal electrode; and a second external electrode connected to the second internal electrode; the plurality of dielectric layers include a dielectric having a temperature compensation characteristic; the first internal electrode and the second internal electrode each contain Cu; the dielectric layer has first interspersed portions containing Cu in a region adjacent to the first internal electrode; and the dielectric layer has second interspersed portions containing Cu in a region adjacent to the second internal electrode.

[0143] <2> The multilayer ceramic capacitor according to <1>, wherein a ratio of a distance in the stacking direction between the first interspersed portion, which is farthest from the first internal electrode in the stacking direction, and the first internal electrode to a thickness of the dielectric layer in the stacking direction is 0.117 or more and 0.400 or less, and a ratio of a distance in the stacking direction between the second interspersed portion, which is farthest from the second internal electrode in the stacking direction, and the second internal electrode to a thickness of the dielectric layer in the stacking direction is 0.117 or more and 0.400 or less.

[0144] <3> The multilayer ceramic capacitor according to <1> or <2>, wherein the distance in the stacking direction between the first interspersed portion that is farthest from the first internal electrode in the stacking direction and the first internal electrode is 0.38 μm or more and 1.25 μm or less, and the distance in the stacking direction between the second interspersed portion that is farthest from the second internal electrode in the stacking direction and the second internal electrode is 0.38 μm or more and 1.25 μm or less.

[0145] <4> The dielectric layer contains (Ca １－ｘ－ｙ , Sr ｘ , Ba ｙ ) ｍ (Zr １－ｚ－α , Ti ｚ , Hf α ) O ３(wherein x is 0 or more and 1 or less, y is 0 or more and 0.4 or less, m is 1.0 or more and 1.1 or less, z is 0 or more and 0.2 or less, and α is 0 or more and 0.3 or less) or BaTi ４ O ９ The multilayer ceramic capacitor according to any one of <1> to <3>,

[0146] <5> The multilayer ceramic capacitor according to any one of <1> to <4>, wherein the length dimension of the laminate is smaller than the width dimension of the laminate.

[0147] REFERENCE SIGNS LIST 1 Multilayer ceramic capacitor 2 Laminate 3 First main surface 4 Second main surface 5 First side surface 6 Second side surface 7 First end surface 8 Second end surface 10 Inner layer portion 12 First outer layer portion 13 Second outer layer portion 20 Dielectric layer 25 Core portion 26 Effective portion 28 First ineffective portion 29 Second ineffective portion 31 First internal electrode 32 Second internal electrode 33 First opposing portion 34 Second opposing portion 35 First lead portion 36 Second lead portion 38 Opposing electrode portion 41 First external electrode 42 Second external electrode 51 First base electrode layer 52 Second base electrode layer 61 First plating layer 62 Second plating layer 111 Width direction center 112 Direction center 113 Stacking direction center 201 First scattered portion 202 Second interspersed portion 203 Floating island interspersed portion 211 Region near first internal electrode 212 Region near second internal electrode 300 Floating island electrode 315 First side edge 316 Second side edge 318 Second end face edge 500 Frame

Claims

1. A multilayer ceramic capacitor comprising: a laminate including a plurality of laminated dielectric layers and a plurality of first and second internal electrodes, the laminate having main surfaces opposing in the lamination direction, side surfaces opposing in a width direction perpendicular to the lamination direction, and end surfaces opposing in a length direction perpendicular to the lamination direction and the width direction; a first external electrode disposed on the end surfaces and connected to the first internal electrode, and a second external electrode connected to the second internal electrode; the plurality of dielectric layers including a dielectric having temperature compensation characteristics; the first internal electrode and the second internal electrode including Cu; the dielectric layer having first interspersed portions containing Cu in a region adjacent to the first internal electrode; and the dielectric layer having second interspersed portions containing Cu in a region adjacent to the second internal electrode.

2. The multilayer ceramic capacitor according to claim 1, wherein the ratio of the distance in the stacking direction between the first interspersed portion that is farthest from the first internal electrode in the stacking direction and the first internal electrode to the thickness of the dielectric layer in the stacking direction is 0.117 or more and 0.400 or less, and the ratio of the distance in the stacking direction between the second interspersed portion that is farthest from the second internal electrode in the stacking direction and the second internal electrode to the thickness of the dielectric layer in the stacking direction is 0.117 or more and 0.400 or less.

3. A multilayer ceramic capacitor according to claim 1 or 2, wherein the distance in the stacking direction between the first interspersed portion that is farthest from the first internal electrode in the stacking direction and the first internal electrode is 0.38 μm or more and 1.25 μm or less, and the distance in the stacking direction between the second interspersed portion that is farthest from the second internal electrode in the stacking direction and the second internal electrode is 0.38 μm or more and 1.25 μm or less.

4. The dielectric layer is (Ca １－ｘ－ｙ , Sr ｘ , Ba ｙ ) ｍ (Zr １－ｚ－α , Ti ｚ , Hf α ) O ３ (wherein x is 0 or more and 1 or less, y is 0 or more and 0.4 or less, m is 1.0 or more and 1.1 or less, z is 0 or more and 0.2 or less, and α is 0 or more and 0.3 or less) or BaTi ４ O ９ The multilayer ceramic capacitor according to claim 1 , comprising:

5. The multilayer ceramic capacitor according to any one of claims 1 to 4, wherein the length dimension of the laminate is smaller than the width dimension of the laminate.

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