Multilayer ceramic capacitor

Abstract

The present invention provides a multilayer ceramic capacitor which is capable of improving moisture resistance of the multilayer ceramic capacitor.　A multilayer ceramic capacitor 10 according to the present invention comprises: a multilayer body that has a first surface and a second surface which are opposite to each other in the stacking direction, a third surface and a fourth surface which are opposite to each other in a first direction that is orthogonal to the stacking direction, and a fifth surface and a sixth surface which are opposite to each other in a second direction that is orthogonal to the stacking direction and the first direction; and four external electrodes that are disposed on the multilayer body. The multilayer body comprises a first internal electrode that has one end exposed on the third surface and the other end exposed on the fourth surface, and a second internal electrode that has one end exposed on the third surface and the other end exposed on the fourth surface. If a region surrounded by the third surface, the first internal electrode, and the second internal electrode is defined as a first region when viewed in the stacking direction, the dimension of the first region in the first direction is 5 µm or more, and the dimension of the first region in the second direction is 70 µm or more.

Description

Multilayer ceramic capacitors

[0001] The present invention relates to a multilayer ceramic capacitor.

[0002] In recent years, electronic devices such as mobile phones and portable music players have become smaller and thinner. Accordingly, the multilayer ceramic capacitors mounted in these smaller and thinner electronic devices have also become smaller and thinner (see Patent Document 1). In particular, multilayer ceramic capacitors that have become thinner are now being used by being built into wiring boards, or even when mounted on the surface of a wiring board, they are being mounted in very narrow spaces.

[0003] Japanese Patent Application Laid-Open No. 2021-101449

[0004] As a multilayer ceramic capacitor that can accommodate such thinning, a multilayer ceramic capacitor is disclosed in Patent Document 1. For the multilayer ceramic capacitor described in Patent Document 1 and elsewhere, a method is known in which an area other than the external electrodes is masked and an underlayer is formed as a sputtered film using a sputtering method. However, when viewed in the stacking direction, if the area surrounded by the internal electrodes and each side surface excluding both main surfaces is relatively small, the distance from the outside to the internal electrodes becomes short, and there is a risk that moisture will penetrate from the outside, deteriorating the moisture resistance of the multilayer ceramic capacitor.

[0005] SUMMARY OF THE INVENTION Therefore, a primary object of the present invention is to provide a multilayer ceramic capacitor that can improve the moisture resistance of the multilayer ceramic capacitor.

[0006] A multilayer ceramic capacitor according to the present invention is a multilayer ceramic capacitor comprising: a laminate having first and second surfaces opposed to each other in a stacking direction, third and fourth surfaces opposed to each other in a first direction perpendicular to the stacking direction, and fifth and sixth surfaces opposed to each other in a second direction perpendicular to the stacking direction and the first direction; and four external electrodes arranged on the laminate, wherein the laminate has a first internal electrode having one end exposed on the third surface and the other end exposed on the fourth surface, and a second internal electrode having one end exposed on the third surface and the other end exposed on the fourth surface, and wherein, when a region surrounded by the third surface, the first internal electrode, and the second internal electrode is defined as a first region as viewed in the stacking direction, the dimension of the first region in the first direction is 5 μm or more and the dimension of the first region in the second direction is 70 μm or more.

[0007] According to the multilayer ceramic capacitor of the present invention, when viewed in the stacking direction, the region surrounded by the third surface, the first internal electrode, and the second internal electrode is defined as the first region, the dimension of the first region in the first direction is 5 μm or more, and the dimension of the first region in the second direction is 70 μm or more.Therefore, when viewed in the stacking direction, the region surrounded by the internal electrodes and the third surface can be ensured to have a predetermined size, and the distance from the outside to the internal electrodes can be ensured, which makes it possible to suppress the penetration of moisture from the outside and reduce deterioration of the insulation resistance.

[0008] According to the present invention, a multilayer ceramic capacitor capable of improving the moisture resistance of the multilayer ceramic capacitor is provided.

[0009] The above and other objects, features and advantages of the present invention will become more apparent from the following detailed description of the preferred embodiments of the present invention, which proceeds with reference to the accompanying drawings.

[0010] 1 is an external perspective view showing an example of a multilayer ceramic capacitor according to a first embodiment of the present invention; FIG. 2 is a front view showing an example of a multilayer ceramic capacitor according to the first embodiment of the present invention; FIG. 3 is a side view showing an example of a multilayer ceramic capacitor according to the first embodiment of the present invention; FIG. 4 is a cross-sectional view taken along line IV-IV in FIG. 1; FIG. 5 is a cross-sectional view taken along line V-V in FIG. 1; FIG. 6 is a cross-sectional view taken along line VI-VI in FIG. 1; FIG. 7 is a cross-sectional view taken along line VII-VII in FIG. 1; FIG. 8 is a cross-sectional view taken along line VIIIA-VIIIA in FIG. 2; and FIG. 9 is a cross-sectional view taken along line VIIIB-VIIIB in FIG. 2. An exploded perspective view of the laminate shown in FIG. 1; FIG. 10 is a cross-sectional view showing an example of a multilayer ceramic capacitor according to a first modified example of the first embodiment of the present invention; FIG. 11 is a cross-sectional view showing an example of a multilayer ceramic capacitor according to a second modified example of the first embodiment of the present invention; and FIG. 12 is a cross-sectional view showing an example of a multilayer ceramic capacitor according to a third modified example of the first embodiment of the present invention. 14 is a schematic cross-sectional view taken along line XV-XV in FIG. 13 , illustrating the structure of an example of a multilayer ceramic capacitor according to a second embodiment of the present invention. It is a schematic cross-sectional view taken along line XVI-XVI in FIG. 13 . It is a schematic cross-sectional view taken along line XVII-XVII ...VIII-XVIII in FIG. 13 . It is a schematic cross-sectional view taken along line XIXA-XIXA in FIG. 14 . It is a schematic cross-sectional view taken along line XIXB-XIXB in FIG. 14 . It is an exploded perspective view of the laminate shown in FIG. 13 . It is an external perspective view, seen from one side, of an example of a multilayer ceramic capacitor according to a third embodiment of the present invention. It is an external perspective view, seen from the other side, of an example of a multilayer ceramic capacitor according to the third embodiment of the present invention. It is a schematic cross-sectional view taken along line XXIII-XXIII in FIG. 21 . It is a schematic cross-sectional view taken along line XXIV-XXIV in FIG. 21 . It is a schematic cross-sectional view taken along line XXV-XXV in FIG. 21 .FIG. 26 is a cross-sectional view taken along line XXVI-XXVI in FIG. 21.

[0011] A. First Embodiment 1. Multilayer Ceramic Capacitor Next, an example of a multilayer ceramic capacitor 10 according to an embodiment of the present invention will be described.

[0012] FIG. 1 is an external perspective view showing an example of a multilayer ceramic capacitor according to a first embodiment of the present invention. FIG. 2 is a front view showing an example of a multilayer ceramic capacitor according to the first embodiment of the present invention. FIG. 3 is a side view showing an example of a multilayer ceramic capacitor according to the first embodiment of the present invention. FIG. 4 is a cross-sectional view taken along line IV-IV in FIG. 1. FIG. 5 is a cross-sectional view taken along line V-V in FIG. 1. FIG. 6 is a cross-sectional view taken along line VI-VI in FIG. 1. FIG. 7 is a cross-sectional view taken along line VII-VII in FIG. 1. FIG. 8A is a cross-sectional view taken along line VIIIA-VIIIA in FIG. 2. FIG. 8B is a cross-sectional view taken along line VIIIB-VIIIB in FIG. 2. FIG. 9 is an exploded perspective view of the laminate shown in FIG. 1.

[0013] The multilayer ceramic capacitor 10 includes a laminate 12 and a plurality of external electrodes 30 .

[0014] (Laminate) The laminate 12 has a first surface 12a and a second surface 12b facing in a stacking direction x, a third surface 12c and a fourth surface 12d facing in a first direction y perpendicular to the stacking direction x, and a fifth surface 12e and a sixth surface 12f facing in a second direction z perpendicular to the stacking direction x and the first direction y. The direction connecting the first surface 12a and the second surface 12b of the laminate 12 is the stacking direction x.

[0015] Furthermore, it is preferable that the corners and ridges of the laminate 12 are rounded. Note that the corners refer to the portions where three adjacent faces of the laminate 12 intersect, and the ridges refer to the portions where two adjacent faces of the laminate 12 intersect. Furthermore, unevenness may be formed on part or all of the third face 12c, the fourth face 12d, and the fifth face 12e and the sixth face 12f.

[0016] In addition, either the first surface 12a or the second surface 12b may have a roughened surface.

[0017] The laminate 12 includes a plurality of dielectric layers 14 and a plurality of internal electrodes 16. The dielectric layers 14 include an inner dielectric layer 14a and an outer dielectric layer 14b. The internal electrodes 16 include a first internal electrode 16a and a second internal electrode 16b.

[0018] The laminate 12 also has an inner layer portion 18, a first outer layer portion 20a located on the first surface 12a side, and a second outer layer portion 20b located on the second surface 12b side.

[0019] The first outer layer portion 20a is located on the first surface 12a side of the laminate 12 and is an aggregate of multiple outer dielectric layers 14b located between the first surface 12a and the internal electrode 16 closest to the first surface 12a.

[0020] The second outer layer portion 20b is located on the second surface 12b side of the laminate 12 and is an aggregate of multiple outer dielectric layers 14b located between the second surface 12b and the internal electrode 16 closest to the second surface 12b.

[0021] The region sandwiched between the first outer layer portion 20a and the second outer layer portion 20b is the inner layer portion 18.

[0022] The inner layer portion 18 has a first inner electrode 16a having one end exposed to the third surface 12c and the fifth surface 12e and the other end exposed to the fourth surface 12d and the sixth surface 12f, a second inner electrode 16b having one end exposed to the third surface 12c and the sixth surface 12f and the other end exposed to the fourth surface 12d and the fifth surface 12e, and an inner layer dielectric layer 14a.

[0023] The dielectric layer 14 can be formed from, for example, a dielectric material. Examples of the dielectric material include dielectric ceramics primarily composed of BaTiO3, CaTiO3, SrTiO3, or CaZrO3. Substituents such as Mn compounds, Fe compounds, Cr compounds, Co compounds, and Ni compounds may also be added to these primary components. The inner dielectric layer 14a and the outer dielectric layer 14b may be made of the same dielectric material, or may be made of different dielectric materials to separate the functions of the inner layer 18 and the outer layer 20a, 20b. At least one of Si, Mg, Ba, and Mn may also be added as an additive.

[0024] For example, if the inner dielectric layer 14a contains a large amount of CaTiO3 or CaZrO3 as a dielectric component, it can make it difficult for insulation breakdown to occur between the first inner electrode 16a and the second inner electrode 16b. Furthermore, without being limited to this, the inner dielectric layer 14a can also be mainly composed of SrTiO3 or the like. Separately, in order to increase the capacitance of the multilayer ceramic capacitor 10, it is preferable that the inner dielectric layer 14a be made of a material with a high dielectric constant, such as BaTiO3.

[0025] The dielectric layer 14 may have a plurality of crystal grains containing a perovskite-type compound having a basic structure of BaTiO3.

[0026] The thinner the dielectric layer 14, the greater the capacitance of the capacitor, so the crystal grain size is preferably 1 μm or less.

[0027] The number of dielectric layers 14 to be laminated is not particularly limited, but is preferably 3 to 300, including the first outer layer portion 20a and the second outer layer portion 20b. The thickness of the inner dielectric layer 14a is preferably 0.4 μm to 2.0 μm, and the thickness of the outer dielectric layer 14b is preferably 2.0 μm to 100.0 μm.

[0028] When the direction in which the third surface 12c and the fourth surface 12d face each other is defined as a first direction y and the direction in which the fifth surface 12e and the sixth surface 12f face each other is defined as a second direction z, the dimension L of the laminate 12 in the first direction y and the dimension W of the laminate 12 in the second direction z satisfy the condition 0.85≦L / W≦1.00. In other words, the laminate 12 includes a substantially tetragonal shape.

[0029] (Internal Electrode) The internal electrode 16 includes a plurality of first internal electrodes 16a and a plurality of second internal electrodes 16b. The first internal electrodes 16a and the second internal electrodes 16b are alternately stacked with the dielectric layer 14 interposed therebetween.

[0030] The first internal electrode 16a is disposed on the surface of the inner dielectric layer 14a. The first internal electrode 16a faces the first surface 12a and the second surface 12b, has a first opposing electrode portion 22a facing the second internal electrode 16b, and is laminated in the direction connecting the first surface 12a and the second surface 12b.

[0031] The first internal electrode 16a is extended to the third surface 12c and the fifth surface 12e of the laminate 12 by a first extension electrode portion 24a, and is extended to the fourth surface 12d and the sixth surface 12f of the laminate 12 by a second extension electrode portion 24b. The width of the first extension electrode portion 24a extended to the third surface 12c may be approximately equal to the width of the first extension electrode portion 24a extended to the fifth surface 12e, and the width of the second extension electrode portion 24b extended to the fourth surface 12d may be approximately equal to the width of the second extension electrode portion 24b extended to the sixth surface 12f.

[0032] Furthermore, the first internal electrode 16a is continuously extended to the third surface 12c and the fifth surface 12e of the laminate 12 by the first extension electrode portion 24a, and is continuously extended to the fourth surface 12d and the sixth surface 12f of the laminate 12 by the second extension electrode portion 24b, but this is not limited to this and the electrode may be extended discontinuously.

[0033] The second internal electrode 16b is disposed on a surface of the inner dielectric layer 14a different from the surface of the inner dielectric layer 14a on which the first internal electrode 16a is disposed. The second internal electrode 16b faces the first surface 12a and the second surface 12b, has a second opposing electrode portion 22b facing the first internal electrode 16a, and is laminated in a direction connecting the first surface 12a and the second surface 12b.

[0034] The second internal electrode 16b is extended to the third surface 12c and the sixth surface 12f of the laminate 12 by the third extension electrode portion 24c, and is extended to the fourth surface 12d and the fifth surface 12e of the laminate 12 by the fourth extension electrode portion 24d. The width of the third extension electrode portion 24c extended to the third surface 12c may be approximately equal to the width of the third extension electrode portion 24c extended to the sixth surface 12f, and the width of the fourth extension electrode portion 24d extended to the fourth surface 12d may be approximately equal to the width of the fourth extension electrode portion 24d extended to the fifth surface 12e.

[0035] Furthermore, the second internal electrode 16b is continuously extended to the third surface 12c and the sixth surface 12f of the laminate 12 by the third extension electrode portion 24c, and is continuously extended to the fourth surface 12d and the fifth surface 12e of the laminate 12 by the fourth extension electrode portion 24d, but this is not limited to this and the second internal electrode 16b may be extended discontinuously.

[0036] Furthermore, when the multilayer ceramic capacitor 10 is viewed from the stacking direction x, it is preferable that a straight line connecting the first extraction electrode portion 24a and the second extraction electrode portion 24b of the first internal electrode 16a intersects with a straight line connecting the third extraction electrode portion 24c and the fourth extraction electrode portion 24d of the second internal electrode 16b.

[0037] As shown in FIG. 7 , the laminate 12 also includes a side portion (W gap) 26 a of the laminate 12 located between one end in the first direction y of the second opposing electrode portion 22 b of the second internal electrode 16 b and the third surface 12 c, and a side portion (W gap) 26 b of the laminate 12 located between the other end in the first direction y of the first opposing electrode portion 22 a of the first internal electrode 16 a and the fourth surface 12 d.

[0038] Furthermore, as shown in FIG. 6 , the laminate 12 includes an end portion (L gap) 27 a of the laminate 12 located between one end in the second direction z of the second opposing electrode portion 22 b of the second internal electrode 16 b and the fifth surface 12 e, and a side portion (L gap) 27 b of the laminate 12 located between the other end in the second direction z of the first opposing electrode portion 22 a of the first internal electrode 16 a and the sixth surface 12 f.

[0039] 8A and 8B , when viewed in the stacking direction x, the region surrounded by the third surface 12c, the first internal electrode 16a, and the second internal electrode 16b is defined as the first region A1. The dimension a1 of the first region A1 in the first direction y is 5 μm or more, and the dimension b1 in the second direction z is 70 μm or more. This ensures a predetermined size for the region surrounded by the internal electrode 16 and the third surface 12c excluding both main surfaces 12a and 12b. This ensures a sufficient distance from the outside to the internal electrode 16, thereby suppressing moisture penetration from the outside and minimizing deterioration of insulation resistance. The dimension a1 in the first direction y is the length from the third surface 12c to the closest point, and the dimension b1 in the second direction z is the shortest distance between the internal electrodes 16. In other words, if the internal electrodes 16 are arranged at an angle with respect to the third surface 12c, the straight line connecting the internal electrodes 16 that forms the shortest distance between them for measuring the dimension b1 in the second direction z will not be completely parallel to the second direction z, but will be approximately parallel.

[0040] 8A and 8B , when viewed in the stacking direction x, the region surrounded by the fourth surface 12d, the first internal electrode 16a, and the second internal electrode 16b is defined as a second region A2, and the area ratio of the area of ​​the second region A2 to the area of ​​the first region A1 is preferably 40% or more. In this case, it is preferable that the dimension a2 of the second region A2 in the first direction y is 5 μm or more, and the dimension b2 in the second direction z is 70 μm or more.

[0041] Furthermore, when viewed in the stacking direction x, the region surrounded by the fifth surface 12 e, the first internal electrode 16 a, and the second internal electrode 16 b is defined as a third region A3, and the region surrounded by the sixth surface 12 f, the first internal electrode 16 a, and the second internal electrode 16 b is defined as a fourth region A4, it is more preferable that the area ratio of the smallest region to the largest region among the areas of the first region A1 to the fourth region A4 is 40% or more. In this case, it is preferable that the dimension c1 of the third region A3 in the second direction z is 5 μm or more and the dimension d1 in the first direction y is 70 μm or more, and it is preferable that the dimension c2 of the fourth region A4 in the second direction z is 5 μm or more and the dimension d2 in the first direction y is 70 μm or more.

[0042] The first region A1 has a plurality of voids 40 where no ceramic is present. The ratio of the total void area to the total area of ​​the first region A1 is preferably 2% or less. This ensures the denseness of the laminate 12, thereby further suppressing the intrusion of moisture from the outside and reducing deterioration of insulation resistance. Similarly, the second region A2 to the fourth region A4 have a plurality of voids 40 where no ceramic is present. The ratio of the total void area to the total area of ​​the second region A2 is preferably 2% or less, the ratio of the total void area to the total area of ​​the third region A3 is preferably 2% or less, and the ratio of the total void area to the total area of ​​the fourth region A4 is preferably 2% or less.

[0043] The porosity is calculated as follows. First, the cross section is polished so that it is approximately parallel to the polished surface up to a length of 1 / 2T in the stacking direction x connecting the first surface 12a and the second surface 12b. Then, using image analysis software, the ratio of the total area of ​​voids to the total area of ​​the first region A1 is measured on the polished cross section surface to calculate the porosity. The porosity in the second region A2 to the fourth region A4 can also be calculated in the same way.

[0044] The first internal electrode 16a and the second internal electrode 16b can be made of an appropriate conductive material, such as, for example, metals such as Ni, Cu, Ag, Pd, and Au, or alloys containing at least one of these metals, such as Ni-Cu alloys and Ag-Pd alloys, but are not limited thereto. Furthermore, the first internal electrode 16a and the second internal electrode 16b may be made of the same conductive material or different conductive materials.

[0045] In addition, by including a Sn layer between the first internal electrode 16a and the second internal electrode 16b and the inner dielectric layer 14a, electric field concentration at the interface between the internal electrode 16 and the dielectric layer 14 can be alleviated, leading to improved high-temperature load reliability.

[0046] The total number of the first internal electrodes 16a and the second internal electrodes 16b is preferably 3 to 300. The thickness of the first internal electrodes 16a and the second internal electrodes 16b is not particularly limited, but is preferably 0.2 μm to 2.0 μm, for example.

[0047] The laminate 12 of the multilayer ceramic capacitor 10 may have the following configuration.

[0048] In the multilayer ceramic capacitor 10, the third surface 12c to the sixth surface 12f of the laminate 12 may be curved so as to form a concave shape toward the center of the laminate 12 when viewed in the stacking direction x. In other words, the third surface 12c to the sixth surface 12f of the laminate 12 may have a warped shape. In this case, it is preferable that the center of the curvature or warpage is near the center of the third surface 12c to the sixth surface 12f. This allows the distance between adjacent external electrodes 30, which will be described later, to be increased, thereby reducing the risk of electrical conduction between the external electrodes 30.

[0049] Furthermore, when viewed in at least one of the first direction y and the second direction z, the regions where the internal electrodes 16 are drawn out onto the third surface 12c to the sixth surface 12f preferably have a curved shape from the first surface 12a to the second surface 12b, thereby increasing the exposed area of ​​the internal electrodes 16 and improving the contact area between the internal electrodes 16 and the external electrodes 30.

[0050] 1 to 7, external electrodes 30 are arranged on the laminate 12. The external electrodes 30 include a plurality of external electrodes 30 connected to the first internal electrodes 16a and the second internal electrodes 16b. The external electrodes 30 include a first external electrode 30a, a second external electrode 30b, a third external electrode 30c, and a fourth external electrode 30d.

[0051] The first external electrode 30a is disposed on the third surface 12c and the fifth surface 12e so as to cover the first lead electrode portion 24a of the first internal electrode 16a, and further so as to cover a part of the first surface 12a and a part of the second surface 12b. The first external electrode 30a is electrically connected to the first lead electrode portion 24a of the first internal electrode 16a.

[0052] The second external electrode 30b is disposed on the fourth surface 12d and the sixth surface 12f so as to cover the second lead electrode portion 24b of the first internal electrode 16a, and further so as to cover a part of the first surface 12a and a part of the second surface 12b. The second external electrode 30b is electrically connected to the second lead electrode portion 24b of the first internal electrode 16a.

[0053] The third external electrode 30c is disposed on the third surface 12c and the sixth surface 12f so as to cover the third lead electrode portion 24c of the second internal electrode 16b, and further so as to cover a part of the first surface 12a and a part of the second surface 12b. The third external electrode 30c is electrically connected to the third lead electrode portion 24c of the second internal electrode 16b.

[0054] The fourth external electrode 30d is disposed on the fourth surface 12d and the fifth surface 12e so as to cover the fourth lead electrode portion 24d of the second internal electrode 16b, and further so as to cover a part of the first surface 12a and a part of the second surface 12b. The fourth external electrode 30d is electrically connected to the fourth lead electrode portion 24d of the second internal electrode 16b.

[0055] In the laminate 12, the first opposing electrode portion 22a of the first internal electrode 16a and the second opposing electrode portion 22b of the second internal electrode 16b face each other via the inner dielectric layer 14a, thereby forming a capacitance. Therefore, a capacitance can be obtained between the first external electrode 30a and the second external electrode 30b to which the first internal electrode 16a is connected and the third external electrode 30c and the fourth external electrode 30d to which the second internal electrode 16b is connected, thereby realizing the characteristics of a capacitor.

[0056] Each of the first external electrode 30a, the second external electrode 30b, the third external electrode 30c and the fourth external electrode 30d preferably has a thin film layer 32, an underlayer plating layer 34 and a surface plating layer 36.

[0057] In other words, the first external electrode 30a preferably has a first thin film layer 32a, a first underlayer plating layer 34a, and a first surface plating layer 36a. The second external electrode 30b preferably has a second thin film layer 32b, a second underlayer plating layer 34b, and a second surface plating layer 36b. The third external electrode 30c preferably has a third thin film layer 32c, a third underlayer plating layer 34c, and a third surface plating layer 36c. The fourth external electrode 30d preferably has a fourth thin film layer 32d, a fourth underlayer plating layer 34d, and a fourth surface plating layer 36d.

[0058] (Thin Film Layers) The thin film layers 32 include a first thin film layer 32a, a second thin film layer 32b, a third thin film layer 32c, and a fourth thin film layer 32d.

[0059] The first thin film layer 32a is arranged so as to cover a portion of the first surface 12a and the second surface 12b of the laminate 12 on the third surface 12c side and the fifth surface 12e side, and not to cover the third surface 12c and the fifth surface 12e of the laminate 12.

[0060] The second thin film layer 32b is arranged so as to cover a portion of the first surface 12a and the second surface 12b of the laminate 12 on the fourth surface 12d side and the sixth surface 12f side, and not to cover the fourth surface 12d and the sixth surface 12f.

[0061] The third thin film layer 32c is arranged so as to cover a portion of the first surface 12a and the second surface 12b of the laminate 12 on the third surface 12c side and the sixth surface 12f side, and not to cover the third surface 12c and the sixth surface 12f.

[0062] The fourth thin film layer 32d is arranged so as to cover a portion of the first surface 12a and the second surface 12b of the laminate 12 on the fourth surface 12d side and the fifth surface 12e side, and not to cover the fourth surface 12d and the fifth surface 12e.

[0063] Each of the first to fourth thin film layers 32 a to 32 d is preferably formed by depositing metal particles by sputtering, vapor deposition, etc. This allows the thickness of the first to fourth thin film layers 32 a to 32 d in the direction connecting the first surface 12 a and the second surface 12 b of the laminate 12 to be 1 μm or less, and the dimension of the multilayer ceramic capacitor 10 in the stacking direction x can be sufficiently reduced, thereby making it possible to reduce the height of the multilayer ceramic capacitor 10.

[0064] The dimensions of the first to fourth thin film layers 32 a to 32 d in the stacking direction x can be measured as follows. That is, when the thin film layers are formed by depositing metal particles, a fluorescent X-ray device can be used to convert the concentration of a predetermined element into a thickness using a calibration curve method for the corresponding metal species. Alternatively, a cross section of a component can be observed using an FIB with a scanning microscope, and the thickness can be measured from the actual observation image.

[0065] Furthermore, when the first to fourth thin film layers 32a to 32d are formed by a thin film forming method, these thin film layers are preferably made of a metal such as Cu or Ni.

[0066] The thin film layers 32 of the multilayer ceramic capacitor 10 shown in Fig. 1 are formed by depositing metal particles by sputtering. In this case, if the thickness of the thin film layers 32 is 1 µm or less, the dimension in the stacking direction x can be made sufficiently small.

[0067] The first to fourth thin film layers 32a to 32d can be configured taking into consideration their respective functions. For example, it is preferable that the main component be NiCr or NiCu in consideration of adhesion to the laminate 12. The first to fourth thin film layers 32a to 32d may be multiple layers or may have a two-layer structure of NiCr and NiCu.

[0068] The thin film layer 32 may be formed by screen printing or the like and contain a dielectric material and a metal component. This allows the thin film layer 32 to adhere to the ceramic of the laminate 12, further improving the adhesion between the laminate 12 and the external electrode 30. In this case, the thin film layer 32 may contain a ceramic component having the same main component as the inner dielectric layer 14a in addition to the metal component. The inclusion of a ceramic component in the thin film layer 32 reduces the difference in thermal expansion coefficient between the laminate 12 and the thin film layer 32, thereby alleviating stress on the thin film layer 32. However, the metal component may be other metal components besides Cu and Ni, or may contain a glass component in addition to the ceramic component. Examples of the glass component include oxides of Ba (barium), Sr (strontium), Si (silicon), Ca (calcium), Zn, Al, or B (boron). Other metal components may include, for example, Mg, Cr, Sr, Al, Na, or Fe. The thin film layer 32 may also have a discontinuous shape. The term "discontinuous" means that the film is formed discontinuously when viewed in a direction perpendicular to the longitudinal direction.

[0069] For example, when the thin film layer 32 is formed using a material containing ceramic, one method is to polish the cross section, then take a cross section photograph using a digital microscope (Keyence Corporation: VHX-5000), and use the cross section photograph to calculate the thickness, etc. Another method is to measure the thickness, etc. from the actual observation image of the cross section of the part taken by FIB using a scanning microscope.

[0070] (Underlayer Plating Layer) The underlayer plating layer 34 includes a first underlayer plating layer 34a, a second underlayer plating layer 34b, a third underlayer plating layer 34c, and a fourth underlayer plating layer 34d.

[0071] The first underlayer plating layer 34a is disposed so as to cover the first thin film layer 32a and the third and fifth surfaces 12c, 12e of the laminate 12. The second underlayer plating layer 34b is disposed so as to cover the second thin film layer 32b and the fourth and sixth surfaces 12d, 12f of the laminate 12. The third underlayer plating layer 34c is disposed so as to cover the third thin film layer 32c and the third and sixth surfaces 12c, 12f of the laminate 12. The fourth underlayer plating layer 34d is disposed so as to cover the fourth thin film layer 32d and the fourth and fifth surfaces 12d, 12e of the laminate 12.

[0072] The lower plating layer 34 contains at least one selected from, for example, Cu, Ni, Sn, Ag, Pd, an Ag-Pd alloy, Au, etc. The lower plating layer 34 is preferably Cu plating. In this case, the lower plating layer 34 may be directly connected to the internal electrode 16. In addition to this, another Cu plating layer with a different particle size may be provided.

[0073] The thickness of the lower plating layer 34 is preferably, for example, 1 μm or more and 10 μm or less.

[0074] (Surface Plating Layer) The surface plating layer 36 includes a first surface plating layer 36a, a second surface plating layer 36b, a third surface plating layer 36c, and a fourth surface plating layer 36d.

[0075] The first surface plating layer 36a is disposed so as to cover the first underlayer plating layer 34a. The second surface plating layer 36b is disposed so as to cover the second underlayer plating layer 34b. The third surface plating layer 36c is disposed so as to cover the third underlayer plating layer 34c. The fourth surface plating layer 36d is disposed so as to cover the fourth underlayer plating layer 34d.

[0076] The surface plating layer 36 may be, for example, only Sn plating, or may have a two-layer structure of Ni plating, Sn plating, or Ni plating and Cu plating.

[0077] The thickness of the surface plating layer 36 is preferably, for example, not less than 0.5 μm and not more than 10 μm.

[0078] The plating layer may be composed of only the lower plating layer 34. In this case, the first lower plating layer 34a is disposed so as to cover the first thin film layer 32a, and the second lower plating layer 34b is disposed so as to cover the second thin film layer 32b. Similarly, the third lower plating layer 34c is disposed so as to cover the third thin film layer 32c, and the fourth lower plating layer 34d is disposed so as to cover the fourth thin film layer 32d.

[0079] The plating layer preferably contains at least one metal selected from Cu, Ni, Sn, Pb, Au, Ag, Pd, Bi, Zn, etc., or an alloy containing such a metal. The plating layer preferably does not contain glass.

[0080] The metal content per unit volume of the plating layer is preferably 99% by volume or more.

[0081] The thickness of each plating layer is preferably 0.5 μm or more and 10.0 μm or less.

[0082] The dimension of the multilayer ceramic capacitor 10 including the laminate 12 and the external electrodes 30 in the first direction y is defined as dimension L, the dimension of the multilayer ceramic capacitor 10 including the laminate 12 and the external electrodes 30 in the stacking direction x is defined as dimension T, and the dimension of the multilayer ceramic capacitor 10 including the laminate 12 and the external electrodes 30 in the second direction z is defined as dimension W. The dimensions of the multilayer ceramic capacitor 10 are preferably such that the L dimension in the first direction y is 0.2 mm or more and 3.2 mm or less, the T dimension in the stacking direction x is 0.04 mm or more and 0.22 mm or less, and the W dimension in the second direction z is 0.2 mm or more and 3.2 mm or less. The dimensions of the multilayer ceramic capacitor 10 preferably satisfy the relationship 0.85≦L / W≦1.00. This allows the laminate 12 to have a substantially tetragonal shape, thereby improving the flexibility of mounting.

[0083] 1 , the dimension L in the first direction y and the dimension W in the second direction z of the laminate 12 satisfy the condition of 0.85≦L / W≦1.00, and when the region surrounded by the third surface 12c, the first internal electrode 16a, and the second internal electrode 16b as viewed in the stacking direction x is defined as a first region A1, the dimension a1 in the first direction y of the first region A1 is 5 μm or more, and the dimension b1 in the second direction z is 70 μm or more. As a result, when viewed in the stacking direction x, the region surrounded by the internal electrode 16 and the third surface 12c excluding both main surfaces 12a, 12b can be ensured to have a predetermined size, and therefore the distance from the outside to the internal electrode 16 can be ensured, which can suppress the penetration of moisture from the outside and reduce deterioration of the insulation resistance.

[0084] 2. Modifications (1) First Modification Next, an example of a multilayer ceramic capacitor 10A according to a first modification of the first embodiment of the present invention will be described. Fig. 10 is a cross-sectional schematic diagram showing an example of a multilayer ceramic capacitor according to a first modification of the first embodiment of the present invention. However, the same reference numerals are used to designate the same or corresponding components as those in Figs. 1 to 7, and detailed descriptions thereof will be omitted.

[0085] As shown in FIG. 10, in the multilayer ceramic capacitor 10A according to the first modification, the thin film layers 32 are formed so as to extend around to each side surface of the laminate 12.

[0086] Specifically, the first thin film layer 32a of the first external electrode 30a covers a portion of the first surface 12a and the second surface 12b, and is formed around the first surface 12a and the second surface 12b to cover the third surface 12c and the fifth surface 12e. The second thin film layer 32b of the second external electrode 30b covers a portion of the first surface 12a and the second surface 12b, and is formed around the first surface 12a and the second surface 12b to cover the fourth surface 12d and the sixth surface 12f. Although not shown, the same applies to the third thin film layer 32c of the third external electrode 30c and the fourth thin film layer 32d of the fourth external electrode 30d.

[0087] The first thin film layer 32a is directly electrically connected to the first lead electrode portion 24a of the first internal electrode 16a exposed from the third surface 12c and the fifth surface 12e. The second thin film layer 32b is directly electrically connected to the second lead electrode portion 24b of the first internal electrode 16a exposed from the fourth surface 12d and the sixth surface 12f. Although not shown, the third thin film layer 32c is directly electrically connected to the third lead electrode portion 24c of the second internal electrode 16b, and the fourth thin film layer 32d is directly electrically connected to the fourth lead electrode portion 24d of the second internal electrode 16b.

[0088] The first thin film layer 32a may be formed so that the thin film layers formed on the first surface 12a and the second surface 12b are continuously connected to the thin film layers formed on the third surface 12c and the fifth surface 12e, or may be formed discontinuously. The second thin film layer 32b may be formed so that the thin film layers formed on the first surface 12a and the second surface 12b are continuously connected to the thin film layers formed on the fourth surface 12d and the sixth surface 12f, or may be formed discontinuously. The same applies to the third thin film layer 32c of the third external electrode 30c and the fourth thin film layer 32d of the fourth external electrode 30d.

[0089] The multilayer ceramic capacitor 10A according to the first embodiment shown in FIG. 10 has the same effects as the multilayer ceramic capacitor 10 described above.

[0090] (2) Second Modification Next, an example of a multilayer ceramic capacitor 10B according to a second modification of the first embodiment of the present invention will be described. Fig. 11 is a schematic cross-sectional view showing an example of a multilayer ceramic capacitor according to the second modification of the first embodiment of the present invention. However, the same reference numerals are used to designate the same or corresponding components as those in Figs. 1 to 7, and detailed descriptions thereof will be omitted.

[0091] As shown in FIG. 11, the external electrodes 30 of the multilayer ceramic capacitor 10B according to the second modified example of the first embodiment include a direct plating layer 33.

[0092] (Direct Plated Layer) The first external electrode 30a includes a first direct plated layer 33a, the second external electrode 30b includes a second direct plated layer 33b, and although not shown, the third external electrode 30c includes a third direct plated layer, and the fourth external electrode 30d includes a fourth direct plated layer.

[0093] The first direct plating layer 33a is arranged to cover a portion of each of the third surface 12c and the fifth surface 12e of the laminate 12, as well as the ridge line sandwiched therebetween. The first direct plating layer 33a is electrically and directly connected to the first lead electrode portion 24a of the first internal electrode 16a. The second direct plating layer 33b is arranged to cover a portion of each of the fourth surface 12d and the sixth surface 12f of the laminate 12, as well as the ridge line sandwiched therebetween. The second direct plating layer 33b is electrically and directly connected to the second lead electrode portion 24b of the first internal electrode 16a. Although not shown, the same applies to the third direct plating layer of the third external electrode 30c and the fourth direct plating layer of the fourth external electrode 30d.

[0094] The upper end of the first direct plating layer 33a of the first external electrode 30a is preferably arranged so as to overlap the underside of the first thin film layer 32a on the ridge formed by the first surface 12a, the third surface 12c, and the fifth surface 12e of the laminate 12. The upper end of the second direct plating layer 33b of the second external electrode 30b is preferably arranged so as to overlap the underside of the second thin film layer 32b on the ridge formed by the first surface 12a, the fourth surface 12d, and the sixth surface 12f of the laminate 12. Although not shown, the same applies to the third direct plating layer of the third external electrode 30c and the fourth direct plating layer of the fourth external electrode 30d.

[0095] A portion of the first direct plating layer 33 a may be disposed so as to wrap around to the second surface 12 b, and a portion of the second direct plating layer 33 b may be disposed so as to wrap around to the second surface 12 b. Also, a portion of the third direct plating layer and a portion of the fourth direct plating layer may be disposed so as to wrap around to the second surface 12 b.

[0096] The upper ends of the first and second direct plating layers 33 a and 33 b may be spaced apart from the first and second thin film layers 32 a and 32 b, respectively. The upper ends of the third and fourth direct plating layers may be spaced apart from the third and fourth thin film layers 32 c and 32 d, respectively.

[0097] The direct plating layer 33 is not particularly limited as long as it contains, as a main metal component, at least one metal selected from, for example, Cu, Ni, Ag, Pd, an Ag—Pd alloy, Au, etc. For example, when the first internal electrode 16 a and the second internal electrode 16 b are formed using Ni, it is preferable to adopt Cu plating as the direct plating layer 33, which has good bonding properties with Ni.

[0098] The direct plating layer 33 is formed by plating growing from the internal electrode 16 .

[0099] The thickness of each direct plating layer 33 is preferably 0.5 μm or more and 10.0 μm or less.

[0100] 11 according to the first embodiment, the multilayer ceramic capacitor 10B has the same effects as the above-described multilayer ceramic capacitor 10. That is, by forming the plating layer 33 directly on each side surface of the laminate 12, the thickness in the lamination direction of the external electrodes 30 formed on the first surface 12a and the second surface 12b can be further reduced, and therefore a multilayer ceramic capacitor with an even lower profile can be provided without impairing mountability during mounting.

[0101] (3) Third Modification Next, a multilayer ceramic capacitor 10C according to a third modification of the first embodiment of the present invention will be described. Fig. 12 is a schematic cross-sectional view showing an example of a multilayer ceramic capacitor according to the third modification of the first embodiment of the present invention. However, the same reference numerals are used to designate the same or corresponding components as those in Figs. 1 to 7, and detailed descriptions thereof will be omitted.

[0102] The external electrodes 30 of the multilayer ceramic capacitor 10C according to the third modification do not include a plating layer and are composed of a plurality of thin film layers. In the multilayer ceramic capacitor 10C shown in Fig. 12, the first external electrode 30a does not include a plating layer and is composed of only four thin film layers 32a1 to 32a4, and the second external electrode 30b does not include a plating layer and is composed of only four thin film layers 32b1 to 32b4.

[0103] In the first external electrode 30a, the thin film layer 32a is formed so as to wrap around from the first surface 12a to the third surface 12c and the fifth surface 12e. Then, thin film layers 32a2, 32a3, and 32a4 are formed in this order on the surface of the thin film layer 32a1. In the second external electrode 30b, the thin film layer 32b1 is formed so as to wrap around from the first surface 12a to the fourth surface 12d and the sixth surface 12f. Then, thin film layers 32b2, 32b3, and 32b4 are formed in this order on the surface of the thin film layer 32b1. Although not shown, the same applies to the third thin film layer 32c of the third external electrode 30c and the fourth thin film layer 32d of the fourth external electrode 30d.

[0104] In the first external electrode 30a, the edge portions of the laminate 12 made up of the four thin film layers 32a1 to 32a4 near the center may or may not be formed to cover the corresponding edge portions of the lower layers. Similarly, in the second external electrode 30b, the edge portions of the laminate 12 made up of the four thin film layers 32b1 to 32b4 near the center may or may not be formed to cover the corresponding edge portions of the lower layers. Although not shown, the same applies to the third thin film layer 32c of the third external electrode 30c and the fourth thin film layer 32d of the fourth external electrode 30d.

[0105] 12 according to the first embodiment, the multilayer ceramic capacitor 10C has the same effects as the multilayer ceramic capacitor 10 described above, and also has the following effect: The multilayer ceramic capacitor 10C does not include a plating layer, and the first external electrode 30a is composed only of thin film layers 32a1 to 32a4, the second external electrode 30b is composed only of thin film layers 32b1 to 32b4, and the third external electrode 30c and the fourth external electrode 30d also have a similar configuration, which reduces the T dimension in the stacking direction x, the L dimension in the first direction y, and the W dimension in the second direction z, thereby making it possible to reduce the dimensions of the multilayer ceramic capacitor.

[0106] 3. Method for Manufacturing a Multilayer Ceramic Capacitor A method for manufacturing a multilayer ceramic capacitor according to the first embodiment will now be described.

[0107] First, a dielectric sheet and a conductive paste for the internal electrodes are prepared. The conductive paste for the dielectric sheet and the internal electrodes contains a binder and a solvent. Known binders and solvents can be used.

[0108] Next, a conductive paste for the internal electrodes is printed in a predetermined pattern on the dielectric sheet by, for example, inkjet printing, screen printing, gravure printing, etc. This prepares a dielectric sheet on which the pattern of the first internal electrode is formed and a dielectric sheet on which the pattern of the second internal electrode is formed. Thereafter, the sheet on which the pattern of the first internal electrode is printed and the sheet on which the pattern of the second internal electrode is printed are laminated together to form the portion that becomes the inner layer portion 18.

[0109] Next, a predetermined number of dielectric sheets not printed with an internal electrode pattern are stacked to form the portion that will become the first outer layer portion 20a on the first surface 12a. After that, the portion that will become the inner layer portion 18 prepared above is stacked, and a predetermined number of dielectric sheets not printed with an internal electrode pattern are stacked on top of this portion that will become the inner layer portion 18 to form the portion that will become the second outer layer portion 20b on the second surface 12b. In this way, a laminated sheet is produced.

[0110] Next, the laminated sheet is pressed in the lamination direction by means of a hydrostatic press or the like to produce a laminated block.

[0111] The laminated block is then cut to a predetermined size to cut out laminated chips, the corners and ridges of which may be rounded by barrel polishing or the like.

[0112] Next, the laminated chip is fired to produce the laminate 12. The firing temperature depends on the ceramic and internal electrode materials, but is preferably 900° C. or higher and 1400° C. or lower.

[0113] Subsequently, external electrodes 30 are formed on the laminate 12. That is, the obtained laminate 12 is aligned on a work table, and thin film layers 32 are formed on the first surface 12a and the second surface 12b by sputtering.

[0114] Thereafter, an underlayer plating layer 34 is formed on the thin film layer 32 and the surface of the laminate 12, and a surface plating layer 36 is formed to cover the underlayer plating layer 34. More specifically, a Cu plating layer is formed on the thin film layer 32 as the underlayer plating layer 34. Then, a Ni plating layer and an Sn plating layer are formed on the surface of the underlayer plating layer 34 as the surface plating layer 36. Either electrolytic plating or electroless plating may be used for the plating process. However, electroless plating has the disadvantage of requiring pretreatment using a catalyst or the like to improve the plating deposition rate, which complicates the process. Therefore, it is usually preferable to use electrolytic plating.

[0115] In this manner, the multilayer ceramic capacitor 10 according to the embodiment shown in Fig. 1 can be manufactured. When manufacturing the multilayer ceramic capacitor 10A of the first modified example shown in Fig. 10, the multilayer ceramic capacitor 10B of the second modified example shown in Fig. 11, and the multilayer ceramic capacitor 10B of the third modified example shown in Fig. 12, the shapes of the corresponding portions are made different in each process as appropriate.

[0116] B. Second Embodiment 1. Multilayer Ceramic Capacitor An example of a multilayer ceramic capacitor 110 according to a second embodiment of the present invention will now be described.

[0117] FIG. 13 is an external perspective view showing an example of a multilayer ceramic capacitor according to a second embodiment of the present invention. FIG. 14 is a front view showing an example of a multilayer ceramic capacitor according to the second embodiment of the present invention. FIG. 15 is a cross-sectional view taken along line XV-XV in FIG. 13 , illustrating the structure of an example of a multilayer ceramic capacitor according to the second embodiment of the present invention. FIG. 16 is a cross-sectional view taken along line XVI-XVI in FIG. 13 . FIG. 17 is a cross-sectional view taken along line XVII-XVII in FIG. 13 . FIG. 18 is a cross-sectional view taken along line XVIII-XVIII in FIG. 13 . FIG. 19A is a cross-sectional view taken along line XIXA-XIXA in FIG. 14 . FIG. 19B is a cross-sectional view taken along line XIXB-XIXB in FIG. 14 . FIG. 20 is an exploded perspective view of the laminate shown in FIG. 13 . Note that components that are the same as or correspond to those in FIGS. 1 to 7 are designated by the same reference numerals, and detailed description thereof will be omitted.

[0118] The multilayer ceramic capacitor 110 includes a laminate 112 and external electrodes 130 .

[0119] (Laminate) The laminate 12 includes a plurality of dielectric layers 114 and a plurality of internal electrodes 116. The dielectric layers 114 include an inner dielectric layer 114a and an outer dielectric layer 114b. The internal electrodes 116 include a first internal electrode 116a and a second internal electrode 116b.

[0120] The laminate 112 also has an inner layer portion 118, a first outer layer portion 120a located on the first surface 112a side, and a second outer layer portion 120b located on the second surface 112b side.

[0121] The first outer layer portion 120a is located on the first surface 112a side of the laminate 112 and is an aggregate of multiple outer layer dielectric layers 114b located between the first surface 112a and the internal electrode 116 closest to the first surface 112a.

[0122] The second outer layer portion 120b is located on the second surface 112b side of the laminate 112 and is an aggregate of multiple outer layer dielectric layers 114b located between the second surface 112b and the internal electrode 116 closest to the second surface 112b.

[0123] The region sandwiched between the first outer layer portion 120 a and the second outer layer portion 120 b is the inner layer portion 118 .

[0124] The inner layer portion 118 has a first inner electrode 116a having one end exposed to the third surface 112c and the other end exposed to the fourth surface 112d, a second inner electrode 116b having one end exposed to the third surface 112c and the other end exposed to the fourth surface 112d, and an inner layer dielectric layer 114a.

[0125] The material of the dielectric layer 114 is the same as that of the dielectric layer 14, and therefore a description thereof will be omitted.

[0126] (Internal Electrode) The internal electrode 116 includes a plurality of first internal electrodes 116a and a plurality of second internal electrodes 116b. The first internal electrodes 116a and the second internal electrodes 116b are alternately stacked with the dielectric layer 114 interposed therebetween.

[0127] The first internal electrode 116a is disposed on the surface of the inner dielectric layer 114a. The first internal electrode 116a faces the first surface 112a and the second surface 112b, has a first opposing electrode portion 122a facing the second internal electrode 116b, and is laminated in the direction connecting the first surface 112a and the second surface 112b.

[0128] The first internal electrode 116a is extended to the third surface 112c of the laminate 112 by a first extension electrode portion 124a, and is extended to the fourth surface 112d of the laminate 112 by a second extension electrode portion 124b. The first extension electrode portion 124a is extended to the fifth surface 112e of the laminate 112, and the second extension electrode portion 124b is extended to the sixth surface 112f of the laminate 112.

[0129] The second internal electrode 116b is disposed on a surface of the inner dielectric layer 114a different from the surface of the inner dielectric layer 114a on which the first internal electrode 116a is disposed. The second internal electrode 116b faces the first surface 112a and the second surface 112b, has a second opposing electrode portion 122b facing the first internal electrode 116a, and is laminated in a direction connecting the first surface 112a and the second surface 112b.

[0130] The second internal electrode 116b is extended to the third surface 112c of the laminate 12 by a third extension electrode portion 124c, and is extended to the fourth surface 112d of the laminate 112 by a fourth extension electrode portion 124d. The third extension electrode portion 124c is extended to the sixth surface 112f of the laminate 112, and the fourth extension electrode portion 124d is extended to the fifth surface 112e of the laminate 112.

[0131] The first internal electrode 116 a and the second internal electrode 116 b are not exposed on the fifth surface 112 e and the sixth surface 112 f of the laminate 112 .

[0132] Furthermore, when the multilayer ceramic capacitor 110 is viewed from the stacking direction x, it is preferable that a straight line connecting the first extraction electrode portion 124a and the second extraction electrode portion 124b of the first internal electrode 116a intersects with a straight line connecting the third extraction electrode portion 124c and the fourth extraction electrode portion 124d of the second internal electrode 116b.

[0133] Furthermore, on the surfaces 112c, 112d, 112e, and 112f of the laminate 112, it is preferable that the first extraction electrode portion 124a of the first internal electrode 116a and the fourth extraction electrode portion 124d of the second internal electrode 116b are extracted to opposing positions, and that the second extraction electrode portion 124b of the first internal electrode 116a and the third extraction electrode portion 124c of the second internal electrode 116b are extracted to opposing positions.

[0134] As shown in FIG. 18 , the laminate 112 also includes a side portion (W gap) 126a of the laminate 12 located between one end in the first direction y of the second opposing electrode portion 122b of the second internal electrode 116b and the third surface 112c, and a side portion (W gap) 126b of the laminate 112 located between the other end in the first direction y of the first opposing electrode portion 122a of the first internal electrode 116a and the fourth surface 112d.

[0135] Furthermore, as shown in FIG. 17 , the laminate 112 includes an end portion (L gap) 127a of the laminate 112 located between one end in the second direction z of the second opposing electrode portion 122b of the second internal electrode 116b and the fifth surface 112e, and a side portion (L gap) 127b of the laminate 112 located between the other end in the second direction z of the first opposing electrode portion 122a of the first internal electrode 116a and the sixth surface 112f.

[0136] 19A and 19B , when viewed in the stacking direction x, the region surrounded by the third surface 112c, the first internal electrode 116a, and the second internal electrode 116b is defined as the first region A1. The dimension a1 of the first region A1 in the first direction y is 5 μm or more, and the dimension b1 in the second direction z is 70 μm or more. This ensures a predetermined size for the region surrounded by the internal electrode 116 and the third surface 112c excluding both main surfaces 112a and 112b, as viewed in the stacking direction x. This ensures a sufficient distance from the outside to the internal electrode 116, thereby suppressing moisture penetration from the outside and minimizing deterioration of insulation resistance. The dimension a1 in the first direction y is the length from the third surface 112c to the closest point, and the dimension b1 in the second direction z is the shortest distance between the internal electrodes 116. In other words, if the internal electrodes 116 are arranged at an angle with respect to the third surface 112c, the straight line connecting the internal electrodes 16 that forms the shortest distance between them for measuring the dimension b1 in the second direction z will not be completely parallel to the second direction z, but will be approximately parallel.

[0137] 19A and 19B , when viewed from the stacking direction x, the area surrounded by the fourth surface 112d, the first internal electrode 116a, and the second internal electrode 116b is defined as a second region A2, and the area ratio of the area of ​​the second region A2 to the area of ​​the first region A1 is preferably 40% or more. In this case, it is preferable that the dimension a2 of the second region A2 in the first direction y is 5 μm or more, and the dimension b2 in the second direction z is 70 μm or more.

[0138] The first region A1 has a plurality of voids 40 where no ceramic is present. The ratio of the total area of ​​the voids to the total area of ​​the first region A1 is preferably 2% or less. Similarly, the second region A2 has a plurality of voids 40 where no ceramic is present. The ratio of the total area of ​​the voids to the total area of ​​the second region A2 is preferably 2% or less. This ensures the denseness of the laminate 112, thereby further suppressing the intrusion of moisture from the outside and reducing deterioration of insulation resistance.

[0139] 13 to 18, external electrodes 130 are arranged on the laminate 112. The external electrodes 130 include a plurality of external electrodes 130 connected to the first internal electrodes 116a and the second internal electrodes 116b. The external electrodes 130 include a first external electrode 130a, a second external electrode 130b, a third external electrode 130c, and a fourth external electrode 130d.

[0140] The first external electrode 130a is disposed on the third surface 112c so as to cover the first lead electrode portion 124a of the first internal electrode 116a, and further so as to cover a portion of the first surface 112a and a portion of the second surface 112b. The first external electrode 130a is electrically connected to the first lead electrode portion 124a of the first internal electrode 116a.

[0141] The second external electrode 130b is disposed on the fourth surface 112d so as to cover the second lead electrode portion 124b of the first internal electrode 116a, and further so as to cover a portion of the first surface 112a and a portion of the second surface 112b. The second external electrode 130b is electrically connected to the second lead electrode portion 124b of the first internal electrode 116a.

[0142] The third external electrode 130c is disposed on the third surface 112c so as to cover the third lead electrode portion 124c of the second internal electrode 116b, and further so as to cover a part of the first surface 112a and a part of the second surface 112b. The third external electrode 130c is electrically connected to the third lead electrode portion 124c of the second internal electrode 116b.

[0143] The fourth external electrode 130d is disposed on the fourth surface 112d so as to cover the fourth lead electrode portion 124d of the second internal electrode 116b, and further so as to cover a part of the first surface 112a and a part of the second surface 112b. The fourth external electrode 130d is electrically connected to the fourth lead electrode portion 124d of the second internal electrode 116b.

[0144] Furthermore, as shown in Figure 13, it is preferable that the external electrode 130 arranged on the fifth surface 112e or the sixth surface 112f from which the internal electrode 116 is not pulled out covers in a U-shape one of the short sides of the side surface from which the internal electrode 116 is not pulled out and the portion from the end of that short side to the middle of both long sides.

[0145] In the laminate 112, the first opposing electrode portion 122a of the first internal electrode 116a and the second opposing electrode portion 122b of the second internal electrode 116b face each other via the inner dielectric layer 114a, thereby forming a capacitance. Therefore, a capacitance can be obtained between the first external electrode 130a and the second external electrode 130b to which the first internal electrode 116a is connected and the third external electrode 130c and the fourth external electrode 130d to which the second internal electrode 116b is connected, thereby realizing the characteristics of a capacitor.

[0146] Each of the first external electrode 130 a , the second external electrode 130 b , the third external electrode 130 c and the fourth external electrode 130 d preferably has a thin film layer 132 , an underlayer plating layer 134 and a surface plating layer 136 .

[0147] The multilayer ceramic capacitor 110 shown in FIG. 13 has the same effects as the multilayer ceramic capacitor 10 according to the first embodiment.

[0148] The multilayer ceramic capacitor 110 according to the second embodiment of the present invention may also be combined with all or part of the first to third modified examples described above. Furthermore, it may also be combined with all or part of the first to third modified examples of the multilayer ceramic capacitor 10 according to the first embodiment, and with other modified examples shown in the respective drawings.

[0149] 2. Method for Manufacturing a Multilayer Ceramic Capacitor A method for manufacturing a multilayer ceramic capacitor according to a second embodiment will now be described.

[0150] First, a dielectric sheet and a conductive paste for the internal electrodes are prepared. The dielectric sheet, the conductive paste for the internal electrodes, and the conductive paste for the peripheral electrodes contain a binder and a solvent. Known binders and solvents can be used.

[0151] Next, a conductive paste for the internal electrodes is printed in a predetermined pattern on the dielectric sheet by, for example, inkjet printing, screen printing, gravure printing, etc. This prepares a dielectric sheet on which the pattern of the first internal electrode is formed and a dielectric sheet on which the pattern of the second internal electrode is formed. Thereafter, the sheet on which the pattern of the first internal electrode is printed and the sheet on which the pattern of the second internal electrode is printed are laminated together to form the portion that becomes the inner layer portion 18.

[0152] Next, a predetermined number of dielectric sheets without printed internal electrode patterns are stacked to form the portion that will become the first outer layer portion 120a on the first surface 112a. After that, the portion that will become the inner layer portion 118 prepared above is stacked, and a predetermined number of dielectric sheets without printed internal electrode patterns are stacked on top of this portion that will become the inner layer portion 118 to form the portion that will become the second outer layer portion 120b on the second surface 112b. In this way, a laminated sheet is produced.

[0153] Next, the laminated sheet is pressed in the lamination direction by means of a hydrostatic press or the like to produce a laminated block.

[0154] The laminated block is then cut to a predetermined size to cut out laminated chips, the corners and ridges of which may be rounded by barrel polishing or the like.

[0155] Next, the laminated chip is fired to produce the laminate 12. The firing temperature depends on the ceramic and internal electrode materials, but is preferably 900° C. or higher and 1400° C. or lower.

[0156] At this time, the first lead electrode portion 124a of the first internal electrode 116a and the third lead electrode portion 124c of the second internal electrode 116b are exposed from the third surface 112c of the laminate 112. Furthermore, the second lead electrode portion 124b of the first internal electrode 116a and the fourth lead electrode portion 124d of the second internal electrode 116b are exposed from the fourth surface 112d of the laminate 112.

[0157] Subsequently, external electrodes 130 are formed on the laminate 112. That is, the obtained laminate 112 is aligned on a work table, and thin film layers 132 are formed on the first surface 112a and the second surface 112b by sputtering.

[0158] Thereafter, an underlayer plating layer 134 is formed on the thin film layer 132 and the surface of the laminate 112, and a surface plating layer 136 is formed to cover the underlayer plating layer 134. More specifically, a Cu plating layer is formed on the thin film layer 132 as the underlayer plating layer 134. Then, a Ni plating layer and an Sn plating layer are formed on the surface of the underlayer plating layer 134 as the surface plating layer 136. Either electrolytic plating or electroless plating may be used for the plating process. However, electroless plating has the disadvantage of requiring pretreatment using a catalyst or the like to improve the plating deposition rate, which complicates the process. Therefore, it is usually preferable to use electrolytic plating.

[0159] At this time, the external electrode 130 arranged on the side surface from which the internal electrode 116 is not pulled out is formed in a U-shape by the underlayer plating layer 134 and the surface plating layer 136 so as to cover both short sides of the side surface from which the internal electrode 116 is not pulled out and the portions from the ends of both short sides to the middle parts of both long sides.

[0160] In this manner, a multilayer ceramic capacitor 110 as shown in FIG. 13 is manufactured.

[0161] C. Third Embodiment 1. Multilayer Ceramic Capacitor An example of a multilayer ceramic capacitor 210 according to a third embodiment of the present invention will now be described.

[0162] FIG. 21 is an external perspective view, seen from one side, of an example of a multilayer ceramic capacitor according to the third embodiment of the present invention. FIG. 22 is an external perspective view, seen from the other side, of an example of a multilayer ceramic capacitor according to the third embodiment of the present invention. FIG. 23 is a cross-sectional view taken along line XXIII-XXIII in FIG. 21. FIG. 24 is a cross-sectional view taken along line XXIV-XXIV in FIG. 21. FIG. 25 is a cross-sectional view taken along line XXV-XXV in FIG. 21. FIG. 26 is a cross-sectional view taken along line XXVI-XXVI in FIG. 21. Note that components that are the same as or equivalent to those in FIGS. 1 to 7 are designated by the same reference numerals, and detailed description thereof will be omitted.

[0163] The multilayer ceramic capacitor 210 includes a laminate 12 and a plurality of external electrodes 230 .

[0164] (Laminate) In the multilayer ceramic capacitor 210 according to the second embodiment, the laminate 12 has the same configuration as the laminate 12 according to the first embodiment of the present invention shown in FIG.

[0165] (Internal electrode) The first internal electrode 16a is extended to the third surface 12c and the fifth surface 12e of the laminate 12 by the first extension electrode portion 24a, and is extended to the fourth surface 12d and the sixth surface 12f of the laminate 12 by the second extension electrode portion 24b.

[0166] The second internal electrode 16b is extended to the third surface 12c and the sixth surface 12f of the laminate 12 by the third extension electrode portion 24c, and is extended to the fourth surface 12d and the fifth surface 12e of the laminate 12 by the fourth extension electrode portion 24d.

[0167] The configurations of the first region A1 to the fourth region A4 in the multilayer ceramic capacitor 210 according to the third embodiment are characterized in the same way as those in the multilayer ceramic capacitor 10 according to the first embodiment.

[0168] (External Electrodes) In the multilayer ceramic capacitor 210 according to the third embodiment, the external electrodes 230 are arranged so as to cover the first surface 12a of the laminate 12 but not the second surface 12b.

[0169] 21 to 26, external electrodes 230 are arranged on the laminate 12. The external electrodes 230 include a plurality of external electrodes 230 connected to the first internal electrodes 16a and the second internal electrodes 16b. The external electrodes 230 include a first external electrode 230a, a second external electrode 230b, a third external electrode 230c, and a fourth external electrode 230d.

[0170] The first external electrode 230a is disposed on the third surface 12c and the fifth surface 12e so as to cover the first lead electrode portion 24a of the first internal electrode 16a, and further so as to cover a portion of the first surface 12a. The first external electrode 230a is electrically connected to the first lead electrode portion 24a of the first internal electrode 16a.

[0171] The second external electrode 230b is disposed on the fourth surface 12d and the sixth surface 12f so as to cover the second lead electrode portion 24b of the first internal electrode 16a, and further so as to cover a portion of the first surface 12a. The second external electrode 230b is electrically connected to the second lead electrode portion 24b of the first internal electrode 16a.

[0172] The third external electrode 230c is disposed on the third surface 12c and the sixth surface 12f so as to cover the third lead electrode portion 24c of the second internal electrode 16b, and further so as to cover a part of the first surface 12a. The third external electrode 230c is electrically connected to the third lead electrode portion 24c of the second internal electrode 16b.

[0173] The fourth external electrode 230d is disposed on the fourth surface 12d and the fifth surface 12e so as to cover the fourth lead electrode portion 24d of the second internal electrode 16b, and further so as to cover a part of the first surface 12a. The fourth external electrode 230d is electrically connected to the fourth lead electrode portion 24d of the second internal electrode 16b.

[0174] The multilayer ceramic capacitor 210 according to the third embodiment shown in Fig. 21 has the same effects as the multilayer ceramic capacitor 10 described above, and also has the following effect. That is, according to the multilayer ceramic capacitor 210 according to the third embodiment shown in Fig. 21, even in a multilayer ceramic capacitor in which the external electrodes 130 are disposed so as to cover only the first surface 12a of the laminate 12 and not cover the second surface 12b, it is possible to provide a multilayer ceramic capacitor with a reduced height without impairing mountability during mounting, similar to the multilayer ceramic capacitor 10 shown in Fig. 1.

[0175] The multilayer ceramic capacitor 210 according to the third embodiment may be configured such that the external electrodes 230 cover a portion of the second surface 12b and do not cover the first surface 12a.

[0176] The multilayer ceramic capacitor 210 according to the third embodiment of the present invention may also be combined with all or part of the first to third modified examples described above. Furthermore, it may also be combined with all or part of the first to third modified examples of the multilayer ceramic capacitor 10 according to the first embodiment, and with other modified examples shown in the respective drawings.

[0177] 2. Method for Manufacturing a Multilayer Ceramic Capacitor A method for manufacturing a multilayer ceramic capacitor according to the third embodiment will now be described.

[0178] First, a dielectric sheet and a conductive paste for the internal electrodes are prepared. The dielectric sheet, the conductive paste for the internal electrodes, and the conductive paste for the peripheral electrodes contain a binder and a solvent. Known binders and solvents can be used.

[0179] Next, a conductive paste for the internal electrodes is printed in a predetermined pattern on the dielectric sheet by, for example, inkjet printing, screen printing, gravure printing, etc. This prepares a dielectric sheet on which the first internal electrode pattern and the first peripheral electrode pattern are formed, and a dielectric sheet on which the second internal electrode pattern is formed. Thereafter, the sheet on which the first internal electrode pattern is printed and the sheet on which the second internal electrode pattern is printed are laminated together to form the portion that becomes the inner layer portion 18.

[0180] Next, a predetermined number of dielectric sheets not printed with internal electrode patterns or peripheral electrode patterns are stacked to form the portion that will become the first outer layer portion 20a on the first surface 12a. After that, the portion that will become the inner layer portion 18 prepared above is stacked, and a predetermined number of dielectric sheets not printed with internal electrode patterns are stacked on top of this portion that will become the inner layer portion 18 to form the portion that will become the second outer layer portion 20b on the second surface 12b. In this way, a laminated sheet is produced.

[0181] Next, the laminated sheet is pressed in the lamination direction by means of a hydrostatic press or the like to produce a laminated block.

[0182] The laminated block is then cut to a predetermined size to cut out laminated chips, the corners and ridges of which may be rounded by barrel polishing or the like.

[0183] Next, external electrodes 230 are formed on the laminate 12. That is, the laminated chip is fired to produce the laminate 12. The firing temperature depends on the ceramic and internal electrode materials, but is preferably 900°C or higher and 1400°C or lower.

[0184] Next, the resulting laminate 12 is aligned on a work table, and a thin film layer 32 is formed on the first surface 12a by sputtering.

[0185] Thereafter, an underlayer plating layer 34 is formed on the thin film layer 32 and the surface of the laminate 12, and a surface plating layer 36 is formed to cover the underlayer plating layer 34. More specifically, a Cu plating layer is formed on the thin film layer 32 as the underlayer plating layer 34. Then, a Ni plating layer and an Sn plating layer are formed on the surface of the underlayer plating layer 34 as the surface plating layer 36. Either electrolytic plating or electroless plating may be used for the plating process. However, electroless plating has the disadvantage of requiring pretreatment using a catalyst or the like to improve the plating deposition rate, which complicates the process. Therefore, it is usually preferable to use electrolytic plating.

[0186] In this manner, the multilayer ceramic capacitor 210 according to the third embodiment shown in FIG. 21 can be manufactured.

[0187] According to the method for manufacturing a multilayer ceramic capacitor according to this embodiment, it is possible to reduce the thickness of the external electrode 230 formed on the first surface 12 a in the lamination direction x, which is the dimension T, and therefore it is possible to provide a multilayer ceramic capacitor with a reduced height without impairing mountability during mounting.

[0188] D. Experimental Examples 1. Experimental Example 1 Next, in order to confirm the effects of the multilayer ceramic capacitor according to the present invention described above, an insulation test was conducted to evaluate each sample in which the dimension a1 of the first region A1 in the first direction y and the dimension b1 of the first region A1 in the second direction z were changed.

[0189] (1) Specifications of the multilayer ceramic capacitor fabricated as the sample of Experimental Example 1 Using the manufacturing method according to the above embodiment, the multilayer ceramic capacitors of Comparative Examples 1-1 to 1-5 and Examples 1-1 to 1-4 were fabricated. Structure of the multilayer ceramic capacitor: multilayer ceramic capacitor shown in FIG. 1 Dimension of the multilayer ceramic capacitor in the first direction: 600 μm Dimension of the multilayer ceramic capacitor in the second direction: 600 μm Dimension of the multilayer ceramic capacitor in the lamination direction: 220 μm Ceramic material: BaTiO3 Material of the internal electrode: Ni Structure of the external electrode Undercoat plating layer: Cu plating Thin film layer: sputtered film containing at least one of Ni, Cr, and Cu Top plating layer: two-layer structure of Ni plating and Sn plating

[0190] (2) Evaluation Method First, an insulation test was performed on each sample of multilayer ceramic capacitor by applying a 4 V DC current to the external electrodes of the multilayer ceramic capacitor in an environment of 85°C and 85% RH for 50 hours. The insulation resistance value of each sample was then measured after the insulation test. A sample with an insulation resistance value after the humidity test that was three orders of magnitude lower than the insulation resistance value before the insulation test was deemed defective (NG). A defective rate of 0.1% or less was deemed good and rated as "◯," a defective rate of 0.1% to 1.0% was deemed good and rated as "Δ," and a defective rate of more than 1.0% was deemed defective and rated as "×." Each sample was tested in a quantity of 1,000 or more.

[0191] (3) Void Measurement Method The porosity of the voids in the first region A1 of each sample was set to 2% or less. The porosity was calculated as follows. First, the cross section was polished to a length of 1 / 2T in the stacking direction x connecting the first surface 12a and the second surface 12b so that it was approximately parallel to the polished surface. Then, on the polished cross section surface, a binarization analysis was performed on the first region A1 using image analysis software to identify voids and areas other than voids. In this case, the voids had a diameter of 0.01 μm or more and 1.00 μm or less. The porosity was calculated by measuring the ratio of the sum of the void areas to the total area of ​​the first region A1.

[0192] (4) Results The evaluation results are shown in Table 1. Table 1 shows the evaluation results of the insulation test of the multilayer ceramic capacitor samples with respect to changes in the dimension a1 in the first direction y and the dimension b1 in the second direction z of the first region A1.

[0193]

[0194] According to Table 1, in Examples 1-1 to 1-4, the dimension a1 in the first direction of the first region A1 is 5 μm or more, and the dimension b1 in the second direction is 70 μm or more. Therefore, the region surrounded by the internal electrode and the third surface can be ensured to have a predetermined size. Therefore, the distance from the outside to the internal electrode can be ensured, which makes it possible to suppress the penetration of moisture from the outside. As a result, the number of defects in the first region A1 was 1.0% or less, and good results were obtained.

[0195] On the other hand, in Comparative Examples 1-1 to 1-3, the dimension a1 in the first direction of the first region A1 was smaller than 5 μm, and in Comparative Examples 1-4 and 1-5, the dimension b1 in the second direction of the first region A1 was smaller than 70 μm, so the number of defects was greater than 1.0%.

[0196] 2. Experimental Example 2 Furthermore, in order to confirm the effects of the multilayer ceramic capacitor according to the present invention, the mountability was evaluated with respect to changes in the areas of the first region A1 to the fourth region A4.

[0197] Using the manufacturing method according to the above embodiment, multilayer ceramic capacitors were fabricated as samples of Comparative Example 2-1, Comparative Example 2-2, and Examples 2-1 to 2-4. Structure of multilayer ceramic capacitor: multilayer ceramic capacitor shown in FIG. 1 Dimension of multilayer ceramic capacitor in first direction: 600 μm Dimension of multilayer ceramic capacitor in second direction: 600 μm Dimension of multilayer ceramic capacitor in lamination direction: 220 μm Ceramic material: BaTiO3 Internal electrode material: Ni External electrode structure Undercoat plating layer: Cu plating Thin film layer: sputtered film containing at least one of Ni, Cr, and Cu Top plating layer: two-layer structure of Ni plating and Sn plating

[0198] (2) Evaluation Method: The areas of the first region A1 to the fourth region A4 of each sample of multilayer ceramic capacitor having the above-described configuration were changed as shown in Table 2, and an implementation experiment was conducted to measure the rotation angle of each sample of multilayer ceramic capacitor. The number of samples was 100, and the average value for each sample was taken as the rotation angle. (3) Void Measurement Method: The porosity of the voids in the first region A1 to the fourth region A4 of each sample was set to 2% or less. The porosity was calculated in the same manner as in Experimental Example 1.

[0199] (4) Results The evaluation results are shown in Table 2. Table 2 shows the evaluation results of the mountability of each sample of the multilayer ceramic capacitor with respect to the change in the area of ​​the first region A1 to the fourth region A4 of the multilayer ceramic capacitor of each sample. Specifically, Table 2 shows the evaluation results based on the ratio of the minimum area (Min) to the maximum area (Max) of each of the areas of the first region A1 to the fourth region A4 of each sample.

[0200]

[0201] According to Table 2, in Examples 2-1 to 2-4, the ratio of the minimum area to the maximum area among the areas of the first region A1 to the fourth region A4 was 40% or more, and therefore the rotation angle of the multilayer ceramic capacitor of each sample was 5° or less, which was a good result.

[0202] On the other hand, in Comparative Examples 2-1 and 2-2, the ratio of the area of ​​the smallest value to the area of ​​the largest value among the areas of the first region A1 to the fourth region A4 was less than 40%, and therefore the rotation angle of the multilayer ceramic capacitor of each sample exceeded 5°.

[0203] Although the embodiments of the present invention have been disclosed above, the present invention is not limited thereto. In other words, various modifications can be made to the above-described embodiments in terms of mechanism, shape, material, quantity, position, arrangement, etc., without departing from the scope of the technical idea and purpose of the present invention, and such modifications are included in the present invention.

[0204] <1> A multilayer ceramic capacitor comprising: a laminate having first and second surfaces opposed to each other in a stacking direction, third and fourth surfaces opposed to each other in a first direction perpendicular to the stacking direction, and fifth and sixth surfaces opposed to each other in a second direction perpendicular to the stacking direction and the first direction; and four external electrodes arranged on the laminate, wherein the laminate has: a first internal electrode having one end exposed on the third surface and the other end exposed on the fourth surface; and a second internal electrode having one end exposed on the third surface and the other end exposed on the fourth surface, wherein, when a region surrounded by the third surface, the first internal electrode, and the second internal electrode is defined as a first region as viewed in the stacking direction, a dimension of the first region in the first direction is 5 μm or more, and a dimension of the first region in the second direction is 70 μm or more.

[0205] <2> The multilayer ceramic capacitor according to <1>, wherein the porosity of the first region is 2% or less.

[0206] <3> The multilayer ceramic capacitor according to <1> or <2>, wherein, when viewed in the stacking direction, a region surrounded by the fourth surface, the first internal electrode, and the second internal electrode is defined as a second region, an area ratio of an area of ​​the second region to an area of ​​the first region is 40% or more.

[0207] <4> The multilayer ceramic capacitor according to <3>, wherein one end of the first internal electrode is exposed on the third surface and the fifth surface, and the other end is exposed on the fourth surface and the sixth surface; the second internal electrode is exposed on the third surface and the sixth surface, and the other end is exposed on the fourth surface and the fifth surface; a region surrounded by the fifth surface, the first internal electrode, and the second internal electrode is defined as a third region when viewed in the stacking direction; a region surrounded by the sixth surface, the first internal electrode, and the second internal electrode is defined as a fourth region when viewed in the stacking direction; and an area ratio of the smallest region to the largest region among the areas of the first region to the fourth region is 40% or more.

[0208] <5> The multilayer ceramic capacitor according to any one of <1> to <4>, wherein, when the dimension of the multilayer ceramic capacitor in the first direction is L and the dimension of the multilayer ceramic capacitor in the second direction is W, 0.85≦L / W≦1.0.

[0209] 10, 10A, 10B, 10C, 110, 210 Multilayer ceramic capacitor 12 Laminate 12a, 112a First surface 12b, 112b Second surface 12c, 112c Third surface 12d, 112d Fourth surface 12e, 112e Fifth surface 12f, 112f Sixth surface 14, 114 Dielectric layer 14a, 114a Inner dielectric layer 14b, 114b Outer dielectric layer 16, 116 Internal electrode 16a, 116a First internal electrode 16b, 116b Second internal electrode 18, 118 Internal layer portion 20a, 120a First outer layer portion 20b, 120b Second outer layer portion 22a, 122a First opposing electrode portion 22b, 122b Second opposing electrode portion 24a, 124a First lead electrode portion 24b, 124b Second lead electrode portion 24c, 124c Third lead electrode portion 24d, 124d Fourth lead electrode portion 26a, 26b, 126a, 126b Side portion of laminate (W gap) 27a, 27b, 127a, 127b End portion of laminate (L gap) 30, 130, 230 External electrode 30a, 130a, 230a First external electrode 30b, 130b, 230b Second external electrode 30c, 130c, 230c Third external electrode 30d, 130d, 230d Fourth external electrode 32, 132 Thin film layer 32a, 132a First thin film layer 32b, 132b Second thin film layer 32c, 132c Third thin film layer 32d, 132d Fourth thin film layer 34, 134 Underlayer plating layer 34a, 134a First underlayer plating layer 34b, 134b Second underlayer plating layer 34c, 134c Third underlayer plating layer 34d, 134d Fourth underlayer plating layer 36, 136 Surface plating layer 36a, 136a First surface plating layer 36b, 136b Second surface plating layer 36c, 136c Third surface plating layer 36d, 136d Fourth surface plating layer 33 Direct plating layer 33a First direct plating layer 33b Second direct plating layer 40 Air gap x Stacking direction y First direction z Second direction L Dimension of the multilayer ceramic capacitor in the first direction W Dimension of the multilayer ceramic capacitor in the second direction T Dimension of the multilayer ceramic capacitor in the lamination direction

Claims

1. A multilayer ceramic capacitor comprising: a laminate having first and second surfaces opposed to each other in a stacking direction, third and fourth surfaces opposed to each other in a first direction perpendicular to the stacking direction, and fifth and sixth surfaces opposed to each other in a second direction perpendicular to the stacking direction and the first direction; and four external electrodes arranged on the laminate, wherein the laminate has: a first internal electrode having one end exposed on the third surface and the other end exposed on the fourth surface; and a second internal electrode having one end exposed on the third surface and the other end exposed on the fourth surface, wherein, when a region surrounded by the third surface, the first internal electrode, and the second internal electrode is defined as a first region as viewed in the stacking direction, the dimension of the first region in the first direction is 5 μm or more, and the dimension of the first region in the second direction is 70 μm or more.

2. The multilayer ceramic capacitor according to claim 1, wherein the porosity of the first region is 2% or less.

3. A multilayer ceramic capacitor according to claim 1 or 2, wherein, when viewed in the stacking direction, a region surrounded by said fourth surface, said first internal electrode, and said second internal electrode is defined as a second region, and the area ratio of the area of ​​said second region to the area of ​​said first region is 40% or more.

4. The multilayer ceramic capacitor according to claim 3, wherein the first internal electrode has one end exposed on the third surface and the fifth surface and the other end exposed on the fourth surface and the sixth surface, the second internal electrode has one end exposed on the third surface and the sixth surface and the other end exposed on the fourth surface and the fifth surface, a region surrounded by the fifth surface, the first internal electrode, and the second internal electrode as viewed in the stacking direction is defined as a third region, a region surrounded by the sixth surface, the first internal electrode, and the second internal electrode as viewed in the stacking direction is defined as a fourth region, and an area ratio of the smallest area to the largest area of ​​each of the first region to the fourth region is 40% or more.

5. A multilayer ceramic capacitor according to any one of claims 1 to 4, wherein, when the dimension of the multilayer ceramic capacitor in the first direction is L and the dimension of the multilayer ceramic capacitor in the second direction is W, 0.85≦L / W≦1.0.

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