Semiconductor storage device and semiconductor integrated circuit device

Abstract

In this semiconductor storage device, a ROM memory cell (M00) includes a first nanosheet FET having a nanosheet (36a), and a second nanosheet FET having a nanosheet (32a). The nanosheets (32a, 36a) overlap each other in plan view. The second nanosheet FET is a dummy transistor that does not contribute to the function of the ROM memory cell (M00). Data is stored in the ROM memory cell (M00) according to the state of connection between the source and drain of the first nanosheet FET, and a bit line (BL0) and power supply wiring (11). The first nanosheet FET and the second nanosheet FET have different conductivity types.

Description

Semiconductor memory device and semiconductor integrated circuit device

[0001] The present disclosure relates to a semiconductor memory device, and more particularly to a layout structure of a mask ROM (Read Only Memory) using a CFET (Complementary FET).

[0002] A mask ROM includes an array of memory cells, each of which is programmed and manufactured to have a fixed data state. The transistors that make up the memory cells are provided between a bit line and VSS, and the word line is connected to the gate. Bit data "1" or "0" is stored depending on whether the source or drain is connected to the bit line or VSS. The presence or absence of a connection is achieved, for example, by the presence or absence of a contact or via.

[0003] Furthermore, transistors, which are the basic components of LSIs, have achieved increased integration density, reduced operating voltages, and improved operating speeds through the reduction of gate length (scaling). However, in recent years, excessive scaling has led to problems with off-state current and the resulting significant increase in power consumption. To solve this problem, three-dimensional transistors, which change the transistor structure from the conventional planar type to a three-dimensional type, have been actively researched.

[0004] Patent Documents 1 and 2 disclose layout structures of ROM memory cells using CFETs.

[0005] International Publication No. WO 2020 / 230665 International Publication No. WO 2020 / 230666

[0006] In the configurations of Patent Documents 1 and 2, the upper and lower transistors constituting the ROM have the same conductivity type (N-type). On the other hand, in a logic cell constructed using CFETs, the upper and lower transistors have different conductivity types. Therefore, when manufacturing a semiconductor integrated circuit device including a ROM and a logic cell, different manufacturing methods must be used for the ROM region and the logic cell region, which increases manufacturing costs.

[0007] In addition, in the configurations of Patent Documents 1 and 2, the bit lines and power supply lines are provided separately in the buried wiring layer and the upper wiring layer, thereby increasing the wiring width of the lines provided in the upper wiring layer. However, since the lines in the buried wiring layer cannot be formed overlapping with the transistor (nanosheet), the wiring width cannot be increased, resulting in increased wiring resistance. Therefore, when bit lines are provided in the buried wiring layer, the operating speed decreases, and when power supply lines are provided in the buried wiring layer, the power supply voltage drop increases, resulting in decreased operating stability and operating speed.

[0008] The present disclosure provides a layout that can suppress increases in manufacturing costs by using CFETs for a semiconductor memory device including ROM memory cells and a semiconductor integrated circuit device including ROM memory cells and logic cells.

[0009] In a first aspect of the present disclosure, a semiconductor memory device having a ROM (Read Only Memory) memory cell comprises a word line extending in a first direction, a bit line extending in a second direction perpendicular to the first direction, and a power supply wiring extending in the second direction, wherein the ROM memory cell comprises a first nanosheet FET of a first conductivity type, whose channel, source, and drain are formed by a first active region, a first nanosheet included in the first active region extending in the second direction as a channel, and whose gate is connected to the word line, and a second nanosheet FET of a second conductivity type, whose channel, source, and drain are formed by a second active region, a second nanosheet included in the second active region extending in the second direction as a channel, and whose gate is connected to the word line, wherein the first nanosheet and the second nanosheet overlap in a planar view, and the second nanosheet FET is a dummy transistor that does not contribute to the function of the ROM memory cell, and data is stored in the ROM memory cell depending on the connection state of the source and drain of the first nanosheet FET with the bit line and the power supply wiring.

[0010] According to this aspect, the ROM memory cell includes first and second nanosheet FETs whose nanosheets overlap in a planar view. The second nanosheet FET is a dummy transistor that does not contribute to the function of the ROM memory cell. Data is stored in the ROM memory cell depending on the connection state between the source and drain of the first nanosheet FET and the bit line and power supply wiring. The first nanosheet FET and the second nanosheet FET have different conductivity types. Therefore, the same manufacturing method as for logic cells configured using CFETs can be used, thereby suppressing increases in manufacturing costs for semiconductor memory devices.

[0011] In a second aspect of the present disclosure, a semiconductor integrated circuit device having a ROM (Read Only Memory) memory cell and a logic cell comprises a word line extending in a first direction, a bit line extending in a second direction perpendicular to the first direction, and a power supply wiring extending in the second direction, wherein the logic cell comprises a first nanosheet FET of a first conductivity type and a second nanosheet FET of a second conductivity type located on top of the first nanosheet FET and overlapping the first nanosheet FET in a planar view, wherein the ROM memory cell is located at the same position as the first nanosheet FET in the depth direction, and has a channel, source, and drain formed by a first active region, and the first nanosheet extending in the second direction included in the first active region serves as a channel, and comprises a third nanosheet FET of the first conductivity type, whose gate is connected to the word line, wherein no nanosheet FET is formed in the ROM memory cell at the same position as the second nanosheet FET in the depth direction, and wherein data is stored in the ROM memory cell depending on the connection state between the source and drain of the third nanosheet FET and the bit line and the power supply wiring.

[0012] According to this aspect, the ROM memory cell includes a third nanosheet FET of the same conductivity type and located at the same depth as the first nanosheet FET of the logic cell. The ROM memory cell stores data based on the connection state between the source and drain of the third nanosheet FET and the bit line and power supply wiring. Furthermore, in the ROM memory cell, the nanosheet FET is not formed at the same depth as the second nanosheet FET of the logic cell. Therefore, the same manufacturing method can be used for the ROM region and the logic cell region, thereby suppressing increases in manufacturing costs for the semiconductor integrated circuit device.

[0013] According to the present disclosure, it is possible to realize a layout structure that uses CFETs and can suppress increases in manufacturing costs for semiconductor memory devices having ROM memory cells and semiconductor integrated circuit devices having ROM memory cells and logic cells.

[0014] 2 and 3. (a) and (b) are plan views showing an example of the layout structure of an inverter cell. (a) and (b) are plan views showing an example of the layout structure of a memory cell according to Modification 1 of the first embodiment. 15A and 15B are plan views showing an example of a layout structure of a memory cell according to Modification 7 of the first embodiment; FIG. 15A and 15B are plan views showing an example of a layout structure of a memory cell according to Modification 8 of the first embodiment; FIG. 15A and 15B are plan views showing an example of a layout structure of a memory cell according to Modification 9 of the first embodiment; FIG. 15B and 15B are plan views showing an example of a layout structure of a memory cell according to Modification 10 of the first embodiment; FIG. 15B are circuit diagrams showing the configuration of a contact-type mask ROM as an example of a semiconductor memory device according to a second embodiment;

[0015] Hereinafter, embodiments will be described with reference to the drawings. In this specification, "VDD" and "VSS" refer to power supply voltages or the power supply itself. In addition, in this specification, the source and drain regions of a transistor are referred to as the "nodes" of the transistor as appropriate. In other words, one node of a transistor refers to the source or drain of the transistor, and both nodes of a transistor refer to the source and drain of the transistor. In addition, in plan views and cross-sectional views, the illustration of each insulating film may be omitted. In addition, in this specification, expressions such as "same size" that mean that the size is the same, include the range of manufacturing variations.

[0016] 1 is a circuit diagram showing the configuration of a contact-type mask ROM as an example of a semiconductor memory device. In the mask ROM shown in FIG. 1, whether the source of a memory cell transistor is connected to a ground line VSS via a contact or not corresponds to "0" or "1" in the stored data.

[0017] In FIG. 1, the mask ROM includes a memory cell array 3 , a column decoder 2 , and a sense amplifier 18 .

[0018] The memory cell array 3 is configured by arranging memory cells Mij (i = 0 to m, j = 0 to n) of N-type MOS transistors in a matrix. The gates of the memory cells Mij are connected to word lines WLi in common in the row direction, and the drains are connected to bit lines BLj in common in the column direction. The source of the memory cell Mij is connected to the ground potential VSS when the stored data is set to "0", and is not connected to the ground potential VSS when the stored data is set to "1".

[0019] The column decoder 2 is composed of N-type MOS transistors Cj, whose drains are all connected in common, whose gates are connected to respective column selection signal lines CLj, and whose sources are connected to respective bit lines BLj.

[0020] The sense amplifier 18 includes a precharge P-type MOS transistor 5, an inverter 8 that determines the output data of the memory cell Mij, and an inverter 9 that buffers the output signal of the inverter 8. A precharge signal NPR is input to the gate of the P-type MOS transistor 5, a power supply voltage VDD is supplied to the source, and the drain is connected to the common drain of the N-type MOS transistor Cj. The inverter 8 receives a signal SIN from the common drain of the N-type MOS transistor Cj and determines the output data of the memory cell Mij. The inverter 9 receives an output signal SOUT from the inverter 8 and outputs the stored data of the memory cell Mij.

[0021] The operation of the mask ROM of FIG. 1 will be described by taking as an example the case where data is read from memory cell M00.

[0022] First, among the column selection signal lines CLj, CL0 is set to high level and the other CL1 to CLn are set to low level. As a result, among the transistors constituting the column decoder 2, C0 is turned on and the other C1 to Cn are turned off. Also, the word line WL0 is transitioned from low level, which indicates a non-selected state, to high level, which indicates a selected state.

[0023] Next, the precharge signal NPR is changed from high level to low level, and the precharge P-type MOS transistor 5 is turned on.

[0024] Here, when the source of memory cell M00 is connected to ground potential VSS, the current capability of memory cell M00 is greater than that of precharge P-type MOS transistor 5, and therefore input signal SIN of inverter 8 has a voltage lower than the switching level of inverter 8. As a result, output signal SOUT of inverter 8 is held at a high level, and output signal OUT of inverter 9 is held at a low level.

[0025] On the other hand, when the source of memory cell M00 is not connected to the ground potential VSS, bit line BL0 is charged by precharge P-type MOS transistor 5, and input signal SIN of inverter 8 becomes a voltage higher than the switching level of inverter 8. As a result, output signal SOUT of inverter 8 becomes low level, and output signal OUT of inverter 9 becomes high level.

[0026] That is, when the source of the memory cell is connected to VSS, a low level is output (storage data "0"), and when the source of the memory cell is not connected to VSS, a high level is output (storage data "1").

[0027] In addition, the mask ROM of the present disclosure may store the value of each memory cell by connecting / disconnecting the memory cell to VSS, or by connecting / disconnecting the memory cell to a bit line.

[0028] 2 and 3 show examples of the layout structure of a mask ROM according to the first embodiment, with FIGS. 2(a) and 2(b) being plan views of a memory cell, and FIGS. 3(a) to 3(c) being cross-sectional views of the memory cell in the horizontal direction in a plan view. Specifically, FIG. 2(a) shows the lower portion, i.e., the portion including a transistor (here, a P-type nanosheet FET) formed on the side closer to the substrate, and FIG. 2(b) shows the upper portion, i.e., the portion including a transistor (here, an N-type nanosheet FET) formed on the side farther from the substrate. FIG. 3(a) is a cross section along line X1-X1', FIG. 3(b) is a cross section along line X2-X2', and FIG. 3(c) is a cross section along line X3-X3'.

[0029] In the following description, in plan views such as Figure 2, the horizontal direction of the drawing is the X direction (corresponding to the first direction), the vertical direction of the drawing is the Y direction (corresponding to the second direction), and the direction perpendicular to the substrate surface is the Z direction (corresponding to the depth direction). Note that the X direction is the direction in which the gate wiring and word lines extend, and the Y direction is the direction in which the nanosheets and bit lines extend.

[0030] Furthermore, the dotted lines running vertically and horizontally in plan views such as FIG. 2 and the dotted lines running vertically in cross-sectional views such as FIG. 3 indicate grids used for component placement during design. The grids are arranged at equal intervals in the X direction and at equal intervals in the Y direction. The grid spacing may be the same or different in the X and Y directions. The grid spacing may also be different for each layer. Furthermore, each component does not necessarily have to be arranged on a grid. However, from the perspective of suppressing manufacturing variations, it is preferable to arrange the components on a grid.

[0031] In each drawing, the contact that determines the stored value of the memory cell is marked with the letter "D."

[0032] 2 corresponds to the layout of memory cells (2×2) bits in the memory cell array 3 of FIG. 1. Dashed lines indicate the frames of the memory cells. That is, FIG. 2 shows a configuration in which two memory cells are arranged in the X direction and two memory cells are arranged in the Y direction. For example, the two memory cells in the left column of the drawing correspond, from bottom to top, to memory cells M00 and M10, respectively, in the circuit diagram of FIG. 1, and the two memory cells in the right column of the drawing correspond, from bottom to top, to memory cells M01 and M11, respectively, in the circuit diagram of FIG. 1.

[0033] Fig. 4 is a circuit diagram of a memory cell. As shown in Fig. 4, the memory cell has an N-type transistor N1 that realizes the function of the memory cell and a P-type transistor P1 that serves as a dummy transistor. Note that Fig. 4 shows the circuit configuration of memory cell M00, but the other memory cells have similar circuit configurations.

[0034] 2 and 3, a P-type transistor P1 serving as a dummy transistor is formed in the lower part, and an N-type transistor N1 that functions as a memory cell is formed in the upper part. Note that the dummy transistor is not shown in the circuit diagram of FIG.

[0035] 2 and 3, power supply wirings 11 and 12 extending in the Y direction are formed in the BM0 wiring layer. The BM0 wiring layer is a wiring layer provided on the back side of the transistors in the semiconductor chip. The power supply wirings 11 and 12 supply VSS.

[0036] In the M1 wiring layer, bit lines 21 and 22 extending in the Y direction are formed. The M1 wiring layer is a wiring layer located above the transistors in the semiconductor chip, i.e., provided on the surface side of the transistors. The bit lines 21 and 22 correspond to bit lines BL0 and BL1, respectively. The power supply wiring 11 and the bit line 21 overlap in a planar view. The power supply wiring 12 and the bit line 22 overlap in a planar view. In addition to the bit lines 21 and 22, wirings 23a, 23b, and 23c extending in the Y direction and supplied with VSS are also formed in the M1 wiring layer. The wirings 23a, 23b, and 23c function as shield wirings for the bit lines 21 and 22. However, the wirings 23a, 23b, and 23c may be omitted.

[0037] Here, in a semiconductor chip, the back side of a transistor refers to the side opposite to the side on which local wiring, metal wiring, etc. connected to the transistor are stacked, and the side on which local wiring, metal wiring, etc. connected to the transistor are stacked is called the front side of the transistor.

[0038] An active region 31 that constitutes the channel, source, and drain of the P-type nanosheet FET is formed above the power supply wiring 11. The active region 31 overlaps the power supply wiring 11 and the bit line 21 in a planar view. The active region 31 includes nanosheets 32a and 32b extending in the Y direction that become the channel of the P-type nanosheet FET. The active region 31 also includes portions 33a, 33b, and 33c that become the source or drain of the P-type nanosheet FET.

[0039] An active region 35 that constitutes the channel, source, and drain of the N-type nanosheet FET is formed below the bit line 21 and above the active region 31. The active region 35 overlaps the power supply wiring 11 and the bit line 21 in a planar view. The active region 35 includes nanosheets 36a and 36b extending in the Y direction that become the channel of the N-type nanosheet FET. The active region 35 also includes portions 37a, 37b, and 37c that become the source or drain of the N-type nanosheet FET.

[0040] Gate wirings 41 and 42 are formed extending in parallel in the X direction. The gate wirings 41 and 42 extend in the Z direction from bottom to top. The gate wiring 41 surrounds the outer peripheries of the nanosheets 32a and 36a in the X and Z directions via a gate insulating film (not shown). The gate wiring 42 surrounds the outer peripheries of the nanosheets 32b and 36b in the X and Z directions via a gate insulating film (not shown). That is, the gate wiring 41 corresponds to the word line WL0 and is connected to the gate of the nanosheet FET included in the memory cell M00. The gate wiring 42 corresponds to the word line WL1 and is connected to the gate of the nanosheet FET included in the memory cell M10.

[0041] Dummy gate wirings 43 and 44 are formed to extend in the X direction.

[0042] Local interconnects 51 and 52 are formed at the bottom, extending in the X direction. In FIG. 2 and other drawings, local interconnect is denoted as LI. The local interconnect 51 contacts the portion 33 a of the active region 31. The local interconnect 52 contacts the portion 33 c of the active region 31. The local interconnects 51 and 52 are connected to the active region 35 through vias.

[0043] A local wiring 53 is formed on the upper portion, extending in the X direction. The local wiring 53 is in contact with the portion 37b of the active region 35. The local wiring 53 is connected to the bit line 21 through a via.

[0044] The presence or absence of contacts 71 and 72 formed in the lower portion determines the stored value of the memory cell. When formed, contact 71 connects portion 33a of active region 31 to power supply wiring 11. When formed, contact 72 connects portion 33c of active region 31 to power supply wiring 11.

[0045] In the above-described configuration, only the N-type nanosheet FET formed in the upper part functions as a transistor of the ROM cell. The P-type nanosheet FET formed in the lower part is a dummy transistor that does not contribute to the function of the ROM cell.

[0046] 5A and 5B show examples of the layout structure of an inverter cell using a CFET. The lower transistor shown in Fig. 5A is a P-type, and the upper transistor shown in Fig. 5B is an N-type. The inverter cell is an example of a logic cell.

[0047] 5, a power supply wiring 611 extending in the X direction is formed in the BM0 wiring layer. The power supply wiring 611 supplies VDD. A power supply wiring 612 extending in the X direction is formed in the M1 wiring layer. The power supply wiring 612 supplies VSS.

[0048] An active region 6P1 that constitutes the channel, source, and drain of the P-type nanosheet FET is formed at the bottom. The active region 6P1 includes a nanosheet 621 that serves as the channel of the P-type nanosheet FET and portions 622 and 623 that serve as nodes of the P-type nanosheet FET. An active region 6N1 that constitutes the channel, source, and drain of the N-type nanosheet FET is formed at the top. The active region 6N1 includes a nanosheet 624 that serves as the channel of the N-type nanosheet FET and portions 625 and 626 that serve as nodes of the N-type nanosheet FET. The active regions 6P1 and 6N1 overlap with the power supply wiring 611 and 612 in a planar view.

[0049] The gate wiring 631 extends in the Y direction and also extends in the Z direction from bottom to top. The gate wiring 631 surrounds the outer peripheries of the nanosheets 621 and 624 in the Y and Z directions via a gate insulating film (not shown).

[0050] The local wirings 651a and 651b extend in the Y direction and are connected to portions 622 and 623 of the active region 6P1, respectively. The local wirings 652a and 652b extend in the Y direction and are connected to portions 625 and 626 of the active region 6N1, respectively.

[0051] A portion 622 of the active region 6P1 is connected to the power supply wiring 611 through a via. A portion 625 of the active region 6N1 is connected to the power supply wiring 612 through a via and a local wiring 652a. The local wiring 651b and the local wiring 652b are connected to each other through a via.

[0052] An M1 wiring 661 serving as the input of the inverter is connected to the gate wiring 631. An M1 wiring 662 serving as the output of the inverter is connected to a local wiring 652b through a via.

[0053] Therefore, in this embodiment, the conductivity types of the upper and lower transistors are the same in the mask ROM cell and the logic cell. Therefore, it is not necessary to use different manufacturing methods for the mask ROM region and the logic cell region. Therefore, it is possible to suppress an increase in manufacturing costs for semiconductor memory devices and semiconductor integrated circuit devices equipped with mask ROM.

[0054] Furthermore, in the above-described configuration, the power supply wirings 11 and 12 that supply VSS are formed in a wiring layer provided on the back side of the transistor. This allows the wiring width of the power supply wirings 11 and 12 to be increased, thereby reducing the wiring resistance. This makes it possible to suppress a power supply voltage drop, thereby improving the operational stability and operating speed of the semiconductor memory device or semiconductor integrated circuit device.

[0055] Furthermore, in the above-described configuration, the setting of the memory value of the mask ROM is achieved by the presence or absence of a contact between the active region constituting the lower transistor and the VSS wiring formed in the back wiring layer. In the manufacturing process of a semiconductor memory device, the formation of wiring in the back wiring layer is performed after the formation of wiring in the surface wiring layer. Therefore, in this embodiment, the contact for setting the memory value of the memory cell can be formed in a later process. This shortens the manufacturing time required to change the memory value of the memory cell.

[0056] In the above-described configuration, the power supply wirings 11 and 12 in the BM0 wiring layer are formed for each bit string, but for example, the power supply wiring may be formed integrally for a plurality of bit strings.

[0057] As described above, according to this embodiment, for example, memory cell M00 comprises a P-type nanosheet FET formed in the lower portion and comprising nanosheet 32a, and an N-type nanosheet FET formed in the upper portion and comprising nanosheet 36a. Nanosheets 32a and 32b overlap in plan view. The P-type nanosheet FET in the lower portion is a dummy transistor that does not contribute to the function of memory cell M00. Because the conductivity types of the transistors in the lower and upper portions are different, the same manufacturing method as for logic cells constructed using CFETs can be used. Therefore, increases in the manufacturing costs of semiconductor memory devices and semiconductor integrated circuit devices can be suppressed.

[0058] 6A and 6B are diagrams showing an example of a layout structure of a mask ROM according to a first modification of the first embodiment, where (a) is a lower portion and (b) is an upper portion. Also, Fig. 7 is a circuit diagram of a memory cell.

[0059] In this modification, the wiring layers of the power supply wiring and the bit lines are swapped compared to the first embodiment. That is, in this modification, the bit lines are formed in the BM0 wiring layer, and the power supply wiring that supplies VSS is formed in the M1 wiring layer. Furthermore, a contact for setting a memory value is provided between the local wiring that contacts the upper active region and the power supply wiring formed in the M1 wiring layer.

[0060] 6, bit lines 13 and 14 extending in the Y direction are formed in the BM0 wiring layer. The bit lines 13 and 14 correspond to bit lines BL0 and BL1, respectively. In addition to the bit lines 13 and 14, wirings 15a, 15b, and 15c extending in the Y direction and supplied with VSS are also formed in the BM0 wiring layer. The wirings 15a, 15b, and 15c function as shield wirings for the bit lines 13 and 14. However, the wirings 15a, 15b, and 15c may be omitted.

[0061] In the M1 wiring layer, power supply wirings 24 and 25 extending in the Y direction are formed. The power supply wirings 24 and 25 supply VSS. However, in the M1 wiring layer, the power supply wirings may be formed integrally for a plurality of bit strings.

[0062] The active regions 31 and 35 and the gate wirings 41 and 42 have the same configuration as in the embodiment 1. The portion 33b of the active region 31 is connected to the bit line 13 through a via.

[0063] A local wiring 54 extending in the X direction is formed at the bottom. The local wiring 54 is in contact with the portion 33b of the active region 31. The local wiring 54 is connected to the active region 35 through a via.

[0064] Local wirings 55 and 56 are formed on the upper portion thereof, extending in the X direction. The local wirings 55 and 56 are in contact with the portions 37a and 37c of the active region 35, respectively.

[0065] The presence or absence of contacts 73 and 74 formed on the upper portion determines the stored value of the memory cell. When formed, contact 73 connects local wiring 55, which is in contact with portion 37 a of active region 35, to power supply wiring 24. When formed, contact 74 connects local wiring 56, which is in contact with portion 37 c of active region 35, to power supply wiring 24.

[0066] In the above-described configuration, only the N-type nanosheet FET formed in the upper part functions as a transistor of the ROM cell. The P-type nanosheet FET formed in the lower part is a dummy transistor that does not contribute to the function of the ROM cell. Therefore, even in this modified example, there is no need to use different manufacturing methods for the mask ROM region and the logic cell region, so that the increase in manufacturing costs for semiconductor memory devices and semiconductor integrated circuit devices can be suppressed.

[0067] Furthermore, in the above-described configuration, the bit lines 13 and 14 are formed in a wiring layer provided on the back side of the transistor. This allows the wiring width of the bit lines 13 and 14 to be increased, thereby reducing the wiring resistance. This allows the operating speed of the semiconductor memory device or semiconductor integrated circuit device to be improved.

[0068] (Modification 2) FIGS. 8A and 8B are diagrams showing an example of the layout structure of a mask ROM according to Modification 2 of the first embodiment, where (a) is the lower part and (b) is the upper part.

[0069] In this modification, compared to the first embodiment, bit lines are further provided in the back wiring layer. That is, as shown in FIG. 8, bit lines 16a, 16b, and 16c extending in the Y direction are formed in the BM0 wiring layer. The bit lines 16a, 16b, and 16c correspond to bit lines BL0, BL1, and BL2, respectively. However, within the memory cell array, the bit lines 16a, 16b, and 16c are not connected to transistors or the like. Outside the memory cell array, the bit lines 16a, 16b, and 16c are connected to bit lines in the M1 wiring layer. Note that, although FIG. 8 shows the bit lines 16a, 16b, and 16c arranged at the boundaries of memory cells, the arrangement positions of the bit lines in the BM0 wiring layer are not limited to this.

[0070] According to this modification, in addition to the effects of the first embodiment, it is possible to realize a higher speed of operation due to a lower resistance of the bit line.

[0071] (Modification 3) FIGS. 9A and 9B are diagrams showing an example of the layout structure of a mask ROM according to Modification 3 of the first embodiment, where (a) is the lower part and (b) is the upper part.

[0072] In this modification, compared to the first modification, bit lines are further provided in the surface wiring layer. That is, as shown in FIG. 9, bit lines 26a, 26b, and 26c extending in the Y direction are formed in the M1 wiring layer. The bit lines 26a, 26b, and 26c correspond to bit lines BL0, BL1, and BL2, respectively. However, within the memory cell array, the bit lines 26a, 26b, and 26c are not connected to transistors or the like. Outside the memory cell array, the bit lines 26a, 26b, and 26c are connected to bit lines in the BM0 wiring layer. Note that, although FIG. 9 shows the bit lines 26a, 26b, and 26c arranged at the boundaries of memory cells, the arrangement positions of the bit lines in the M1 wiring layer are not limited to this.

[0073] According to this modification, in addition to the effect of the first modification, it is possible to realize a higher speed of operation due to the lower resistance of the bit line.

[0074] 10A and 10B are diagrams showing an example of the layout structure of a mask ROM according to Modification 4 of the first embodiment, with (a) being the lower part and (b) being the upper part. Also, Fig. 11 is a circuit diagram of a memory cell. In this modification, unlike Modification 2, contacts for setting the memory value of the memory cell are provided on the M1 wiring side.

[0075] 10, power supply wirings 17 and 18 that extend in the Y direction and supply VDD are formed in the BM0 wiring layer. At the bottom, portions 33a, 33b, and 33c of the active region 31 are connected to the power supply wiring 17 through vias. Also, local wirings 51 and 52 are omitted.

[0076] In the M1 wiring layer, bit lines 21 and 22 extending in the Y direction are formed. However, the positions of the bit lines 21 and 22 are different from those in the first embodiment and Modification 2. In addition, power supply lines 27 and 28 extending in the Y direction for supplying VSS are formed.

[0077] Local interconnections 57, 58, and 59 are formed on the upper portion, extending in the X direction. The local interconnections 57, 58, and 59 are in contact with the portions 37a, 37b, and 37c, respectively, of the active region 35. The local interconnection 58 is connected to the bit line 21 through a via.

[0078] The presence or absence of contacts 75 and 76 formed on the upper portion determines the stored value of the memory cell. When formed, contact 75 connects local wiring 57, which is in contact with portion 37 a of active region 35, to power supply wiring 27. When formed, contact 76 connects local wiring 59, which is in contact with portion 37 c of active region 35, to power supply wiring 27.

[0079] This modification provides the same effects as those of the first embodiment and the second modification. In addition, the node of the upper N-type nanosheet FET is connected to the VSS power supply wiring without passing through the active region of the lower P-type nanosheet FET. This reduces the resistance in the power supply, suppressing power supply voltage drops, thereby improving the speed and stability of the mask ROM operation.

[0080] The power supply wiring 17, 18 that supplies VDD formed in the BM0 wiring layer is connected only to the node of the lower P-type nanosheet FET within the memory cell. However, the power supply wiring 17, 18 does not have to be connected to the transistor within the memory cell. In this case, for example, the power supply wiring 17, 18 may supply VSS and be connected to the VSS wiring of the M1 wiring layer outside the memory cell array. In this case, since the power supply strengthening can suppress the power supply voltage drop, the speed and stability of the mask ROM operation can be improved.

[0081] 12 is a circuit diagram showing the configuration of a contact-type mask ROM according to Modification 5 and subsequent modifications of the first embodiment. In the configuration of Fig. 12, unlike the configuration of Fig. 1, the column decoder 2X and the memory cell array 3X are configured using P-type MOS transistors.

[0082] The memory cell array 3X is configured by arranging memory cells Mij (i = 0 to m, j = 0 to n) of P-type MOS transistors in a matrix. The gates of the memory cells Mij are connected to word lines NWLi in common in the row direction, and the drains are connected to bit lines BLj in common in the column direction. The source of the memory cell Mij is not connected to the power supply VDD when the stored data is set to "0," and is connected to the power supply VDD when the stored data is set to "1."

[0083] The column decoder 2X is composed of P-type MOS transistors Cj, whose drains are all connected in common, whose gates are connected to respective column selection signal lines NCLj, and whose sources are connected to respective bit lines BLj.

[0084] The sense amplifier 18X includes a precharge N-type MOS transistor 5X, an inverter 8 that determines the output data of the memory cell Mij, and an inverter 9 that buffers the output signal of the inverter 8. A precharge signal PR is input to the gate of the N-type MOS transistor 5X, a ground voltage VSS is supplied to its source, and the drain is connected to the common drain of the P-type MOS transistor Cj. The inverter 8 receives a signal SIN from the common drain of the P-type MOS transistor Cj and determines the output data of the memory cell Mij. The inverter 9 receives an output signal SOUT from the inverter 8 and outputs the stored data of the memory cell Mij.

[0085] The operation of the mask ROM of FIG. 12 will be described by taking as an example the case where data is read from memory cell M00.

[0086] First, among the column selection signal lines NCLj, NCL0 is set to low level and the other NCL1 to NCLn are set to high level. As a result, among the transistors constituting the column decoder 2X, C0 is turned on and the other C1 to Cn are turned off. Also, the word line NWL0 is transitioned from high level, which indicates a non-selected state, to low level, which indicates a selected state.

[0087] Next, the precharge signal PR is changed from low level to high level, and the precharge N-type MOS transistor 5X is turned on.

[0088] Here, when the source of the memory cell M00 is connected to the power supply VDD, the current capability of the memory cell M00 is greater than that of the precharge N-type MOS transistor 5X, and therefore the input signal SIN of the inverter 8 has a voltage higher than the switching level of the inverter 8. As a result, the output signal SOUT of the inverter 8 becomes low level, and the output signal OUT of the inverter 9 becomes high level.

[0089] On the other hand, when the source of memory cell M00 is not connected to the power supply VDD, the bit line BL0 is discharged by the precharge N-type MOS transistor 5X, and the input signal SIN of inverter 8 becomes a voltage lower than the switching level of inverter 8. As a result, the output signal SOUT of inverter 8 is held at a high level, and the output signal OUT of inverter 9 is held at a low level.

[0090] That is, when the source of the memory cell is connected to VDD, a high level is output (storage data "1"), and when the source of the memory cell is not connected to VDD, a low level is output (storage data "0").

[0091] In addition, the mask ROM of the present disclosure may store the value of each memory cell by connecting / disconnecting the memory cell to VDD, or by connecting / disconnecting the memory cell to a bit line.

[0092] 13A and 13B are diagrams showing an example of the layout structure of a mask ROM according to the fifth modification of the first embodiment, where (a) is the lower part and (b) is the upper part. Also, Fig. 14 is a circuit diagram of a memory cell.

[0093] As shown in Figure 14, the memory cell has a P-type transistor P1 that functions as a memory cell and an N-type transistor N1 that serves as a dummy transistor. In this modified example, a P-type nanosheet FET that functions as a memory cell is formed in the lower part, and an N-type nanosheet FET that serves as a dummy transistor is formed in the upper part. Note that the dummy transistor is not shown in Figure 12.

[0094] As shown in FIG. 13 , power supply wiring 111 and 112 extending in the Y direction are formed in the BM0 wiring layer. The power supply wiring 111 and 112 supply VDD. Bit lines 121 and 122 extending in the Y direction are formed in the M1 wiring layer. The bit lines 121 and 122 correspond to bit lines BL0 and BL1, respectively. The power supply wiring 111 and the bit line 121 overlap in a planar view. The power supply wiring 112 and the bit line 122 overlap in a planar view. In addition to the bit lines 121 and 122, wiring 123a, 123b, and 123c extending in the Y direction and supplied with VDD are also formed in the M1 wiring layer. The wiring 123a, 123b, and 123c function as shield wiring for the bit lines 121 and 122. However, the wiring 123a, 123b, and 123c may be omitted.

[0095] An active region 131 that constitutes the channel, source, and drain of the P-type nanosheet FET is formed above the power supply wiring 111. The active region 131 overlaps the power supply wiring 111 and the bit line 121 in a planar view. The active region 131 includes nanosheets 132a and 132b extending in the Y direction that become the channel of the P-type nanosheet FET. The active region 131 also includes portions 133a, 133b, and 133c that become the source or drain of the P-type nanosheet FET.

[0096] An active region 135 that constitutes the channel, source, and drain of the N-type nanosheet FET is formed below the bit line 121 and above the active region 131. The active region 135 overlaps the power supply wiring 111 and the bit line 121 in a planar view. The active region 135 includes nanosheets 136a and 136b extending in the Y direction that become the channel of the N-type nanosheet FET. The active region 135 also includes portions 137a, 137b, and 137c that become the source or drain of the N-type nanosheet FET.

[0097] Gate wirings 141 and 142 are formed extending in parallel in the X direction. The gate wirings 141 and 142 extend in the Z direction from bottom to top. The gate wiring 141 surrounds the outer peripheries of the nanosheets 132a and 136a in the X and Z directions via a gate insulating film (not shown). The gate wiring 142 surrounds the outer peripheries of the nanosheets 132b and 136b in the X and Z directions via a gate insulating film (not shown). That is, the gate wiring 141 corresponds to the word line NWL0 and is connected to the gate of the nanosheet FET included in the memory cell M00. The gate wiring 142 corresponds to the word line NWL1 and is connected to the gate of the nanosheet FET included in the memory cell M10.

[0098] Dummy gate wirings 143 and 144 are formed to extend in the X direction.

[0099] A local wiring 151 extending in the X direction is formed at the bottom. The local wiring 151 contacts the portion 133b of the active region 131. The local wiring 151 is connected to the active region 135 through a via.

[0100] A local interconnect 152 extending in the X direction is formed on the upper portion. The local interconnect 152 contacts the portion 137b of the active region 135. The local interconnect 152 is connected to the bit line 121 through a via.

[0101] The presence or absence of contacts 171 and 172 formed in the lower portion determines the stored value of the memory cell. When formed, contact 171 connects portion 133a of active region 131 to power supply wiring 111. When formed, contact 172 connects portion 133c of active region 131 to power supply wiring 111.

[0102] In the above-described configuration, only the P-type nanosheet FET formed in the lower part functions as a transistor of the ROM cell. The N-type nanosheet FET formed in the upper part is a dummy transistor that does not contribute to the function of the ROM cell.

[0103] Therefore, in this modification, the conductivity types of the upper and lower transistors are the same in the mask ROM cell and the logic cell, and therefore it is not necessary to use different manufacturing methods for the mask ROM region and the logic cell region, which makes it possible to suppress increases in manufacturing costs for semiconductor memory devices and semiconductor integrated circuit devices.

[0104] Furthermore, in the above-described configuration, the power supply wiring 111, 112 that supplies VDD is formed in a wiring layer provided on the back side of the transistor. This allows the wiring width of the power supply wiring 111, 112 to be increased, thereby reducing the wiring resistance. This makes it possible to suppress a power supply voltage drop, thereby improving the operational stability and operating speed of the semiconductor memory device or semiconductor integrated circuit device.

[0105] Furthermore, in the above-described configuration, the setting of the memory value of the mask ROM is achieved by the presence or absence of a contact between the active region constituting the lower transistor and the VDD wiring formed in the back wiring layer. In the manufacturing process of a semiconductor memory device, the formation of wiring in the back wiring layer is performed after the formation of wiring in the surface wiring layer. Therefore, in this embodiment, the contact for setting the memory value of the memory cell can be formed in a later process. This shortens the manufacturing time required to change the memory value of the memory cell.

[0106] In the above-described configuration, the power supply wirings 111 and 112 in the BM0 wiring layer are formed for each bit string, but for example, the power supply wiring may be formed integrally for a plurality of bit strings.

[0107] 15A and 15B are diagrams showing an example of a layout structure of a mask ROM according to Modification 6 of the first embodiment, where (a) is the lower part and (b) is the upper part. Also, Fig. 16 is a circuit diagram of a memory cell.

[0108] In this modification, the wiring layers of the power supply wiring and the bit lines are swapped compared to modification 5. That is, in this modification, the bit lines are formed in the BM0 wiring layer, and the power supply wiring that supplies VDD is formed in the M1 wiring layer. Furthermore, a contact for setting a memory value is provided between the local wiring that contacts the upper active region and the power supply wiring formed in the M1 wiring layer.

[0109] 15, bit lines 113 and 114 extending in the Y direction are formed in the BM0 wiring layer. The bit lines 113 and 114 correspond to bit lines BL0 and BL1, respectively. In addition to the bit lines 113 and 114, wirings 115a, 115b, and 115c extending in the Y direction and supplied with VSS are also formed in the BM0 wiring layer. The wirings 115a, 115b, and 115c function as shield wirings for the bit lines 113 and 114. However, the wirings 115a, 115b, and 115c may be omitted.

[0110] In the M1 wiring layer, power supply wirings 124 and 125 extending in the Y direction are formed. The power supply wirings 124 and 125 supply VDD. However, in the M1 wiring layer, the power supply wirings may be formed integrally for a plurality of bit strings.

[0111] The active regions 131 and 135 and the gate wirings 141 and 142 have the same configuration as in Modification 5. A portion 133b of the active region 131 is connected to the bit line 113 through a via.

[0112] Local interconnects 153 and 154 are formed at the bottom, extending in the X direction. The local interconnects 153 and 154 are in contact with portions 133a and 133c, respectively, of the active region 131. The local interconnects 153 and 154 are connected to the active region 135 through vias.

[0113] Local interconnects 155 and 156 are formed on the upper portion thereof, extending in the X direction. The local interconnects 155 and 156 are in contact with portions 137a and 137c of the active region 135, respectively.

[0114] The presence or absence of contacts 173 and 174 formed on the upper portion determines the stored value of the memory cell. When formed, contact 173 connects local interconnect 155, which is in contact with portion 137 a of active region 135, to power supply interconnect 124. When formed, contact 174 connects local interconnect 156, which is in contact with portion 137 c of active region 135, to power supply interconnect 124.

[0115] In the above-described configuration, only the P-type nanosheet FET formed at the bottom functions as a transistor of the ROM cell. The N-type nanosheet FET formed at the top is a dummy transistor that does not contribute to the function of the ROM cell. Therefore, even in this modified example, there is no need to use different manufacturing methods for the mask ROM region and the logic cell region, so that the increase in manufacturing costs for semiconductor memory devices and semiconductor integrated circuit devices can be suppressed.

[0116] Furthermore, in the above-described configuration, the bit lines 113 and 114 are formed in a wiring layer provided on the back side of the transistor. This allows the wiring width of the bit lines 113 and 114 to be increased, thereby reducing the wiring resistance. This allows the operating speed of the semiconductor memory device or semiconductor integrated circuit device to be improved.

[0117] (Seventh Modification) FIGS. 17A and 17B are diagrams showing an example of the layout structure of a mask ROM according to a seventh modification of the first embodiment, where (a) is the lower part and (b) is the upper part.

[0118] In this modification, compared to modification 5, bit lines are further provided in the back wiring layer. That is, as shown in FIG. 17 , bit lines 116a, 116b, and 116c extending in the Y direction are formed in the BM0 wiring layer. The bit lines 116a, 116b, and 116c correspond to bit lines BL0, BL1, and BL2, respectively. However, within the memory cell array, the bit lines 116a, 116b, and 116c are not connected to transistors or the like. Outside the memory cell array, the bit lines 116a, 116b, and 116c are connected to bit lines in the M1 wiring layer. Note that, although FIG. 17 shows the bit lines 116a, 116b, and 116c arranged at the boundaries of memory cells, the arrangement positions of the bit lines in the BM0 wiring layer are not limited to this.

[0119] According to this modification, in addition to the effect of the fifth modification, it is possible to realize a higher speed of operation due to a lower resistance of the bit line.

[0120] (Modification 8) FIGS. 18A and 18B are diagrams showing an example of the layout structure of a mask ROM according to Modification 8 of the first embodiment, where (a) is the lower part and (b) is the upper part.

[0121] In this modification, compared to modification 6, bit lines are further provided in the surface wiring layer. That is, as shown in FIG. 18, bit lines 126a, 126b, and 126c extending in the Y direction are formed in the M1 wiring layer. The bit lines 126a, 126b, and 126c correspond to bit lines BL0, BL1, and BL2, respectively. However, within the memory cell array, the bit lines 126a, 126b, and 126c are not connected to transistors or the like. Outside the memory cell array, the bit lines 126a, 126b, and 126c are connected to bit lines in the BM0 wiring layer. Note that, although FIG. 18 shows the bit lines 126a, 126b, and 126c arranged at the boundaries of memory cells, the arrangement positions of the bit lines in the M1 wiring layer are not limited to this.

[0122] According to this modification, in addition to the effect of the sixth modification, it is possible to realize a higher speed of operation due to a lower resistance of the bit line.

[0123] (Modification 9) FIGS. 19A and 19B are diagrams showing an example of the layout structure of a mask ROM according to Modification 9 of the first embodiment, where (a) is the lower part and (b) is the upper part.

[0124] In this modification, unlike modification 5, the upper nanosheet FET is not formed, and the node of the lower nanosheet FET is directly connected to the bit line in the M1 wiring layer. That is, the active region 135 and the local wiring 152 are not formed in the upper part. The portion 133b of the lower active region 131 is connected to the local wiring 151 and the bit line 121 through a via.

[0125] If only the lower nanosheet FET is formed without forming the upper nanosheet FET, the following manufacturing method can be used. That is, a nanosheet for the lower nanosheet FET and a nanosheet for the upper nanosheet FET are formed on a semiconductor substrate. Then, the nanosheet for the upper nanosheet FET is removed by etching, and a nanosheet FET is formed in the lower part. This makes it possible to realize a configuration like that of this modified example.

[0126] According to this modification, the node of the lower P-type nanosheet FET that functions as a transistor of the ROM cell is connected to the bit line without going through the upper active region, which enables the reduction of the resistance of the bit line and the increase in operation speed.

[0127] In this modification, similar to the seventh modification, bit lines extending in the Y direction may be formed in the BM0 wiring layer.

[0128] (Modification 10) FIGS. 20A and 20B are diagrams showing an example of the layout structure of a mask ROM according to Modification 10 of the first embodiment, where (a) is the lower part and (b) is the upper part.

[0129] In this modification, unlike modification 6, an upper transistor is not formed, and the lower transistor is directly connected to the power supply wiring in the M1 wiring layer. That is, the active region 135 and the local wirings 155 and 156 are not formed in the upper part. Contacts 175 and 176 for setting the memory value of the memory cell are provided between the local wirings 153 and 154 in the lower part and the power supply wiring 124 in the M1 wiring layer.

[0130] According to this modification, the node of the lower P-type nanosheet FET that functions as a transistor of the ROM cell is connected to the power supply wiring without going through the upper active region when contacts 175 and 176 are provided, which enables the reduction of the resistance of the power supply wiring path and the realization of faster operation.

[0131] In this modification, similar to the eighth modification, bit lines extending in the Y direction may be formed in the M1 wiring layer.

[0132] Second Embodiment Fig. 21 is a circuit diagram showing the configuration of a mask ROM as an example of a semiconductor memory device. In the mask ROM of Fig. 21, whether the source and drain of a memory cell transistor are connected to the same line or different lines out of a bit line and a ground power supply line corresponds to "1" or "0" of stored data.

[0133] 21, the mask ROM includes a memory cell array 3A, a column decoder 2, and a sense amplifier 18.

[0134] The memory cell array 3A is configured by arranging memory cells Mij (i = 0 to m, j = 0 to n) of N-type MOS transistors in a matrix. The gates of the memory cells Mij are connected to word lines WLi in common in the row direction. The source and drain of the memory cell Mij are connected to bit lines BLj or to a ground power supply wiring VSS. When the data stored in the memory cell Mij is set to "0", one of the source and drain is connected to the bit line BLj and the other is connected to the ground power supply wiring VSS. On the other hand, when the data stored in the memory cell Mij is set to "1", both the source and drain are connected to the bit line BLj or the ground power supply wiring VSS.

[0135] The column decoder 2 is composed of N-type MOS transistors Cj, whose drains are all connected in common, whose gates are connected to respective column selection signal lines CLj, and whose sources are connected to respective bit lines BLj.

[0136] The sense amplifier 18 includes a precharge P-type MOS transistor 5, an inverter 8 that determines the output data of the memory cell Mij, and an inverter 9 that buffers the output signal of the inverter 8. A precharge signal NPR is input to the gate of the P-type MOS transistor 5, a power supply voltage VDD is supplied to the source, and the drain is connected to the common drain of the N-type MOS transistor Cj. The inverter 8 receives a signal SIN from the common drain of the N-type MOS transistor Cj and determines the output data of the memory cell Mij. The inverter 9 receives an output signal SOUT from the inverter 8 and outputs the stored data of the memory cell Mij.

[0137] The operation of the mask ROM of Fig. 21 will be described below, taking as an example the case where data is read from memory cells M00 and M10.

[0138] First, among the column selection signal lines CLj, CL0 is set to high level and the other CL1 to CLn are set to low level. As a result, among the transistors constituting the column decoder 2, C0 is turned on and the other C1 to Cn are turned off. Also, the word line WL0 is transitioned from low level, which indicates a non-selected state, to high level, which indicates a selected state.

[0139] Next, the precharge signal NPR is changed from high level to low level, and the precharge P-type MOS transistor 5 is turned on.

[0140] One of the source and drain of memory cell M00 is connected to bit line BL0, and the other is connected to ground power supply wiring VSS. Therefore, current flows from bit line BL0 to ground power supply wiring VSS via memory cell M00, and input signal SIN of inverter 8 becomes a voltage lower than the switching level of inverter 8. Therefore, output signal SOUT of inverter 8 remains high, and output signal OUT of inverter 9 remains low.

[0141] When data in the memory cell M10 is to be read, the word line WL1 is transitioned from a low level, which indicates a non-selected state, to a high level, which indicates a selected state.

[0142] Both the source and drain of memory cell M10 are connected to bit line BL0. Therefore, no current flows through bit line BL0, and input signal SIN of inverter 8 becomes a voltage higher than the switching level of inverter 8. As a result, output signal SOUT of inverter 8 becomes low level, and output signal OUT of inverter 9 becomes high level.

[0143] That is, when one of the source and drain of the memory cell is connected to a bit line and the other is connected to a ground power supply wiring, a low level is output (storage data "0"), and when both the source and drain of the memory cell are connected to a bit line or a ground power supply wiring, a high level is output (storage data "1").

[0144] FIG. 22 is a diagram showing an example of the layout structure of a mask ROM according to the second embodiment, with (a) being the bottom and (b) being the top. FIG. 22 corresponds to the layout of memory cells (2×4) bits in the memory cell array 3A of FIG. 21. That is, in FIG. 22, two memory cells are arranged in the X direction and four memory cells are arranged in the Y direction. For example, the four memory cells in the left column of the drawing correspond, from bottom to top, to memory cells M00, M10, M20, and M30, respectively, in the circuit diagram of FIG. 21, and the four memory cells in the right column of the drawing correspond, from bottom to top, to memory cells M01, M11, M21, and M31, respectively, in the circuit diagram of FIG. 21.

[0145] In the configuration of Figure 22, only the N-type nanosheet FET formed at the top functions as a transistor of the ROM cell. The P-type nanosheet FET formed at the bottom is a dummy transistor that does not contribute to the function of the ROM cell. Note that the dummy transistor is omitted from the circuit diagram of Figure 21.

[0146] 22, power supply wirings 211 and 212 extending in the Y direction are formed in the BM0 wiring layer. The power supply wirings 211 and 212 supply VDD.

[0147] In the M1 wiring layer, bit lines 221 and 222 extending in the Y direction and power supply lines 223 and 224 extending in the Y direction are formed. The bit lines 221 and 222 correspond to the bit lines BL0 and BL1, respectively. The power supply lines 223 and 224 supply VSS.

[0148] An active region 231 that constitutes the channel, source, and drain of the P-type nanosheet FET is formed above the power wiring 211. The active region 231 overlaps the power wiring 211 in a planar view. The active region 231 includes nanosheets 232a, 232b, 232c, and 232d extending in the Y direction that become the channel of the P-type nanosheet FET. The active region 231 also includes portions 233a, 233b, 233c, 233d, and 233e that become the source or drain of the P-type nanosheet FET. The portions 233a, 233b, 233c, 233d, and 233e of the active region 231 are connected to the power wiring 211 via vias.

[0149] An active region 235 constituting the channel, source, and drain of the N-type nanosheet FET is formed below the bit line 221 and power supply wiring 223 and above the active region 231. The active region 235 overlaps with the power supply wiring 211, the bit line 221, and the power supply wiring 223 in a planar view. The active region 235 includes nanosheets 236a, 236b, 236c, and 236d extending in the Y direction that become the channel of the N-type nanosheet FET. The active region 235 also includes portions 237a, 237b, 237c, 237d, and 237e that become the source or drain of the N-type nanosheet FET.

[0150] Gate wirings 241, 242, 243, and 244 are formed, extending in parallel in the X direction. The gate wirings 241, 242, 243, and 244 extend in the Z direction from bottom to top. The gate wiring 241 surrounds the outer peripheries of the nanosheets 232a and 236a in the X and Z directions via a gate insulating film (not shown). The gate wiring 242 surrounds the outer peripheries of the nanosheets 232b and 236b in the X and Z directions via a gate insulating film (not shown). The gate wiring 243 surrounds the outer peripheries of the nanosheets 232c and 236c in the X and Z directions via a gate insulating film (not shown). The gate wiring 244 surrounds the outer peripheries of the nanosheets 232d and 236d in the X and Z directions via a gate insulating film (not shown).

[0151] That is, gate wiring 241 corresponds to word line WL0 and is connected to the gate of the nanosheet FET provided in memory cell M00. Gate wiring 242 corresponds to word line WL1 and is connected to the gate of the nanosheet FET provided in memory cell M10. Gate wiring 243 corresponds to word line WL2 and is connected to the gate of the nanosheet FET provided in memory cell M20. Gate wiring 244 corresponds to word line WL3 and is connected to the gate of the nanosheet FET provided in memory cell M30.

[0152] On the upper portion, local interconnections 251, 252, 253, 254, and 255 are formed extending in the X direction. The local interconnections 251, 252, 253, 254, and 255 contact portions 237a, 237b, 237c, 237d, and 237e of the active region 235, respectively.

[0153] Contacts 261, 262, 263, 264, and 265 determine the memory value of the memory cell. In the configuration of FIG. 22 , contact 261 connects local interconnect 251, which is in contact with portion 237a of active region 235, to power supply interconnect 223. Contact 262 connects local interconnect 252, which is in contact with portion 237b of active region 235, to bit line 221. Contact 263 connects local interconnect 253, which is in contact with portion 237c of active region 235, to bit line 221. Contact 264 connects local interconnect 254, which is in contact with portion 237d of active region 235, to power supply interconnect 223. Contact 265 connects local interconnect 255, which is in contact with portion 237e of active region 235, to power supply interconnect 223.

[0154] A memory cell has stored data "1" when both nodes are connected to the VSS power supply line or when both nodes are connected to a bit line. On the other hand, each memory cell has stored data "0" when one node is connected to the VSS power supply line and the other node is connected to a bit line.

[0155] 22, memory cell M00 has one node connected to the VSS power supply line 223 and the other node connected to the bit line 221, and therefore stores data "0." Memory cell M10 has both nodes connected to the bit line 221, and therefore stores data "1." Memory cell M20 has one node connected to the bit line 221 and the other node connected to the VSS power supply line 223, and therefore stores data "0." Memory cell M30 has both nodes connected to the VSS power supply line 223, and therefore stores data "1."

[0156] As described above, in this embodiment, only the N-type nanosheet FET formed in the upper part functions as a transistor of the ROM cell. The P-type nanosheet FET formed in the lower part is a dummy transistor that does not contribute to the function of the ROM cell. Therefore, according to this embodiment, the conductivity types of the upper and lower transistors in the mask ROM cell and the logic cell are the same. Therefore, there is no need to use different manufacturing methods for the mask ROM region and the logic cell region, which makes it possible to suppress increases in manufacturing costs for semiconductor memory devices and semiconductor integrated circuit devices.

[0157] The power supply wiring 211, 212 formed in the BM0 wiring layer, which supplies VDD, is connected only to the node of the lower P-type nanosheet FET within the memory cell. However, the power supply wiring 211, 212 does not have to be connected to the transistor within the memory cell. In this case, for example, the power supply wiring 211, 212 may supply VSS and be connected to the VSS wiring of the M1 wiring layer outside the memory cell array. In this case, the power supply strengthening can suppress power supply voltage drops, thereby improving the speed and stability of mask ROM operation. Furthermore, the power supply wiring 211, 212 in the BM0 wiring layer is formed for each bit string, but for example, the power supply wiring may be formed integrally for multiple bit strings.

[0158] 23 is a circuit diagram showing the configuration of a contact-type mask ROM according to Modification 1 and subsequent modifications of the second embodiment. In the configuration of Fig. 23, unlike the configuration of Fig. 21, the column decoder 2X and the memory cell array 3AX are configured using P-type MOS transistors.

[0159] The memory cell array 3AX is configured by arranging memory cells Mij (i = 0 to m, j = 0 to n) of P-type MOS transistors in a matrix. The gates of the memory cells Mij are connected to word lines NWLi in common in the row direction. The source and drain of the memory cell Mij are connected to bit lines BLj or to a power supply line VDD. When the data stored in the memory cell Mij is set to "1", one of the source and drain is connected to the bit line BLj and the other is connected to the power supply line VDD. On the other hand, when the data stored in the memory cell Mij is set to "0", both the source and drain are connected to the bit line BLj or the power supply line VDD.

[0160] The column decoder 2X is composed of P-type MOS transistors Cj, whose drains are all connected in common, whose gates are connected to respective column selection signal lines NCLj, and whose sources are connected to respective bit lines BLj.

[0161] The sense amplifier 18X includes a precharge N-type MOS transistor 5X, an inverter 8 that determines the output data of the memory cell Mij, and an inverter 9 that buffers the output signal of the inverter 8. A precharge signal PR is input to the gate of the N-type MOS transistor 5X, a power supply voltage VSS is supplied to the source, and the drain is connected to the common drain of the P-type MOS transistor Cj. The inverter 8 receives a signal SIN from the common drain of the P-type MOS transistor Cj and determines the output data of the memory cell Mij. The inverter 9 receives an output signal SOUT from the inverter 8 and outputs the stored data of the memory cell Mij.

[0162] The operation of the mask ROM shown in Fig. 23 will be described below, taking as an example the case where data is read from memory cells M00 and M10.

[0163] First, among the column selection signal lines NCLj, NCL0 is set to low level and the other NCL1 to NCLn are set to high level. As a result, among the transistors constituting the column decoder 2X, C0 is turned on and the other C1 to Cn are turned off. Also, the word line NWL0 is transitioned from high level, which indicates a non-selected state, to low level, which indicates a selected state.

[0164] Next, the precharge signal PR is changed from low level to high level, and the precharge N-type MOS transistor 5X is turned on.

[0165] One of the source and drain of memory cell M00 is connected to bit line BL0, and the other is connected to power supply wiring VDD. Therefore, current flows from power supply wiring VDD to bit line BL0 via memory cell M00, and input signal SIN of inverter 8 becomes a voltage higher than the switching level of inverter 8. As a result, output signal SOUT of inverter 8 becomes low level, and output signal OUT of inverter 9 remains high level.

[0166] When data in the memory cell M10 is to be read, the word line NWL1 is transitioned from a high level indicating a non-selected state to a low level indicating a selected state.

[0167] Both the source and drain of memory cell M10 are connected to bit line BL0. Therefore, no current flows through bit line BL0, and input signal SIN of inverter 8 becomes a voltage lower than the switching level of inverter 8. As a result, output signal SOUT of inverter 8 remains high, and output signal OUT of inverter 9 remains low.

[0168] That is, when one of the source and drain of the memory cell is connected to a bit line and the other is connected to a power supply line, a high level is output (storage data "1"), and when both the source and drain of the memory cell are connected to a bit line or a power supply line, a low level is output (storage data "0").

[0169] 24A and 24B are diagrams showing an example of the layout structure of a mask ROM according to Modification 1 of the second embodiment, where (a) is the lower part and (b) is the upper part. In this modification, a P-type nanosheet FET that functions as a memory cell is formed in the lower part, and no transistor is formed in the upper part.

[0170] 24, power supply wirings 213 and 214 extending in the Y direction are formed in the BM0 wiring layer. The power supply wirings 213 and 214 supply VDD.

[0171] In the M1 wiring layer, bit lines 225 and 226 extending in the Y direction and power supply lines 227 and 228 extending in the Y direction are formed. The bit lines 225 and 226 correspond to the bit lines BL0 and BL1, respectively. The power supply lines 227 and 228 supply VDD.

[0172] An active region 231 is formed in the lower portion, similar to the configuration in Fig. 22. On the other hand, no active region 235 is formed in the upper portion.

[0173] Gate wiring 241 surrounds the outer peripheries of nanosheet 232a in the X and Z directions via a gate insulating film (not shown). Gate wiring 242 surrounds the outer peripheries of nanosheet 232b in the X and Z directions via a gate insulating film (not shown). Gate wiring 243 surrounds the outer peripheries of nanosheet 232c in the X and Z directions via a gate insulating film (not shown). Gate wiring 244 surrounds the outer peripheries of nanosheet 232d in the X and Z directions via a gate insulating film (not shown).

[0174] Local interconnections 256, 257, 258, 259, and 260 are formed at the bottom, extending in the X direction. The local interconnections 256, 257, 258, 259, and 260 contact portions 233a, 233b, 233c, 233d, and 233e of the active region 231, respectively.

[0175] Contacts 271, 272, 273, 274, and 275 determine the memory value of the memory cell. In the configuration of FIG. 24 , contact 271 connects local interconnect 256, which is in contact with portion 233a of active region 231, to power supply interconnect 227. Contact 272 connects local interconnect 257, which is in contact with portion 233b of active region 231, to bit line 225. Contact 273 connects local interconnect 258, which is in contact with portion 233c of active region 231, to bit line 225. Contact 274 connects local interconnect 259, which is in contact with portion 233d of active region 231, to power supply interconnect 227. Contact 275 connects local interconnect 260, which is in contact with portion 233e of active region 231, to power supply interconnect 227.

[0176] 24, memory cell M00 has one node connected to VDD power supply wiring 227 and the other node connected to bit line 225, and therefore stores data "1". Memory cell M10 has both nodes connected to bit line 225, and therefore stores data "0". Memory cell M20 has one node connected to bit line 225 and the other node connected to VDD power supply wiring 227, and therefore stores data "1". Memory cell M30 has both nodes connected to VDD power supply wiring 227, and therefore stores data "0".

[0177] According to this modification, the node of the lower P-type nanosheet FET that functions as a transistor of the ROM cell is connected to the bit line without going through the upper active region, which enables the reduction of the resistance of the bit line and the increase in operation speed.

[0178] (Modification 2) FIGS. 25A and 25B are diagrams showing an example of the layout structure of a mask ROM according to Modification 2 of the second embodiment, where (a) is the lower part and (b) is the upper part.

[0179] This modification is different from the first modification in that bit lines, rather than power supply lines, are formed in the back wiring layer.

[0180] 25, bit lines 215 and 216 extending in the Y direction are formed in the BM0 wiring layer. The bit lines 215 and 216 correspond to bit lines BL0 and BL1, respectively. Power supply lines 229 and 230 extending in the Y direction are formed in the M1 wiring layer. The power supply lines 229 and 230 supply VDD.

[0181] As in FIG. 24, an active region 231, gate wirings 241, 242, 243, and 244, and local wirings 256, 257, 258, 259, and 260 are formed.

[0182] Contacts 281, 282, 291, 292, and 293 determine the memory value of the memory cell. In the configuration of FIG. 25 , contact 291 connects local interconnect 256, which is in contact with portion 233a of active region 231, to power supply interconnect 229 in the M1 wiring layer. Contact 281 connects portion 233b of active region 231 to bit line 215 in the BM0 wiring layer. Contact 282 connects portion 233c of active region 231 to bit line 215 in the BM0 wiring layer. Contact 292 connects local interconnect 259, which is in contact with portion 233d of active region 231, to power supply interconnect 229 in the M1 wiring layer. Contact 293 connects local interconnect 260, which is in contact with portion 233e of active region 231, to power supply interconnect 229 in the M1 wiring layer.

[0183] 25, memory cell M00 has one node connected to VDD power supply wiring 229 and the other node connected to bit line 215, and therefore stores data "1". Memory cell M10 has both nodes connected to bit line 215, and therefore stores data "0". Memory cell M20 has one node connected to bit line 215 and the other node connected to VDD power supply wiring 229, and therefore stores data "1". Memory cell M30 has both nodes connected to VDD power supply wiring 229, and therefore stores data "0".

[0184] In this modification, the wiring layers of the bit lines and the power supply wiring may be interchanged, with the VDD power supply wiring formed in the BM0 wiring layer and the bit lines formed in the M1 wiring layer.

[0185] In the above description, the nanosheet FET has two sheets that overlap in a planar view, and the cross-sectional shape of the sheets is rectangular, but the number and cross-sectional shape of the nanosheets of the nanosheet FET are not limited to this.

[0186] In the present disclosure, CFETs are used for semiconductor memory devices having ROM memory cells and semiconductor integrated circuit devices having ROM memory cells and logic cells, and manufacturing costs can be reduced, which is useful for reducing the costs of SoCs (System on Chip), for example.

[0187] 11, 12 Power supply wiring 13, 14 Bit lines 16a, 16b, 16c Bit lines 17, 18 Power supply wiring 21, 22 Bit lines 24, 25 Power supply wiring 26a, 26b, 26c Bit lines 27, 28 Power supply wiring 31, 35 Active area 32a, 32b, 36a, 36b Nanosheet 41, 42 Gate wiring 111, 112 Power supply wiring 113, 114 Bit lines 116a, 116b, 116c Bit lines 121, 122 Bit lines 124, 125 Power supply wiring 126a, 126b, 126c Bit lines 131, 135 Active area 132a, 132b, 136a, 136b Nanosheet 141, 142 Gate wiring 211, 212 Power supply wiring 221, 222 Bit lines 223, 224 Power supply wiring 231, 235 Active areas 232a, 232b, 232c, 232d, 236a, 236b, 236c, 236d Nanosheets 241, 242, 243, 244 Word lines BLi (i is an integer) Bit lines Mij (i, j are integers) Memory cells WLi (i is an integer) Word lines NWLi (i is an integer) Word lines

Claims

1. A semiconductor memory device having a ROM (Read Only Memory) memory cell, the semiconductor memory device comprising: word lines extending in a first direction; bit lines extending in a second direction perpendicular to the first direction; and power supply wiring extending in the second direction, wherein the ROM memory cell comprises: a first nanosheet FET of a first conductivity type, the channel, source, and drain of which are formed by a first active region, a first nanosheet included in the first active region and extending in the second direction serving as the channel, and a gate connected to the word line; and a second nanosheet FET of a second conductivity type, the channel, source, and drain of which are formed by a second active region, a second nanosheet included in the second active region and extending in the second direction serving as the channel, and a gate connected to the word line, wherein the first nanosheet and the second nanosheet overlap in a planar view, and the second nanosheet FET is a dummy transistor that does not contribute to the function of the ROM memory cell, The ROM memory cell is a semiconductor memory device in which data is stored depending on the connection state between the source and drain of the first nanosheet FET and the bit line and the power supply wiring.

2. A semiconductor memory device according to claim 1, wherein the first nanosheet FET is located above the second nanosheet FET.

3. A semiconductor memory device according to claim 2, wherein the bit line is formed in a wiring layer on the surface side of the first and second nanosheet FETs, the power supply wiring is formed in a wiring layer on the back side of the first and second nanosheet FETs, the drain of the first nanosheet FET is connected to the bit line, the source of the first nanosheet FET is connected to the second active region, and the ROM memory cell stores data depending on whether or not there is an electrical connection between the second active region and the power supply wiring.

4. A semiconductor memory device according to claim 3, wherein second bit lines extending in the second direction are formed in a wiring layer in which the power supply wiring is formed.

5. A semiconductor memory device according to claim 2, wherein the bit line is formed in a wiring layer on the back side of the first and second nanosheet FETs, the power supply wiring is formed in a wiring layer on the front side of the first and second nanosheet FETs, the drain of the first nanosheet FET is connected to the bit line via the second active region, and the ROM memory cell stores data depending on whether or not there is an electrical connection between the source of the first nanosheet FET and the power supply wiring.

6. A semiconductor memory device according to claim 5, wherein second bit lines extending in the second direction are formed in a wiring layer in which the power supply wiring is formed.

7. A semiconductor memory device according to claim 2, wherein the bit line is formed in a wiring layer on the surface side of the first and second nanosheet FETs, the power supply wiring is formed in the same wiring layer as the bit line, the drain of the first nanosheet FET is connected to the bit line, and the ROM memory cell stores data depending on whether or not there is an electrical connection between the source of the first nanosheet FET and the power supply wiring.

8. A semiconductor memory device according to claim 7, further comprising a second power supply wiring formed in a wiring layer on the back side of the first and second nanosheet FETs, wherein the source and drain of the second nanosheet FET are connected to the second power supply wiring.

9. A semiconductor memory device according to claim 2, wherein the bit lines are formed in a wiring layer on the surface side of the first and second nanosheet FETs, the power supply wiring is formed in the same wiring layer as the bit lines, and the ROM memory cells store data depending on whether the source and drain of the first nanosheet FET are connected to the same or different lines from the bit line and the power supply wiring.

10. A semiconductor memory device according to claim 1, wherein the first nanosheet FET is located below the second nanosheet FET.

11. A semiconductor memory device according to claim 10, wherein the bit line is formed in a wiring layer on the surface side of the first and second nanosheet FETs, the power supply wiring is formed in a wiring layer on the back side of the first and second nanosheet FETs, the drain of the first nanosheet FET is connected to the bit line via the second active region, and the ROM memory cell stores data depending on whether or not there is an electrical connection between the source of the first nanosheet FET and the power supply wiring.

12. A semiconductor memory device according to claim 11, wherein second bit lines extending in the second direction are formed in a wiring layer in which the power supply wiring is formed.

13. A semiconductor memory device according to claim 10, wherein the bit line is formed in a wiring layer on the back side of the first and second nanosheet FETs, the power supply wiring is formed in a wiring layer on the front side of the first and second nanosheet FETs, the drain of the first nanosheet FET is connected to the bit line, the source of the first nanosheet FET is connected to the second active region, and the ROM memory cell stores data depending on whether or not there is an electrical connection between the second active region and the power supply wiring.

14. A semiconductor memory device according to claim 13, wherein second bit lines extending in the second direction are formed in a wiring layer in which the power supply wiring is formed.

15. A semiconductor integrated circuit device comprising a ROM (Read Only Memory) memory cell and a logic cell, the device comprising: word lines extending in a first direction; bit lines extending in a second direction perpendicular to the first direction; and power supply wiring extending in the second direction; the logic cell comprising: a first nanosheet FET of a first conductivity type; and a second nanosheet FET of a second conductivity type located above the first nanosheet FET and overlapping the first nanosheet FET in a planar view; the ROM memory cell comprising: a third nanosheet FET of the first conductivity type located at the same position in the depth direction as the first nanosheet FET, the channel, source, and drain being formed by a first active region, the first nanosheet extending in the second direction included in the first active region serving as the channel, and the gate being connected to the word line; and in the ROM memory cell, no nanosheet FET is formed at the same position in the depth direction as the second nanosheet FET, The ROM memory cell is a semiconductor integrated circuit device in which data is stored depending on the connection state between the source and drain of the third nanosheet FET and the bit line and the power supply wiring.

16. A semiconductor integrated circuit device according to claim 15, wherein the bit line is formed in a wiring layer on the surface side of the first, second and third nanosheet FETs, the power supply wiring is formed in a wiring layer on the back side of the first, second and third nanosheet FETs, the drain of the third nanosheet FET is connected to the bit line, and the ROM memory cell stores data depending on whether or not there is an electrical connection between the source of the third nanosheet FET and the power supply wiring.

17. A semiconductor integrated circuit device according to claim 15, wherein the bit line is formed in a wiring layer on the back side of the first, second and third nanosheet FETs, the power supply wiring is formed in a wiring layer on the front side of the first, second and third nanosheet FETs, the drain of the third nanosheet FET is connected to the bit line, and the ROM memory cell stores data depending on whether or not there is an electrical connection between the source of the third nanosheet FET and the power supply wiring.

18. A semiconductor integrated circuit device according to claim 15, wherein the bit lines are formed in a wiring layer on the surface side of the first, second and third nanosheet FETs, the power supply wiring is formed in the same wiring layer as the bit lines, and the ROM memory cell stores data depending on whether the source and drain of the third nanosheet FET are connected to the same or different lines among the bit lines and the power supply wiring.

19. A semiconductor integrated circuit device according to claim 15, wherein the bit line is formed in either a first wiring layer on the back side of the first, second and third nanosheet FETs or a second wiring layer on the front side of the first, second and third nanosheet FETs, the power supply wiring is formed in the other of the first wiring layer or the second wiring layer, and the ROM memory cell stores data depending on whether the source and drain of the third nanosheet FET are connected to the same line or different lines among the bit line and the power supply wiring.

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