Display device and operation method therefor

Abstract

A display device and an operation method therefor are provided. The display device comprises: a transmission circuit; a reception circuit; a transmission / reception interface for connecting the reception circuit and the transmission circuit; a memory for storing one or more instructions; and at least one processor for executing the one or more instructions stored in the memory, wherein the one or more instructions are executed individually or in combination by the at least one processor, so that the display device identifies a frame rate of an input image, adjusts a clock parameter of a clock signal to generate an adjusted clock signal on the basis of the identified frame rate, and transmits, from the transmission circuit to the reception circuit through the transmission / reception interface, a data signal generated on the basis of the adjusted clock signal and image data corresponding to the input image.

Description

Display device and method of operation thereof

[0001] The present disclosure relates to a display device and a method of operating the display device. More particularly, the present disclosure relates to a display device and a method of operating the display device that varies a clock signal.

[0002] A display device processes image signals or image data received from an external source using various image processing processes. The display device can display the processed image signals as images on a display panel.

[0003] Image data can be transmitted from a transmitter to a receiver via a standardized interface. The transmitter and receiver may each be implemented as a device or a board. An example of image data being transmitted between boards is when the image processing board within a device is output to a timing controller board. Various transmission / reception interface standards for transmitting image data have been proposed.

[0004] For example, the transmission / reception interface for transmitting video data may include an LVDS (Low-Voltage Differential Signaling) interface, a DVI (Digital Video Interface) interface, an HDMI (High Definition Multimedia Interface) interface, a DisplayPort (DP) interface, and a V-by-One interface.

[0005] Here, the V-by-One interface (or, referred to as the 'Vx1 interface') has a form that adopts a clock embedded method that transmits data signals and clock information through a single signal line. The clock embedded method embeds clock information in the data signal, extracts the clock information from the CDR (Clock Data Recovery) circuit of the receiver, and synchronizes the image data to the clock information. Since the V-by-One interface does not transmit a separate clock from the transmitter, it solves problems that occur in the LVDS interface that transmits data signals and clock signals through separate signal lines (for example, the skew adjustment problem caused by clock transmission).

[0006] Meanwhile, conventional display devices can process and transmit image data using a fixed clock. Here, the clock can indicate the speed at which image data, which is a digital signal, is transmitted. The clock used to transmit image data can be synchronized with the image's frame rate, providing timing for transmitting a certain amount of image data each time the display panel screen is refreshed. Conventional display devices primarily reduce power consumption through backlighting or screen settings, but have limitations in that they cannot directly reduce power consumption during signal processing or transmission.

[0007] Furthermore, conventional displays used a fixed clock frequency tuned to high frame rates, resulting in unnecessarily high power consumption even when the frame rate of the image input to the display device was low. This was particularly problematic when playing low-frame-rate content, resulting in energy waste.

[0008] According to one embodiment of the present disclosure, a display device includes a transmitting circuit, a receiving circuit, a transmitting / receiving interface connecting the receiving circuit and the transmitting circuit, a memory storing one or more instructions, and at least one processor executing one or more instructions stored in the memory. The display device identifies a frame rate of an input image by individually or in combination executing the one or more instructions by the at least one processor. The display device adjusts a clock parameter of a clock signal to generate an adjusted clock signal based on the identified frame rate by individually or in combination executing the one or more instructions by the at least one processor. The display device transmits a data signal generated based on the adjusted clock signal and image data corresponding to the input image from the transmitting circuit to the receiving circuit through the transmitting / receiving interface.

[0009] According to one embodiment of the present disclosure, a method of operating a display device including a transmitting circuit, a receiving circuit, and a transmitting / receiving interface connecting the transmitting circuit and the receiving circuit includes the steps of identifying a frame rate of an input image, adjusting a clock parameter of a clock signal to generate an adjusted clock signal based on the identified frame rate, and transmitting a data signal generated based on the adjusted clock signal and image data corresponding to the input image from the transmitting circuit to the receiving circuit through the transmitting / receiving interface.

[0010] In one embodiment of the present disclosure, a computer-readable recording medium is provided having recorded thereon instructions that operate an electronic device when individually or collectively executed by at least one processor to identify a frame rate of an input image, adjust a clock parameter of a clock signal to generate an adjusted clock signal based on the identified frame rate, and transmit a data signal generated based on the adjusted clock signal and image data corresponding to the input image from a transmitting circuit to a receiving circuit through a transmitting / receiving interface.

[0011] The present disclosure can be readily understood by the following detailed description and its accompanying drawings, wherein reference numerals refer to structural elements.

[0012] FIG. 1 is a diagram for explaining an operation of generating different clock signals according to the frame rate of content input to a display device according to one embodiment of the present disclosure.

[0013] FIG. 2 is a schematic block diagram of a display device according to one embodiment of the present disclosure.

[0014] FIG. 3 is a block diagram of a configuration for signal transmission between a first board and a second board through a transmission / reception interface of a display device according to one embodiment of the present disclosure.

[0015] FIG. 4 is a block diagram of a configuration for adjusting a clock parameter of a clock signal in a display device according to one embodiment of the present disclosure.

[0016] FIG. 5 is a drawing for explaining the form of a data signal transmitted by a transmission / reception interface according to one embodiment of the present disclosure.

[0017] FIG. 6 is a flowchart for explaining the operation of a display device according to one embodiment of the present disclosure.

[0018] FIG. 7 is a flowchart illustrating an operation of a display device according to one embodiment of the present disclosure to adjust clock parameters and generate a clock signal.

[0019] FIG. 8 is a table showing an example of clock parameters adjusted according to the frame rate of an input image, according to one embodiment of the present disclosure.

[0020] FIG. 9 is an example of a data signal with adjusted clock parameters according to one embodiment of the present disclosure.

[0021] FIG. 10 is a detailed flowchart for explaining an operation of a display device according to one embodiment of the present disclosure to generate different clock signals depending on the frame rate of content.

[0022] FIG. 11 is an example of an operation of transmitting a signal through a transmission / reception interface of a display device according to one embodiment of the present disclosure.

[0023] FIG. 12 is an example of an operation of transmitting a signal through a transmission / reception interface of a display device according to one embodiment of the present disclosure.

[0024] FIG. 13 is a drawing for explaining the operation of a display device when an image input to the display device according to one embodiment of the present disclosure is changed.

[0025] FIG. 14 is a detailed flowchart for explaining an operation of a display device according to one embodiment of the present disclosure to generate different clock signals depending on the frame rate of content.

[0026] FIG. 15 is a detailed block diagram of a display device according to one embodiment of the present disclosure.

[0027] In this disclosure, the expression “at least one of a, b or c” may refer to “a”, “b”, “c”, “a and b”, “a and c”, “b and c”, “all of a, b and c”, or variations thereof.

[0028] In the present disclosure, when a first element and a second element are “connected,” it may be referred to as the first element being “connected” to the second element, and it may also be referred to as the second element being “connected” to the first element.

[0029] In accordance with the conventions of the art, embodiments of the present invention are described and illustrated in the drawings in the form of functional blocks, units (or, ... portions) and / or modules. Those skilled in the art will understand that such blocks, units and / or modules may be physically implemented by electronic (or optical) circuits such as logical circuits, discrete components, microprocessors, hard-wired circuits, memory elements, wiring connections, etc., and that these may be formed using semiconductor-based manufacturing techniques or other manufacturing techniques. When such blocks, units and / or modules are implemented by a microprocessor or the like, they may be programmed using software (e.g., microcode) to perform various functions, and may optionally be driven by firmware and / or software. In another example, each block, unit, and / or module may be implemented by dedicated hardware that performs a specific function, or may be implemented in a combination in which some functions are performed by dedicated hardware and other functions are performed by a processor (e.g., one or more programmed microprocessors and associated circuitry). Furthermore, each block, unit, and / or module of the embodiments of the present disclosure may be physically separated into two or more interacting individual blocks, units, and / or modules, without departing from the scope of the present disclosure. Furthermore, the blocks, units, and / or modules of the embodiments of the present disclosure may be physically combined to be implemented as more complex blocks, units, and / or modules, without departing from the scope of the present disclosure.

[0030] In this disclosure, the expression “in response to an event or occurrence” may mean that the action or operation occurs directly or indirectly in response to or based on the event or occurrence.

[0031] Below, embodiments of the present disclosure are described in detail with reference to the attached drawings so that those skilled in the art can easily implement the present disclosure. However, the present disclosure may be implemented in various different forms and is not limited to the embodiments described herein.

[0032] Although the functions mentioned in this disclosure are described using commonly used terms, they may refer to various other terms depending on the intentions of those skilled in the art, precedents, the emergence of new technologies, etc. Therefore, the terms used in this disclosure should not be interpreted solely based on their names, but rather based on the meanings of the terms and the overall content of this disclosure.

[0033] Additionally, the terminology used in this disclosure is for the purpose of describing specific embodiments only and is not intended to limit the present disclosure.

[0034] When a part of the specification is said to "include" a component, this does not exclude other components, but rather implies the inclusion of other components, unless otherwise specifically stated. Furthermore, terms such as "part," "module," etc., used throughout the specification refer to a unit that processes at least one function or operation, which may be implemented in hardware, software, or a combination of hardware and software.

[0035] Additionally, when a component is referred to as being “connected” or “connected” to another component in the present disclosure, it should be understood that the component may be directly connected or connected to the other component, but may also be connected or connected via another component in between, unless otherwise specifically stated.

[0036] Below, with reference to the attached drawings, embodiments of the present invention are described in detail so that those skilled in the art can easily implement the present invention. However, the present invention can be implemented in various different forms and is not limited to the embodiments described herein. In the drawings, parts irrelevant to the description have been omitted to clearly explain the present invention, and similar parts have been designated with similar reference numerals throughout the specification.

[0037] In this disclosure, a "processor" may include various processing circuits and / or multiple processors. For example, the term "processor" as used herein, including in the claims, may include various processing circuits, including at least one processor. One or more processors in at least one processor may be configured to perform various functions described herein, individually and / or collectively, in a distributed fashion. As used herein, "processor," "at least one processor," and "one or more processors" may be configured to perform various functions. However, these terms encompass, without limitation, situations where one processor performs some of the functions and other processor(s) perform other parts of the functions, and situations where a single processor may perform all of the functions. Furthermore, at least one processor may include a combination of processors that perform various functions of the disclosed functions in a distributed manner. At least one processor may execute program instructions to achieve or perform various functions.

[0038] In this disclosure, the term “user” means a person who controls a system, function, or operation, and may include a developer, an administrator, an installer, or a repair technician.

[0039] In the present disclosure, an 'image' may include a still image, a graphic, a picture, a frame, a moving image composed of a plurality of consecutive still images, or a video.

[0040] The present disclosure will be described in detail with reference to the attached drawings below.

[0041] FIG. 1 is a diagram for explaining an operation of generating different clock signals according to the frame rate of content input to a display device according to one embodiment of the present disclosure.

[0042] Referring to FIG. 1, in one embodiment of the present disclosure, a display device (100) may be a device that displays an image and provides it to a user. For example, the display device (100) may include at least one of a TV, a smartphone, a tablet PC, a digital camera, a camcorder, a laptop computer, a desktop, an e-book reader, a digital broadcasting terminal, a PDA (Personal Digital Assistants), a PMP (Portable Multimedia Player), a navigation device, an MP3 player, a wearable device, a smart watch, a home network system, a security system, a medical device, a head-mounted display (HMD), a hemispherical display, a large display, and a projector display.

[0043] In one embodiment of the present disclosure, the display device (100) can process image data received from the outside according to various image processing processes. The display device (100) can display the processed image data as an image on the display. The image input to the display device (100) can include a plurality of frames. Each image has a predetermined frame rate, and the frame rate can indicate the number of frames per second or the speed at which the frames are played. The display device (100) can refresh the image in each of the plurality of frames and display it on the display.

[0044] In one embodiment of the present disclosure, a display device (100) may include an image processing board (10) that processes image data, a timing controller board (20) that generates a driving control signal corresponding to the image data transmitted from the image processing board (10), and a display panel (30) that displays the image data as an image according to the driving control signal output from the timing controller board (20). However, the board structure inside the display device (100) is not limited thereto. For example, in FIG. 1, the image processing board (10) and the timing controller board (20) are illustrated as being implemented as separate boards, but the image processing board (10) and the timing controller board (20) may be implemented as one board. Or, for example, the timing controller board (20) and the display panel (30) may be implemented as one board.

[0045] According to one embodiment of the present disclosure, the image processing board (10), the timing controller board (20), and the display panel (30) may each be, or may include, a circuit board (e.g., a printed circuit board) on which one or more components or elements are mounted or otherwise attached. However, the present invention is not limited thereto. For example, in one embodiment, at least one of the image processing board (10), the timing controller board (20), and the display panel (30) may be, or may include, a “unit” or a “module” as described above. For example, in one embodiment, the image processing board (10) may be, or may include, an image processing unit or an image processing module, the timing controller board (20) may be, or may include, a timing controller unit or a timing controller module, and the display panel (30) may be, or may include, a display unit or a display module.

[0046] In one embodiment of the present disclosure, the image processing board (10), the timing controller board (20), and the display panel (30) can transmit and receive images by being connected through various types of transmission / reception interfaces (e.g., transmission / reception interface (50), transmission / reception interface (60)). The transmission / reception interface can be implemented as, for example, a cable, and each of the transmission board and the reception board can include one or more signal input / output ports for cable connection. Depending on the type of the transmission / reception interface, the format of the data signal exchanged between the transmission board and the reception board can be different. One or more signal input / output ports can transmit or receive a data signal corresponding to the standard of the connected transmission / reception interface.

[0047] For example, the display device (100) may include a transmission / reception interface (50) connecting between an image processing board (10) and a timing controller board (20) and a transmission / reception interface (60) connecting between the timing controller board (20) and a display panel (30). Through the transmission / reception interface, data may be transmitted from the image processing board (10) to the timing controller board (20) and also from the timing controller board (20) to the display panel (30).

[0048] The image processing board (10) can process an image input to the display device (100) according to various image processing processes and output the processed image data to the timing controller board (20). The image processing process performed in the image processing board (10) can include, for example, de-multiplexing that divides an input transmission stream into each sub-stream of an image signal, an audio signal, and additional data, decoding corresponding to the image format of the image signal, scaling that adjusts the image signal to a preset resolution, noise reduction for improving image quality, detail enhancement, frame rate conversion, etc.

[0049] In addition to the aforementioned image processing process, the image processing board (10) can perform various processes depending on the type and characteristics of data. The image processing board (10) can be implemented by integrating such functions into a single chip, or by mounting individual chip sets capable of independently performing each process on a printed circuit board. The image processing board (10) can include at least one processor for performing various processes.

[0050] The timing controller board (20) includes a timing controller, and can control the amount of data transmitted to the display panel (30) and control each driving circuit included in the display panel (30). The timing controller board (20) can transmit image data received from the image processing board (10) to each driving circuit. The timing controller board (20) may be referred to as a T-con board.

[0051] The display panel (30) may include a pixel array and a driving circuit for driving the pixel array. The driving circuit drives the display panel (30) using image data received from the timing controller board (20), and the display panel (30) may display the image data as an image.

[0052] In one embodiment of the present disclosure, the display device (100) can process and transmit a certain amount of image data using a clock. Here, the clock can provide timing for processing and transmitting data in a digital signal. For example, the clock can be synchronized with the frame rate of an image to provide timing for transmitting a certain amount of image data each time the screen of the display panel is refreshed. Here, the clock frequency (or frequency of the clock signal) is a value indicating how many cycles the clock signal generates per second, and can determine the speed of transmitting image data (i.e., data transmission speed) and data processing speed through the transmission / reception interface. For example, when the clock frequency decreases, the clock speed decreases, and the transmission speed of image data may decrease. For example, when the clock frequency increases, the clock speed increases, and the transmission speed of image data may increase. That is, the data transmission speed of the data signal can be adjusted based on the adjusted clock frequency.

[0053] The frame rate of an image input to the display device (100) according to one embodiment of the present disclosure may be variable. For example, the display device (100) may process / transmit a high frame rate image and then process / transmit a low frame rate image, or conversely, may process / transmit a low frame rate image and then process / transmit a high frame rate image. In this case, if the display device (100) processes / transmits a low frame rate image using the same clock frequency as that used while processing / transmitting a high frame rate image, unnecessary power consumption may occur. For example, assume a case where a clock frequency of 95 MHz is used to transmit 165 Hz image data from a transmission circuit to a reception circuit, and the frame rate of the image is changed to 60 Hz. If the transmission circuit transmits 60 Hz image data to the reception circuit using a fixed clock frequency of 95 MHz, the amount of data transmitted per second decreases, resulting in a decrease in efficiency and an increase in power consumption.

[0054] In order to reduce the power consumption described above, the display device (100) according to one embodiment of the present disclosure may generate clock signals having different frequencies according to changes in the frame rate of an input image. For example, the display device (100) may identify or detect the frame rate of the input image. Based on the identified frame rate, the display device (100) may generate a clock signal having an adjusted clock frequency (e.g., an adjusted clock signal having an adjusted clock frequency). The display device (100) may transmit a data signal corresponding to the adjusted clock frequency from a transmission circuit to a reception circuit through a transmission / reception interface. Here, when the transmission circuit is included in the image processing board (10), the reception circuit may be included in the timing controller board (20), and when the transmission circuit is included in the timing controller board (20), the reception circuit may be included in the display panel (30).

[0055] For example, if the display device (100) determines that the changed frame rate is a low frame rate, it can generate a clock signal having a low frequency. Also, for example, if the display device (100) determines that the changed frame rate is a high frame rate, it can generate a clock signal having a high frequency. The terms “low” and “high” used herein may be relative terms. For example, a “low” frequency may mean a first frequency, and a “high” frequency may mean a second frequency higher than the first frequency. Similarly, a “low” frame rate may mean the first frame rate, and a “high” frame rate may mean a second frame rate higher than the first frame rate. The display device (100) may transmit and receive image data according to the speed of the clock signal having the changed frequency. That is, the display device (100) may adjust the transmission speed of the data signal according to the frame rate of the input image.

[0056] For example, in FIG. 1, the image processing board (10) can transmit a data signal to the timing controller board (20) through the transmission / reception interface (50) according to the speed of the clock signal. When the frame rate of the input image is changed from a high frame rate to a low frame rate, the image processing board (10) can generate a clock signal having a low frequency and transmit the data signal to the timing controller board (20) at a slow speed. Conversely, when the frame rate of the input image is changed from a low frame rate to a high frame rate, the image processing board (10) can generate a clock signal having a high frequency and transmit the data signal to the timing controller board (20) at a fast speed.

[0057] Here, when the frequency of the clock signal decreases, the clock speed decreases, and as the clock speed decreases, the power consumption of the display device (100) may decrease. This is because the switching power, leakage power, and dynamic power of the display device (100) decrease as the clock speed decreases. For example, switching power is the power consumed when the transistors within the device turn on and off, and as the clock speed increases, the switching power may increase because the switching frequency of the transistors increases. For example, in the case of leakage power, the leakage power may increase because as the clock speed increases, more transistors are activated simultaneously. For example, in the case of dynamic power, as the clock speed increases, the amount of data that can be processed increases, and this increases the load on the circuit being processed, so the dynamic power may increase.

[0058] In addition, the display device (100) according to one embodiment of the present disclosure may adjust the clock parameter of the clock signal according to a change in the frame rate of the input image in order to reduce the power consumption described above. Here, the clock parameter is for defining the characteristics and operation of the clock signal, and may include at least one of the clock frequency of the clock signal, the voltage strength of the clock signal, or the ratio of the SSC (Spread Spectrum Clocking) of the clock signal. Here, the voltage strength of the clock signal is re-expressed as a voltage level, and may mean the voltage value in the 'high' state and the 'low' state of the clock signal (e.g., the logic high and logic low states of the clock signal). Here, the SSC is a technology for reducing EMI (Electromagnetic Interference) by adjusting the variable range of the clock frequency, and the variable range of the clock frequency can be adjusted through the SSC ratio of the clock signal. For example, when applying 0.1% SSC to a 100 mHz clock, the clock speed can be spread to about 99.5 mHz to 100.5 mHz. However, without limitation, the clock parameters may further include the period, duty cycle, phase, waveform shape, transition time, etc. of the clock signal.

[0059] For example, the display device (100) can generate clock signals having different voltage levels depending on changes in the frame rate of the input image. For example, if the display device (100) determines that the changed frame rate is a low frame rate, it can generate a clock signal having a low voltage level. In addition, for example, if the display device (100) determines that the changed frame rate is a high frame rate, it can generate a clock signal having a high voltage level. The display device (100) can transmit and receive image data through a transmission / reception interface in response to the clock signal having the changed voltage level.

[0060] For example, the display device (100) can set a different SSC application ratio of the clock signal depending on a change in the frame rate of the input image. For example, if the display device (100) determines that the changed frame rate is a low frame rate, it can generate a clock signal to which a high SSC ratio is applied. In addition, for example, if the display device (100) determines that the changed frame rate is a high frame rate, it can apply a low SSC ratio or generate a clock signal to which no SSC ratio is applied. The display device (100) can transmit and receive image data through a transmission / reception interface in response to a clock signal having a changed SSC ratio.

[0061] Here, when the clock speed decreases, the eye margin of the clock signal widens, so that the signal transmission becomes stable, and the signal can be transmitted stably even with a relatively low voltage level. Accordingly, when the clock speed decreases, the voltage level of the clock signal can be lowered. When the voltage level is reduced, power consumption can be reduced. In addition, when the eye margin of the clock signal widens, the effect on signal quality can be reduced even if more SSC is applied. As the ratio of SSC increases, EMI is reduced as electromagnetic energy is dispersed, and as system efficiency improves, power consumption can be reduced. Here, the improved system efficiency can mean a reduction in protection circuit and filter load, improved signal integrity, error minimization, and signal interference minimization.

[0062] Meanwhile, in one embodiment of the present disclosure, in order for high-resolution image data to be transmitted between a transmitting circuit and a receiving circuit, a pre-agreed transmission / reception interface standard may be applied. In this case, the display device (100) may convert the image data into a data signal that can be transmitted according to the transmission / reception interface standard. For example, the display device (100) may convert a clock signal generated through the above-described method into a data signal that can be transmitted according to the transmission / reception interface standard. The display device (100) may transmit a clock signal with an adjusted clock parameter and a data signal corresponding to image data from the transmitting circuit to the receiving circuit through the transmission / reception interface. For example, the transmission / reception interface may include at least one of LVDS (Low-Voltage Differential Signaling) or a Vx1 interface.

[0063] FIG. 2 is a schematic block diagram of a display device according to one embodiment of the present disclosure.

[0064] Referring to FIG. 2, a display device (100) according to one embodiment of the present disclosure may include a processor (110), a memory (120), a transmission / reception interface (130), an image processing unit (140), and a display (150). However, not all of the components illustrated in FIG. 2 are essential components. The display device (100) may be implemented with more components than the components illustrated in FIG. 2, or may be implemented with fewer components.

[0065] Although in one embodiment of the present disclosure, the processor (110) is described as a separate component from the image processing unit (140), depending on the embodiment, the processor (110) may be implemented as a single SoC (System On Chip) by being integrated with various functional chipsets including the image processing unit (140). For example, the image processing unit (140) and the processor (110) may be implemented on an image processing board (10, see FIG. 1). In addition, the transmission / reception interface (130) and the memory (120) may be additionally installed on the image processing board (10, see FIG. 1) or may be separated from the image processing board (10, see FIG. 1) depending on the design method of the display device (100).

[0066] The processor (110) controls the overall operation of the display device (100). For example, the processor (110) may perform the functions of the display device (100) described in the present disclosure by executing one or more instructions stored in the memory (120). In this case, the memory (120) may store one or more instructions executable by the processor (110). In addition, the processor (110) may store one or more instructions in an internally provided memory, and execute one or more instructions stored in the internally provided memory to control the above-described operations to be performed. That is, the processor (110) may perform a predetermined operation by executing at least one instruction or program stored in the internal memory provided in the processor (110) or the memory (120).

[0067] The processor (110) may be configured with at least one of a central processing unit, a microprocessor, a graphic processing unit, an application processor (AP), an application specific integrated circuits (ASICs), a digital signal processor (DSPs), a digital signal processing device (DSPDs), a programmable logic device (PLDs), a field programmable gate array (FPGAs), and a neural processing unit or an artificial intelligence (AI) processor designed with a hardware structure specialized for learning and processing an artificial intelligence (AI) model, but is not limited thereto.

[0068] The memory (120) can store instructions, algorithms, data structures, program codes, and application programs for processing and controlling the processor (110), and can store data input to or output from the display device (100). The memory (120) can include at least one of a flash memory type, a hard disk type, a multimedia card micro type, a card type memory (e.g., SD or XD memory, etc.), a RAM (Random Access Memory), a SRAM (Static Random Access Memory), a ROM (Read-Only Memory), an EEPROM (Electrically Erasable Programmable Read-Only Memory), a PROM (Programmable Read-Only Memory), a Mask ROM, a Flash ROM, a hard disk drive (HDD), or a solid state drive (SSD). A program (one or more instructions) or application stored in memory (120) can be executed by the processor (110).

[0069] In one embodiment of the present disclosure, the transmit / receive interface (130) can transmit data from a transmitter to a receiver. For example, the transmit / receive interface (130) can transmit data from an image input source (external device) to a display device (100). Alternatively, for example, the transmit / receive interface (130) can transmit data from an image processing board (10, see FIG. 1) to a timing controller board (20, see FIG. 2). Alternatively, for example, the transmit / receive interface (130) can transmit data from the timing controller board (20) to a display driving circuit.

[0070] In one embodiment of the present disclosure, the transmission / reception interface (130) can receive video signals received from various video input sources. For example, the transmission / reception interface (130) can receive video (e.g., moving images, etc.), audio (e.g., voice, music, etc.), and additional information (e.g., EPG, etc.) from an external device under the control of the processor (110). The transmission / reception interface (130) can output video received from the external device to the image processing unit (140). The transmission / reception interface (130) can include at least one of a High-Definition Multimedia Interface (HDMI), a Mobile High-Definition Link (MHL), a Universal Serial Bus (USB), a Display Port (DP), a Thunderbolt, a Video Graphics Array (VGA) port, an RGB port, a D-subminiature (D-SUB), a Digital Visual Interface (DVI), a component jack, or a PC port. However, the present disclosure is not limited thereto, and the transmission / reception interface (130) may include various types of interfaces capable of receiving input images from peripheral electronic devices. Hereinafter, the transmission / reception interface (130) for receiving image signals received from various image input sources may be referred to as an image input unit (210, see FIG. 3).

[0071] In one embodiment of the present disclosure, the transmission / reception interface (130) can transmit image data processed by the image processing unit (140) from the transmission circuit to the reception circuit under the control of the processor (110). In one embodiment of the present disclosure, data signals exchanged between the transmission circuit and the reception circuit may differ depending on the type of the transmission / reception interface (130). The processor (110) can convert the image data into a data signal that can be transmitted according to the transmission / reception interface standard. For example, the transmission / reception interface (130) may include a high-speed interface such as an LVDS (Low-Voltage Differential Signaling) interface or a Vx1 interface that can transmit image data. The format of the data signal that can be transmitted according to each interface standard is described in FIG. 5. Hereinafter, the transmission / reception interface (130) for transmitting image data between the transmission board and the reception board may be referred to as a first cable (260, see FIG. 3).

[0072] In one embodiment of the present disclosure, the transmit / receive interface (130) may include a low-speed interface such as an Inter-Integrated Circuit (I2C) or a Universal Serial Bus (USB) under the control of the processor (110). The low-speed interface may be used to transmit control commands such as frame rate information of an input image, display setting information (e.g., resolution, brightness, color, etc.), clock frequency information, and a reset command. Hereinafter, the transmit / receive interface (130) for transmitting control commands between a transmit board and a receive board may be referred to as a second cable (270, see FIG. 3).

[0073] The image processing unit (140) performs processing on image data received by the display device (100) under the control of the processor (110). The image processing unit (140) can perform various image processing operations, such as at least one of decoding, scaling, noise filtering, frame rate conversion, or resolution conversion on the image data.

[0074] The display (150) can display an image according to the received image data under the control of the processor (110). The display (150) according to one embodiment of the present disclosure can include at least one of a timing controller, a source driver, a gate driver, or a display panel.

[0075] The display (150) may include at least one of a liquid crystal display (LCD), a thin film transistor-liquid crystal display, a light-emitting diode (LED), an organic light-emitting diode (OLED), a micro LED, a flexible display, a 3D display, and an electrophoretic display.

[0076] FIG. 3 is a block diagram of a configuration for signal transmission between a first board and a second board through a transmission / reception interface of a display device according to one embodiment of the present disclosure.

[0077] Referring to FIG. 3, a display device (100) according to one embodiment of the present disclosure may include a first board (200), a second board (300), a first cable (260), and a second cable (270). Here, when the first board (200) is an image processing board (10, see FIG. 1), the second board (300) is an example of a timing controller board (20, see FIG. 1). However, the present invention is not limited thereto, and when the first board (200) is a timing controller board (20), the second board (300) may be a display panel (30, see FIG. 1).

[0078] The first cable (260) may include a Vx1 interface. According to the specifications of the Vx1 interface, the clock signal is not transmitted alone during the image transmission process, but may be transmitted by including the clock signal in the image data. Accordingly, when transmitting data using the Vx1 interface, clock embedding may be performed during the transmission process, and clock data recovery (CDR) may be performed during the reception process.

[0079] The second cable (270) may include an I2C interface. The I2C interface may be an interface for transmitting control commands.

[0080] First, the first board (200) may include an image input unit (210), an image processing unit (220), a clock generation unit (230), a first first transmission circuit (240), and a second transmission circuit (250).

[0081] The video input unit (210) receives video signals from various video input sources. For example, the video input unit (210) may include a tuner for receiving live streams coming in through broadcasting, a USB for playing videos, an HDMI for receiving external input, a component, etc.

[0082] The clock generation unit (230) can generate a clock signal (MCLK) used for data processing and data transmission of the first board (200). Here, the clock signal (MCLK) generated in the first board (200) can be referred to as a main clock signal (MCLK) to distinguish it from the data clock signal (DCLK) generated in the second board (300) described later. The clock generation unit (230) can transmit the clock signal (MCLK) to the image processing unit (220) and the first transmission circuit (240).

[0083] For example, the clock generation unit (230) may include a PLL (Phase-Locked Loop) circuit for controlling the clock frequency of the clock signal. In addition, for example, the clock generation unit (230) may include a voltage control module for controlling the voltage intensity of the clock signal or an SSC modulator for applying SSC to the clock signal. This will be described in detail in FIG. 4.

[0084] The image processing unit (220) processes the image signal received from the image input unit (210). The image processing unit (220) can generate image data (DATA) by converting the processed image signal in synchronization with the clock signal (MCLK) received from the clock generation unit (230). The image processing unit (220) can transmit the image data (DATA) to the first transmission circuit (240). The image processing unit (220) corresponds to the image processing unit (140, see FIG. 2).

[0085] The first transmission circuit (240) can convert image data into a format according to an interface standard established for transmitting image data. For example, the first transmission circuit (240) can convert image data (DATA) into the format of the first cable (260). For example, the first transmission circuit (240) can embed information about a clock signal (MCLK) into image data (DATA) to generate a clock-embedded data signal (DATA_C). The data signal (DATA_C) can include information about the clock signal (MCLK) and image data (DATA). The image data (DATA) included in the data signal (DATA_C) can be transmitted according to the speed of the clock signal (MCLK). The data transmission cycle of the first transmission circuit (240) can correspond to the frequency of the clock signal (MCLK).

[0086] The data signal (DATA_C) transmitted from the first transmission circuit (240) can be transmitted to the first reception circuit (310) of the second board (300) via the first cable (260).

[0087] Next, the second board (300) may include a first receiving circuit (310), a data conversion unit (320), a clock generation unit (330), and a second receiving circuit (340).

[0088] The first receiving circuit (310) can receive a data signal (DATA_C) from the first transmitting circuit (240) through the first cable (260). The data receiving cycle of the first receiving circuit (310) can correspond to the frequency of the clock signal (MCLK). The first receiving circuit (310) can restore image data and a clock signal from the clock-embedded data signal (DATA_C). The first receiving circuit (310) can include a CDR (Clock Data Recovery) circuit for restoring the embedded data signal. The first receiving circuit (310) can transmit the restored image data to the data conversion unit (320) and transmit the restored clock signal to the clock generation unit (330).

[0089] The clock generation unit (330) can receive a restored clock signal from the first receiving circuit (310). The clock generation unit (330) can convert the restored clock signal to suit the settings of the display panel and generate a data clock signal (DCLK). The generated data clock signal (DCLK) can be output to the data conversion unit (320).

[0090] Meanwhile, the frequency of the main clock signal (MCLK) may be the same as or different from the frequency of the data clock signal (DCLK). The clock generation unit (330) may generate a data clock signal (DCLK) having a predetermined frequency regardless of the frequency of the main clock signal (MCLK). For example, the clock generation unit (330) may generate the data clock signal (DCLK) from the restored clock signal based on the setting information of the display panel (e.g., the resolution of the display, the refresh rate of the display, etc.). For example, the clock frequency of the data clock signal (DCLK) may be fixed to a frequency at which the display panel can operate normally, but is not limited thereto. For example, when the first board (200) and the second board (300) are implemented as one board, the frequency of the data clock signal (DCLK) may change depending on the frame rate of the input image.

[0091] The data conversion unit (320) can receive image data restored by the first receiving circuit (310). The data conversion unit (320) can convert the received image data in synchronization with the data clock signal (DCLK), and then output the converted image data (DATA') to the display driving circuit. The display driving circuit can drive the display panel based on the image data (DATA') and the data clock signal (DCLK).

[0092] A control command may be transmitted from the second transmitting circuit (250) to the second receiving circuit (340) via the second cable (270). The second transmitting circuit (250) may transmit control commands such as frame rate information of an input image, display setting information (e.g., resolution, brightness, color, etc.), clock frequency information, and a reset command via the second cable (270). The second receiving circuit (340) may receive the above-described control command via the second cable (270). For example, the second receiving circuit (340) may receive a reset command from the second transmitting circuit (250) via the second cable (270) and reset the first receiving circuit (310). For example, the second receiving circuit (340) may receive clock frequency information from the second transmitting circuit (250) via the second cable (270) and set or update the data receiving cycle of the first receiving circuit (310).

[0093] In the present disclosure, the first cable (260) is exemplified as a Vx1 interface, but is not limited thereto, and the first cable (260) may be another type of image transmission interface, such as an LVDS interface. In this case, the functions and operations of the first transmitting circuit (240) and the first receiving circuit (310) may be changed to perform signal processing in accordance with the specifications of each interface.

[0094] In the present disclosure, the first transmitting circuit (240) and the second transmitting circuit (250) may be referred to as a 'transmitting unit'. The first receiving circuit (310) and the second receiving circuit (340) may be referred to as a 'receiving unit'.

[0095] FIG. 4 is a block diagram of a configuration for adjusting a clock parameter of a clock signal in a display device according to one embodiment of the present disclosure.

[0096] Referring to FIG. 4, the display device (100) may include a PLL circuit (400). The PLL circuit (400) may be a circuit used to amplify a frequency received from an oscillator or generate a fixed frequency. The PLL circuit (400) may adjust the clock frequency of a clock signal by utilizing the phase difference between an input signal having a frequency of several tens of MHz and a feedback signal at the output.

[0097] The PLL circuit (400) may include a voltage-controlled oscillator (VCO) (440) that modulates a frequency according to an input voltage, a divider (450) that divides the output frequency of the VCO (440) by a specific ratio, a phase frequency detector (PFD) (410) that compares the phase of the input frequency (fosc) and the VCO output frequency and controls the VCO (440) so that the two frequencies are synchronized. The PLL circuit (400) may further include a charge pump (420) and a low-pass filter (LPF) (430).

[0098] According to one embodiment of the present disclosure, the processor (110) can control the PLL circuit (400) to adjust the clock frequency of the clock signal. For example, the output clock frequency (fout) in the PLL circuit (400) can be determined through the following mathematical expression 1.

[0099] [Mathematical Formula 1]

[0100]

[0101] Here, fosc is the input clock frequency, which is a signal input from the oscillator. fout is the output clock frequency. P is the setting value of the divider (450) for dividing the output frequency of the VCO (440) compared with the reference frequency. K2 is the setting value of another divider for dividing the output frequency from the VCO (440) to obtain the desired final frequency. N is the setting value of a multiplier (not shown) that re-amplifies the frequency of the feedback signal divided by the divider (450). The output frequency (fout) can be varied depending on the setting values ​​(N, P, K2).

[0102] For example, the processor (110) can adjust the clock frequency by transmitting a control command including setting values ​​(N, P, K2) for determining the output clock frequency (fout) to the PLL circuit. The processor (110) can obtain the varied output frequency (fout) based on the control command.

[0103] Alternatively, according to one embodiment of the present disclosure, the display device (100) may further include a switching module (not shown) for performing switching between clock frequencies. The processor (110) may perform switching between clock frequencies to adjust the clock frequency. For example, the processor (110) may use a clock source operating at a fixed frequency such as 95 MHz, 92 MHz, or 75 MHz. By executing the switching module, the processor (110) may switch from a first clock source operating at a first frequency to a second clock source operating at a second frequency according to the frame rate of the input image.

[0104] Meanwhile, in one embodiment of the present disclosure, the display device (100) may further include a voltage control module (not shown) for controlling the voltage intensity of a clock signal. The voltage control module may include DVFS (Dynamic Voltage and Frequency Scaling), LDO (Low Dropout Regulator), etc. The processor (110) may control the voltage intensity of the clock signal through the voltage control module.

[0105] Meanwhile, in one embodiment of the present disclosure, the display device (100) may further include an SSC modulator (not shown) for adjusting the SSC ratio of the clock signal. The SSC modulator may receive a clock signal having an output frequency of the PLL circuit (400). The SSC modulator may vary the output frequency to generate a modulated clock frequency. The SSC modulator may vary the frequency and expand the variable range of the frequency. The processor (110) may generate the modulated clock frequency by controlling the SSC modulator.

[0106] FIG. 5 is a drawing for explaining the form of a data signal transmitted by a transmission / reception interface according to one embodiment of the present disclosure.

[0107] Referring to FIG. 5, the data signal (510) may include a clock signal (CLK) and image data (DATA). In the data signal (510), the clock signal (CLK) and image data (DATA) may be distinguished as separate signals. The data signal (510) may be generated in the image processing unit (220, see FIG. 3) before being clock embedded processed.

[0108] Alternatively, the data signal (510) may be a signal transmitted according to the specifications of the LVDS interface. The LVDS interface may have separate data lines and clock lines to transmit the clock signal (CLK) and image data (DATA) of the data signal (510), respectively.

[0109] The data signal (520) may have a clock-embedded form in which information about the clock signal is reflected in the image data. The data signal (520) may be a signal transmitted according to the specifications of the Vx1 interface. The Vx1 interface may transmit the data signal (520) through a single line (e.g., a single cable or wire).

[0110] FIG. 6 is a flowchart for explaining the operation of a display device according to one embodiment of the present disclosure.

[0111] Referring to FIG. 6, operations 610 to 630 may be performed by a processor (e.g., 110 of FIG. 2) of the display device (100). The operating method of the display device (100) is not limited to that illustrated in FIG. 6, and any of the operations illustrated in FIG. 6 may be omitted, or operations not illustrated in FIG. 6 may be further included. FIG. 6 is described in conjunction with FIG. 3.

[0112] In operation 610, the display device (100) can identify the frame rate of the input image.

[0113] A display device (100) according to one embodiment of the present disclosure can receive input images from various input sources connected with or without wires. For example, the display device (100) can be connected to an external device through an image input unit (210, see FIG. 3) such as HDMI to receive various images. Alternatively, for example, the display device (100) can be connected to an external device through a communication module such as Wi-Fi or WLAN to receive images.

[0114] A display device (100) according to one embodiment of the present disclosure can identify the frame rate of an input image through metadata of the input image. For example, a signal transmitted through an image input unit (210), such as HDMI, may include metadata, and the metadata may include frame rate information of the input image.

[0115] A display device (100) according to one embodiment of the present disclosure receives a transmission stream transmitted from various input sources, and can identify a frame rate by analyzing a frame number or timestamp of a frame header included in the transmission stream.

[0116] The method for identifying the frame rate of an input video is not limited to the examples described above.

[0117] Frame rate is referred to as frames per second or refresh rate, and can have various frame rates such as 165Hz, 120Hz, and 60Hz depending on the input image.

[0118] In the present disclosure, the meanings of "high frame rate" and "low frame rate" are not limited to specific values, but may be relative. For example, if the frame rate of an input video decreases (e.g., changes from 165 Hz to 120 Hz), it can be said that the input video has changed from a high frame rate to a low frame rate. For example, if the frame rate of an input video increases (e.g., changes from 60 Hz to 165 Hz), it can be said that the input video has changed from a low frame rate to a high frame rate.

[0119] Alternatively, for example, the display device (100) may identify the input image as having a high frame rate or a low frame rate if the frame rate of the input image corresponds to a value defined as a high frame rate or a low frame rate.

[0120] In operation 620, the display device (100) can adjust the clock parameter of the clock signal based on the identified frame rate. The display device (100) can generate a clock signal with the adjusted clock parameter.

[0121] A display device (100) according to one embodiment of the present disclosure can generate a clock signal through a clock generation unit (330, see FIG. 3). The clock signal can provide timing for processing and transmitting image data. The clock parameter is for defining the characteristics and operation of the clock signal, and can include at least one of a clock frequency of the clock signal, a voltage strength of the clock signal, or a ratio of Spread Spectrum Clocking (SSC) of the clock signal. The characteristics and operation of the clock signal can vary depending on at least one of the clock frequency, the voltage strength of the clock signal, or the ratio of SSC of the clock signal. However, the present invention is not limited thereto, and the clock parameter may further include a period, a duty cycle, a phase, a waveform shape, a transition time, etc. of the clock signal.

[0122] A display device (100) according to one embodiment of the present disclosure can generate clock signals having different frequencies depending on changes in the frame rate of an input image. For example, a processor (110, see FIG. 2) can transmit a control command to a clock generation unit (330, see FIG. 3) to adjust at least one of a clock frequency, voltage level, and SSC ratio. This will be described in detail with reference to FIG. 7.

[0123] FIG. 7 is a flowchart illustrating an operation of a display device according to one embodiment of the present disclosure to adjust clock parameters and generate a clock signal.

[0124] Referring to FIG. 7, operations 710 to 755 may be performed by a processor (e.g., 110 of FIG. 2) of the display device (100). The method by which the display device (100) operates clock parameters is not limited to that illustrated in FIG. 7, and any one of the operations illustrated in FIG. 7 may be omitted, or operations not illustrated in FIG. 7 may be further included.

[0125] In operation 710, the display device (100) can identify whether the frame rate of the input image has changed. For example, the display device (100) can identify whether the frame rate of the input image has changed whenever the input image changes. If the display device (100) identifies that the frame rate of the input image has changed, it can perform operation 720. If the display device (100) identifies that the frame rate of the input image has not changed, it can perform operation 710 again.

[0126] In operation 720, the display device (100) can identify whether the frame rate of the input image has increased or decreased. For example, if the display device (100) identifies that the frame rate of the input image has increased, the display device (100) can perform at least one of operations 730, 735, and 740. For example, if the display device (100) identifies that the frame rate of the input image has decreased, the display device (100) can perform at least one of operations 745, 750, and 755.

[0127] In operation 730, if the display device (100) determines that the frame rate of the input image has increased, the display device (100) can increase the clock frequency of the clock signal. In operation 735, if the display device (100) determines that the frame rate of the input image has increased, the display device (100) can increase the voltage intensity of the clock signal. In operation 740, if the display device (100) determines that the frame rate of the input image has increased, the display device (100) can apply a low rate SSC to the clock signal. For example, as the input image changes to a high frame rate, the display device (100) can generate at least one of a clock signal having a high clock frequency, a clock signal having a high voltage intensity, or a clock signal having a low rate SSC applied as an adjusted clock signal.

[0128] In operation 745, if the display device (100) determines that the frame rate of the input image has decreased, the display device (100) may lower the clock frequency of the clock signal. In operation 750, if the display device (100) determines that the frame rate of the input image has decreased, the display device (100) may lower the voltage intensity of the clock signal. In operation 755, if the display device (100) determines that the frame rate of the input image has decreased, the display device (100) may apply a high SSC ratio to the clock signal. For example, as the input image changes to a low frame rate, the display device (100) may generate at least one of a clock signal having a low clock frequency, a clock signal having a low voltage intensity, or a clock signal having a high SSC ratio applied as an adjusted clock signal.

[0129] For example, if the display device (100) determines that the frame rate of the input image corresponds to a value defined as the first frame rate, the display device (100) may adjust the clock parameters so that the clock signal has first clock parameters (e.g., a first clock frequency, a first voltage level, a first ratio of SSC) set to match the first frame rate. The first clock frequency, the first voltage level, and the first ratio of SSC may each have predetermined values ​​depending on whether the first frame rate is a high frame rate or a low frame rate. This will be described in detail in table (800) of FIG. 8.

[0130] Again, referring to FIG. 6, at operation 630, the display device (100) may generate a data signal based on a clock signal corresponding to the adjusted clock parameter (i.e., an adjusted clock signal) and image data corresponding to the input image.

[0131] A display device (100) according to one embodiment of the present disclosure can generate a clock signal having an adjusted clock parameter (i.e., an adjusted clock signal). The clock signal can have at least one of a clock frequency, a voltage level, or a ratio of SSC adjusted according to a frame rate of an input image.

[0132] A display device (100) according to one embodiment of the present disclosure can generate image data corresponding to an input image. The image data can be generated through an image processing unit (220, see FIG. 3). The image data can be synchronized to a clock signal corresponding to an adjusted clock parameter.

[0133] A display device (100) according to one embodiment of the present disclosure may convert image data into a format according to a predetermined interface standard in order to transmit image data through a transmission / reception interface. For example, the display device (100) may convert a clock signal having an adjusted clock parameter and image data into a format of a Vx1 interface through a first transmission circuit (240, see FIG. 3). For example, the display device (100) may embed information about the clock signal into the image data to generate a clock-embedded data signal. The data signal may include information about the clock signal and image data. The data signal may have a form in which the clock signal is reflected in the image data.

[0134] In the present disclosure, a data signal can be transmitted according to the speed of a clock signal, and the data signal can be referred to as a 'data signal corresponding to a clock signal', a 'data signal corresponding to a clock parameter', a 'data signal corresponding to a clock frequency', or 'image data corresponding to the speed of the clock signal'.

[0135] In operation 640, the display device (100) can transmit a data signal from a transmitting circuit to a receiving circuit through a transmitting / receiving interface.

[0136] A display device (100) according to one embodiment of the present disclosure can transmit a data signal from a first transmission circuit (240, see FIG. 3) to a first reception circuit (310, see FIG. 3) via a first cable (260, see FIG. 3).

[0137] The clock frequency of the clock signal can determine the transmission speed of the transmission / reception interface. The display device (100) can adjust the transmission speed of the data signal by adjusting the clock frequency of the clock signal according to the frame rate of the input image. If the display device (100) determines that the input image has a low frame rate, it can lower the clock frequency of the clock signal to lower the data transmission speed of the data signal. Accordingly, the power consumption that occurs when transmitting image data through the transmission / reception interface can be reduced.

[0138] For example, if the display device (100) determines that the input image has a high frame rate, it can increase the clock frequency of the clock signal to increase the data transmission speed of the data signal. Accordingly, when transmitting image data through the transmission / reception interface, a large amount of data can be transmitted at a high speed, thereby increasing transmission efficiency.

[0139] Meanwhile, the first receiving circuit (310, see FIG. 3) receives a data signal and, through a clock data recovery process, can recover the clock signal and image data. The display device (100) can perform an operation for driving a display panel, and this has been described in relation to the second board (300) of FIG. 3.

[0140] FIG. 8 is a table showing an example of clock parameters adjusted according to the frame rate of an input image, according to one embodiment of the present disclosure.

[0141] Referring to the table (800) of FIG. 8, for example, if the display device (100) determines that the frame rate of the input image is the maximum value (e.g., 165 Hz), the display device (100) can generate an adjusted clock signal by at least one of adjusting the clock frequency to the maximum value (e.g., 95 MHz), adjusting the clock voltage intensity to the maximum value, or adjusting the SSC ratio to the minimum value (e.g., 0%). For example, if the display device determines that the frame rate of the input image is the intermediate value (e.g., 120 Hz), the display device can generate an adjusted clock signal by at least one of adjusting the clock frequency to the intermediate value (e.g., 92 MHz), adjusting the clock voltage intensity to the intermediate value, or adjusting the SSC ratio to the intermediate value (e.g., 0.3%). For example, if the display device determines that the frame rate of the input image is at a minimum value (e.g., 60 Hz), it can generate an adjusted clock signal by at least one of adjusting the clock frequency to a minimum value (e.g., 75 MHz), adjusting the voltage strength of the clock to a minimum value, or adjusting the ratio of the SSC to a maximum value (e.g., 0.5%).

[0142] In the present disclosure, maximum, median, and minimum are terms used to indicate relative strength and are not limited to specific numerical values.

[0143] FIG. 9 is an example of a data signal with adjusted clock parameters according to one embodiment of the present disclosure.

[0144] Referring to FIG. 9, the data signal (910) and the data signal (920) may each be signals in which information regarding a clock signal is embedded in image data.

[0145] In the data signal (910), the clock signal may have a clock frequency higher than the clock frequency of the data signal (920) and a voltage intensity higher than the voltage intensity of the data signal (920). For example, the amount of data transmitted during one clock period may be large. For example, the voltage value of the first level and the voltage value of the second level of the clock signal may be high. Here, the first level may be a high state of the clock signal (i.e., a logic high level), and the second level may be a low state of the clock signal (i.e., a logic low level). The data signal (910) may be a signal used to process and transmit a high frame rate video. That is, in order to transmit a high frame rate video, the more the amount of data transmitted during one clock period, the higher the transmission efficiency and the higher the speed.

[0146] In the data signal (920), the clock signal may have a clock frequency lower than the clock frequency of the data signal (910) and a voltage intensity lower than the voltage intensity of the data signal (910). For example, the amount of data transmitted during one clock cycle may be small. For example, the voltage values ​​of the first level and the second level of the clock signal may be low. The data signal (920) may be a signal used to process and transmit a low frame rate image. That is, when transmitting a low frame rate image, since the amount of data is small, transmitting it at a slow speed may result in less power waste than transmitting it at a fast speed.

[0147] Additionally, in the data signal (920), when the clock frequency of the clock signal is low, the clock signal's eye margin widens, thereby ensuring signal stability. Accordingly, a high SSC ratio can be applied to the clock signal. When a clock signal with a high SSC ratio is used, power consumption can be reduced as system efficiency is improved.

[0148] FIG. 10 is a detailed flowchart for explaining an operation of a display device according to an embodiment of the present disclosure to generate different clock signals depending on the frame rate of content. Referring to FIG. 10, an operation method (1000) of a display device (100) may include operations 1010 to 1090. The operation method (1000) of a display device (100) is not limited to that illustrated in FIG. 10, and any one of the operations illustrated in FIG. 10 may be omitted, or operations not illustrated in FIG. 10 may be further included.

[0149] In operation 1010, the display device (100) can identify the frame rate of the input image. Operation 1010 corresponds to operation 610 of FIG. 6.

[0150] In operation 1020, the display device (100) may perform muting of the display screen based on the identified frame rate. For example, the display device (100) may transmit a data signal corresponding to muting of the display screen from the image processing board (10) to the timing controller board (20) via the first cable (260). The data signal corresponding to muting of the display screen may be black data in which RGB data is (0, 0, 0), but is not limited thereto.

[0151] In operation 1030, the display device (100) can control the display panel (30) based on black data.

[0152] For example, the display device (100) can identify whether the frame rate has changed. If the display device (100) determines that the frame rate has changed, the display device (100) can output a black image. The display device (100) can be in a screen mute state while adjusting the clock parameter of the clock signal according to the frame rate. Accordingly, noise occurring on the display screen can be minimized while adjusting the clock parameter (e.g., clock frequency) of the clock signal.

[0153] In operation 1035, the display device (100) may transmit a reset command of the first receiving circuit (310) from the image processing board (10) to the timing controller board (20) via the second cable (270). In operation 1040, the display device (100) may reset the first receiving circuit (310) based on the reset command. When the first receiving circuit (310) is reset, the protocol of the transmission / reception interface may be initialized. For example, the data reception cycle of the first receiving circuit (310) is reset, and then communication may be newly performed according to the changed clock frequency. In this case, since the display panel (30) outputs a black image while the first receiving circuit (310) is being reset, a noise problem may not occur. The reset first receiving circuit (310) may set the data reception cycle according to the new clock frequency according to operation 1060, which will be described later.

[0154] Meanwhile, according to one embodiment, operations 1035 and 1040 may be omitted. This is described in FIG. 14.

[0155] In operation 1050, the display device (100) may generate a clock signal (i.e., an adjusted clock signal) with an adjusted clock parameter based on the identified frame rate. Operation 1050 may correspond to operation 620 of FIG. 6.

[0156] In operation 1060, the display device (100) can transmit the adjusted clock frequency information from the image processing board (10) to the timing controller board (20) via the second cable (270). In operation 1070, the display device (100) can set the data reception cycle of the first receiving circuit (310) based on the adjusted clock frequency information.

[0157] For example, the first receiving circuit (310) can preset the data reception cycle according to the increased or decreased clock frequency. The first receiving circuit (310) can preset the data reception cycle before receiving a data signal corresponding to the adjusted clock frequency through the first cable (260). Accordingly, even if the clock speed of the transmitting unit changes, the receiving unit can smoothly receive data according to the changed clock speed.

[0158] The clock speed of the clock signal, the data transmission cycle of the first transmission circuit (240), the transmission speed of the first cable (260), and the data reception cycle of the first reception circuit (310) may correspond to each other. For example, if the clock frequency increases, the data reception cycle of the first reception circuit (310) may become faster. If the clock frequency decreases, the data reception cycle of the first reception circuit (310) may become slower.

[0159] In operation 1080, the display device (100) may transmit a data signal based on the adjusted clock parameter and pixel data from the image processing board (10) to the timing controller board (20) via the first cable (260). Operation 1080 may correspond to 640 of FIG. 6. The data signal may include pixel data corresponding to the input image. The data signal may be in an embedded form in which a clock signal corresponding to the adjusted clock parameter is reflected in the pixel data.

[0160] In operation 1090, the display device (100) can control the display panel (30) based on pixel data.

[0161] FIG. 11 is an example of an operation of transmitting a signal through a transmission / reception interface of a display device according to an embodiment of the present disclosure. FIG. 12 is an example of an operation of transmitting a signal through a transmission / reception interface of a display device according to an embodiment of the present disclosure. In FIGS. 11 and 12, it is assumed that the first board (200) of FIG. 3 corresponds to the image processing board (10), and the second board (300) of FIG. 3 corresponds to the timing controller board (20). Here, the timing controller (1130) may include the data conversion unit (320) and the clock generation unit (330) of FIG. 3. The first transmission circuit (240) and the second transmission circuit (250) may be referred to as a transmission unit (1110). The first reception circuit (310) and the second reception circuit (340) may be referred to as a reception unit (1120).

[0162] Referring to FIG. 11, operations 1020, 1030, 1035, and 1040 of FIG. 10 are described in detail.

[0163] In operation 1020, the processor (110) can control the first transmission circuit (240) to transmit a data signal corresponding to muting of the display screen, black data, to the first reception circuit (310) through the first cable (260).

[0164] Here, the black data can be converted to conform to the specifications of the first cable (260). For example, the processor (110) can control the first transmission circuit (240) to generate a data signal (DATA_C1) based on the first clock signal (CLK1) and the black data. The first clock signal (CLK1) can be a clock signal adjusted to correspond to the frame rate of the input image before modification. The data signal (DATA_C1) can be in the form of the first clock signal (CLK1) embedded in the black data. The data signal (DATA_C1) can be restored to the black data and the first clock signal (CLK1) again in the first reception circuit (310). Meanwhile, the data signal (DATA_C1) can also include a synchronization signal (Sync).

[0165] In operation 1030, the timing controller (1130) provided in the timing controller board (20) can control the display panel (30) based on the received black data. For example, the timing controller (1130) can transmit black data to the display panel (30). The display panel (30) can output a black image in response to screen muting.

[0166] At operation 1035, the processor (110) can control the second transmitting circuit (250) to transmit a reset command of the first receiving circuit (310) to the second receiving circuit (340) via the second cable (270). At operation 1040, the timing controller (1130) can reset the first receiving circuit (310) based on the reset command of the first receiving circuit (310).

[0167] Next, operations 1060, 1070, 1080, and 1090 of FIG. 10 will be described in detail with reference to FIG. 12.

[0168] In operation 1060, the processor (110) may change the first clock signal (CLK1) to the second clock signal (CLK2) based on the changed frame rate of the input image. For example, when the frame rate of the input image decreases, the clock frequency of the second clock signal (CLK2) may be lower than the clock frequency of the first clock signal (CLK1). The processor (110) may control the second transmission circuit (250) to transmit the frequency information of the second clock signal (CLK2) to the second reception circuit (340) through the second cable (270). In operation 1070, the timing controller (1130) may set the data reception cycle of the first reception circuit (310) to correspond to the clock frequency of the second clock signal (CLK2). For example, if the clock frequency of the second clock signal (CLK2) is reduced from 95 MHz to 75 MHz, the first receiving circuit (310) may change from receiving data 95 million times per second to receiving data 75 million times per second.

[0169] At operation 1080, the processor (110) can control the first transmitting circuit (240) to transmit a data signal (DATA_C2) based on the adjusted clock parameter and pixel data to the first receiving circuit (310) via the first cable (260).

[0170] Here, the data signal (DATA_C2) can be converted to conform to the specifications of the first cable (260). For example, the processor (110) can control the first transmission circuit (240) to generate the data signal (DATA_C2) based on the second clock signal (CLK2) and pixel data. The data signal (DATA_C2) may be in the form of the second clock signal (CLK2) embedded in the pixel data. The data signal (DATA_C2) can be restored to pixel data and the second clock signal (CLK2) again in the first reception circuit (310). Meanwhile, the data signal (DATA_C2) may also include a synchronization signal (Sync).

[0171] The data signal may include pixel data corresponding to the input image. The data signal may be in an embedded form in which a clock signal corresponding to an adjusted clock parameter is reflected in the pixel data.

[0172] In operation 1090, the timing controller (1130) can control the display panel (30) based on the received pixel data. The display panel (30) can output an input image with a changed frame rate.

[0173] FIG. 13 is a drawing for explaining the operation of a display device when an image input to the display device according to one embodiment of the present disclosure is changed.

[0174] Referring to FIG. 13, the display device (100) can output an image based on a first frame rate (operation 1310).

[0175] The display device (100) can identify that the frame rate of the input image has changed (operation 1311).

[0176] When the display device (100) identifies that the frame rate of the input image has changed, it can output a black image in response to muting of the display screen (operation 1320).

[0177] While the display device (100) outputs a black image, the receiving circuit of the timing controller can be reset (operation 1321), the clock parameter of the clock signal used in the image processing board can be adjusted (operation 1322), the data cycle of the receiving circuit of the timing controller can be newly set to match the adjusted clock parameter (operation 1323), and a data signal corresponding to the adjusted clock parameter can be generated and transmitted to the timing controller board (operation 1324).

[0178] The timing controller can control the display based on the data signal (operation 1331). The display device (100) can output an image based on the second frame rate (operation 1330).

[0179] FIG. 14 is a detailed flowchart for explaining an operation of a display device according to one embodiment of the present disclosure to generate different clock signals depending on the frame rate of content.

[0180] The operating method of the display device (100) of FIG. 14 may include operations 1410 to 1480. Operations 1410, 1420, and 1430 may each correspond to operations 1010, 1020, and 1030. The operating method (1400) of the display device (100) of FIG. 14 differs from the operating method (1000) of FIG. 10 in that operations 1035 and 1040 of FIG. 10 are omitted. Accordingly, operation 1440 may correspond to operation 1050, operation 1450 may correspond to operation 1060, operation 1460 may correspond to operation 1070, operation 1460 may correspond to operation 1070, operation 1470 may correspond to operation 1080, and operation 1480 may correspond to operation 1090.

[0181] A display device (100) according to one embodiment of the present disclosure may omit a reset procedure for the first receiving circuit (310) of the timing controller board (20). Even if the first receiving circuit (310) is not reset, the data receiving cycle may be set to match a new clock frequency according to operation 1450 described below.

[0182] FIG. 15 is a detailed block diagram of a display device according to one embodiment of the present disclosure.

[0183] Referring to FIG. 15, the display device (100) may further include a tuner unit (1540), a communication unit (1550), a detection unit (1530), an image input unit (1570), an audio processing unit (1585), an audio output unit (1560), a memory (120), and a power supply unit (1595) in addition to a processor (110), a memory (120), a transmission / reception interface (130), an image processing unit (140), and a display (150).

[0184] A tuner unit (1540) according to one embodiment can select and tune only the frequency of a channel to be received by the display device (100) among many radio wave components through amplification, mixing, resonance, etc. of a broadcast signal received wired or wirelessly. The broadcast signal includes audio, video, and additional information (e.g., EPG (Electronic Program Guide)).

[0185] The tuner unit (1540) can receive broadcast signals from various sources, such as terrestrial broadcasting, cable broadcasting, satellite broadcasting, and internet broadcasting. The tuner unit (1540) can also receive broadcast signals from sources, such as analog broadcasting or digital broadcasting.

[0186] The communication unit (1550) can transmit and receive data or signals with an external device or server. For example, the communication unit (1550) may include a Wi-Fi module, a Bluetooth module, an infrared communication module, a wireless communication module, a LAN module, an Ethernet module, a wired communication module, etc. In this case, each communication module may be implemented in the form of at least one hardware chip.

[0187] The Wi-Fi module and Bluetooth module perform communication in the Wi-Fi and Bluetooth modes, respectively. When using the Wi-Fi module or Bluetooth module, various connection information such as the SSID and session key are first transmitted and received, and after establishing a communication connection using this, various information can be transmitted and received. The wireless communication module may include at least one communication chip that performs communication according to various wireless communication standards such as Zigbee, 3G (3rd Generation), 3GPP (3rd Generation Partnership Project), LTE (Long Term Evolution), LTE-A (LTE Advanced), 4G (4th Generation), and 5G (5th Generation).

[0188] According to one embodiment, a detection unit (1530) detects a user's voice, a user's image, or a user's interaction, and may include a microphone (1531), a camera unit (1532), and a light receiving unit (1533).

[0189] The microphone (1531) receives the user's spoken voice. The microphone (1531) can convert the received voice into an electrical signal and output it to the processor (110).

[0190] The optical receiver (1533) receives an optical signal (including a control signal) from an external control device through an optical window (not shown) of a bezel of the display (150), etc. The optical receiver (1533) can receive an optical signal corresponding to a user input (e.g., touch, pressing, touch gesture, voice, or motion) from the control device. A control signal can be extracted from the received optical signal under the control of the processor (110).

[0191] According to one embodiment, the video input unit (1570) can receive video (e.g., moving images, etc.), audio (e.g., voice, music, etc.), and additional information (e.g., EPG, etc.) from the outside of the display device (100). The input / output unit (1270) can include any one of a High-Definition Multimedia Interface (HDMI), a Mobile High-Definition Link (MHL), a Universal Serial Bus (USB), a Display Port (DP), a Thunderbolt, a Video Graphics Array (VGA) port, an RGB port, a D-subminiature (D-SUB), a Digital Visual Interface (DVI), a component jack, and a PC port. The video input unit (1570) can correspond to the video input unit (210) of FIG. 3.

[0192] The processor (110) may include at least one of a CPU (Central Processing Unit), a GPU (Graphics Processing Unit), and a VPU (Video Processing Unit). Alternatively, according to an embodiment, the processor may be implemented in the form of a SoC (System On Chip) that integrates at least one of a CPU, a GPU, and a VPU. Alternatively, the processor (110) may further include an NPU (Neural Processing Unit).

[0193] The memory (120) can store various data, programs, or applications for driving and controlling the display device (100). In addition, the program stored in the memory (120) can include one or more instructions. The program (one or more instructions) or application stored in the memory (120) can be executed by the processor (110).

[0194] According to one embodiment, the processor (110) may acquire an image by executing one or more instructions stored in the memory (120). The image may be an image previously stored in the memory (120) or an image received from an external device through the tuner unit (1540) or the communication unit (1550). In addition, the image may be an image on which various image processing such as decoding, scaling, noise filtering, frame rate conversion, and resolution conversion have been performed in the image processing unit (140).

[0195] A display (150) according to one embodiment generates a driving signal by converting a video signal, a data signal, an OSD signal, a control signal, etc. processed by a processor (110). The display (150) is configured as a touch screen and can be used as an input device in addition to an output device.

[0196] The audio processing unit (1585) processes audio data. The audio processing unit (1585) may perform various processing operations, such as decoding, amplification, and noise filtering, on audio data. Meanwhile, the audio processing unit (1585) may include multiple audio processing modules to process audio corresponding to multiple contents.

[0197] The audio output unit (1560) outputs audio included in a broadcast signal received through the tuner unit (1540) under the control of the processor (110). The audio output unit (1560) can output audio (e.g., voice, sound) input through the communication unit (1550) or the video input unit (1570). In addition, the audio output unit (1560) can output audio stored in the memory (120) under the control of the processor (110). The audio output unit (1560) can include at least one of a speaker, a headphone output terminal, or a S / PDIF (Sony / Philips Digital Interface:) output terminal.

[0198] The power supply unit (1595) supplies power input from an external power source to components inside the display device (100) under the control of the processor (110). In addition, the power supply unit (1595) can supply power output from one or more batteries (not shown) located inside the display device (100) to the internal components under the control of the processor (110).

[0199] The memory (120) may include a broadcast reception module (not shown), a channel control module, a volume control module, a communication control module, a voice recognition module, a motion recognition module, an optical reception module, a display control module, an audio control module, an external input control module, a power control module, a power control module of an external device connected wirelessly (e.g., Bluetooth), a voice database (DB), or a motion database (DB). The processor (110) may perform each function using the software stored in the memory (120).

[0200] A display device according to one embodiment of the present disclosure includes a transmitting circuit, a receiving circuit, a transmitting / receiving interface connecting the receiving circuit and the transmitting circuit, a memory storing one or more instructions, and at least one processor executing one or more instructions stored in the memory. The at least one processor according to one embodiment of the present disclosure identifies a frame rate of an input image by executing the one or more instructions. The at least one processor according to one embodiment of the present disclosure adjusts a clock parameter of a clock signal to generate an adjusted clock signal based on the identified frame rate by executing the one or more instructions. The at least one processor according to one embodiment of the present disclosure transmits a data signal generated based on the adjusted clock signal and image data corresponding to the input image from the transmitting circuit to the receiving circuit through the transmitting / receiving interface by executing the one or more instructions.

[0201] According to one embodiment of the present disclosure, the transmitting circuit may be included in an image processing board having at least one processor, and the receiving circuit may be included in a timing controller board.

[0202] According to one embodiment of the present disclosure, at least one processor can convert the clock signal and the image data into the data signal so as to be transmittable according to the specifications of the transmission / reception interface by executing the one or more instructions.

[0203] The specification of the transmission / reception interface according to one embodiment of the present disclosure includes a V-by-One specification, and within the data signal, the clock signal may be included in the image data.

[0204] According to one embodiment of the present disclosure, the clock parameter may include at least one of a clock frequency, a voltage level, or a ratio of a Spread Spectrum Clock (SSC) of the clock signal.

[0205] According to one embodiment of the present disclosure, the at least one processor may generate the adjusted clock signal by setting a clock frequency of the clock signal by executing the one or more instructions. When the frame rate is a first frame rate, the adjusted clock frequency may be set to a first clock frequency. When the frame rate is a second frame rate higher than the first frame rate, the adjusted clock frequency may be set to a second clock frequency higher than the first clock frequency. The data transmission speed of the data signal may be characterized in that it is adjusted based on the adjusted clock frequency.

[0206] According to one embodiment of the present disclosure, the at least one processor may generate the adjusted clock signal by setting the voltage intensity of the clock signal to an adjusted voltage intensity by executing the one or more instructions. When the frame rate is the first frame rate, the adjusted voltage intensity may be set to a first voltage intensity. When the frame rate is the second frame rate, the adjusted voltage intensity may be set to a second voltage intensity higher than the first voltage intensity.

[0207] According to one embodiment of the present disclosure, the at least one processor may generate the adjusted clock signal to which a first SSC ratio is applied, by executing the one or more instructions, when the frame rate is the first frame rate. When the frame rate is the second frame rate, the at least one processor may generate the adjusted clock signal to which at least one of a second SSC ratio lower than the first SSC ratio or an SSC ratio of 0 is applied.

[0208] According to one embodiment of the present disclosure, the at least one processor can transmit image data corresponding to muting of the display screen from the transmission circuit to the reception circuit through the transmission / reception interface by identifying that the frame rate of the input image is changed by executing the one or more instructions.

[0209] In one embodiment of the present disclosure, the clock parameter of the clock signal may be adjusted while the display screen is in a mute state.

[0210] The display device may further include a cable that is distinct from the transmission / reception interface and connects between a first board including the transmission circuit and a second board including the reception circuit.

[0211] According to one embodiment of the present disclosure, at least one processor may generate the clock signal having an adjusted clock frequency based on the identified frame rate by executing the one or more instructions.

[0212] According to one embodiment of the present disclosure, at least one processor can transmit adjusted clock frequency information from the first board to the second board via the cable.

[0213] According to one embodiment of the present disclosure, the second board can set the data reception cycle of the receiving circuit based on the clock frequency information received through the cable. As the data reception cycle of the receiving circuit is set, the second board can receive the data signal corresponding to the adjusted clock frequency through the transmission / reception interface.

[0214] According to one embodiment of the present disclosure, the at least one processor may transmit a reset command for resetting the receiving circuit from the first board to the second board through the cable, upon identifying that the frame rate of the input image has changed by executing the one or more instructions.

[0215] The data reception cycle of the above receiving circuit may be characterized in that it is reset based on the reset command.

[0216] According to one embodiment of the present disclosure, a method of operating a display device including a transmitting circuit, a receiving circuit, and a transmitting / receiving interface connecting the transmitting circuit and the receiving circuit includes the steps of identifying a frame rate of an input image, adjusting a clock parameter of a clock signal to generate an adjusted clock signal based on the identified frame rate, and transmitting a data signal generated based on the adjusted clock signal and image data corresponding to the input image from the transmitting circuit to the receiving circuit through the transmitting / receiving interface.

[0217] The operating method of a display device according to one embodiment of the present disclosure may further include a step of converting the clock signal and the image data into the data signal so that they can be transmitted according to the specifications of the transmission / reception interface.

[0218] The specification of the transmission / reception interface according to one embodiment of the present disclosure includes a V-by-One specification, and within the data signal, the clock signal may be included in the image data.

[0219] According to one embodiment of the present disclosure, the step of adjusting a clock parameter of a clock signal based on the identified frame rate includes the step of setting a clock frequency of the clock signal to generate the adjusted clock signal, wherein when the frame rate is a first frame rate, the adjusted clock frequency is set to a first clock frequency, and when the frame rate is a second frame rate higher than the first frame rate, the adjusted clock frequency may be set to a second clock frequency higher than the first clock frequency.

[0220] According to one embodiment of the present disclosure, the step of adjusting a clock parameter of a clock signal based on the identified frame rate includes the step of generating the adjusted clock signal by setting a voltage intensity of the clock signal to an adjusted voltage intensity, wherein when the frame rate is the first frame rate, the adjusted voltage intensity may be set to a first voltage intensity, and when the frame rate is the second frame rate, the adjusted voltage intensity may be set to a second voltage intensity higher than the first voltage intensity.

[0221] The step of adjusting a clock parameter of a clock signal based on the identified frame rate according to one embodiment of the present disclosure may include the step of generating the adjusted clock signal to which a first SSC ratio is applied, as the frame rate is the first frame rate, and the step of generating the adjusted clock signal to which at least one of a second SSC ratio lower than the first SSC ratio or an SSC ratio of 0 is applied, as the frame rate is the second frame rate.

[0222] A method of operating a display device according to one embodiment of the present disclosure may further include a step of transmitting image data corresponding to muting of a display screen from the transmitting circuit to the receiving circuit via the transmitting / receiving interface upon identifying that the frame rate of the input image has changed. The step of adjusting a clock parameter of the clock signal may be characterized in that it is performed while the display screen is in a mute state.

[0223] The step of adjusting a clock parameter of a clock signal based on the identified frame rate according to one embodiment of the present disclosure may include the step of generating the clock signal with an adjusted clock frequency based on the identified frame rate.

[0224] A method of operating a display device according to one embodiment of the present disclosure may further include a step of transmitting adjusted clock frequency information from a first board including the transmission circuit to a second board including the reception circuit through a cable connecting between the first board including the transmission circuit and the second board including the reception circuit, a step of setting a data reception period of the reception circuit based on the clock frequency information received through the cable, and a step of receiving the data signal corresponding to the adjusted clock frequency through the transmission / reception interface as the data reception period of the reception circuit is set.

[0225] In one embodiment of the present disclosure, a computer-readable recording medium having recorded thereon a program for performing a method of operating a display device on a computer is provided.

[0226] A device-readable storage medium may be provided in the form of a non-transitory storage medium. Here, the term "non-transitory storage medium" simply means a tangible device that does not contain signals (e.g., electromagnetic waves). This term does not distinguish between cases where data is permanently stored in the storage medium and cases where data is temporarily stored. For example, a "non-transitory storage medium" may include a buffer in which data is temporarily stored.

[0227] According to one embodiment, the method according to various embodiments disclosed in the present document may be provided as included in a computer program product. The computer program product may be traded as a product between a seller and a buyer. The computer program product may be distributed in the form of a machine-readable storage medium (e.g., compact disc read-only memory (CD-ROM)), or may be distributed online (e.g., downloaded or uploaded) through an application store or directly between two user devices (e.g., smartphones). In the case of online distribution, at least a portion of the computer program product (e.g., a downloadable app) may be temporarily stored or temporarily generated in a machine-readable storage medium, such as the memory of a manufacturer's server, an application store's server, or an intermediary server.

Claims

1. In the display device (100), Transmitter circuit (240); Receiving circuit (310); A transmission / reception interface (130, 260) connecting the above receiving circuit (310) and the above transmitting circuit (240); A memory (120) storing one or more instructions; and At least one processor (110) that executes one or more instructions stored in the above memory (120), The display device (100) is configured such that the one or more instructions are individually or collectively executed by the at least one processor (110). Identify the frame rate of the input video, Based on the identified frame rate, adjusting the clock parameters of the clock signal to generate an adjusted clock signal, A display device (100) that transmits a data signal generated based on the adjusted clock signal and image data corresponding to the input image from the transmission circuit (240) to the reception circuit (310) through the transmission / reception interface (130, 260).

2. In paragraph 1, The above transmission circuit (240) is included in an image processing board (10, 200) having at least one processor (110), A display device, characterized in that the above receiving circuit (310) is included in a timing controller board (20, 300).

3. In paragraph 1 or 2, By executing the one or more commands individually or in combination by the at least one processor (110), the display device (100) A display device (100) that converts the clock signal and the image data into the data signal so that they can be transmitted according to the specifications of the transmission / reception interface (130).

4. In paragraph 3, The specifications of the above transmission / reception interface (130) include the V-by-One specifications, A display device (100) wherein, within the above data signal, the clock signal is included in the image data.

5. In any one of paragraphs 1 to 4, A display device (100), wherein the clock parameter includes at least one of a clock frequency, voltage strength, or SSC (Spread Spectrum Clock) ratio of the clock signal.

6. In any one of paragraphs 1 to 5, By executing the one or more commands individually or in combination by the at least one processor (110), the display device (100) Generating the adjusted clock signal by setting the clock frequency of the clock signal, As the above frame rate is the first frame rate, the adjusted clock frequency is set to the first clock frequency, As the frame rate is a second frame rate higher than the first frame rate, the adjusted clock frequency is set to a second clock frequency higher than the first clock frequency, A display device (100), characterized in that the data transmission speed of the data signal is adjusted based on the adjusted clock frequency.

7. In paragraph 6, By executing the one or more commands individually or in combination by the at least one processor (110), the display device (100) Generating the adjusted clock signal by setting the voltage intensity of the clock signal to an adjusted voltage intensity, As the above frame rate is the first frame rate, the adjusted voltage intensity is set to the first voltage intensity, A display device (100) in which the adjusted voltage intensity is set to a second voltage intensity higher than the first voltage intensity, as the frame rate is the second frame rate.

8. In paragraph 6 or 7, By executing the one or more commands individually or in combination by the at least one processor (110), the display device (100) As the above frame rate is the first frame rate, the adjusted clock signal to which the first SSC ratio is applied is generated, A display device (100) that generates the adjusted clock signal to which at least one of a second SSC rate lower than the first SSC rate or an SSC rate of 0 is applied, as the frame rate is the second frame rate.

9. In any one of paragraphs 1 to 8, By executing the one or more commands individually or in combination by the at least one processor (110), the display device (100) Upon identifying that the frame rate of the input image has changed, image data corresponding to muting of the display screen is transmitted from the transmitting circuit (240) to the receiving circuit (310) through the transmitting / receiving interface (130). A display device (100), characterized in that the clock parameter of the clock signal is adjusted while the display screen is in a mute state.

10. In any one of paragraphs 1 to 9, The above display device (100) is It is distinguished from the above transmission / reception interface (130) and further includes a cable (270) connecting between the first board (200) including the transmission circuit (240) and the second board (300) including the reception circuit (310). By executing the one or more commands individually or in combination by the at least one processor (110), the display device (100) Based on the identified frame rate, generating the adjusted clock signal, Transmit the adjusted clock frequency information from the first board (200) to the second board (300) through the cable (270), The above second board (300) is, Based on the adjusted clock frequency information received through the above cable (270), the data reception cycle of the receiving circuit (310) is set, A display device (100) that receives the data signal corresponding to the adjusted clock frequency through the transmission / reception interface (130) as the data reception cycle of the above receiving circuit (310) is set.

11. In paragraph 10, By executing the one or more commands individually or in combination by the at least one processor (110), the display device (100) Upon identifying that the frame rate of the input image has changed, a reset command for resetting the receiving circuit (310) is transmitted from the first board (200) to the second board (300) through the cable (270), A display device (100), characterized in that the data reception cycle of the above receiving circuit (310) is reset based on the reset command.

12. In a method of operating a display device (100) including a transmitting circuit (240), a receiving circuit (310), and a transmitting / receiving interface (130) connecting the transmitting circuit (240) and the receiving circuit (310), A step of identifying the frame rate of the input image; A step of adjusting a clock parameter of a clock signal to generate an adjusted clock signal based on the identified frame rate; and A method comprising a step of transmitting a data signal generated based on the adjusted clock signal and image data corresponding to the input image from the transmission circuit (240) to the reception circuit (310) through the transmission / reception interface (130).

13. In paragraph 12, Based on the identified frame rate, the step of adjusting the clock parameter of the clock signal is: A step of generating the adjusted clock signal by setting the clock frequency of the clock signal, As the above frame rate is the first frame rate, the adjusted clock frequency is set to the first clock frequency, As the frame rate is a second frame rate higher than the first frame rate, the adjusted clock frequency is set to a second clock frequency higher than the first clock frequency, A method characterized in that the data transmission speed of the data signal is adjusted based on the adjusted clock frequency.

14. In paragraph 12 or 13, Based on the identified frame rate, the step of adjusting the clock parameter of the clock signal is: A step of generating the adjusted clock signal by setting the voltage intensity of the clock signal to an adjusted voltage intensity, As the above frame rate is the first frame rate, the adjusted voltage intensity is set to the first voltage intensity, A method in which the adjusted voltage intensity is set to a second voltage intensity higher than the first voltage intensity, as the frame rate is the second frame rate.

15. Identify the frame rate of the input video, Based on the identified frame rate, adjusting the clock parameters of the clock signal to generate an adjusted clock signal, A computer-readable recording medium having recorded thereon instructions for operating an electronic device when individually or collectively executed by at least one processor to transmit a data signal generated based on the adjusted clock signal and image data corresponding to the input image from a transmitting circuit to a receiving circuit through a transmitting / receiving interface.

Images