Decision feedback equalization method and apparatus based on digital-to-analog conversion

Abstract

A decision feedback equalization apparatus based on digital-to-analog conversion, according to an embodiment of the disclosed invention, may comprise: a GM circuit for receiving an input signal that has passed through a channel; a sampler circuit configured to receive an analog signal from the GM circuit and convert the analog signal into a digital signal; a switching circuit configured to generate an analog signal from the digital signal output from the sampler circuit and output the analog signal; and a feedback circuit configured to feed back the analog signal output from the switching circuit back to an output terminal of the GM circuit.

Description

Digital-to-analog conversion-based decision feedback equalization method and device

[0001] The present invention relates to a digital-to-analog conversion-based decision feedback equalization method and device, and more specifically, to a digital-to-analog conversion-based decision feedback equalization method and device having an improved structure that enables a decision feedback equalization device to perform small signal operation by converting a digital signal into an analog signal in the process of feeding back a high-speed signal.

[0002] Decision Feedback Equalizer (DFE) is an electrical dispersion compensation technology that reduces inter-symbol errors caused by signal distortion by adding a decision value and a weight to a received signal and then performing feedback equalization.

[0003] Specifically, the decision feedback equalizer (DFE) is composed of a decision circuit and a transverse filter in the feedback section, and feeds back an amount that depends on the weighting ratio and the bit judged to the actual bit based on the decision of the previous bit.

[0004] This can be implemented as a type of nonlinear filter that can overcome even very severe distortion.

[0005] A conventional decision feedback equalizer is a non-linear equalizer that quantizes the input analog data into digital form once the sampler determines the symbol or bit data.

[0006] At this time, the quantized data can go through a kind of digital logic to directly remove ISI from the signal mixed with ISI due to the channel.

[0007] However, the decision feedback equalizer according to the prior art has a problem in that the voltage becomes lower than the common mode of the existing output terminal.

[0008] In addition, the decision feedback equalizer according to the prior art has a problem in that the decrease in common mode voltage slows down the operation of the sampler, and thus a separate common mode restoration circuit is required, resulting in a decrease in speed.

[0009] Accordingly, the digital-to-analog conversion-based decision feedback equalization method and device according to one embodiment of the disclosed invention is an invention created to solve the problems of the above-described prior art, and more specifically, the purpose is to provide a digital-to-analog conversion-based decision feedback equalization method and device capable of small signal operation by converting a digital signal into an analog signal in the process of feeding it back.

[0010] In addition, the purpose of the digital-to-analog conversion-based decision feedback equalization method and device according to one embodiment of the disclosed invention is to provide a digital-to-analog conversion-based decision feedback equalization method and device capable of compensating for common mode voltage without a separate common mode restoration circuit.

[0011] In addition, the purpose of the digital-to-analog conversion-based decision feedback equalization method and device according to one embodiment of the disclosed invention is to provide a digital-to-analog conversion-based decision feedback equalization method and device that is robust to noise by implementing a differential swing based on a common mode voltage.

[0012] A digital-to-analog conversion-based decision feedback equalization device according to one embodiment of the disclosed invention may include a GM circuit for receiving an input signal passing through a channel, a sampler circuit configured to receive an analog signal from the GM circuit and convert it into a digital signal, a switching circuit configured to generate and output an analog signal from the digital signal output from the sampler circuit, and a feedback circuit configured to feed back the analog signal output from the switching circuit to an output terminal of the GM circuit.

[0013] The analog signal output by the switching circuit can remove the post-cursor ISI of the input signal generated at the output terminal of the GM circuit by using the current difference.

[0014] The above switching circuit can output a common mode voltage when the values ​​of the digital signals output from the P terminal and the N terminal of the sampler circuit are the same.

[0015] The above switching circuit can output a VH voltage to the P terminal and a VL voltage to the N terminal when the value of the digital signal output from the P terminal of the sampler circuit is 1 and the value of the digital signal output from the N terminal is 0.

[0016] The above switching circuit can output a VL voltage to the P terminal and a VH voltage to the N terminal when the value of the digital signal output from the P terminal of the sampler circuit is 0 and the value of the digital signal output from the N terminal is 1.

[0017] The above switching circuit can adjust the output voltage only when compensation of the input signal passing through the channel is required.

[0018] The above digital-to-analog conversion-based decision feedback equalization device can operate differentially based on a common mode voltage.

[0019] The sampler circuit may include a first sampler circuit that receives an odd signal of the GM circuit and a second sampler circuit that receives an even signal of the GM circuit.

[0020] The above sampler circuit can be configured as a quarter-rate sampler circuit.

[0021] A decision feedback equalization method based on digital-to-analog conversion according to one embodiment of the disclosed invention may include a step of receiving an input signal that has passed through a channel through a GM circuit, a step of receiving an analog signal from the GM circuit through a sampler circuit and converting the analog signal into a digital signal, a step of generating and outputting an analog signal from the digital signal output from the sampler circuit through a switching circuit, and a step of feeding back the analog signal output from the switching circuit to an output terminal of the GM circuit through a feedback circuit.

[0022] The analog signal output by the switching circuit can remove the post-cursor ISI of the input signal generated at the output terminal of the GM circuit by using the current difference.

[0023] The above digital-to-analog conversion-based decision feedback equalization method may further include a step of outputting a common mode voltage through the switching circuit when the values ​​of the digital signals output from the P terminal and the N terminal of the sampler circuit are the same.

[0024] The above digital-to-analog conversion-based decision feedback equalization method may further include a step of outputting a VH voltage to the P terminal and a VL voltage to the N terminal through the switching circuit when the value of the digital signal output from the P terminal of the sampler circuit is 1 and the value of the digital signal output from the N terminal is 0.

[0025] The above digital-to-analog conversion-based decision feedback equalization method may further include a step of outputting a VL voltage to the P terminal and a VH voltage to the N terminal through the switching circuit when the value of the digital signal output from the P terminal of the sampler circuit is 0 and the value of the digital signal output from the N terminal is 1.

[0026] A digital-to-analog conversion-based decision feedback equalization device according to one embodiment of the disclosed invention includes a GM circuit for receiving an input signal passing through a channel, a sampler circuit configured to receive an analog signal from the GM circuit and convert the analog signal into a digital signal, a switching circuit configured to generate and output an analog signal from the digital signal output from the sampler circuit, and a feedback circuit configured to feed back the analog signal output from the switching circuit to an output terminal of the GM circuit, wherein the switching circuit can adjust an output voltage only when compensation of the input signal passing through the channel is required.

[0027] A digital-to-analog conversion-based decision feedback equalization method and device according to one embodiment of the disclosed invention has the advantage of enabling small signal operation by converting a digital signal into an analog signal during the process of feeding it back.

[0028] In addition, the digital-to-analog conversion-based decision feedback equalization method and device according to one embodiment of the disclosed invention has the advantage of being able to compensate for common mode voltage without a separate common mode restoration circuit.

[0029] In addition, the digital-to-analog conversion-based decision feedback equalization method and device according to one embodiment of the disclosed invention has the advantage of being robust to noise by being implemented to differentially swing based on a common mode voltage.

[0030] Fig. 1 is a drawing showing the basic structure of a decision feedback equalizer (DEF) according to the prior art.

[0031] FIG. 2 is a diagram of a summation circuit of a decision feedback equalizer (DEF) according to the prior art illustrated in FIG. 1 implemented as a current mode logic (CML) circuit with a resistive load.

[0032] FIG. 3 is a diagram showing an output waveform for a decision feedback equalizer according to the prior art illustrated in FIG. 2.

[0033] Fig. 4 is a diagram showing a circuit that applies current mirroring and common mode compensation circuits as a decision feedback equalizer according to the prior art.

[0034] FIG. 5 is a circuit diagram of a digital-to-analog conversion-based decision feedback equalization device according to one embodiment of the disclosed invention.

[0035] FIG. 6 is a diagram showing the output of a switching circuit according to the output of a sampler circuit in a digital-to-analog conversion-based decision feedback equalization device according to one embodiment of the disclosed invention.

[0036] FIG. 7 is a diagram showing an output waveform for a decision feedback equalization value according to one embodiment of the disclosed invention illustrated in FIG. 5.

[0037] FIG. 8 is a flowchart illustrating a digital-to-analog conversion-based decision feedback equalization method according to one embodiment of the disclosed invention.

[0038] FIG. 9 is a diagram comparing the output waveform of a decision feedback equalization device according to one embodiment of the disclosed invention illustrated in FIG. 5, and the difference in the output waveform when the decision feedback equalization device is turned OFF and when it is turned ON.

[0039] The embodiments described in this specification and the configurations illustrated in the drawings are merely preferred examples of the disclosed invention, and there may be various modified examples that can replace the embodiments and drawings of this specification at the time of filing of this application.

[0040] Additionally, the same reference numbers or symbols presented in each drawing of this specification represent parts or components that perform substantially the same function.

[0041] Additionally, the terminology used herein is for the purpose of describing embodiments and is not intended to limit and / or restrict the disclosed invention. Singular expressions include plural expressions unless the context clearly dictates otherwise.

[0042] In this specification, terms such as “include” or “have” are intended to specify the presence of a feature, number, step, operation, component, part or combination thereof described in the specification, but do not preclude the possibility of the presence or addition of one or more other features, numbers, steps, operations, components, parts or combinations thereof.

[0043] Additionally, terms including ordinal numbers such as “first,” “second,” etc., used herein may be used to describe various components, but the components are not limited by the terms, and the terms are used only for the purpose of distinguishing one component from another.

[0044] For example, without departing from the scope of the present invention, a first component could be referred to as a second component, and similarly, a second component could also be referred to as a first component. The term "and / or" includes any combination of a plurality of related listed items or any one of a plurality of related listed items.

[0045] Hereinafter, embodiments according to the present invention will be described in detail with reference to the attached drawings.

[0046] Fig. 1 is a diagram showing the basic structure of a decision feedback equalizer (DEF) according to the prior art. Fig. 2 is a diagram showing the summation circuit of the decision feedback equalizer (DEF) according to the prior art shown in Fig. 1 implemented as a current mode logic (CML) circuit with a resistive load. Fig. 3 is a diagram showing the output waveform of the decision feedback equalizer according to the prior art shown in Fig. 2. Fig. 4 is a diagram showing a circuit of a decision feedback equalizer according to the prior art, to which a current mirroring and common mode compensation circuit are applied.

[0047] Referring to FIG. 1, a decision feedback equalizer (DEF) according to the prior art is a non-linear equalizer, and can be configured to quantize input analog data into digital data when a sampler (SAMP) determines symbol or bit data.

[0048] At this time, the quantized data can go through a kind of digital logic to directly remove ISI from the signal mixed with ISI due to the channel.

[0049] Additionally, the decision feedback equalizer illustrated in FIG. 2 can compensate for post-cursor ISI by utilizing the difference in current in a summer circuit that loads a resistor.

[0050] More specifically, the decision feedback equalizer illustrated in FIG. 2 can be implemented in a manner in which analog signals from the OUTP node and the OUTN node are transmitted to a sampler circuit, the sampler circuit quantizes the signal into digital form, and then transmits the signal to the gate of the transistor through the H1 node and the H1B node.

[0051] Such a decision feedback equalizer according to the prior art can compensate according to the characteristics of the channel, and its size can be adjusted by controlling the current of the H1 node.

[0052] At this time, the output values ​​of the H1 node and H1B node are digitally determined as 1 (VDD) or 0 (GND).

[0053] Therefore, the decision feedback equalizer according to the prior art can effectively remove ISI caused by data of the previous symbol by creating a difference in current at the OUTP node and the OUTN node by receiving data of the previous signal through a sampler circuit.

[0054] However, when the decision feedback equalizer according to the prior art is operated, the voltage becomes lower than the common mode of the existing OUTP node and OUTN node.

[0055] This can cause the transistors of the GM stage, which are the core of the summer circuit operation, to move out of the saturation region, and it becomes a factor that hinders the voltage gain and linearity of the summer circuit.

[0056] And the output of the summer circuit is connected to the input of the sampler circuit, and changes in the common mode voltage affect the operating characteristics of this sampler circuit.

[0057] In particular, a drop in common mode voltage is likely to slow down the operation of the sampler circuit.

[0058] Referring to FIG. 3, the waveform output for the embodiment of FIG. 2 can be confirmed.

[0059] Specifically, in the case of the decision feedback equalizer according to the prior art illustrated in FIG. 2, when the equalizer is turned off, the common mode voltage is maintained, but there is a possibility that the sampler circuit may not properly detect the analog signal or may detect it slowly due to ISI.

[0060] Additionally, when the equalizer is turned on, the voltage size increases due to compensation, but the common mode voltage decreases, slowing down the operation speed of the sampler circuit.

[0061] Referring to FIG. 4, a method of adding a common mode compensation circuit is proposed to compensate for the phenomenon of a common mode voltage being lowered in a decision feedback equalizer according to the prior art as described above.

[0062] Specifically, the method of adding a common mode compensation circuit illustrated in FIG. 4 can be implemented by mirroring the current of the H1 node to the PMOS, thereby preserving in the PMOS the amount of current drawn by the NMOS of the equalizer.

[0063] However, when a common mode compensation circuit is inserted as shown in Fig. 4, the additionally generated PMOS acts as parasitic capacitance on the OUTP node and OUTN node, which are the output nodes of the summer circuit, thereby slowing down the speed of the circuit.

[0064] In addition, in a conventional equalizer, the GM circuit (110) swings a small signal based on the common mode, but the feedback circuit (feedback path) has a negative effect on the common mode noise characteristics because the gate voltage of the transistor swings between VDD and 0 V.

[0065]

[0066] FIG. 5 is a circuit diagram of a decision feedback equalization device based on a digital-to-analog conversion according to an embodiment of the disclosed invention. FIG. 6 is a diagram showing the output of a switching circuit according to the output of a sampler circuit in a decision feedback equalization device based on a digital-to-analog conversion according to an embodiment of the disclosed invention. FIG. 7 is a diagram showing an output waveform for a decision feedback equalization value according to an embodiment of the disclosed invention illustrated in FIG. 5.

[0067] Referring to FIG. 5, a digital-to-analog conversion-based decision feedback equalization device (100) according to one embodiment of the disclosed invention may include a GM circuit (110), a sampler circuit (120), a switching circuit (130), and a feedback circuit (140).

[0068] More specifically, the GM circuit (110) of the digital-to-analog conversion-based decision feedback equalization device (100) according to one embodiment of the disclosed invention can receive an input signal passing through a channel.

[0069] Specifically, a signal with ISI added by a channel can be transmitted to a sampler circuit (120) through a GM circuit (110).

[0070] In addition, the sampler circuit (120) of the digital-to-analog conversion-based decision feedback equalization device (100) according to one embodiment of the disclosed invention may be configured to receive an analog signal from the GM circuit (110) and convert it into a digital signal.

[0071] More specifically, the sampler circuit (120) can receive an analog signal and digitize it.

[0072] However, due to channel loss, ISI is input to the input signal of the sampler circuit (120).

[0073] In this case, since there is a possibility that the sampler circuit (120) may output an incorrect value, the digital-to-analog conversion-based decision feedback equalization device according to one embodiment of the disclosed invention can generate an analog signal according to a digital voltage by passing the output of the sampler circuit (120) through a switching circuit (130).

[0074] In addition, the sampler circuit (120) of the digital-to-analog conversion-based decision feedback equalization device (100) according to one embodiment of the disclosed invention may include a first sampler circuit (121) that receives an odd signal from a P terminal output terminal of a GM circuit (110) and a second sampler circuit (122) that receives an even signal from an N terminal output terminal of the GM circuit (110).

[0075] That is, the digital-to-analog conversion-based decision feedback equalization device (100) according to one embodiment of the disclosed invention illustrated in FIG. 5 is an embodiment in which an equalizer is configured for a sampler circuit (120) operating at half-rate.

[0076] However, the embodiment of the digital-to-analog conversion-based decision feedback equalization device (100) according to one embodiment of the disclosed invention is not limited thereto, and the sampler circuit (120) may be configured as a quarter-rate sampler circuit.

[0077] Additionally, an embodiment of a digital-to-analog conversion-based decision feedback equalization device (100) according to one embodiment of the disclosed invention may be configured with a full-rate sampler circuit.

[0078] In addition, the switching circuit (130) of the digital-to-analog conversion-based decision feedback equalization device (100) according to one embodiment of the disclosed invention may be configured to generate and output an analog signal from a digital signal output from a sampler circuit (120).

[0079] More specifically, the switching circuit (130) of the digital-to-analog conversion-based decision feedback equalization device (100) according to one embodiment of the disclosed invention can generate an analog signal according to a digital voltage by passing the output of the quantized (digitized) sampler circuit (120) through a DAC or an analog switch.

[0080] In addition, the analog signal output by the switching circuit (130) of the digital-to-analog conversion-based decision feedback equalization device (100) according to one embodiment of the disclosed invention can remove the post-cursor ISI of the input signal generated at the output terminal of the GM circuit (110) by using the current difference.

[0081] At this time, the switching circuit (130) may include a first switching circuit (131) connected to the first sampler circuit (121) and a second switching circuit (1320) connected to the second sampler circuit (122).

[0082] More specifically, referring to FIG. 6, the switching circuit (130) of the digital-to-analog conversion-based decision feedback equalization device (100) according to one embodiment of the disclosed invention can output a common mode voltage to the H1 node and the H1B node when the values ​​of the digital signals output from the P terminal (DOUTP) and the N terminal (DOUTN) of the sampler circuit (120) are the same.

[0083] In addition, the switching circuit (130) of the digital-to-analog conversion-based decision feedback equalization device (100) according to one embodiment of the disclosed invention can output the VH voltage to the P terminal and the VL voltage to the N terminal when the value of the digital signal output from the P terminal of the sampler circuit (120) is 1 and the value of the digital signal output from the N terminal is 0.

[0084] Specifically, the switching circuit (130) of the digital-to-analog conversion-based decision feedback equalization device (100) according to one embodiment of the disclosed invention can output VH voltage to the H1 node and VL voltage to the H1B node when the value of the digital signal output from the P terminal (DOUTP) of the sampler circuit (120) is 1 and the value of the digital signal output from the N terminal (DOUTN) is 0.

[0085] In addition, the switching circuit (130) of the digital-to-analog conversion-based decision feedback equalization device (100) according to one embodiment of the disclosed invention can output the VL voltage to the P terminal and the VH voltage to the N terminal when the value of the digital signal output from the P terminal of the sampler circuit (120) is 0 and the value of the digital signal output from the N terminal is 1.

[0086] Specifically, the switching circuit (130) of the digital-to-analog conversion-based decision feedback equalization device (100) according to one embodiment of the disclosed invention can output the VL voltage to the H1 node and the VH voltage to the H1B node when the value of the digital signal output from the P terminal (DOUTP) of the sampler circuit (120) is 0 and the value of the digital signal output from the N terminal (DOUTN) is 1.

[0087] That is, the switching circuit (130) of the digital-to-analog conversion-based decision feedback equalization device (100) according to one embodiment of the disclosed invention can adjust the output voltage only when compensation of the input signal passing through the channel is required.

[0088] Specifically, the output voltage of the sampler circuit (120) is usually periodically reset with a Return-to-Vdd or Return-to-zero signal.

[0089] Therefore, the switching circuit (130) of the digital-to-analog conversion-based decision feedback equalization device (100) according to one embodiment of the disclosed invention outputs an analog voltage according to the VH and VL values ​​when the signal is spread between 0 and 1.

[0090] And, the switching circuit (130) of the digital-to-analog conversion-based decision feedback equalization device (100) according to one embodiment of the disclosed invention outputs a common mode voltage for a section in which a signal is reset, i.e., a section in which the OUTP node and the OUTN node have the same value.

[0091] At this time, the values ​​of VH and VL can be applied using a circuit capable of applying analog bias, such as RDAC.

[0092] At this time, the output of the switching circuit (130) of the digital-to-analog conversion-based decision feedback equalization device (100) according to one embodiment of the disclosed invention becomes a signal such as a small signal that periodically resets to a common mode, and the signal passes through the H1 node to generate a difference in current with the GM circuit (110) in the summer circuit to compensate for the post-cursor ISI.

[0093] In addition, the feedback circuit (140) of the digital-to-analog conversion-based decision feedback equalization device (100) according to one embodiment of the disclosed invention may be configured to feed back an analog signal output from the switching circuit (130) to the output terminal of the GM circuit (110).

[0094] More specifically, the feedback circuit (140) of the digital-to-analog conversion-based decision feedback equalization device (100) according to one embodiment of the disclosed invention may include a first feedback circuit (141) connected to a first switching circuit (131) and a second feedback circuit (142) connected to a second switching circuit (132).

[0095] In addition, referring to FIG. 7, the waveform of the present invention can be confirmed for the operational flow starting from the summer circuit to the sampler circuit (120) and equalizer.

[0096] First, a digital-to-analog conversion-based decision feedback equalization device (100) according to one embodiment of the disclosed invention can receive VINP and VINN as inputs of a summer circuit and output OUTP and OUTN.

[0097] At this time, the output of the summer circuit moves to the input of the half rate sampler circuit (120) and samples the values ​​according to the rising edge of CLK and CLKB.

[0098] Additionally, the sampler circuit (120) outputs a signal of 0 or 1, such as DOUTP and DOUTN, as output.

[0099] At this time, if the values ​​of the DOUTP node and the DOUTN node are different digital values ​​(0 or 1), it means that the voltage has been sampled, and if the values ​​of the DOUTP node and the DOUTN node are the same 1, it means that it has been reset.

[0100] Therefore, the digital signal output of the sampler, which appears as Return-to-VDD, is output in the form of a small signal having a common mode voltage of 750 mV through the switching circuit (130).

[0101] The waveform representing this is the output waveform of the H1 node and H1B, and the output values ​​of the H1 node and the H1B node pass through the feedback circuit (140) to remove the post-cursor ISI generated from the output of the GM circuit (110) into a small signal waveform, thereby removing the ISI of the input signal.

[0102] That is, the digital-to-analog conversion-based decision feedback equalization device (100) according to one embodiment of the disclosed invention can operate differentially based on a common mode voltage.

[0103] Therefore, the digital-to-analog conversion-based decision feedback equalization device (100) according to one embodiment of the disclosed invention eliminates the need for a common mode compensation circuit used in the conventional technology.

[0104] If the channel loss is small and therefore compensation of the equalizer is not necessary, the digital-to-analog conversion-based decision feedback equalizer (100) according to one embodiment of the disclosed invention sets the VH and VL voltages to the same as the common mode voltage to maintain the output of the switching circuit (130) at a constant common mode voltage, so that the H1 node does not compensate for ISI.

[0105] On the other hand, when compensation for channel loss is required, the digital-to-analog conversion-based decision feedback equalization device (100) according to one embodiment of the disclosed invention can adjust the small signal swing for compensation by adjusting the VH and VL voltages according to the channel characteristics.

[0106] That is, in the conventional technology, a common mode compensation circuit was added according to the amount of current consumed by the equalizer to compensate for the decrease in the common mode voltage, but in the digital-to-analog conversion-based decision feedback equalizer (100) according to one embodiment of the disclosed invention, there is a technical effect that this is not necessary.

[0107]

[0108] FIG. 8 is a flowchart illustrating a digital-to-analog conversion-based decision feedback equalization method according to one embodiment of the disclosed invention.

[0109] More specifically, a digital-to-analog conversion-based decision feedback equalization method according to one embodiment of the disclosed invention may include a step (S110) of receiving an input signal passing through a channel.

[0110] More specifically, in the step (S110) of receiving an input signal that has passed through a channel, a signal to which ISI has been added by the channel can be transmitted to a sampler circuit (120) through a GM circuit (110).

[0111] In addition, a digital-to-analog conversion-based decision feedback equalization method according to one embodiment of the disclosed invention may include a step (S120) of receiving an analog signal and converting it into a digital signal.

[0112] More specifically, the sampler circuit (120) used in the step (S120) of receiving an analog signal and converting it into a digital signal may include a first sampler circuit (121) that receives an odd signal from a P terminal output terminal of a GM circuit (110) and a second sampler circuit (122) that receives an even signal from an N terminal output terminal of the GM circuit (110).

[0113] However, the embodiment of the digital-to-analog conversion-based decision feedback equalization device (100) according to one embodiment of the disclosed invention is not limited thereto, and the sampler circuit (120) may be configured as a quarter-rate sampler circuit.

[0114] Additionally, an embodiment of a digital-to-analog conversion-based decision feedback equalization device (100) according to one embodiment of the disclosed invention may be configured with a full-rate sampler circuit.

[0115] In addition, a digital-to-analog conversion-based decision feedback equalization method according to one embodiment of the disclosed invention may include a step (S130) of generating and outputting an analog signal from a digital signal output from a sampler circuit (120).

[0116] More specifically, the step (S130) of generating and outputting an analog signal from a digital signal output from a sampler circuit (120) may include a step of passing the output of the quantized (digitized) sampler circuit (120) through a DAC or an analog switch to generate an analog signal according to a digital voltage.

[0117] In addition, in the step (S130) of generating and outputting an analog signal from a digital signal output from a sampler circuit (120), the output analog signal can remove the post-cursor ISI of the input signal generated at the output terminal of the GM circuit (110) by using the current difference.

[0118] More specifically, the step (S130) of generating and outputting an analog signal from a digital signal output from a sampler circuit (120) may include the step of outputting a common mode voltage to the H1 node and the H1B node when the values ​​of the digital signals output from the P terminal (DOUTP) and the N terminal (DOUTN) of the sampler circuit (120) are the same.

[0119] Additionally, the step (S130) of generating and outputting an analog signal from a digital signal output from a sampler circuit (120) may include the step of outputting a VH voltage to the P terminal and a VL voltage to the N terminal when the value of the digital signal output from the P terminal of the sampler circuit (120) is 1 and the value of the digital signal output from the N terminal is 0.

[0120] Specifically, the step (S130) of generating and outputting an analog signal from a digital signal output from a sampler circuit (120) may include the step of outputting a VH voltage to the H1 node and outputting a VL voltage to the H1B node when the value of the digital signal output from the P terminal (DOUTP) of the sampler circuit (120) is 1 and the value of the digital signal output from the N terminal (DOUTN) is 0.

[0121] Additionally, the step (S130) of generating and outputting an analog signal from a digital signal output from a sampler circuit (120) may include the step of outputting a VL voltage to the P terminal and a VH voltage to the N terminal when the value of the digital signal output from the P terminal of the sampler circuit (120) is 0 and the value of the digital signal output from the N terminal is 1.

[0122] Specifically, the step (S130) of generating and outputting an analog signal from a digital signal output from a sampler circuit (120) may include a step of outputting a VL voltage to the H1 node and a VH voltage to the H1B node when the value of the digital signal output from the P terminal (DOUTP) of the sampler circuit (120) is 0 and the value of the digital signal output from the N terminal (DOUTN) is 1.

[0123] That is, the step (S130) of generating and outputting an analog signal from a digital signal output from a sampler circuit (120) may include a step of adjusting the output voltage only when compensation of an input signal passing through a channel is required.

[0124] In addition, the digital-to-analog conversion-based decision feedback equalization method according to one embodiment of the disclosed invention may include a step (S140) of feeding back an analog signal output from a switching circuit (130) to an output terminal of a GM circuit (110) through a feedback circuit (140).

[0125]

[0126] FIG. 9 is a diagram comparing the output waveform of a decision feedback equalization device according to one embodiment of the disclosed invention illustrated in FIG. 5, and the difference in the output waveform when the decision feedback equalization device is turned OFF and when it is turned ON.

[0127] Referring to FIG. 9, it can be confirmed that the output waveforms when the decision feedback equalization decision feedback equalization device according to one embodiment of the disclosed invention is turned OFF and when it is turned ON are maintained identically in the common mode voltage.

[0128] Accordingly, it can be confirmed that the digital-to-analog conversion-based decision feedback equalization device (100) according to one embodiment of the disclosed invention eliminates the need for a common mode compensation circuit used in the conventional technology.

[0129] Therefore, the digital-to-analog conversion-based decision feedback equalization method and device according to one embodiment of the disclosed invention has the advantage of enabling small signal operation by converting a digital signal into an analog signal during the process of feeding it back.

[0130] In addition, the digital-to-analog conversion-based decision feedback equalization method and device according to one embodiment of the disclosed invention has the advantage of being able to compensate for common mode voltage without a separate common mode restoration circuit.

[0131] In addition, the digital-to-analog conversion-based decision feedback equalization method and device according to one embodiment of the disclosed invention has the advantage of being robust to noise by being implemented to differentially swing based on a common mode voltage.

[0132] The devices described above may be implemented as hardware components, software components, and / or a combination of hardware components and software components. For example, the devices and components described in the embodiments may be implemented using one or more general-purpose computers or special-purpose computers, such as, for example, a processor, a controller, an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field programmable array (FPA), a programmable logic unit (PLU), a microprocessor, or any other device capable of executing instructions and responding to them. The processing device may execute an operating system (OS) and one or more software applications running on the operating system. Furthermore, the processing device may access, store, manipulate, process, and generate data in response to the execution of the software. For ease of understanding, the processing device is sometimes described as being used singly; however, those skilled in the art will appreciate that the processing device may include multiple processing elements and / or multiple types of processing elements. For example, the processing device may include multiple processors, or one processor and one controller. Additionally, other processing configurations, such as parallel processors, are also possible.

[0133] Software may include a computer program, code, instructions, or a combination of one or more of these, which may configure a processing device to perform a desired operation or may independently or collectively command the processing device. The software and / or data may be embodied in any type of machine, component, physical device, virtual equipment, computer storage medium, or device for interpretation by the processing device or for providing instructions or data to the processing device. The software may also be distributed over networked computer systems and stored or executed in a distributed manner. The software and data may be stored on one or more computer-readable recording media.

[0134] The method according to the embodiment may be implemented in the form of program commands that can be executed through various computer means and recorded on a computer-readable medium. The computer-readable medium may include program commands, data files, data structures, etc., alone or in combination. The program commands recorded on the medium may be those specially designed and configured for the embodiment or may be those known and available to those skilled in the art of computer software. Examples of the computer-readable recording medium include magnetic media such as hard disks, floppy disks, and magnetic tapes, optical media such as CD-ROMs and DVDs, magneto-optical media such as floptical disks, and hardware devices specially configured to store and execute program commands such as ROMs, RAMs, and flash memories. Examples of program commands include not only machine language codes such as those generated by a compiler, but also high-level language codes that can be executed by a computer using an interpreter, etc.

[0135] Although the embodiments have been described with limited examples and drawings, those skilled in the art will appreciate that various modifications and variations can be made based on the above teachings. For example, appropriate results can be achieved even if the described techniques are performed in a different order than described, and / or components of the described systems, structures, devices, circuits, etc. are combined or combined in a different manner than described, or are replaced or substituted with other components or equivalents. Therefore, other implementations, other embodiments, and equivalents of the claims also fall within the scope of the claims described below.

Claims

1. GM circuit that receives input signals passing through the channel; A sampler circuit configured to receive an analog signal from the above GM circuit and convert it into a digital signal; A switching circuit configured to generate and output an analog signal from the digital signal output from the sampler circuit; and A feedback circuit configured to feed back the analog signal output from the switching circuit to the output terminal of the GM circuit; characterized in that it includes; Digital-to-analog conversion based decision feedback equalizer.

2. In paragraph 1, The analog signal output by the above switching circuit is, It is characterized in that the post-cursor ISI of the input signal generated at the output terminal of the GM circuit is removed using the current difference. Digital-to-analog conversion based decision feedback equalizer.

3. In paragraph 1, The above switching circuit, When the values ​​of the digital signals output from the P terminal and N terminal of the sampler circuit are the same, it is characterized in that a common mode voltage is output. Digital-to-analog conversion based decision feedback equalizer.

4. In paragraph 1, The above switching circuit When the value of the digital signal output from the P terminal of the sampler circuit is 1 and the value of the digital signal output from the N terminal is 0, the VH voltage is output to the P terminal and the VL voltage is output to the N terminal. Digital-to-analog conversion based decision feedback equalizer.

5. In paragraph 1, The above switching circuit When the value of the digital signal output from the P terminal of the sampler circuit is 0 and the value of the digital signal output from the N terminal is 1, the VL voltage is output to the P terminal and the VH voltage is output to the N terminal. Digital-to-analog conversion based decision feedback equalizer.

6. In paragraph 5, The above switching circuit is characterized in that it adjusts the output voltage only when compensation of the input signal passing through the channel is required. Digital-to-analog conversion based decision feedback equalizer.

7. In paragraph 1, characterized by differential operation based on common mode voltage, Digital-to-analog conversion based decision feedback equalizer.

8. In paragraph 1, The above sampler circuit A first sampler circuit that receives an odd signal of the above GM circuit; and A second sampler circuit that receives an even signal of the GM circuit; characterized in that it includes; Digital-to-analog conversion based decision feedback equalizer.

9. In paragraph 1, The above sampler circuit is characterized in that it is composed of a quarter-rate sampler circuit. Digital-to-analog conversion based decision feedback equalizer.

10. A step of receiving an input signal that has passed through a channel through a GM circuit; A step of receiving an analog signal from the GM circuit through a sampler circuit and converting it into a digital signal; A step of generating and outputting an analog signal from the digital signal output from the sampler circuit through a switching circuit; and A step of feeding back the analog signal output from the switching circuit to the output terminal of the GM circuit through a feedback circuit; characterized in that it includes; Decision feedback equalization method based on digital-to-analog conversion.

11. In paragraph 10, The analog signal output by the above switching circuit is, It is characterized in that the post-cursor ISI of the input signal generated at the output terminal of the GM circuit is removed using the current difference. Decision feedback equalization method based on digital-to-analog conversion.

12. In paragraph 10, A method characterized in that it further includes a step of outputting a common mode voltage through the switching circuit when the values ​​of the digital signals output from the P terminal and the N terminal of the sampler circuit are the same. Decision feedback equalization method based on digital-to-analog conversion.

13. In paragraph 10, A method characterized in that it further includes a step of outputting a VH voltage to the P terminal and a VL voltage to the N terminal through the switching circuit when the value of the digital signal output from the P terminal of the sampler circuit is 1 and the value of the digital signal output from the N terminal is 0; Decision feedback equalization method based on digital-to-analog conversion.

14. In paragraph 10, A method characterized in that it further includes a step of outputting a VL voltage to the P terminal and a VH voltage to the N terminal through the switching circuit when the value of the digital signal output from the P terminal of the sampler circuit is 0 and the value of the digital signal output from the N terminal is 1; Decision feedback equalization method based on digital-to-analog conversion.

15. GM circuit that receives input signals passing through the channel; A sampler circuit configured to receive an analog signal from the above GM circuit and convert it into a digital signal; A switching circuit configured to generate and output an analog signal from the digital signal output from the sampler circuit; and A feedback circuit configured to feed back the analog signal output from the switching circuit to the output terminal of the GM circuit; The above switching circuit is characterized in that it adjusts the output voltage only when compensation of the input signal passing through the channel is required. Digital-to-analog conversion based decision feedback equalizer.

Images