Integrated battery and method for manufacturing same

Abstract

According to exemplary embodiments, an integrated battery is provided. The integrated battery comprises: a substrate; a plurality of patterns which are in contact with the substrate and have a polarity opposite to that of the substrate; and a plurality of energy source patterns configured to irradiate radiation to the substrate and the plurality of patterns, wherein each of the plurality of energy source patterns has a tapered shape.

Description

Integrated battery and method for manufacturing the same

[0001] The present invention relates to an integrated battery and a method for manufacturing the same. This application claims the benefit of Korean Application No. 10-2024-0121832, filed June 6, 2024, and Korean Application No. 10-2025-0125548, filed September 4, 2025, which are incorporated herein by reference in their entirety.

[0002] A radiobattery is a type of battery that generates electricity by utilizing the decay of radioactive isotopes. These batteries primarily use radioisotopes that emit beta and / or alpha rays and semiconductor materials to generate electricity. Radiobatteries operate by directly converting the energy released during radioactive decay into electrical energy.

[0003] Radioactive batteries can continuously produce energy throughout the half-life of their radioisotopes, resulting in extremely long lifespans. Furthermore, they can provide a constant power output regardless of environmental conditions, allowing for reliable operation even in extreme environments.

[0004] The technical idea of ​​the present invention is to provide an integrated battery and a method for manufacturing the same.

[0005] According to exemplary embodiments of the present invention for solving the above-described problem, a direct battery is provided. The integrated battery comprises: a substrate; a plurality of patterns in contact with the substrate and having a polarity opposite to that of the substrate; and a plurality of energy source patterns configured to irradiate radiation to the substrate and the plurality of patterns, wherein each of the plurality of energy source patterns has a tapered shape.

[0006] The above substrate includes a plurality of holes extending in a direction perpendicular to an upper surface of the substrate, and each of the plurality of energy source patterns is located in a corresponding one of the plurality of holes.

[0007] Each of the above plurality of holes has a tapered shape.

[0008] The width of each of the plurality of energy source patterns decreases as it moves away from the upper surface.

[0009] Each of the above plurality of patterns has a uniform thickness.

[0010] Each of the above plurality of patterns is between the corresponding one of the above description and the above plurality of energy source patterns.

[0011] The above plurality of holes are arranged in a honeycomb structure.

[0012] The plurality of holes constitute a plurality of hole arrays, and the plurality of hole arrays are staggered with each other.

[0013] The above plurality of holes are arranged in a matrix. Each of the above plurality of holes has a line shape.

[0014] Each of the above plurality of holes has a roughened surface.

[0015] Each of the above plurality of holes has a star shape when viewed from above.

[0016] The interface between the above-described substrate and the plurality of patterns is roughened.

[0017] The interface between the plurality of patterns and the plurality of energy source patterns is roughened.

[0018] Each of the above plurality of energy source patterns is configured to emit beta rays.

[0019] Each of the plurality of energy source patterns is configured to emit alpha rays.

[0020] The integrated cell further comprises a plurality of sub-flash patterns configured to emit photons in response to the alpha rays.

[0021] Each of the plurality of lower flash patterns is between a corresponding one of the plurality of energy source patterns and a corresponding one of the plurality of patterns.

[0022] The integrated cell further comprises a plurality of upper scintillation patterns configured to emit photons corresponding to the alpha rays.

[0023] Each of the plurality of upper flash patterns is on a corresponding one of the plurality of energy source patterns.

[0024] Each of the plurality of energy source patterns is surrounded by a corresponding one of the plurality of upper flash patterns and a corresponding one of the plurality of lower flash patterns.

[0025] Each of the plurality of upper flash patterns forms a layer that is continuous with a corresponding one of the plurality of lower flash patterns.

[0026] According to exemplary embodiments, a direct battery is provided. The direct battery includes a first battery layer including a first layer comprising a plurality of first holes, a plurality of first energy source patterns within the plurality of first holes, and a plurality of first patterns interposed between the plurality of first energy source patterns and the first layer and having a polarity opposite to that of the first layer; a second battery layer including a plurality of second holes, a plurality of second energy source patterns within the plurality of second holes, and a plurality of second patterns interposed between the plurality of second energy source patterns and the second layer and having a polarity opposite to that of the second layer; and an insulating layer interposed between the first battery layer and the second battery layer.

[0027] The battery further includes a plurality of vias penetrating the insulating layer and connecting the first battery layer and the second battery layer, wherein the plurality of vias connect the first battery layer and the second battery layer in series.

[0028] Each of the plurality of vias is in contact with a corresponding one of the second layer and the plurality of first patterns.

[0029] The above plurality of vias connect the first battery layer and the second battery layer in series.

[0030] The first layer has the same polarity as the second layer.

[0031] The above plurality of vias connect the first battery layer and the second battery layer in parallel.

[0032] The first layer has an opposite polarity to the second layer.

[0033] Each of the plurality of first energy source patterns and the plurality of second energy source patterns has a tapered shape.

[0034] Each of the plurality of first patterns and the plurality of second patterns has a cup shape.

[0035] Each of the plurality of first patterns and the plurality of second patterns has a uniform thickness.

[0036] Each of the plurality of first holes and the plurality of second holes has a tapered shape.

[0037] The above integrated cell further comprises a core layer including peripheral transistors, and the first cell layer is on the core layer.

[0038] The above peripheral transistors constitute a voltage regulator that controls the output voltage of the first and second battery layers.

[0039] According to exemplary embodiments, a direct battery is provided. The direct battery includes a substrate including a plurality of holes; a plurality of energy source patterns within the plurality of holes and having a narrowed neck shape; and a plurality of patterns interposed between the plurality of energy source patterns and the substrate and having a polarity opposite to that of the substrate.

[0040] Each of the above plurality of holes has a narrow neck shape.

[0041] An integrated circuit according to exemplary embodiments of the present invention has an oblique interface between a layer and an energy source. Accordingly, the energy efficiency of the energy source can be improved.

[0042] The effects that can be obtained from the exemplary embodiments of the present invention are not limited to the effects mentioned above, and other effects not mentioned can be clearly derived and understood by those skilled in the art to which the exemplary embodiments of the present disclosure pertain from the following description. In other words, unintended effects resulting from practicing the exemplary embodiments of the present disclosure can also be derived by those skilled in the art from the exemplary embodiments of the present disclosure.

[0043] Figure 1 is a flowchart illustrating a method for manufacturing an integrated battery.

[0044] FIG. 2 is a plan view illustrating a method for manufacturing an integrated battery according to exemplary embodiments.

[0045] Figure 3 is a cross-sectional view taken along the cutting line 2I-2I' of Figure 2.

[0046] FIG. 4 is a plan view illustrating a method for manufacturing an integrated battery according to exemplary embodiments.

[0047] Figure 5 is a cross-sectional view taken along the cutting line 4I-4I' of Figure 4.

[0048] FIG. 6 is a plan view illustrating a method for manufacturing an integrated battery according to exemplary embodiments.

[0049] Figure 7 is a cross-sectional view taken along the cutting line 6I-6I' of Figure 6.

[0050] FIG. 8 is a plan view illustrating a method for manufacturing an integrated battery according to exemplary embodiments.

[0051] Fig. 9 is a cross-sectional view taken along the cutting line 8I-8I' of Fig. 8.

[0052] FIG. 10 is a plan view illustrating a method for manufacturing an integrated battery according to exemplary embodiments.

[0053] Fig. 11 is a cross-sectional view taken along the cutting line 10I-10I' of Fig. 10.

[0054] Fig. 12 is a cross-sectional view illustrating a method for manufacturing an integrated battery according to exemplary embodiments. Fig. 13 is a flowchart illustrating a method for manufacturing an integrated battery.

[0055] FIGS. 14 to 16 are drawings for explaining a method of manufacturing an integrated battery according to exemplary embodiments.

[0056] Figure 17 is a flowchart for explaining a method for manufacturing an integrated battery.

[0057] FIGS. 18 to 21 are cross-sectional views illustrating a method for manufacturing an integrated battery according to exemplary embodiments.

[0058] FIG. 22 is a plan view illustrating a method for manufacturing an integrated battery according to exemplary embodiments.

[0059] Fig. 23 is a cross-sectional view taken along the cutting line 22I-22I' of Fig. 22.

[0060] FIG. 24 is a cross-sectional view illustrating a method for manufacturing an integrated battery according to exemplary embodiments.

[0061] FIG. 25 is a drawing showing an integrated battery according to other exemplary embodiments.

[0062] FIG. 26 is a plan view of an integrated battery according to other exemplary embodiments.

[0063] Fig. 27 is a cross-sectional view taken along the cutting line 26I-26I' of Fig. 26.

[0064] FIG. 28 is a plan view of an integrated battery according to other exemplary embodiments.

[0065] Figure 29 is a cross-sectional view taken along the cutting line 28I-28I' of Figure 28.

[0066] FIG. 30 is a plan view of an integrated battery according to other exemplary embodiments.

[0067] Fig. 31 is a cross-sectional view taken along the cutting line 30I-30I' of Fig. 30.

[0068] FIG. 32 is a plan view of an integrated battery according to other exemplary embodiments.

[0069] Figure 33 is a cross-sectional view taken along the cutting line 32I-32I' of Figure 32.

[0070] FIG. 34 is a plan view illustrating a method for manufacturing an integrated battery according to exemplary embodiments.

[0071] Figure 35 is a cross-sectional view taken along the cutting line 34I-34I' of Figure 34.

[0072] FIG. 36 is a plan view illustrating a method for manufacturing an integrated battery according to exemplary embodiments.

[0073] Figure 37 is a cross-sectional view taken along the cutting line 36I-36I' of Figure 36.

[0074] Fig. 38 is a cross-sectional view illustrating a method for manufacturing an integrated battery according to exemplary embodiments. More specifically, Fig. 38 shows a portion corresponding to Fig. 37.

[0075] FIG. 39 is a flowchart illustrating a method for manufacturing another integrated battery in other exemplary embodiments.

[0076] FIGS. 40 to 46 are cross-sectional views illustrating a method of manufacturing another integrated battery according to other exemplary embodiments.

[0077] Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the attached drawings. Prior to this, it should be noted that the terms and words used in this specification and claims should not be construed as limited to their conventional or dictionary meanings. Based on the principle that the inventor can appropriately define the concepts of terms to best explain his or her invention, they should be interpreted in a way that aligns with the technical spirit of the present invention.

[0078] Accordingly, the embodiments described in this specification and the configurations illustrated in the drawings are merely the most preferred embodiments of the present invention and do not represent all of the technical ideas of the present invention. Therefore, it should be understood that there may be various equivalents and modified examples that can replace them at the time of filing this application.

[0079] In addition, when describing the present invention, if it is determined that a detailed description of a related known configuration or function may obscure the gist of the present invention, the detailed description is omitted.

[0080] Since the embodiments of the present invention are provided to more fully explain the present invention to those skilled in the art, the shapes and sizes of components in the drawings may be exaggerated, omitted, or schematically illustrated for clearer explanation. Accordingly, the sizes and proportions of each component do not fully reflect the actual sizes or proportions.

[0081]

[0082] (Embodiments 1 and 2)

[0083] Figure 1 is a flowchart illustrating a method for manufacturing an integrated battery.

[0084] FIG. 2 is a plan view illustrating a method for manufacturing an integrated battery according to exemplary embodiments.

[0085] Figure 3 is a cross-sectional view taken along the cutting line 2I-2I' of Figure 2.

[0086] FIG. 4 is a plan view illustrating a method for manufacturing an integrated battery according to exemplary embodiments.

[0087] Figure 5 is a cross-sectional view taken along the cutting line 4I-4I' of Figure 4.

[0088] FIG. 6 is a plan view illustrating a method for manufacturing an integrated battery according to exemplary embodiments.

[0089] Figure 7 is a cross-sectional view taken along the cutting line 6I-6I' of Figure 6.

[0090] FIG. 8 is a plan view illustrating a method for manufacturing an integrated battery according to exemplary embodiments.

[0091] Fig. 9 is a cross-sectional view taken along the cutting line 8I-8I' of Fig. 8.

[0092] FIG. 10 is a plan view illustrating a method for manufacturing an integrated battery according to exemplary embodiments.

[0093] Fig. 11 is a cross-sectional view taken along the cutting line 10I-10I' of Fig. 10.

[0094] Fig. 12 is a cross-sectional view illustrating a method for manufacturing an integrated battery according to exemplary embodiments. More specifically, Fig. 12 shows a portion corresponding to Fig. 11.

[0095] Referring to FIGS. 1 to 3, a substrate (110) can be provided at P110.

[0096] The above-mentioned material (100) may be an insulator or a semiconductor.

[0097] The above-described substrate (100) may include, for example, a III-V group semiconductor material. The III-V group semiconductor material may include InAlP, InGaP, InAlGaP, ZnSe, AlAs, AlAsP, or yttria-stabilized zirconia (YSZ).

[0098] According to exemplary embodiments, the substrate (110) may include any one of a diamond substrate, a SiC substrate, a GaN substrate, a Bi2O3 / GeO2 substrate, a Sm2O3 / Bi2O3 / GeO2 substrate, a Sm2O3 / Bi2O3 / B2O3 substrate, a Sm2O3 / Bi2O3 / GeO2 / B2O3 substrate, and a sapphire substrate. The substrate (110) may be processed by any one of ion implantation and diffusion. The substrate (110) may be doped with a dopant of a first conductivity type. The dopant of the first conductivity type may be a p-type dopant or an n-type dopant.

[0099] The p-type dopant may include one or more of boron (B), aluminum (Al), gallium (Ga), and indium (In). The n-type dopant may include one or more of nitrogen (N), phosphorus (P), arsenic (As), and antimony (Sb).

[0100] The substrate (110) may include a metal oxide having a band gap energy of 2.7 eV or more. In some embodiments, the substrate (110) may include a material represented by AMO3 (wherein A is at least one selected from the group consisting of La, Ba, Sr, and K, and M is at least one selected from the group consisting of Al, In, Ga, Ti, Sn, Hf, Ta, and Zr).

[0101] For example, the substrate (110) is BaSnO3, BaHfO3, BaZrO3, BaHf 1-x Ti x O3 (where 0 <x<1), Ba 1-x La x SnO3 (where 0 <x<1), Bi4Ge3O 12 , Al2O3, Y2O3, La2O3, Ga2O3, Bi2O3, ZrO2, HfO2, Ta2O5, TiO2, LaInO3, LaGaO3, SrZrO3, SrHfO3, SrTaO7, LaIn 1-x Ga xO3 (where 0 <x<1), LaGaO3, SrTiO3, KTaO3, HfSiO4, Ta3Ti2O x (0 here <x<1) 및 LaAlO3중 하나 이상을 포함할 수 있다.

[0102]

[0103] Next, referring to FIGS. 1, 4, and 5, the substrate (110) can be patterned at P120. The substrate (110) can be patterned by any one of reactive ion etching (RIE) including low-temperature etching and ion beam etching. The substrate (110) can also be patterned by a laser beam. The substrate (110) can also be patterned by anisotropic wet etching.

[0104] Before patterning the substrate (110), a mask pattern may be formed on the substrate (110). The mask pattern may be formed by photolithography. The mask pattern may expose a portion of the substrate (110) to be etched (i.e., a portion where a plurality of recesses (110R) are to be formed) and cover a non-etched portion (i.e., a portion between the plurality of recesses (110R)). A hard mask may also be additionally provided between the mask pattern and the substrate (110).

[0105] A plurality of recesses (110R) can be formed by patterning the substrate (110). According to exemplary embodiments, the plurality of recesses (110R) may have a circular shape when viewed from above. When the plurality of recesses (110R) have a circular shape when viewed from above, the plurality of recesses (110R) can be said to have a circular planar shape.

[0106] Two directions substantially parallel to the upper surface (110U) of the substrate (110) are defined as the X direction and the Y direction, and a direction substantially perpendicular to each of the X direction and the Y direction is defined as the Z direction. The X direction, the Y direction, and the Z direction can be substantially perpendicular to each other.

[0107] According to exemplary embodiments, the plurality of recesses (110R) may be arranged in a honeycomb structure. The plurality of recesses (110R) being arranged in a honeycomb structure means that the center (110RC) of each of the plurality of recesses (110R) is at the vertices and centers of a plurality of regular hexagons of the same size filling the plane.

[0108] Each of the plurality of recesses (110R) may have a variable width along the Z direction (e.g., a horizontal width such as a width in the X direction and / or a width in the Y direction). Each of the plurality of recesses (110R) may have a tapered shape in the Z direction. Each of the plurality of recesses (110R) may extend in the Z direction from the upper surface (110U), and a width of each of the plurality of recesses (110R) may decrease as it moves away from the upper surface (110U). A width of each of the plurality of recesses (110R) at a first depth from the upper surface (110U) may be smaller than a width of each of the plurality of recesses (110R) at a second depth from the upper surface (110U) that is smaller than the first depth.

[0109]

[0110] Next, referring to FIGS. 1, 6, and 7, a layer (120L) can be formed at P130. The layer (120L) can have a uniform thickness, and thus, the layer (120L) can have a conformal shape. That the layer (120L) has a conformal shape means that the shape of the structure (i.e., the substrate (110) and the plurality of recesses (110R)) prior to the formation of the layer (120L) is transferred to the shape of the layer (120L).

[0111] The layer (120L) may be formed by, but is not limited to, either chemical vapor deposition (CVD) or physical vapor deposition (PVD). The layer (120L) may also be formed by an oxidation process of a metal layer formed by metal CVD.

[0112] The layer (120L) may include a metal oxide having a band gap energy of 2.7 eV or more. In some embodiments, the layer (120L) may include a material represented by AMO3 (wherein A is at least one selected from the group consisting of La, Ba, Sr, and K, and M is at least one selected from the group consisting of Al, In, Ga, Ti, Sn, Hf, Ta, and Zr).

[0113] For example, the layer (120L) is BaSnO3, BaHfO3, BaZrO3, BaHf 1-x Ti x O3 (where 0 <x<1), Ba 1-x La x SnO3 (where 0 <x<1), Bi4Ge3O 12 , Al2O3, Y2O3, La2O3, Ga2O3, Bi2O3, ZrO2, HfO2, Ta2O5, TiO2, LaInO3, LaGaO3, SrZrO3, SrHfO3, SrTaO7, LaIn 1-x Ga x O3 (where 0 <x<1), LaGaO3, SrTiO3, KTaO3, HfSiO4, Ta3Ti2O x (0 here <x<1) 및 LaAlO3중 하나 이상을 포함할 수 있다.

[0114] Metal oxides are stable even in high-temperature and high-humidity environments and exhibit high carrier mobility. Carrier movement within the layer (120L) is free of inelastic collisions. Accordingly, integrated cells manufactured based on the layer (120L) can exhibit high energy efficiency and excellent heat dissipation properties.

[0115] According to exemplary embodiments, the mobility of the carrier in the layer (120L) is about 45 cm 2 / (Vs) or more. According to exemplary embodiments, the mobility of the carrier in the layer (120L) is about 80 cm 2 / (Vs) or more. According to exemplary embodiments, the mobility of the carrier in the layer (120L) is about 120 cm 2 / (Vs) or more. According to exemplary embodiments, the mobility of the carrier in the layer (120L) is about 300 cm 2 / (Vs) can be more than that.

[0116] The layer (120L) may include one of a doped semiconductor material, a compound semiconductor, an oxide semiconductor, or a metal alloy. According to exemplary embodiments, the layer (120L) may be silicon (Si) doped with boron (B), silicon (Si) doped with one of phosphorus (P) and arsenic (As), gallium arsenide (GaAs) doped with zinc (Zn), gallium arsenide (GaAs) doped with one of silicon (Si) and tellurium (Te), germanium (Ge) doped with boron (B), germanium (Ge) doped with one of phosphorus (P) and antimony (Sb), gallium nitride (GaN) doped with magnesium (Mg), gallium nitride (GaN) doped with silicon (Si), silicon carbide (SiC) doped with one of aluminum (Al) and boron (B), silicon carbide (SiC) doped with one of nitrogen (N) and phosphorus (P), indium phosphate (InP) doped with zinc (Zn), indium doped with one of sulfur (S) and silicon (Si). It may also include one of cadmium phosphate (InP), cadmium telluride (CdTe), cadmium sulfide (CdS), tin oxide (SnO), and zinc oxide (ZnO).

[0117] The layer (120L) may be doped with a second conductive type dopant opposite to the first conductive type dopant. For example, when the first conductive type dopant is a p-type dopant, the second conductive type dopant may be an n-type dopant, and when the first conductive type dopant is an n-type dopant, the second conductive type dopant may be a p-type dopant. Accordingly, a pn junction and a resulting depletion region may be formed between the substrate (110) and the layer (120L).

[0118]

[0119] Next, referring to FIGS. 1, 8, and 9, an energy source layer (130L) can be formed at P140. The energy source layer (130L) can be formed by any one of evaporation, sputtering, CVD, electroplating, and electroless plating. The energy source layer (130L) can be provided in an amount sufficient to fill the recess (110R). When the energy source layer (130L) is formed by electroplating or electroless plating, a seed layer can be formed between the energy source layer (130L) and the layer (120L).

[0120] The energy source layer (130L) may include a radioactive isotope. The energy source layer (130L) may be configured to emit radiation. The energy source layer (130L) may include, for example, a radioactive isotope that emits beta rays. The energy source layer (130L) may include, for example, tritium ( 3 H, tritium), Calcium-45( 45 Ca), nickel-63( 63 Ni), copper-67( 67 Cu), strontium-90( 90 Sr), promethium-147( 147 Pm), osmium-194( 194 OS), thulium-171( 171Tm), tantalum-179( 179 Ta), cadmium-109( 109 Cd), germanium-68( 68 Ge), cerium-159( 159 Ce) and tungsten-181( 181 W) may contain one or more of the following: Radioisotopes may emit only beta rays, or they may emit radiation other than beta rays, such as alpha rays or gamma rays.

[0121] Next, referring to FIGS. 1, 10, and 11, a first CMP (Chemical Mechanical Polishing) process can be performed at P150. The upper surface (110U) of the substrate (110) can be the end point of the first CMP process. The CMP process can be determined by changes in reflectivity or concentration of a specific chemical component within the CMP chamber.

[0122] By the first CMP process, the layer (120L) can be separated into a plurality of patterns (120). By the first CMP process, the energy source layer (130L) can be separated into a plurality of energy source patterns (130). The upper surface of each of the plurality of patterns (120) and the upper surface of each of the plurality of energy source patterns (130) can be coplanar with the upper surface (110U) of the substrate (110).

[0123]

[0124] Next, referring to FIGS. 1, 11, and 12, a second CMP process may be performed at P160. A plurality of energy source patterns (130) may be the end point of the second CMP process. Through the second CMP process, an integrated battery (100) including a substrate (110), a plurality of patterns (120), and a plurality of energy source patterns (130) may be provided.

[0125] The plurality of recesses (110R) of FIG. 11 may be a plurality of holes (110H) extending to a new lower surface (110L') of the substrate (110). Each of the plurality of holes (110H) may penetrate the substrate (110). The lower surface of each of the plurality of patterns (120) and the lower surface of each of the plurality of energy source patterns (130) may be coplanar with the lower surface (110L').

[0126] According to exemplary embodiments, the substrate (110) may include a plurality of holes (110H) having a tapered shape. The plurality of holes (110H) may extend in the Z direction perpendicular to the upper surface (110U) of the substrate (110). The plurality of holes (110H) may penetrate the substrate (110).

[0127] A plurality of energy source patterns (130) may be located within corresponding ones of the plurality of holes (110H). Each of the plurality of energy source patterns (130) may have a tapered shape.

[0128] A plurality of patterns (120) may be in contact with the substrate (110). The plurality of patterns (120) may have an opposite polarity to the substrate (110). Each of the plurality of patterns (120) may be between the substrate (110) and a corresponding one of the plurality of energy source patterns (130). The thickness of each of the plurality of patterns (120) may be uniform.

[0129]

[0130] (Examples 3 and 4)

[0131] Figure 13 is a flowchart for explaining a method for manufacturing an integrated battery.

[0132] FIGS. 14 to 16 are drawings for explaining a method of manufacturing an integrated battery according to exemplary embodiments.

[0133] Referring to FIGS. 13 and 14, the upper surface (210U) of the substrate (210) can be patterned at P210. The substrate (210) can include the same material as the substrate (110) of FIG. 2. The substrate (210) can be doped in the same manner as the substrate (110) of FIG. 2. The substrate (210) can be patterned by any one of RIE and ion beam etching.

[0134] A plurality of recesses (210R) can be formed by patterning the substrate (210). Each of the plurality of recesses (210R) can have one of a circular shape and a line shape. Each of the plurality of recesses (210R) can be arranged in a matrix, in a honeycomb structure, or in a line-and-space pattern.

[0135] Each of the plurality of recesses (210R) may have a variable width along the Z direction. Each of the plurality of recesses (210R) may have a tapered shape in the Z direction. Each of the plurality of recesses (210R) may extend in the Z direction from the upper surface (210U), and the width of each of the plurality of recesses (210R) may decrease as it moves away from the upper surface (210U). The width of each of the plurality of recesses (210R) at a first depth from the upper surface (210U) may be smaller than the width of each of the plurality of recesses (210R) at a second depth from the upper surface (210U) that is smaller than the first depth.

[0136]

[0137] Next, referring to FIGS. 13 to 15, the lower surface (210L) of the substrate (210) can be patterned at P220. The substrate (210) can be patterned by any one of RIE and ion beam etching.

[0138] The patterning position of the lower surface (210L) of the substrate (210) can be aligned with the patterning position of the upper surface (210U) of the substrate. Accordingly, a plurality of recesses (210R) extending from the upper surface (210U) of the substrate (210) can be connected to a plurality of recesses formed from the lower surface (210L) of the substrate (210), thereby forming a plurality of holes (210H).

[0139] Each of the plurality of holes (210H) may have an hourglass shape. Each of the plurality of holes (210H) may have a necked shape.

[0140]

[0141] Next, referring to FIGS. 13 and 16, a plurality of patterns (220) and a plurality of energy source patterns (230) can be formed at P230. Accordingly, an integrated battery (200) including a substrate (210), a plurality of patterns (220), and a plurality of energy source patterns (230) can be provided.

[0142] In P230, forming a plurality of patterns (220) and a plurality of energy source patterns (230) may include forming a layer through any one of a CVD, PVD, and oxidation process, forming an energy source layer through any one of an evaporation method, sputtering, CVD, electroplating, and electroless plating, performing a first CMP process with an upper surface (210U) of the substrate (210) as an end point, and performing a second CMP process with a lower surface (210L) of the substrate (210) as an end point.

[0143] Each of the plurality of patterns (220) may include the same material as the layer (120L) of FIG. 7. Each of the plurality of energy source patterns (230) may include the same material as the energy source layer (130L) of FIG. 9.

[0144] Each of the plurality of patterns (220) may have a uniform thickness. Accordingly, the shape of the plurality of holes (210H) may be transferred to the plurality of patterns (220). Each of the plurality of patterns (220) may have a conformal shape.

[0145] A plurality of energy source patterns (230) may be within a plurality of holes (210H). The plurality of energy source patterns (230) may fill a space defined by the plurality of patterns (220). The plurality of patterns (220) may be interposed between the plurality of energy source patterns (230) and the substrate (210). Each of the plurality of energy source patterns (230) may have an hourglass shape. Each of the plurality of energy source patterns (230) may have a shape with a narrowed neck.

[0146]

[0147] (Examples 5 and 6)

[0148] Figure 17 is a flowchart for explaining a method for manufacturing an integrated battery.

[0149] FIGS. 18 to 21 are cross-sectional views illustrating a method for manufacturing an integrated battery according to exemplary embodiments.

[0150] FIG. 22 is a plan view illustrating a method for manufacturing an integrated battery according to exemplary embodiments.

[0151] Fig. 23 is a cross-sectional view taken along the cutting line 22I-22I' of Fig. 22.

[0152] FIG. 24 is a cross-sectional view illustrating a method for manufacturing an integrated battery according to exemplary embodiments.

[0153]

[0154] Referring to FIGS. 17 and 18, a core layer (LC) can be formed in P310. Forming the core layer (LC) may include forming a device isolation film (311) on a substrate (310), sequentially forming a p-well region and an n-well region in the substrate (310) (or in the opposite order) through an ion implantation process using a photoresist pattern of the substrate (310), forming peripheral transistors (315), and forming conductive vias (319V) and conductive lines (319L) by patterning a conductive material and providing an insulating layer (320).

[0155] The substrate (310) may include a semiconductor material such as, for example, silicon, germanium, silicon-germanium, etc., and may further include an epitaxial layer, a silicon on insulator (SOI) layer, a germanium on insulator (GOI) layer, a semiconductor on insulator (SeOI) layer, etc.

[0156] Each of the peripheral transistors (315) may include a gate oxide film (316), a gate electrode (317), and source / drain regions (318). Each of the peripheral transistors (315) may be formed through a CMOS (Complementary Metal-Oxide-Semiconductor) logic process.

[0157] Here, the CMOS logic process may include forming a gate oxide film (316), forming a gate electrode (317) comprising polysilicon or metal, and forming source / drain regions (318) through ion implantation. Although not explicitly shown, gate spacers may be further formed after forming the gate electrode (317).

[0158] Each of the conductive vias (319V) and the conductive lines (319L) may include a conductive material. Each of the conductive vias (319V) and the conductive lines (319L) may include, but is not limited to, copper. Each of the conductive vias (319V) and the conductive lines (319L) may also include one or more of tungsten, tantalum, cobalt, nickel, tungsten silicide, tantalum silicide, cobalt silicide, and nickel silicide. Each of the conductive vias (319V) and the conductive lines (319L) may also include polysilicon.

[0159] Each of the conductive vias (319V) may extend in the Z direction. The conductive vias (319V) may be embedded in the insulating layer (151). The conductive vias (319V) may be connected to peripheral transistors (315) or may be connected to conductive lines (319L).

[0160] Each of the conductive lines (319L) may extend in a horizontal direction. The conductive lines (319L) may be embedded in an insulating layer (320). Each of the conductive lines (319L) may extend, for example, in the X direction and / or the Y direction. The conductive lines (319L) may be connected to conductive vias (319V).

[0161] The insulating layer (320) may include one or more of silicate (e.g., TEOS), silicon nitride (SiN), hafnium oxide, hafnium silicon oxide, hafnium aluminum oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, and aluminum oxide.

[0162] The insulating layer (320) may include a plurality of sequentially formed insulating layers. For example, an insulating layer for forming a conductive via (319V) may be formed for each layer, and an insulating layer for forming a conductive line (319L) may be formed for each layer.

[0163]

[0164] Next, referring to FIGS. 17 and 19, a layer (330) can be formed in P320. The layer (330) can be formed by either CVD or epitaxial growth. The layer (330) can be doped with a first dopant. The first dopant can be introduced into the layer (330) during the growth of the layer (330), or the layer (330) can be doped by ion implantation and diffusion after the layer (330) is formed.

[0165]

[0166] Next, referring to FIGS. 17 and 20, the layer (330) can be patterned in P330. The layer (330) can be patterned by either RIE or ion beam etching. The layer (330) can also be patterned by anisotropic wet etching.

[0167] A plurality of holes (330H) exposing the insulating layer (320) can be formed by patterning the layer (330). Each of the plurality of holes (330H) can have one of a circular shape and a line shape. Each of the plurality of holes (330H) can be arranged in a matrix, in a honeycomb structure, or in a line-and-space pattern.

[0168] Each of the plurality of holes (330H) may have a variable width along the Z direction. Each of the plurality of holes (330H) may have a tapered shape in the Z direction. Each of the plurality of holes (330H) may extend in the Z direction from the upper surface (210U), and the width of each of the plurality of holes (330H) may decrease as it approaches the substrate (310). The width of each of the plurality of holes (330H) at a first level from the substrate (310) may be smaller than the width of each of the plurality of holes (330H) at a second level from the substrate (310) that is larger than the first level.

[0169]

[0170] Next, referring to FIG. 17 and FIG. 21, in P340, a plurality of patterns (340) and a plurality of energy source patterns (350) can be formed.

[0171] Forming a plurality of patterns (340) and a plurality of energy source patterns (350) may include forming a layer through any one of a CVD, PVD, and oxidation process, forming an energy source layer through any one of an evaporation method, sputtering, CVD, electroplating, and electroless plating, and performing a CMP process with the upper surface of the layer (330) as an end point.

[0172] A plurality of patterns (340) can partially fill a plurality of holes (330H). Each of the plurality of patterns (340) can have a uniform thickness. Each of the plurality of patterns (340) can have a conformal shape. Each of the plurality of patterns (340) can have a cup shape.

[0173] Each of the plurality of patterns (340) may be doped with a second dopant having an opposite polarity to the first dopant. Accordingly, the polarity of each of the patterns (340) may be opposite to that of the layer (330), and a pn junction and a depletion region may be formed at the interface between the patterns (340) and the layer (330). Each of the layer (330) and the patterns (340) may include one of a doped semiconductor material, a compound semiconductor, an oxide semiconductor, or a metal alloy. According to exemplary embodiments, the layer (330) may include silicon (Si) doped with boron (B), and each of the plurality of patterns (340) may include silicon (Si) doped with one of phosphorus (P) and arsenic (As). The layer (330) may include silicon (Si) doped with one of phosphorus (P) and arsenic (As), and each of the plurality of patterns (340) may include silicon (Si) doped with boron (B).

[0174] According to exemplary embodiments, the layer (330) may include gallium arsenide (GaAs) doped with zinc (Zn), and each of the plurality of patterns (340) may include gallium arsenide (GaAs) doped with one of silicon (Si) and tellurium (Te). The layer (330) may include gallium arsenide (GaAs) doped with one of silicon (Si) and tellurium (Te), and each of the plurality of patterns (340) may include gallium arsenide (GaAs) doped with zinc (Zn).

[0175] According to exemplary embodiments, the layer (330) may include germanium (Ge) doped with boron (B), and each of the plurality of patterns (340) may include germanium (Ge) doped with one of phosphorus (P) and antimony (Sb). The layer (330) may include germanium (Ge) doped with one of phosphorus (P) and antimony (Sb), and each of the plurality of patterns (340) may include germanium (Ge) doped with boron (B).

[0176] According to exemplary embodiments, the layer (330) may include gallium nitride (GaN) doped with magnesium (Mg) and each of the plurality of patterns (340) may include gallium nitride (GaN) doped with silicon (Si). The layer (330) may include gallium nitride (GaN) doped with silicon (Si) and each of the plurality of patterns (340) may include gallium nitride (GaN) doped with magnesium (Mg).

[0177] According to exemplary embodiments, the layer (330) may include silicon carbide (SiC) doped with one of aluminum (Al) and boron (B), and each of the plurality of patterns (340) may include silicon carbide (SiC) doped with one of nitrogen (N) and phosphorus (P). The layer (330) may include silicon carbide (SiC) doped with one of nitrogen (N) and phosphorus (P), and each of the plurality of patterns (340) may include silicon carbide (SiC) doped with one of aluminum (Al) and boron (B). According to exemplary embodiments, the layer (330) may include indium phosphate (InP) doped with zinc (Zn), and each of the plurality of patterns (340) may include indium phosphate (InP) doped with one of sulfur (S) and silicon (Si). The layer (330) may include indium phosphate (InP) doped with one of sulfur (S) and silicon (Si), and each of the plurality of patterns (340) may include indium phosphate (InP) doped with zinc (Zn).

[0178] According to exemplary embodiments, the layer (330) may include cadmium telluride (CdTe) and each of the plurality of patterns (340) may include cadmium sulfide (CdS). The layer (330) may include cadmium sulfide (CdS) and each of the plurality of patterns (340) may include cadmium telluride (CdTe).

[0179] According to exemplary embodiments, the layer (330) may include tin oxide (SnO) and each of the plurality of patterns (340) may include zinc oxide (ZnO). The layer (330) may include zinc oxide (ZnO) and each of the plurality of patterns (340) may include tin oxide (SnO).

[0180] The plurality of energy source patterns (350) may include the same material as the energy source layer (130L) of FIG. 9. Each of the plurality of energy source patterns (350) may have a tapered shape. The plurality of patterns (340) may be interposed between the layer (330) and the plurality of energy source patterns (350).

[0181]

[0182] Next, referring to FIGS. 17, 22, and 23, an insulating layer (361) and a plurality of vias (371) may be formed in P350. The insulating layer (361) may include one of the materials exemplified with respect to the insulating layer (320). The plurality of vias (371) may extend in the Z direction. Each of the plurality of vias (371) may be in contact with the plurality of patterns (340). Each of the plurality of vias (371) may include a conductive material. Each of the plurality of vias (371) may include a metal. Each of the plurality of vias (371) may include one or more of aluminum (Al), copper (Cu), tungsten (W), and titanium (Ti). One of ordinary skill in the art will readily arrive at an embodiment in which a wiring structure including two or more layers of vias and one or more layers of patterns is embedded within the insulating layer (361) based on the description herein.

[0183] Forming the plurality of vias (371) may include depositing an insulating material to form an insulating material layer, etching the insulating material layer to form an insulating layer (361) including a plurality of via holes exposing the top surface of the plurality of patterns (340), providing a conductive material layer that fills the plurality of via holes, and separating the conductive material layer into the plurality of vias (371) through a planarization process.

[0184]

[0185] Next, referring to FIGS. 17 and 24, at P360, a layer (330), a plurality of patterns (340), and a plurality of energy source patterns (350) may be formed. Forming the layer (330), the plurality of patterns (340), and the plurality of energy source patterns (350) at P360 may include forming a layer at P320, patterning the layer P330, and forming the plurality of patterns and the plurality of energy source patterns at P340. Accordingly, an integrated battery (300) including a core layer (LC), a first battery layer (L1), and a second battery layer (L2) may be provided. The first battery layer (L1) may be on the core layer (LC). An insulating layer (361) may be interposed between the first battery layer (L1) and the second battery layer (L2).

[0186] The core layer (LC) may include a plurality of transistors (315) formed on a substrate (310). Additional passive components may be formed on the substrate (310). The core layer (LC) may include a voltage regulator configured to regulate the resulting voltage of the first battery layer (L1) and the second battery layer (L2). The core layer (LC) may include one of a linear voltage regulator, a buck regulator, a boost regulator, and a buck-boost regulator.

[0187] The layer (330), the plurality of patterns (340), and the plurality of energy source patterns (350) of the second battery layer (L2) can be provided by substantially the same method as the layer (330), the plurality of patterns (340), and the plurality of energy source patterns (350) of the first battery layer (L1). The layer (330), the plurality of patterns (340), and the plurality of energy source patterns (350) of the second battery layer (L2) can be substantially the same as the layer (330), the plurality of patterns (340), and the plurality of energy source patterns (350) of the first battery layer (L1).

[0188] Each of the first battery layer (L1) and the second battery layer (L2) may include a layer (330), a plurality of patterns (340), and a plurality of energy source patterns (350). Each of the plurality of patterns (340) of the first battery layer (L1) may be connected to a layer (330) of the second battery layer (L2) by a plurality of vias (371). Accordingly, the first battery layer (L1) may be connected in series with the second battery layer (L2).

[0189] Each of the first battery layer (L1) and the second battery layer (L2) of the integrated battery (300) may be a unit battery layer. According to exemplary embodiments, by performing a semiconductor manufacturing process on a single substrate, the unit battery layers can be connected in series, thereby increasing the voltage output from the integrated battery (300). A person skilled in the art will readily be able to achieve an integrated battery comprising three or more unit battery layers connected in series with each other based on the description herein.

[0190]

[0191] (Example 7)

[0192] FIG. 25 is a drawing showing an integrated battery (301) according to other exemplary embodiments.

[0193] Referring to FIG. 25, the integrated battery (301) may include a core layer (LC), a first battery layer (L1), and a second battery layer (L2'). The core layer (LC) and the first battery layer (L1) are substantially the same as those described with reference to FIGS. 17 to 24, and therefore, a redundant description thereof will be omitted.

[0194] The second battery layer (L2') may include a plurality of patterns (430), a layer (440), and a plurality of energy source patterns (350). In the second battery layer (L2'), the layer (440) may have substantially the same shape as the layer (330), but may have a polarity opposite to that of the layer (330). Each of the plurality of patterns (430) may have substantially the same shape as each of the plurality of patterns (340), but may have a polarity opposite to that of each of the plurality of patterns (340). Each of the plurality of patterns (430) may have a polarity opposite to that of the layer (440).

[0195] In the example of FIG. 25, each of the plurality of patterns (340) of the first battery layer (L1) can be connected to a layer (440) of the second battery layer (L2') by a plurality of vias (371). Accordingly, the first battery layer (L1) can be connected in parallel with the second battery layer (L2').

[0196] Each of the first battery layer (L1) and the second battery layer (L2') of the integrated battery (301) may be a unit battery layer. According to exemplary embodiments, by performing a semiconductor manufacturing process on a single substrate, the unit battery layers can be connected in parallel, thereby increasing the current output from the integrated battery (301). A person skilled in the art will be able to easily achieve an integrated battery including three or more unit battery layers connected in parallel with each other based on the description herein.

[0197]

[0198] (Example 8)

[0199] FIG. 26 is a plan view of an integrated battery (100a) according to other exemplary embodiments.

[0200] Fig. 27 is a cross-sectional view taken along the cutting line 26I-26I' of Fig. 26.

[0201] Referring to FIGS. 26 and 27, the integrated battery (100a) may include a substrate (110), a plurality of patterns (120), and a plurality of energy source patterns (130). The substrate (110), the plurality of patterns (120), and the plurality of energy source patterns (130) are substantially the same as those described with reference to FIGS. 1 to 12, except for the arrangement of the plurality of holes (110H), and therefore, a redundant description thereof will be omitted.

[0202] Unlike the plurality of holes (110H) arranged in a honeycomb structure in FIG. 12, the plurality of holes (110H) in FIGS. 26 and 27 may be arranged in a non-honeycomb structure. At least some of the centers of the plurality of holes (110H) may be offset from positions for forming the honeycomb structure. When each of the plurality of holes (110H) aligned along the Y direction is defined as a hole array (HAR), adjacent hole arrays (HAR) may be staggered. The plurality of holes (110H) may be arranged in a zigzag manner along the X direction.

[0203] The plurality of patterns (120) and the plurality of energy source patterns (130) together fill the plurality of holes (110H), and the description of the arrangement of the plurality of holes (110H) can also be applied to the plurality of patterns (120) and the plurality of energy source patterns (130).

[0204]

[0205] (Example 9)

[0206] FIG. 28 is a plan view of an integrated battery (100b) according to other exemplary embodiments.

[0207] Figure 29 is a cross-sectional view taken along the cutting line 28I-28I' of Figure 28.

[0208] Referring to FIGS. 28 and 29, the integrated battery (100b) may include a substrate (110), a plurality of patterns (120), and a plurality of energy source patterns (130). The substrate (110), the plurality of patterns (120), and the plurality of energy source patterns (130) are substantially the same as those described with reference to FIGS. 1 to 12, except for the arrangement of the plurality of holes (110H), and therefore, a redundant description thereof will be omitted.

[0209] Unlike the plurality of holes (110H) arranged in a honeycomb structure in FIG. 12, the plurality of holes (110H) in this example may be arranged in a matrix. The plurality of holes (110H) may be aligned in the X direction. The plurality of holes (110H) may be aligned in the Y direction.

[0210] The plurality of patterns (120) and the plurality of energy source patterns (130) together fill the plurality of holes (110H), and the description of the arrangement of the plurality of holes (110H) can also be applied to the plurality of patterns (120) and the plurality of energy source patterns (130).

[0211]

[0212] (Example 10)

[0213] FIG. 30 is a plan view of an integrated battery (100c) according to other exemplary embodiments.

[0214] Fig. 31 is a cross-sectional view taken along the cutting line 30I-30I' of Fig. 30.

[0215] Referring to FIGS. 30 and 31, the integrated battery (100c) may include a substrate (110), a plurality of patterns (120'), and a plurality of energy source patterns (130'). The substrate (110), the plurality of patterns (120'), and the plurality of energy source patterns (130') are substantially the same as those described with reference to FIGS. 1 to 12, except for changes in the shape of the plurality of holes (110H'), and therefore, a redundant description thereof will be omitted.

[0216] Unlike the plurality of holes (110H) in FIG. 12 having a circular shape, the plurality of holes (110H') in this example may have a line shape. The plurality of holes (110H') may form a line-and-space structure. Each of the plurality of holes (110H') may extend in the X direction. The plurality of holes (110H') may be spaced apart from each other in the Y direction.

[0217] Each of the plurality of patterns (120') may be on a side wall of a corresponding one of the plurality of holes (110H'). Each of the plurality of patterns (120') may extend in the X direction. Each of the plurality of patterns (120') may have a uniform thickness.

[0218] A plurality of energy source patterns (130') can fill a plurality of holes (110H'). Each of the plurality of energy source patterns (130') can extend in the X direction. Each of the plurality of energy source patterns (130') can have a line shape. Each of the plurality of energy source patterns (130') can have a tapered shape in the Z direction.

[0219]

[0220] (Example 11)

[0221] FIG. 32 is a plan view of an integrated battery (100d) according to other exemplary embodiments.

[0222] Figure 33 is a cross-sectional view taken along the cutting line 32I-32I' of Figure 32.

[0223] Referring to FIGS. 32 and 33, the integrated battery (100d) may include a substrate (110), a plurality of patterns (120"), and a plurality of energy source patterns (130"). The substrate (110), the plurality of patterns (120"), and the plurality of energy source patterns (130") are substantially the same as those described with reference to FIGS. 1 to 12, except for changes in the shape of the plurality of holes (110H"), and therefore, a redundant description thereof will be omitted.

[0224] According to exemplary embodiments, before a material layer is formed to form a plurality of patterns (120"), such as a layer (120L, see FIG. 7), an additional etching process may be formed to roughen a plurality of holes (110H"). The additional etching process may be, for example, a wet etching process.

[0225] According to exemplary embodiments, each of the plurality of holes (110H") may have a circular shape when viewed from above. According to exemplary embodiments, each of the plurality of holes (110H") may have a star shape when viewed from above.

[0226] According to exemplary embodiments, each of the patterns (120") may have a roughened ring shape when viewed from above. Each of the patterns (120") may have a hollow star shape when viewed from above.

[0227] According to exemplary embodiments, each of the plurality of energy source patterns (130") may have a circular shape when viewed from above. According to exemplary embodiments, each of the plurality of energy source patterns (130") may have a star shape when viewed from above.

[0228] According to exemplary embodiments, the interface between the substrate (110) and the plurality of patterns (120") can be roughened. According to exemplary embodiments, the interface between the plurality of patterns (120") and the plurality of energy source patterns (130") can be roughened.

[0229]

[0230] (Examples 12 and 13)

[0231] FIG. 34 is a plan view illustrating a method for manufacturing an integrated battery according to exemplary embodiments.

[0232] Figure 35 is a cross-sectional view taken along the cutting line 34I-34I' of Figure 34.

[0233] FIG. 36 is a plan view illustrating a method for manufacturing an integrated battery according to exemplary embodiments.

[0234] Figure 37 is a cross-sectional view taken along the cutting line 36I-36I' of Figure 36.

[0235] Fig. 38 is a cross-sectional view illustrating a method for manufacturing an integrated battery according to exemplary embodiments. More specifically, Fig. 38 shows a portion corresponding to Fig. 37.

[0236]

[0237] Referring to FIGS. 34 and 35, an energy source layer (130L') may be formed. Unlike FIG. 9, where the energy source layer (130L) is provided to sufficiently fill the plurality of recesses (110R), in this example, the energy source layer (130L') may partially fill the plurality of recesses (110R). The energy source layer (130L') may have a uniform thickness. The energy source layer (130L') may have a conformal shape.

[0238]

[0239] Next, referring to FIGS. 36 and 37, a first CMP process can be performed. By the first CMP process, the energy source layer (130L') can be separated into a plurality of energy source patterns (130"'). Each of the plurality of patterns (120) is substantially the same as that described with reference to FIGS. 10 and 11, and therefore, a redundant description thereof will be omitted.

[0240]

[0241] Next, referring to FIGS. 36 and 37, at P160, a second CMP process may be performed. The plurality of energy source patterns (130"') may be an end point of the second CMP process. By the second CMP process, an integrated battery (100e) including a substrate (110), a plurality of patterns (120), and a plurality of energy source patterns (130"') may be provided. According to exemplary embodiments, the plurality of energy source patterns (130"') may have a cup shape. According to exemplary embodiments, additional filling patterns may be further provided that fill a space defined by the plurality of energy source patterns (130"').

[0242]

[0243] (Examples 14 and 15)

[0244] FIG. 39 is a flowchart illustrating a method for manufacturing another integrated battery in other exemplary embodiments.

[0245] FIGS. 40 to 45 are cross-sectional views illustrating a method of manufacturing another integrated battery in other exemplary embodiments.

[0246] Referring to FIGS. 39 and 40, providing the substrate (110) at P410 is substantially the same as providing the substrate (110) at P110, patterning the substrate (110) at P420 is substantially the same as patterning the substrate (110) at P120, and forming the layer (120L) at P430 is substantially the same as forming the layer (120L) at P130. At this time, the shape and arrangement of the recesses (110R) may follow any one of FIGS. 4, 26, 28, 30, and 32.

[0247]

[0248] Next, in P440, a lower scintillation layer (140L) can be formed. The lower scintillation layer (140L) can be formed by a deposition process such as CVD. The lower scintillation layer (140L) can have a uniform thickness. The lower scintillation layer (140L) can have a conformal shape. The lower scintillation layer (140L) can be configured to emit photons in response to high-energy radiation. The lower scintillation layer (140L) can include, but is not limited to, one or more of Ba2Ca(BO3)2, BaHfO3, BaI2:Ce, BeO, BaF2, BaMgF4, Cs2LiLuCi6:Ce, K2YF5, KCaF3, and YI3:Ce. Various examples of lower scintillator layers (140L) are disclosed at https: / scintillator.lbl.gov / inorganic-scintillator-library / .

[0249]

[0250] Next, referring to FIGS. 39 and 41, in P450, an energy source layer (150L) may be formed. The energy source layer (150L) may be provided sufficiently to fill the recesses (110R). The energy source layer (150L) may be formed by any one of evaporation, sputtering, CVD, electroplating, and electroless plating. When the energy source layer (150L) is formed by electroplating or electroless plating, a seed layer may be formed between the energy source layer (150L) and the lower flash layer (140L).

[0251] The energy source layer (150L) may include radioisotopes that emit only alpha rays, or that emit radiation other than alpha rays, such as beta rays or gamma rays. The energy source layer (150L) may be neodymium-144( 144 Nd), samarium-147( 147 Sm), Terbium-158( 158 Tb), tellurium-104( 104Te), bismuth-212( 212 Bi), astatine-210( 210 At), astatine-211( 211 At), radon-222( 222 Rn), francium-223( 223 Fr), radium-224( 224 Ra), radium-226( 226 Ra), actinium-225( 225 Ac), actinium-227( 227 Ac), thorium-228( 228 Th), thorium-230( 230 Th), thorium-232( 232 Th), protactinium-231( 231 Pa), uranium-234( 234 U), uranium-235( 235 U), uranium-238( 238 U), neptunium-237( 237 Np), plutonium-238( 238 Pu), plutonium-239( 239 Pu), plutonium-240( 240 Pu), plutonium-241( 241 Pu), americium-241( 241 Am), americium-243( 243 Am), Curium-242( 242 Cm), curium-243( 243 Cm), curium-244( 244 Cm), Curium-245( 245 Cm), Berkelium-247( 247 Bk), Berkelium-249( 249 Bk), Californium-249( 249 Cf), californium-250( 250 Cf), californium-251( 251 Cf), californium-252( 252 Cf), Einsteinium-252( 252 Es), Einsteinium-253( 253 Es), fermium-257( 257 Fm), mandelevium-258( 258 Md), Nobelium-255(255 No), lawrencium-260( 260 Lr), polonium-208( 208 Po), polonium-210( 210 Po) and polonium-212( 212 It may include one or more of the following:

[0252]

[0253] Next, referring to FIGS. 39, 41, and 42, at P460, a first CMP process can be performed. The upper surface (110U) of the substrate (110) can be the end point of the first CMP process.

[0254] By the first CMP process, the layer (120L) can be separated into a plurality of patterns (120). By the first CMP process, the lower glare layer (140L) can be separated into a plurality of lower glare patterns (140). By the first CMP process, the energy source layer (150L) can be separated into a plurality of energy source patterns (150). The upper surface of each of the plurality of patterns (120), the upper surface of each of the plurality of lower glare patterns (140), and the upper surface of each of the plurality of energy source patterns (150) can be coplanar with the upper surface (110U) of the substrate (110).

[0255]

[0256] Next, referring to FIGS. 39, 42, and 43, at P470, a plurality of energy source patterns (150) can be etched. The plurality of energy source patterns (150) can be etched using an etching mask (EM). The etching mask (EM) can expose the energy source patterns (150) and cover the plurality of patterns (120) and the plurality of lower flash patterns (140).

[0257] The plurality of energy source patterns (150) can be etched by anisotropic dry etching. The plurality of energy source patterns (150) can be etched by a plasma-based process such as, but is not limited to, RIE. The plurality of energy source patterns (150) can be partially removed by an etching process of P470. Accordingly, the upper surface of each of the plurality of energy source patterns (150) can be at a lower level than the upper surface of each of the plurality of patterns (120), the upper surface of each of the plurality of lower flash patterns (140), and the upper surface (110U) of the substrate (110). The upper surface of each of the plurality of energy source patterns (150) can be between the upper surface (110U) of the substrate (110) and the lower surface (110L) of the substrate (110). After etching of the plurality of energy source patterns (150), the etch mask (EM) can be removed by any one of ashing, O2 plasma treatment, and wet stripping.

[0258]

[0259] Next, referring to FIGS. 39 and 44, an upper glare layer (160L) can be formed at P480. The upper glare layer (160L) can be formed by a deposition process such as CVD. The upper glare layer (160L) can have a uniform thickness. The upper glare layer (160L) can have a conformal shape. The upper glare layer (160L) can be configured to emit photons in response to high energy radiation. The upper glare layer (160L) can include one of the materials exemplified with respect to the lower glare layer (140L, see FIG. 41). The upper glare layer (160L) can include the same material as the lower glare layer (140L), but is not limited thereto. The upper glare layer (160L) can also include a different material from the lower glare layer (140L).

[0260]

[0261] Next, referring to FIGS. 39, 44, and 45, a plurality of upper flash patterns (160) can be formed at P490. The plurality of upper flash patterns (160) can be formed by CMP with the upper surface (110U) of the substrate (110) as the end point. The upper flash layer (160L) can be separated into a plurality of upper flash patterns (160) by CMP.

[0262] According to exemplary embodiments, the plurality of upper flash patterns (160) and the plurality of lower flash patterns (140) may be integrated. According to exemplary embodiments, each of the plurality of upper flash patterns (160) may form a continuous layer with a corresponding one of the plurality of lower flash patterns (140). According to exemplary embodiments, there may be no observable interface between the plurality of upper flash patterns (160) and the plurality of lower flash patterns (140).

[0263] According to exemplary embodiments, the plurality of upper flash patterns (160) and the plurality of lower flash patterns (140) may be distinct. According to exemplary embodiments, the plurality of upper flash patterns (160) and the plurality of lower flash patterns (140) may be distinct, separate layers. According to exemplary embodiments, there may be an observable interface between the plurality of upper flash patterns (160) and the plurality of lower flash patterns (140).

[0264]

[0265] Next, referring to FIGS. 39 and 46, a second CMP process can be performed at P500. A plurality of lower flash patterns (140) can be the end point of the second CMP process. By the second CMP process, an integrated battery (100f) including a substrate (110), a plurality of patterns (120), a plurality of lower flash patterns (140), a plurality of energy source patterns (150), and a plurality of upper flash patterns (160) can be provided.

[0266] The plurality of recesses (110R) of FIG. 45 may be a plurality of holes (110H) extending to a new lower surface (110L') of the substrate (110). Each of the plurality of holes (110H) may penetrate the substrate (110). Each of the plurality of patterns (120) may be within a corresponding one of the plurality of holes (110H). Each of the plurality of lower flash patterns (140) may be within a corresponding one of the plurality of holes (110H). Each of the plurality of energy source patterns (150) may be within a corresponding one of the plurality of holes (110H). Each of the plurality of upper flash patterns (160) may be within a corresponding one of the plurality of holes (110H).

[0267] Each of the plurality of energy source patterns (150) may be surrounded by a corresponding one of the plurality of lower flash patterns (140) and a corresponding one of the plurality of upper flash patterns (160). Accordingly, high-energy radiation emitted from the plurality of energy source patterns (150) may be converted into photons by the plurality of lower flash patterns (140) and the plurality of upper flash patterns (160), and the substrate (110) and the plurality of patterns (120) may be prevented from being damaged by the high-energy radiation.

[0268] Each of the plurality of energy source patterns (150) may have a tapered shape. Each of the plurality of energy source patterns (150) may be spaced apart from the plurality of patterns (120). Each of the plurality of lower flash patterns (140) may be between a corresponding one of the plurality of energy source patterns (150) and a corresponding one of the plurality of patterns (120). Each of the plurality of upper flash patterns (140) may be on a corresponding one of the plurality of energy source patterns (150).

[0269]

[0270] The present invention has been described in more detail through drawings and examples. However, the configurations described in the drawings or examples described in this specification are merely embodiments of the present invention and do not represent all of the technical ideas of the present invention. Therefore, it should be understood that various equivalents and modified examples may exist as of the time of this application.

Claims

1. Description; A plurality of patterns in contact with the above substrate and having an opposite polarity to the above substrate; and A plurality of energy source patterns configured to irradiate radiation to the above-described substrate and the plurality of patterns, An integrated battery, wherein each of the plurality of energy source patterns has a tapered shape.

2. In paragraph 1, The above-mentioned substrate includes a plurality of holes extending in a direction perpendicular to the upper surface of the above-mentioned substrate, and An integrated battery, wherein each of the plurality of energy source patterns is located in a corresponding one of the plurality of holes.

3. In paragraph 2, An integrated battery, wherein each of the plurality of holes has a tapered shape.

4. In paragraph 2, An integrated battery characterized in that the width of each of the plurality of energy source patterns becomes smaller as it gets farther from the upper surface.

5. In paragraph 2, An integrated battery, wherein each of the plurality of patterns has a uniform thickness.

6. In paragraph 2, An integrated battery, wherein each of the plurality of patterns is located between a corresponding one of the substrate and the plurality of energy source patterns.

7. In paragraph 2, An integrated battery characterized in that the above plurality of holes are arranged in a honeycomb structure.

8. In paragraph 2, The above plurality of holes constitute a plurality of hole arrays, and An integrated battery characterized in that the plurality of hole arrays are staggered.

9. In paragraph 2, An integrated battery characterized in that the plurality of holes are arranged in a matrix.

10. In paragraph 2, An integrated battery, wherein each of the plurality of holes has a line shape.

11. In paragraph 2, An integrated battery, wherein each of the plurality of holes has a roughened surface.

12. In paragraph 2, An integrated battery, wherein each of the plurality of holes has a star shape when viewed from above.

13. In paragraph 2, An integrated battery characterized in that the interface between the above-mentioned substrate and the plurality of patterns is roughened.

14. In paragraph 2, An integrated battery characterized in that the interface between the plurality of patterns and the plurality of energy source patterns is roughened.

15. In paragraph 1, An integrated battery, wherein each of the plurality of energy source patterns is configured to emit beta rays.

16. In paragraph 1, An integrated battery, wherein each of the plurality of energy source patterns is configured to emit alpha rays.

17. In paragraph 16, An integrated cell further comprising a plurality of sub-flash patterns configured to emit photons in response to the alpha rays.

18. In paragraph 17, An integrated battery, wherein each of the plurality of lower flash patterns is located between a corresponding one of the plurality of energy source patterns and a corresponding one of the plurality of patterns.

19. In paragraph 18, An integrated cell further comprising a plurality of upper flash patterns configured to emit photons in response to the alpha rays.

20. In paragraph 16, An integrated battery, wherein each of the plurality of upper flash patterns is on a corresponding one of the plurality of energy source patterns.

21. In paragraph 20, An integrated battery, wherein each of the plurality of energy source patterns is surrounded by a corresponding one of the plurality of upper flash patterns and a corresponding one of the plurality of lower flash patterns.

22. In paragraph 20, An integrated battery, characterized in that each of the plurality of upper flash patterns forms a continuous layer with a corresponding one of the plurality of lower flash patterns.

23. A first layer including a plurality of first holes, a plurality of first energy source patterns within the plurality of first holes, and a first battery layer including a plurality of first patterns interposed between the plurality of first energy source patterns and the first layer and having a polarity opposite to that of the first layer; A second layer including a plurality of second holes, a plurality of second energy source patterns within the plurality of second holes, and a second battery layer including a plurality of second patterns interposed between the plurality of second energy source patterns and the second layer and having a polarity opposite to that of the second layer; and An integrated battery comprising an insulating layer interposed between a first battery layer and a second battery layer.

24. In paragraph 23, Further comprising a plurality of vias penetrating the insulating layer and connecting the first battery layer and the second battery layer, An integrated battery characterized in that the plurality of vias connect the first battery layer and the second battery layer in series.

25. In paragraph 24, An integrated battery, wherein each of the plurality of vias is in contact with a corresponding one of the second layer and the plurality of first patterns.

26. In paragraph 24, An integrated battery characterized in that the plurality of vias connect the first battery layer and the second battery layer in series.

27. In paragraph 26, An integrated battery, characterized in that the first layer has the same polarity as the second layer.

28. In paragraph 24, An integrated battery characterized in that the plurality of vias connect the first battery layer and the second battery layer in parallel.

29. In paragraph 28, An integrated battery, wherein the first layer has a polarity opposite to that of the second layer.

30. In paragraph 23, An integrated battery, characterized in that each of the plurality of first energy source patterns and the plurality of second energy source patterns has a tapered shape.

31. In paragraph 23, An integrated battery, characterized in that each of the plurality of first patterns and the plurality of second patterns has a cup shape.

32. In paragraph 23, An integrated battery, characterized in that each of the plurality of first patterns and the plurality of second patterns has a uniform thickness.

33. In paragraph 23, An integrated battery, characterized in that each of the plurality of first holes and the plurality of second holes has a tapered shape.

34. In paragraph 23, further comprising a core layer containing peripheral transistors, and An integrated battery, characterized in that the first battery layer is on the core layer.

35. In paragraph 34, An integrated battery characterized in that the peripheral transistors constitute a voltage regulator that controls the output voltage of the first and second battery layers.

36. A description containing multiple holes; a plurality of energy source patterns within the plurality of holes and having a narrowed neck shape; and An integrated battery comprising a plurality of patterns interposed between the plurality of energy source patterns and the substrate and having a polarity opposite to that of the substrate.

37. In paragraph 36, An integrated battery characterized in that each of the plurality of holes has a narrowed neck shape.

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