Semiconductor device and semiconductor device fabrication method

Abstract

Embodiments of the present invention provide a semiconductor device and a fabrication method. The semiconductor device comprises: a semiconductor substrate; an electrode layer disposed on a first surface of the semiconductor substrate and forming a Schottky contact or an ohmic contact with the semiconductor substrate; an inorganic passivation layer disposed on the surface of the electrode layer facing away from the semiconductor substrate and extending to a region of the first surface of the semiconductor substrate not covered by the electrode layer, wherein N gaps are formed on the inorganic passivation layer to divide the inorganic passivation layer into a plurality of independent blocks, and each of the N gaps is located directly above the electrode layer, N being an integer greater than or equal to 1; and a protective layer disposed on the surface of the inorganic passivation layer facing away from the semiconductor substrate and extending into each of the N gaps. In the embodiments of the present invention, gaps are introduced at appropriate positions in the inorganic passivation layer, such that the inorganic passivation layer as a single large-area whole is divided into smaller-area blocks, thereby improving device performance and reliability.

Description

Semiconductor device and method for manufacturing semiconductor device TECHNICAL FIELD

[0001] The present application relates to the technical field of electronic devices, and in particular to a semiconductor device and a method for manufacturing a semiconductor device. BACKGROUND

[0002] In a semiconductor device such as a SiC power semiconductor device, an inorganic passivation layer is usually used to cover the termination region to achieve electrical isolation of the semiconductor surface from the environment. Under high voltage bias, the inorganic passivation layer not only can withstand the potential difference between the semiconductor surface and the environment, but also can block the penetration of water vapor from the environment to the semiconductor surface, thereby ensuring the voltage withstand characteristics of the device and ensuring the reliability of the device in high temperature, high voltage and high humidity environments. Generally, the larger the coverage area and thickness of the inorganic passivation layer, the better the protection effect of the inorganic passivation layer on the device surface. However, as the thickness or area of the inorganic passivation layer increases, the mechanical stress of the inorganic passivation layer also increases, and the inorganic passivation layer may therefore face the risk of delamination or cracking in subsequent process manufacturing, device packaging, and reliability testing. Once delamination or cracking occurs, water vapor may penetrate along the cracks to the semiconductor surface, thereby causing the performance and reliability of the device to decline. Therefore, how to reduce the risk of delamination or cracking of the inorganic passivation layer to improve the performance and reliability of the device is a technical problem to be solved at present. TECHNICAL SOLUTION

[0003] In view of this, the embodiments of the present application provide a semiconductor device and a method for manufacturing a semiconductor device, which can reduce the risk of delamination or cracking of the inorganic passivation layer, thereby improving the performance and reliability of the semiconductor device.

[0004] Specifically, in one aspect, the semiconductor device provided by the embodiments of the present application comprises, for example:

[0005] a semiconductor substrate;

[0006] an electrode layer disposed on a first surface of the semiconductor substrate and forming a Schottky contact or an ohmic contact with the semiconductor substrate;

[0007] an inorganic passivation layer disposed on a surface of the electrode layer facing away from the semiconductor substrate and extending to a region of the first surface of the semiconductor substrate which is not covered by the electrode layer, wherein the inorganic passivation layer is formed with N slits to divide the inorganic passivation layer into a plurality of independent blocks, and each of the N slits is located directly above the electrode layer, N being an integer greater than or equal to 1; and

[0008] a protective layer disposed on a surface of the inorganic passivation layer facing away from the semiconductor substrate and extending into each of the N slits.

[0009] In another aspect, an embodiment of the present application provides a method for manufacturing a semiconductor device, for example, comprising:

[0010] providing a semiconductor structure, wherein the semiconductor structure comprises a semiconductor substrate and an electrode layer, the electrode layer is disposed on a first surface of the semiconductor substrate and forms a Schottky contact or an ohmic contact with the semiconductor substrate;

[0011] forming an inorganic passivation layer on the semiconductor structure, wherein the inorganic passivation layer is formed on a surface of the electrode layer facing away from the semiconductor substrate and extends to an area of the first surface of the semiconductor substrate which is not covered by the electrode layer, the inorganic passivation layer is formed with N slits to divide the inorganic passivation layer into a plurality of independent blocks, and each of the N slits is located directly above the electrode layer, N is an integer greater than or equal to 1; and

[0012] forming a protective layer on a surface of the inorganic passivation layer facing away from the semiconductor substrate, wherein the protective layer extends into each of the N slits. Advantages

[0013] By introducing the N slits in the appropriate position of the inorganic passivation layer, the inorganic passivation layer is divided from a large-area whole into small-area blocks, so that the mechanical stress of the inorganic passivation layer can be reduced; at the same time, the N slits introduced can release the thermal stress caused by the difference in thermal expansion coefficient of adjacent layers, so that the collapse or delamination of the inorganic passivation layer can be avoided, and the performance and reliability of the device can be improved. Furthermore, since the N slits are located directly above the electrode layer, for example, during the H3TRB (High Humidity High Temperature Reverse Bias) reliability test, the electric field formed by high voltage can be shielded inside the semiconductor by the electrode layer, and will not be distributed to the inorganic passivation layer where the slits are located, so that the penetration of water vapor to the surface of the semiconductor substrate through the electric field can be effectively avoided, thereby improving the reliability of the device. BRIEF DESCRIPTION OF DRAWINGS

[0014] The specific embodiments of the present application will be described in detail below with reference to the accompanying drawings.

[0015] FIG. 1 is a schematic diagram of a partial structure of a semiconductor device provided by an embodiment of the present application.

[0016] FIG. 2 is a schematic diagram of the etching stop layer, the front metal layer, the first slit, the second slit and the inorganic passivation layer in a semiconductor device provided by an embodiment of the present application.

[0017] Fig. 3A to Fig. 3E are schematic diagrams of a plurality of process structures of a method for manufacturing a semiconductor device according to Embodiment 2 of the present application.

[0018] Fig. 4 is a schematic diagram of a partial structure of a semiconductor device according to Embodiment 3 of the present application.

[0019] Fig. 5A to Fig. 5D are schematic diagrams of a plurality of process structures of a method for manufacturing a semiconductor device according to Embodiment 4 of the present application.

[0020] Fig. 6 is a schematic diagram of a partial structure of a semiconductor device according to Embodiment 5 of the present application.

[0021] Fig. 7 is a schematic diagram of a partial structure of a semiconductor device according to Embodiment 6 of the present application.

[0022] Fig. 8 is a schematic diagram of a partial structure of a semiconductor device according to Embodiment 7 of the present application.

[0023] Fig. 9A to Fig. 9E are schematic diagrams of a plurality of process structures of a method for manufacturing a semiconductor device according to Embodiment 8 of the present application.

[0024]

BRIEF DESCRIPTION OF DRAWINGS

[0025] 10, semiconductor device; 11, semiconductor substrate; 11S, first surface of semiconductor substrate; 111, epitaxial layer; 112, implanted region; 13, electrode layer; 131, contact metal layer; 131e, side surface of contact metal layer; 133, etching stop layer; 133e, side surface of etching stop layer; 135, front metal layer; 1350, front metal material layer; 135e, side surface of front metal layer; 135T, top surface of front metal layer; 135B, bottom surface of front metal layer; 14, laminated oxide layer; 15, inorganic passivation layer; 151e, inner side surface of inorganic passivation layer; 153e, outer side surface of inorganic passivation layer; 150, inorganic passivation material layer; 17, protective layer; Gap 1, first gap; Gap 2, second gap; w, width; dl, d2, d3, d4, distance; CH, opening; direction from covered region to uncovered region, R. EMBODIMENTS OF THE INVENTION

[0026] In order to make the above objectives, features and advantages of the present application more clear and comprehensible, specific embodiments of the present application will be described in detail below with reference to the accompanying drawings.

[0027] In order to enable a person skilled in the art to better understand the technical solutions of the present application, the technical solutions in the embodiments of the present application will be described clearly and completely below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by a person skilled in the art without creative labor should fall within the protection scope of the present application.

[0028] It should be noted that the terms "first", "second", and the like in the specification and claims of the present application and the above-described drawings are used to distinguish similar objects, and do not necessarily have to be used to describe a specific order or sequence. It should be understood that the terms used in this way can be interchanged under appropriate circumstances, so that the embodiments of the application described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "include" and "have" and any variations thereof are intended to cover non-exclusive inclusion, for example, a process, method, system, product or device including a series of steps or units does not have to be limited to those steps or units clearly listed, but can include other steps or units not clearly listed or inherent to these processes, methods, products or devices.

[0029] It should also be noted that the division of the plurality of embodiments in the present application is only for the convenience of description, and should not constitute a special limitation. The features in the various embodiments can be combined with each other and mutually quoted without contradiction.

[0030] In the related art, the inorganic passivation layer is often arranged on the surface of the electrode layer away from the semiconductor substrate and extends to the area on the surface of the semiconductor substrate not covered by the electrode layer, forming a large-area whole. Due to the large area, the mechanical stress of this inorganic passivation layer topology structure is also large, making the inorganic passivation layer prone to delamination or cracking. Therefore, the inorganic passivation layer topology structure provided in the following embodiments of the present application divides the inorganic passivation layer from a large-area whole into multiple small-area blocks by introducing a gap at an appropriate position, thereby reducing the mechanical stress of the inorganic passivation layer and reducing the risk of delamination or cracking of the inorganic passivation layer. At the same time, the introduced gap can release the thermal stress caused by the difference in thermal expansion coefficient of adjacent layers, avoiding the cracking of the inorganic passivation layer, thereby providing the performance and reliability of the device.

[0031] Specifically, the embodiment of the present application provides a semiconductor device, comprising: a semiconductor substrate; an electrode layer arranged on a first surface of the semiconductor substrate and forming a Schottky contact or an ohmic contact with the semiconductor substrate; an inorganic passivation layer arranged on a surface of the electrode layer facing away from the semiconductor substrate and extending to an area of the first surface of the semiconductor substrate which is not covered by the electrode layer, wherein the inorganic passivation layer is formed with N slits to divide the inorganic passivation layer into multiple independent blocks, and each of the N slits is located directly above the electrode layer, N being an integer greater than or equal to 1; and a protective layer arranged on a surface of the inorganic passivation layer facing away from the semiconductor substrate and extending into each of the N slits.

[0032] In some embodiments, a width of a single slit of the N slits is 1-3 microns in a direction from an area of the first surface covered by the electrode layer to an area of the first surface not covered by the electrode layer; and / or a distance between two adjacent slits of the N slits is 5-50 microns in the direction from the area of the first surface covered by the electrode layer to the area of the first surface not covered by the electrode layer.

[0033] In some embodiments, the electrode layer comprises a contact metal layer arranged on the first surface of the semiconductor substrate and forming the Schottky contact or the ohmic contact with the semiconductor substrate, and a front metal layer arranged on a top surface of the contact metal layer facing away from the semiconductor substrate; the inorganic passivation layer is arranged on a top surface of the front metal layer facing away from the contact metal layer and extends to an area of the first surface not covered by the contact metal layer, the N slits comprise a first slit, and the first slit is located directly above the front metal layer to expose part of the top surface of the front metal layer.

[0034] In some embodiments, the front metal layer has a bottom surface facing the contact metal layer and a side surface connecting the top surface of the front metal layer and the bottom surface of the front metal layer; and the first slit is arranged close to a first boundary line, the first boundary line being a boundary line between the side surface of the front metal layer and the top surface of the front metal layer, and / or the contact metal layer has a bottom surface facing the semiconductor substrate and a side surface connecting the bottom surface of the contact metal layer and the top surface of the contact metal layer, and the side surface of the contact metal layer is aligned with or flush with a second boundary line, the second boundary line being a boundary line between the side surface of the front metal layer and the bottom surface of the front metal layer.

[0035] In some embodiments, the first gap is one, and a distance between the first gap and the first boundary line in a direction from the area of the first surface covered by the contact metal layer to the area of the first surface uncovered by the contact metal layer is 100 nanometers to 10 micrometers; or the first gap is multiple, and the multiple first gaps are distributed in intervals in the direction from the area of the first surface covered by the contact metal layer to the area of the first surface uncovered by the contact metal layer, wherein a distance between the first gap closest to the side surface of the front metal layer and the first boundary line is 100 nanometers to 10 micrometers.

[0036] In some embodiments, the electrode layer further comprises an etching stop layer between the contact metal layer and the front metal layer; the front metal layer has a bottom surface facing the contact metal layer and a side surface connecting a top surface of the front metal layer and the bottom surface of the front metal layer; the etching stop layer has a bottom surface facing the contact metal layer, a top surface away from the contact metal layer, and a side surface connecting the bottom surface of the etching stop layer and the top surface of the etching stop layer; in a direction from the area of the first surface covered by the contact metal layer to the area of the first surface uncovered by the contact metal layer, the side surface of the etching stop layer is closer to the area of the first surface uncovered by the contact metal layer than the side surface of the front metal layer; the inorganic passivation layer is disposed on the top surface of the front metal layer and extends in sequence to the side surface of the front metal layer, the area of the top surface of the etching stop layer uncovered by the front metal layer, and the area of the first surface uncovered by the contact metal layer; the N gaps further comprise a second gap, and the second gap is located directly above the area of the etching stop layer uncovered by the front metal layer to expose part of the top surface of the etching stop layer.

[0037] In some embodiments, the electrode layer includes a contact metal layer, an etch stop layer, and a front metal layer, the contact metal layer is disposed on the first surface of the semiconductor substrate and forms the Schottky contact or the ohmic contact with the semiconductor substrate, the etch stop layer is disposed on a top surface of the contact metal layer facing away from the semiconductor substrate, and the front metal layer is disposed on a top surface of the etch stop layer facing away from the contact metal layer; the front metal layer has a top surface facing away from the contact metal layer, a bottom surface facing the contact metal layer, and a side surface connecting the top surface and the bottom surface of the front metal layer; the etch stop layer has a bottom surface facing the contact metal layer, and a side surface connecting the bottom surface and a top surface of the etch stop layer; in a direction from a region of the first surface covered by the contact metal layer to a region of the first surface not covered by the contact metal layer, the side surface of the etch stop layer is closer to the region of the first surface not covered by the contact metal layer than the side surface of the front metal layer; the inorganic passivation layer is disposed on the top surface of the front metal layer and extends to the side surface of the front metal layer, a region of the top surface of the etch stop layer not covered by the front metal layer, and the region of the first surface not covered by the contact metal layer in sequence; the N number of slits includes a second slit, and the second slit is located directly above the region of the etch stop layer not covered by the front metal layer to expose a portion of the top surface of the etch stop layer.

[0038] In some embodiments, in a direction from a region of the first surface covered by the contact metal layer to a region of the first surface not covered by the contact metal layer, a distance between the second slit and the side surface of the etch stop layer is 3 microns to 7 microns.

[0039] In some embodiments, the second slit is disposed close to a second boundary line, the second boundary line being a boundary line between the side surface of the front metal layer and the bottom surface of the front metal layer; in a direction from a region of the first surface covered by the contact metal layer to a region of the first surface not covered by the contact metal layer, a distance between the second slit and the second boundary line is 100 nanometers to 10 microns.

[0040] In some embodiments, the region of the etch stop layer not covered by the front metal layer is formed with an opening, the opening extending from the etch stop layer to the contact metal layer, and the inorganic passivation layer extends into the opening; in a direction from a region of the first surface covered by the contact metal layer to a region of the first surface not covered by the contact metal layer, the second slit is spaced apart from the opening.

[0041] In some embodiments, the side surface of the contact metal layer is aligned with or flush to the side surface of the etch stop layer, the opening extends from a top surface of the etch stop layer to a bottom surface of the contact metal layer facing away from the etch stop layer to expose a portion of the first surface.

[0042] In some embodiments, further comprising a layer stack oxide layer disposed on the first surface of the semiconductor substrate and between the inorganic passivation layer and the first surface of the semiconductor substrate; wherein the contact metal layer and the etch stop layer both extend to between the inorganic passivation layer and the layer stack oxide layer to partially overlap with the layer stack oxide layer to form a field plate structure.

[0043] In addition, the embodiments of the present application further provide a method for manufacturing a semiconductor device, comprising: providing a semiconductor structure, wherein the semiconductor structure comprises a semiconductor substrate and an electrode layer, the electrode layer is disposed on a first surface of the semiconductor substrate and forms a Schottky contact or an ohmic contact with the semiconductor substrate; forming an inorganic passivation layer on the semiconductor structure, wherein the inorganic passivation layer is formed on a surface of the electrode layer facing away from the semiconductor substrate and extends to an area of the first surface of the semiconductor substrate which is not covered by the electrode layer, the inorganic passivation layer is formed with N slits to divide the inorganic passivation layer into multiple independent blocks, and each of the N slits is located directly above the electrode layer, N is an integer greater than or equal to 1; and forming a protective layer on a surface of the inorganic passivation layer facing away from the semiconductor substrate, wherein the protective layer extends into each of the N slits.

[0044] In order to make the various embodiments of the present application clearer, the following will describe multiple specific embodiments in detail with reference to the accompanying drawings.

[0045]

Embodiment 1

[0046] Referring to FIG. 1, a semiconductor device 10 provided by the embodiments of the present application, for example, comprises a semiconductor substrate 11, an electrode layer 13, an inorganic passivation layer 15 and a protective layer 17.

[0047] The semiconductor substrate 11 includes, for example, an epitaxial layer 111 of a first conductivity type and one or more implant regions 112 of a second conductivity type formed within the epitaxial layer 111, each implant region 112 extending from a top surface of the epitaxial layer 111 toward an interior of the epitaxial layer 111, and when there are a plurality of implant regions 112, the plurality of implant regions 112 can be spaced apart within the epitaxial layer 111. The aforementioned epitaxial layer 111 can also be referred to as a drift layer. The first conductivity type can be n-type and the second conductivity type can be p-type; or, the second conductivity type can be n-type and the first conductivity type can be p-type. For example, the epitaxial layer 111 of the first conductivity type is, for example, a SiC drift layer, and the implant regions 112 of the second conductivity type are, for example, regions formed by ion implantation; of course, these implant regions 112 of the second conductivity type can be partially regions and partially regions. In addition, it is worth mentioning that the semiconductor substrate 11 can also typically have a semiconductor substrate such as a SiC substrate located at a bottom surface of the SiC drift layer. As for the respective doping concentrations and thicknesses of the semiconductor substrate and the epitaxial layer 111 of the first conductivity type, and the design of the longitudinal depth, ion implantation concentration, lateral width, and lateral spacing of the implant regions 112 of the second conductivity type, reference can be made to existing mature technologies, and thus will not be described here.

[0048] The electrode layer 13 is disposed on a first surface 11S of the semiconductor substrate 11 (for example, a top surface of the epitaxial layer 111 of the first conductivity type) and forms a Schottky contact or an ohmic contact with the semiconductor substrate 11, for example, a Schottky contact or an ohmic contact with the epitaxial layer 111 of the first conductivity type.

[0049] The inorganic passivation layer 15 is disposed on a surface of the electrode layer 13 facing away from the semiconductor substrate 11 and extends to an area of the first surface 11S of the semiconductor substrate 11 that is not covered by the electrode layer 13 (for example, the

uncovered area

[0050] A protective layer 17 is disposed on the surface of the inorganic passivation layer 15 facing away from the semiconductor substrate 11 and extends into each of the N gaps, for example into the first gap Gap1 and the second gap Gap2.

[0051] As can be seen from the above, the present embodiment forms N gaps, such as the first gap Gap1 and the second gap Gap2, in the inorganic passivation layer 15 directly above the electrode layer 13, thereby dividing the inorganic passivation layer 15 into multiple independent blocks, forming multiple (for example, four) smaller area regions, so as to reduce the mechanical stress of the inorganic passivation layer 15, thereby reducing the risk of delamination or cracking of the inorganic passivation layer 15. At the same time, the N gaps, such as the first gap Gap1 and the second gap Gap2, used to divide the inorganic passivation layer 15 can release a part of the thermal stress from the adjacent layers, thereby also avoiding the cracking of the inorganic passivation layer caused by the thermal stress of the adjacent layers. Furthermore, since the N gaps, such as the first gap Gap1 and the second gap Gap2, are located directly above the electrode layer 13, for example, during the H3TRB reliability test, the electric field formed by the high voltage will be shielded inside the semiconductor by the electrode layer 13, and will not be distributed to the inorganic passivation layer 15 where the N gaps are located. In this way, the penetration of water vapor into the first surface 11S of the semiconductor substrate 11 through the electric field can be effectively avoided, thereby improving the reliability of the device.

[0052] In some embodiments, referring to FIG. 1, in the direction R from the region of the first surface 11S of the semiconductor substrate 11 covered by the electrode layer 13 (corresponding to the

covered region

uncovered region

[0053] In some embodiments, referring to FIG. 1, in the direction R from the region of the first surface 11S of the semiconductor substrate 11 covered by the electrode layer 13 (corresponding to the

covered region

uncovered region

[0054] In some embodiments, referring to FIG. 1, the electrode layer 13 includes, for example, a contact metal layer 131 and a front metal layer 135, the contact metal layer 131 is disposed on the first surface 11S of the semiconductor substrate 11 and forms a Schottky contact or an ohmic contact with the semiconductor substrate 11; the contact metal layer 131 has a bottom surface facing the semiconductor substrate 11, a top surface facing away from the semiconductor substrate 11, and a side surface 131e connecting the bottom surface of the contact metal layer 131 and the top surface of the contact metal layer 131, the front metal layer 135 is disposed on the top surface of the contact metal layer 131 facing away from the semiconductor substrate 11; the inorganic passivation layer 14 is disposed on the top surface 135T of the front metal layer 135 facing away from the contact metal layer 131 and extends to the region of the first surface 11S not covered by the contact metal layer 131, and the first gap Gap1 in the N gaps is located directly above the front metal layer 135 to expose part of the top surface 135T of the front metal layer 135.

[0055] More specifically, in some embodiments, the electrode layer 13 further includes an etching stop layer 133 located between the contact metal layer 131 and the front metal layer 135; in other words, the etching stop layer 133 is disposed on the top surface of the contact metal layer 131 facing away from the semiconductor substrate 11, and the front metal layer 135 is disposed on the top surface of the etching stop layer 133 facing away from the contact metal layer 131. The front metal layer 135 has a bottom surface 135B facing the contact metal layer and a side surface 135e connecting the top surface 135T of the front metal layer 135 and the bottom surface 135B of the front metal layer 135; the etching stop layer 133 has a bottom surface facing the contact metal layer 131 and a side surface 133e connecting the bottom surface of the etching stop layer 133 and the top surface of the etching stop layer 133; in the direction R from the region of the first surface 11S of the semiconductor substrate 11 covered by the contact metal layer 131 (corresponding to the

covered region

uncovered region

uncovered region

[0056] In some embodiments, referring to FIG. 1, the side surface 131e of the contact metal layer 131 is, for example, aligned with or flush to the second interface line, which is the interface line between the side surface 135e of the front metal layer 135 and the bottom surface 135B of the front metal layer 135.

[0057] In some embodiments, referring to FIG. 1, the side surface 131e of the contact metal layer 131 is, for example, aligned with or flush to the second interface line, which is the interface line between the side surface 135e of the front metal layer 135 and the bottom surface 135B of the front metal layer 135.

[0058] In some embodiments, referring to FIG. 1, the side surface 131e of the contact metal layer 131, the side surface 133e of the etching stop layer 133, and the second interface line (i.e., the interface line between the side surface 135e of the front metal layer 135 and the bottom surface 135B of the front metal layer 135) are all aligned or flush. Further, for example, the contact metal layer 131 can be a NiSi layer, the etching stop layer 133 can be a Ti layer or a TiAl layer, and the front metal layer 135 can be an aluminum (Al) layer, but embodiments of the present application are not limited thereto.

[0059] In some embodiments, referring to FIG. 1, the number of the first gaps Gap1 is multiple (e.g., two), and the multiple first gaps Gap1 are distributed in the direction R from the area of the first surface 11S of the semiconductor substrate 11 covered by the contact metal layer 131 (corresponding to the “covered area” shown in FIG. 1) to the area of the first surface 11S of the semiconductor substrate 11 not covered by the contact metal layer 131 (corresponding to the “uncovered area” shown in FIG. 1), wherein the distance between the first gap Gap1 closest to the side surface 135e of the front metal layer 135 and the first interface line (i.e., the interface line between the side surface 135e of the front metal layer 135 and the top surface 135T of the front metal layer 135) is d2; the minimum value of d2 depends on the process limit, and the maximum value is limited by the size of the passivation layer covering the slope, the greater the distance d2, the larger the size of the slope passivation layer, and the higher the possibility of cracking, therefore embodiments of the present application design d2 to be 100 nanometers to 10 micrometers.

[0060] In some embodiments, the second gap Gap2 should be kept a sufficient distance from the side surface 133e of the etching stop layer 133 to ensure that the second gap Gap2 has no electric field distribution. Specifically, referring to FIG. 1, in the direction R from the area of the first surface 11S of the semiconductor substrate 11 covered by the contact metal layer 131 (corresponding to the

covered area

uncovered area

[0061] In some embodiments, the second gap Gap2 is arranged close to the second boundary line (i.e., the boundary line between the side surface 135e of the front metal layer 135 and the bottom surface 135B of the front metal layer 135). For example, referring to FIG. 1, in the direction R from the area of the first surface 11S of the semiconductor substrate 11 covered by the contact metal layer 131 (corresponding to the

covered area

uncovered area

[0062] In some embodiments, referring to FIG. 2, the inorganic passivation layer 15 is in a ring structure, and the first gap Gap1 and the second gap Gap2 are located between the inner side surface 151e and the outer side surface 153e of the inorganic passivation layer 15. In addition, in the embodiment shown in FIG. 2, the number of the first gap Gap1 is two and the first gap Gap1 is in a closed ring shape and is located directly above the front metal layer 135 to expose the part of the top surface of the front metal layer 135 facing away from the etching stop layer 133; the number of the second gap Gap2 is one and the second gap Gap2 is in a closed ring shape and is located directly above the area of the etching stop layer 133 not covered by the front metal layer 135. Here, it should be noted that the shapes of the first gap Gap1 and the second gap Gap2 can be flexibly designed as long as the inorganic passivation layer 15 can be divided into two or more independent blocks.

[0063]

Embodiment 2

[0064] Referring to FIGS. 3A-3E, a method for manufacturing a semiconductor device provided by an embodiment of the present application can be used to manufacture the semiconductor device 10 shown in FIG. 1, for example, and includes the following steps.

[0065] First, a semiconductor structure is provided, which can be seen from FIG. 3A, FIG. 3B and FIG. 3C, and is specifically as follows:

[0066] A contact metal layer 131 and an etching stop layer 133 located on the contact metal layer 131 and away from the first surface 11S of the semiconductor substrate 11 are formed on the first surface 11S of the semiconductor substrate 11 (for example, on the top surface of the epitaxial layer 111 of the first conductivity type) by using the same photolithography and etching steps, wherein the contact metal layer 131 forms a Schottky contact or an ohmic contact with the semiconductor substrate 11 in subsequent annealing, and a structure as shown in FIG. 3A is obtained;

[0067] Next, a front metal material layer 1350 is formed on the top surface of the etching stop layer 133 away from the contact metal layer 131 and on the region of the first surface 11S of the semiconductor substrate 11 which is not covered by the contact metal layer 131, and a structure as shown in FIG. 3B is obtained;

[0068] Then, based on the front metal material layer 1350, a front metal layer 135 is made on the top surface of the etching stop layer 133 away from the contact metal layer 131; in the direction R (see FIG. 1) from the region of the first surface 11S of the semiconductor substrate 11 covered by the contact metal layer 131 to the region of the first surface 11S of the semiconductor substrate 11 not covered by the contact metal layer 131, the side surface 133e of the etching stop layer 133 is closer to the region of the first surface 11S of the semiconductor substrate 11 not covered by the contact metal layer 131 than the side surface 135e of the front metal layer 135, and a structure as shown in FIG. 3C is obtained; here, the contact metal layer 131, the etching stop layer 133 and the front metal layer 135 together constitute the electrode layer of the semiconductor structure. It is worth mentioning that the front metal layer 135 is formed by wet etching or dry etching the front metal material layer 1350, and in this process, the etching stop layer 133 plays a role of etching barrier to protect the underlying contact metal layer 131 from etching.

[0069] Then, an inorganic passivation layer 15 is formed on the semiconductor structure, which can be seen from FIG. 3D and FIG. 3E, and is specifically as follows:

[0070] As shown in Fig. 3D, an inorganic passivation material layer 150 is deposited on the top surface of the front metal layer 135 facing away from the contact metal layer 131, on the side surface of the front metal layer 135, on the region of the top surface of the etching stop layer 133 not covered by the front metal layer 135, and on the region of the first surface 11S (see Fig. 3A) of the semiconductor substrate 11 not covered by the etching stop layer 133; then the inorganic passivation material layer 150 is patterned by dry etching to form an inorganic passivation layer 15 having N (N is an integer greater than or equal to 1) slits as shown in Fig. 3E, wherein the N slits include a first slit Gap 1 and a second slit Gap 2, the first slit Gap 1 is located directly above the front metal layer 135 to expose the portion of the top surface of the front metal layer 135 facing away from the contact metal layer 131, and the second slit Gap 2 is located directly above the region of the etching stop layer 133 not covered by the front metal layer 135 to expose the portion of the top surface of the etching stop layer 133 facing away from the contact metal layer 131. It is worth mentioning here that the first slit Gap 1 and the second slit Gap 2 are formed simultaneously in the step of dry etching the inorganic passivation material layer 150, and the etching stop layer 133 again plays a role of etching barrier to protect the underlying contact metal layer 131.

[0071] After that, a protection layer 17 is formed on the surface of the inorganic passivation layer 15 facing away from the semiconductor substrate 11, wherein the protection layer 17 covers the inorganic passivation layer 15 and extends into the N slits such as the first slit Gap 1 and the second slit Gap 2; thus the semiconductor device 10 as shown in Fig. 1 can be made. It is worth mentioning here that the material of the organic layer 17 can be imide, which can also be referred to as organic protection layer, which is formed on the device surface by spin coating and patterned by photolithography, for example.

[0072]

Embodiment 3

[0073] Referring to Fig. 4, a semiconductor device provided by an embodiment of the present application, for example, includes a semiconductor substrate 11, an electrode layer 13, an inorganic passivation layer 15, and a protection layer 17.

[0074] The semiconductor substrate 11 includes, for example, an epitaxial layer 111 of a first conductivity type and one or more implant regions 112 of a second conductivity type formed within the epitaxial layer 111 of the first conductivity type, each implant region 112 extending from a top surface of the epitaxial layer 111 toward an interior of the epitaxial layer 111, and when there are multiple implant regions 112, the multiple implant regions 112 can be spaced apart within the epitaxial layer 111. The aforementioned epitaxial layer 111 can also be referred to as a drift layer. The first conductivity type can be n-type and the second conductivity type can be p-type; or, the second conductivity type can be n-type and the first conductivity type can be p-type. For example, the epitaxial layer 111 of the first conductivity type is, for example, a SiC drift layer, and the implant regions 112 of the second conductivity type are, for example, regions formed by ion implantation; of course, the implant regions 112 of the second conductivity type can be partially regions and partially regions. In addition, it is worth mentioning that the semiconductor substrate 11 can also typically have a semiconductor substrate such as a SiC substrate located at a lower surface of the SiC drift layer. As for the respective doping concentrations and thicknesses of the semiconductor substrate and the epitaxial layer 111 of the first conductivity type, and the design of the longitudinal depth, ion implantation concentration, lateral width, and lateral spacing of the implant regions 112 of the second conductivity type, reference can be made to existing mature technologies, and thus will not be described here.

[0075] The electrode layer 13 is disposed on a first surface 11S of the semiconductor substrate 11 (e.g., a top surface of the epitaxial layer 111 of the first conductivity type) and includes a contact metal layer 131 and a front metal layer 135. Specifically, the contact metal layer 131 is disposed on the first surface 11S of the semiconductor substrate 11 and forms a Schottky contact or an ohmic contact with the semiconductor substrate 11, for example, a Schottky contact or an ohmic contact with the epitaxial layer 111 of the first conductivity type. The front metal layer 135 is disposed on a top surface 135T of the contact metal layer 131 facing away from the semiconductor substrate 11.

[0076] The inorganic passivation layer 15 is disposed on the top surface 135T of the front metal layer 135 facing away from the contact metal layer and extends to an area of the first surface 11S of the semiconductor substrate 11 that is not covered by the contact metal layer 131 (corresponding to the

uncovered area

[0077] Further, the first gap Gap1 is arranged close to the first boundary line (i.e. the boundary line between the side surface 135e of the front metal layer 135 and the top surface 135T of the front metal layer 135); as shown in FIG. 4, the number of the first gap Gap1 is, for example, one, and the distance between the first gap Gap1 and the first boundary line in the direction R from the area of the first surface 11S of the semiconductor substrate 11 covered by the contact metal layer 131 (corresponding to the

covered area

uncovered area

[0078] The protective layer 17 is arranged on the surface of the inorganic passivation layer 15 away from the semiconductor substrate 11 and extends into the first gap Gap1. In addition, for example, the material of the protective layer 17 can be an organic material such as imide.

[0079] Compared with the semiconductor device 10 shown in FIG. 1, the semiconductor device of the present embodiment is not provided with the second gap Gap2, and accordingly, the dry etching patterning step of the inorganic passivation layer 15 does not etch to form the second gap Gap2, so that the dry etching does not erode the first surface 11S of the semiconductor substrate 11 below the position corresponding to the second gap Gap2, and therefore, the etching stop layer 133 can be omitted in the present embodiment.

[0080]

Embodiment 4

[0081] Referring to FIGS. 5A to 5D, a method for manufacturing a semiconductor device provided by the present embodiment can manufacture the semiconductor device shown in FIG. 4, for example, and includes the following steps.

[0082] First, a semiconductor structure is provided, which can be seen from FIGS. 5A and 5B, and is specifically as follows:

[0083] The contact metal layer 131 is formed on the first surface 11S of the semiconductor substrate 11 (e.g. the top surface of the first conductive type epitaxial layer 111) by dry etching, wherein the contact metal layer 131 forms a Schottky contact or an ohmic contact with the semiconductor substrate 11 in the subsequent annealing, to obtain the structure shown in FIG. 5A;

[0084] Next, a front metal layer 135 is formed on the top surface of the contact metal layer 131 facing away from the semiconductor substrate 11; wherein the front metal layer 135 and the contact metal layer 131 are stacked together as the electrode layer 13 of the semiconductor structure, obtaining a structure as shown in FIG. 5B. It is worth mentioning that the front metal layer 135 is formed, for example, by wet etching or dry etching.

[0085] Then, an inorganic passivation layer 15 is formed on the semiconductor structure, which can be seen from FIG. 5C and FIG. 5D, and is specifically as follows:

[0086] The inorganic passivation material layer 150 is deposited on the top surface of the front metal layer 135 facing away from the contact metal layer 131, on the side surface of the front metal layer 135, and on the region of the first surface 11S of the semiconductor substrate 11 which is not covered by the contact metal layer 131, and then the inorganic passivation material layer 150 is patterned by dry etching to form the inorganic passivation layer 15 with the first gap Gap1, obtaining a structure as shown in FIG. 5D. In addition, it can also be known from FIG. 5D that the first gap Gap1 is located directly above the front metal layer 135 to expose the portion of the top surface of the front metal layer 135 facing away from the contact metal layer 131, and the first gap Gap1 is located between the inner side surface 151e and the outer side surface 153e of the inorganic passivation layer 15.

[0087] After that, a protection layer 17 is formed on the surface of the inorganic passivation layer 15 facing away from the semiconductor substrate 11, wherein the protection layer 17 covers the inorganic passivation layer 15 and extends into the first gap Gap1; at this time, the semiconductor device as shown in FIG. 4 can be obtained. It is worth mentioning that the material of the organic layer 17 here can be imide, which can also be called organic protection layer, which is formed on the surface of the device by spin coating and patterned by photolithography, for example.

[0088]

Embodiment 5

[0089] Referring to FIG. 6, a semiconductor device provided by the embodiment of the present application has substantially the same structure as the semiconductor device 10 shown in FIG. 1, and the difference is that: in the embodiment, only the second gap Gap2 is formed in the inorganic passivation layer 15 directly above the region of the etching stop layer 133 which is not covered by the front metal layer 135, and the first gap Gap1 is not formed in the inorganic passivation layer 15. Correspondingly, the inorganic passivation layer 15 is divided into two independent blocks by the second gap Gap2.

[0090] In addition, as shown in FIG. 6, the second gap Gap2 is disposed close to the second interface (i.e., the interface between the side surface 135e of the front metal layer 135 and the bottom surface 135B of the front metal layer 135), and the distance between the second gap Gap2 and the second interface in the direction R from the area of the first surface 11S of the semiconductor substrate 11 covered by the contact metal layer 131 (corresponding to the

covered area

uncovered area

[0091] Embodiment 6

[0092] Referring to FIG. 7, a semiconductor device provided by an embodiment of the present application has substantially the same structure as the semiconductor device 10 shown in FIG. 1, except that the area of the etching stop layer 133 in the electrode layer 13 of the semiconductor device of the present embodiment which is not covered by the front metal layer 135 is formed with an opening CH extending from the etching stop layer 133 to the contact metal layer 131; the opening CH is disposed apart from the second gap Gap2 in the direction R from the area of the first surface 11S of the semiconductor substrate 11 covered by the contact metal layer 131 (corresponding to the

covered area

uncovered area

[0093] More specifically, the side surface 131e of the contact metal layer 131 is aligned with or flush with the side surface 133e of the etching stop layer 133, and the opening CH extends from the top surface of the etching stop layer 133 facing away from the contact metal layer 131 to the bottom surface of the contact metal layer 131 facing away from the etching stop layer 133 to expose the first surface 11S of the semiconductor substrate 11 (e.g., the top surface of the first-conductivity-type epitaxial layer 111).

[0094] Embodiment 7

[0095] Referring to FIG. 8, a semiconductor device according to an embodiment of the present application has substantially the same structure as the semiconductor device 10 shown in FIG. 1, except that the semiconductor device according to the embodiment further includes a field oxide layer, such as a stacked oxide layer 14, disposed on the first surface 11S of the semiconductor substrate 11 between the inorganic passivation layer 15 and the first surface 11S of the semiconductor substrate 11, wherein the contact metal layer 131 and the etch stop layer 133 both extend to partially overlap the stacked oxide layer 14 to form a field plate structure. For example, the stacked oxide layer 14 includes a thermal oxide layer and an interlayer oxide layer deposited on a surface of the thermal oxide layer away from the semiconductor substrate 11, and the thermal oxide layer and the interlayer oxide layer can be silicon oxide layers.

[0096] Embodiment 8

[0097] Referring to FIGS. 9A to 9E, a method of fabricating a semiconductor device according to an embodiment of the present application can be used to fabricate the semiconductor device shown in FIG. 8, and includes the following steps.

[0098] First, a semiconductor structure is provided, which can be seen in FIGS. 9A, 9B and 9C, and is as follows:

[0099] A thermal oxide layer is formed on the first surface 11S of the semiconductor substrate 11, such as the top surface of the first conductivity type epitaxial layer 111, by a thermal oxidation method, and an interlayer oxide layer is formed on the thermal oxide layer by chemical vapor deposition, to obtain a field oxide layer, such as the stacked oxide layer 14, on the first surface 11S of the semiconductor substrate 11, thereby obtaining the structure shown in FIG. 9A;

[0100] Next, the contact metal layer 131 and the etch stop layer 133 on the top surface of the contact metal layer 131 away from the semiconductor substrate 11 are formed on the first surface 11S of the semiconductor substrate 11 by the same photolithography and etching steps, wherein the contact metal layer 131 and the etch stop layer 133 both extend to partially overlap the stacked oxide layer 14 to form a field plate structure, and the contact metal layer 131 forms a Schottky contact or an ohmic contact with the semiconductor substrate 11 in a subsequent annealing process, thereby obtaining the structure shown in FIG. 9B;

[0101] Next, a front metal layer 135 is formed on the top surface of the etch stop layer 133 facing away from the contact metal layer 131; in the direction R (see FIG. 8) from the region of the first surface 11S of the semiconductor substrate 11 covered by the contact metal layer 131 to the region of the first surface 11S of the semiconductor substrate 11 not covered by the contact metal layer 131, the side surface 133e of the etch stop layer 133 is closer to the region of the first surface 11S of the semiconductor substrate 11 not covered by the contact metal layer 131 than the side surface 135e of the front metal layer 135, resulting in the structure shown in FIG. 9C; here, the contact metal layer 131, the etch stop layer 133 and the front metal layer 135 together constitute the electrode layer 13 of the semiconductor structure. It is worth mentioning that the front metal layer 135 is formed, for example, by wet etching or dry etching, and in this process, the etch stop layer 133 plays an etching blocking role to protect the underlying contact metal layer 131 from etching.

[0102] Then, an inorganic passivation layer 15 is formed on the semiconductor structure, as shown in FIG. 9D and FIG. 9E, as follows:

[0103] As shown in FIG. 9D, an inorganic passivation material layer 150 is deposited on the top surface of the front metal layer 135 facing away from the contact metal layer 131, on the side surface of the front metal layer 135, on the region of the top surface of the etch stop layer 133 not covered by the front metal layer 135, and on the region of the first surface 11S of the semiconductor substrate 11 not covered by the etch stop layer 133; then the inorganic passivation material layer 150 is patterned by dry etching to form an inorganic passivation layer 15 with N (N is an integer greater than or equal to 1) slits, as shown in FIG. 9E. Among them, the N slits include, for example, a first slit Gap1 and a second slit Gap2, the first slit Gap1 is located directly above the front metal layer 135 to expose the portion of the top surface of the front metal layer 135 facing away from the etch stop layer 133, and the second slit Gap2 is located directly above the region of the etch stop layer 133 not covered by the front metal layer 135 to expose the portion of the top surface of the etch stop layer 133 facing away from the contact metal layer 131. It is worth mentioning here that the first slit Gap1 and the second slit Gap2 are formed simultaneously in the step of patterning the inorganic passivation material layer 150 by dry etching, and the etch stop layer 133 again plays an etching blocking role to protect the underlying contact metal layer 131.

[0104] Afterwards, a protective layer 17 is formed on the surface of the inorganic passivation layer 15 facing away from the semiconductor substrate 11, wherein the protective layer 17 covers the inorganic passivation layer 15 and extends into the N gaps, such as the first gap Gap1 and the second gap Gap2; thus a semiconductor device as shown in FIG. 8 can be made. It is worth mentioning that the material of the organic layer 17 here can be imide, which can also be referred to as an organic protective layer, which is formed on the surface of the device by spin coating and patterned by photolithography, for example.

[0105] In addition, it is worth mentioning that the semiconductor device of the foregoing embodiments of the present application can be a diode device or a three-terminal transistor device, and the present application does not make specific limitations here.

[0106] The above is only a preferred embodiment of the present application, and does not limit the present application in any form. Although the present application has been disclosed as above with a preferred embodiment, it is not intended to limit the present application. Any person skilled in the art can make some changes or modifications to the above disclosed technical content without departing from the scope of the technical solution of the present application, and any simple modification, equivalent change and modification of the above embodiments made according to the technical essence of the present application shall still fall within the scope of the technical solution of the present application.

Claims

1. A semiconductor device, characterized by, The semiconductor substrate comprises: a semiconductor substrate; an electrode layer disposed on a first surface of the semiconductor substrate and forming a Schottky contact or an ohmic contact with the semiconductor substrate; an inorganic passivation layer disposed on a surface of the electrode layer facing away from the semiconductor substrate and extending to an area of the first surface of the semiconductor substrate which is not covered by the electrode layer, wherein the inorganic passivation layer is formed with N slits to divide the inorganic passivation layer into multiple independent blocks, and each of the N slits is located directly above the electrode layer, N being an integer greater than or equal to 1; and a protective layer disposed on a surface of the inorganic passivation layer facing away from the semiconductor substrate and extending into each of the N slits.

2. The semiconductor device according to claim 1, characterized by In a direction from an area of the first surface covered by the electrode layer to an area of the first surface not covered by the electrode layer, a width of a single slit of the N slits is 1-3 microns; and / or, In a direction from an area of the first surface covered by the electrode layer to an area of the first surface not covered by the electrode layer, a distance between two adjacent slits of the N slits is 5-50 microns.

3. The semiconductor device of claim 1, wherein The electrode layer comprises a contact metal layer disposed on the first surface of the semiconductor substrate and forming the Schottky contact or the ohmic contact with the semiconductor substrate, and a front metal layer disposed on a top surface of the contact metal layer facing away from the semiconductor substrate; The inorganic passivation layer is disposed on a top surface of the front metal layer facing away from the contact metal layer and extends to an area of the first surface not covered by the contact metal layer, the N slits comprise a first slit, and the first slit is located directly above the front metal layer to expose part of the top surface of the front metal layer.

4. The semiconductor device according to claim 3, characterized by The front metal layer has a bottom surface facing the contact metal layer and a side surface connecting the top surface of the front metal layer and the bottom surface of the front metal layer; The first slit is disposed close to a first boundary line, the first boundary line being a boundary line between the side surface of the front metal layer and the top surface of the front metal layer; and / or, the contact metal layer has a bottom surface facing the semiconductor substrate and a side surface connecting the bottom surface of the contact metal layer and the top surface of the contact metal layer, the side surface of the contact metal layer is aligned with or flush with a second boundary line, the second boundary line being a boundary line between the side surface of the front metal layer and the bottom surface of the front metal layer.

5. The semiconductor device according to claim 4, wherein The number of the first slits is one, and in a direction from an area of the first surface covered by the contact metal layer to an area of the first surface not covered by the contact metal layer, a distance between the first slit and the first boundary line is 100 nanometers-10 microns; Alternatively, the first gap is a plurality of first gaps, the plurality of first gaps are distributed in a direction from a region of the first surface covered by the contact metal layer to a region of the first surface uncovered by the contact metal layer, and a distance between the first gap closest to the side surface of the front metal layer and the first boundary line is 100 nanometers to 10 micrometers.

6. The semiconductor device of claim 3, wherein The electrode layer further comprises an etching stop layer between the contact metal layer and the front metal layer; The front metal layer has a bottom surface facing the contact metal layer and a side surface connecting a top surface of the front metal layer and the bottom surface of the front metal layer; The etching stop layer has a bottom surface facing the contact metal layer and a side surface connecting the bottom surface of the etching stop layer and a top surface of the etching stop layer; In a direction from a region of the first surface covered by the contact metal layer to a region of the first surface uncovered by the contact metal layer, the side surface of the etching stop layer is closer to the region of the first surface uncovered by the contact metal layer than the side surface of the front metal layer; The inorganic passivation layer is disposed on the top surface of the front metal layer and sequentially extends to the side surface of the front metal layer, a region of the top surface of the etching stop layer uncovered by the front metal layer, and a region of the first surface uncovered by the contact metal layer; The N gaps further comprise a second gap, and the second gap is located directly above a region of the etching stop layer uncovered by the front metal layer to expose a portion of the top surface of the etching stop layer.

7. The semiconductor device of claim 1, wherein The electrode layer comprises a contact metal layer, an etching stop layer, and a front metal layer, the contact metal layer is disposed on the first surface of the semiconductor substrate and forms the Schottky contact or the ohmic contact with the semiconductor substrate, the etching stop layer is disposed on a top surface of the contact metal layer facing away from the semiconductor substrate, and the front metal layer is disposed on a top surface of the etching stop layer facing away from the contact metal layer; The front metal layer has a top surface facing away from the contact metal layer, a bottom surface facing the contact metal layer, and a side surface connecting the top surface of the front metal layer and the bottom surface of the front metal layer; The etching stop layer has a bottom surface facing the contact metal layer and a side surface connecting the bottom surface of the etching stop layer and a top surface of the etching stop layer; In a direction from a region of the first surface covered by the contact metal layer to a region of the first surface uncovered by the contact metal layer, the side surface of the etching stop layer is closer to the region of the first surface uncovered by the contact metal layer than the side surface of the front metal layer; The inorganic passivation layer is disposed on the top surface of the front metal layer and sequentially extends to the side surface of the front metal layer, a region of the top surface of the etching stop layer uncovered by the front metal layer, and a region of the first surface uncovered by the contact metal layer; The N slits include a second slit, and the second slit is located directly above a region of the etching stop layer that is not covered by the front metal layer to expose a portion of a top surface of the etching stop layer.

8. The semiconductor device according to claim 6 or 7, characterized by In a direction from a region of the first surface covered by the contact metal layer to a region of the first surface not covered by the contact metal layer, a distance between the second slit and a side surface of the etching stop layer is 3-7 microns.

9. The semiconductor device according to claim 6 or 7, characterized by The second slit is disposed close to a second boundary line, which is a boundary line between a side surface of the front metal layer and a bottom surface of the front metal layer. In a direction from a region of the first surface covered by the contact metal layer to a region of the first surface not covered by the contact metal layer, a distance between the second slit and the second boundary line is 100 nanometers-10 microns.

10. The semiconductor device according to claim 6 or 7, characterized by The region of the etching stop layer not covered by the front metal layer is formed with an opening, the opening extending from the etching stop layer to the contact metal layer, and the inorganic passivation layer extends into the opening. In a direction from a region of the first surface covered by the contact metal layer to a region of the first surface not covered by the contact metal layer, the second slit is disposed apart from the opening.

11. The semiconductor device of claim 10, wherein, A side surface of the contact metal layer is aligned with or flush with a side surface of the etching stop layer, and the opening extends from a top surface of the etching stop layer to a bottom surface of the contact metal layer facing away from the etching stop layer to expose a portion of the first surface.

12. The semiconductor device according to claim 6 or 7, characterized by Further comprising a laminated oxide layer disposed on the first surface of the semiconductor substrate and between the inorganic passivation layer and the first surface of the semiconductor substrate; wherein the contact metal layer and the etching stop layer both extend to between the inorganic passivation layer and the laminated oxide layer to partially overlap with the laminated oxide layer to form a field plate structure.

13. A method of manufacturing a semiconductor device, characterized by Comprise: A semiconductor structure is provided, wherein the semiconductor structure comprises a semiconductor substrate and an electrode layer disposed on a first surface of the semiconductor substrate and forming a Schottky contact or an ohmic contact with the semiconductor substrate; An inorganic passivation layer is formed on the semiconductor structure, wherein the inorganic passivation layer is formed on a surface of the electrode layer facing away from the semiconductor substrate and extends to a region of the first surface of the semiconductor substrate not covered by the electrode layer, the inorganic passivation layer is formed with N slits to divide the inorganic passivation layer into multiple independent blocks, and each of the N slits is located directly above the electrode layer, N being an integer greater than or equal to 1; and A protective layer is formed on a surface of the inorganic passivation layer facing away from the semiconductor substrate, wherein the protective layer extends into each of the N slits.

Images