Semiconductor structure

Abstract

Provided in the embodiments of the present disclosure is a semiconductor structure, comprising a plurality of rows of first word lines and a plurality of first conductive lines, wherein each first conductive line is arranged corresponding to and connected to a first word line of an odd-numbered or even-numbered row; a plurality of first conductive contacts are arranged corresponding to the first conductive lines, and a plurality of second conductive contacts are arranged corresponding to and isolated from the first conductive contacts; and the second conductive contacts are connected to first contact pads. The semiconductor structure in the embodiments of the present disclosure has a simpler interconnection manner, which simplifies the process flow while increasing the signal density.

Description

Semiconductor structure

[0001] The present application claims priority to the Chinese patent application No. 202411267639.6 filed on September 10, 2024, and entitled "Semiconductor structure", the content of which is incorporated herein by reference in its entirety. TECHNICAL FIELD

[0002] Embodiments of the present disclosure relate to the field of semiconductor technology, and in particular to a semiconductor structure. BACKGROUND

[0003] Memory is used to store data in modern computing architecture, and dynamic random access memory (DRAM) has the advantages of simple structure, low cost and high speed, and is widely used in personal computers, servers and various electronic devices as main memory.

[0004] With the continuous rapid growth of data, the density of DRAM is slowing down, resulting in a growing gap between memory demand and DRAM capacity. Increasing the integration by increasing the packaging density to obtain higher storage capacity has become an important target of integrated circuit manufacturing at this stage, and memories with tight packaging are urgently needed to be developed. SUMMARY

[0005] Embodiments of the present disclosure provide a semiconductor structure with higher integration.

[0006] The problems to be solved by the technical spirits of the present disclosure are not limited to the above-mentioned problems, and other problems not mentioned will be clearly understood by those skilled in the art from the following description.

[0007] An example embodiment of the present disclosure provides a semiconductor structure, comprising: a first memory cell array, the first memory array comprising a plurality of first word lines extending along a first direction, each first word line being isolated from each other; a first interconnection region comprising a plurality of first conductive lines extending along the first direction, each first conductive line being disposed corresponding to each first word line of odd rows or even rows and connected to each other; a first conductive contact combination disposed in the first interconnection region, the first conductive contact combination comprising a plurality of first conductive contacts, each first conductive contact being disposed corresponding to each first conductive line, and each first conductive contact extending along a second direction to connect to each first conductive line; a second interconnection region disposed adjacent to the first memory cell array and the first interconnection region along the first direction, the second interconnection region being provided with a second conductive contact combination, the second conductive contact combination comprising a plurality of second conductive contacts, each second conductive contact being disposed corresponding to each first conductive contact and isolated from each other; a plurality of first contact pads being disposed in the second interconnection region, each second conductive contact extending along the second direction to connect to each first contact pad; wherein each first conductive contact has a minimum spacing D0 between each first conductive contact adjacent along the first direction, each second conductive contact has a minimum spacing D1 between each second conductive contact adjacent along the first direction, the minimum spacing D0 is less than the minimum spacing D1, each first conductive contact has a minimum length L0 along the second direction, each second conductive contact has a minimum length L1 along the second direction, and the minimum length L0 is less than the minimum length L1.

[0008] According to an example embodiment of the present disclosure, each first conductive contact in the first conductive contact combination has an average width W0 along the first direction, each second conductive contact in the second conductive contact combination has an average width W1 along the first direction, and the average width W0 of each first conductive contact is less than the average width W1 of each second conductive contact.

[0009] According to an example embodiment of the present disclosure, the first conductive contact combination comprises a first column of first conductive contact combinations and a second column of first conductive contact combinations arranged along a third direction, each first conductive contact in the first column of first conductive contact combinations connecting each first conductive line of odd rows, and each first conductive contact in the second column of first conductive contact combinations connecting each first conductive line of even rows, wherein along the first direction, each first conductive contact in the first column of first conductive contact combinations and a corresponding second conductive contact in the second conductive contact combination has a maximum spacing D2, the first conductive contact and the second conductive contact having the maximum spacing D2 form a first reference row, and each first conductive contact in the second column of first conductive contact combinations disposed adjacent to the first reference row has a maximum spacing less than the maximum spacing D2 from each second conductive contact disposed corresponding thereto.

[0010] According to an example embodiment of the present disclosure, each first conductive contact and each second conductive contact disposed adjacent to the first reference row forms a first reference row and a second reference row, respectively, the first conductive contacts and the second conductive contacts in the first reference row have a maximum spacing D3 therebetween, the first conductive contacts and the second conductive contacts in the second reference row have a maximum spacing D4 therebetween, the maximum spacing D3 is greater than the maximum spacing D4, and the maximum spacing D3 and the maximum spacing D4 are both less than the maximum spacing D2.

[0011] According to an example embodiment of the present disclosure, in the first direction, at least one first conductive contact and a corresponding second conductive contact in the second column of the first conductive contact combination and the second conductive contact combination have a maximum spacing D5 therebetween, the first conductive contact and the second conductive contact having the maximum spacing D5 form a second reference row, each first conductive contact in the first column of the first conductive contact combination disposed adjacent to the second reference row has a maximum spacing less than the maximum spacing D5 with each second conductive contact disposed adjacent thereto.

[0012] According to an example embodiment of the present disclosure, each first conductive contact and each second conductive contact disposed adjacent to the second reference row forms a third reference row and a fourth reference row, respectively, the first conductive contacts and the second conductive contacts in the third reference row have a maximum spacing D6 therebetween, the first conductive contacts and the second conductive contacts in the fourth reference row have a maximum spacing D7 therebetween, the maximum spacing D6 is greater than the maximum spacing D7, and the maximum spacing D6 and the maximum spacing D7 are both less than the maximum spacing D5.

[0013] According to an example embodiment of the present disclosure, the first memory cell array further includes a plurality of columns of first bit lines extending in a third direction, each first bit line being isolated from each other; a third interconnection region including a plurality of second conductive lines extending in the third direction, each second conductive line being disposed adjacent to each first bit line of an odd column or an even column and connected to each other; a fourth interconnection region disposed adjacent to the first cell array and the third interconnection region in the third direction, a portion of the second conductive lines being disposed in the third interconnection region, and a portion of the second conductive lines extending from the third interconnection region to the fourth interconnection region; a third conductive contact combination including a plurality of third conductive contacts, each third conductive contact including a plurality of third conductive contacts disposed in the third interconnection region and a plurality of third conductive contacts disposed in the fourth interconnection region, each third conductive contact being connected to a corresponding first conductive line; and a fourth conductive contact combination disposed in the third interconnection region, the fourth conductive contact combination including a plurality of fourth conductive contacts, each fourth conductive contact being disposed adjacent to each third conductive contact and connected to each other.

[0014] According to an example embodiment of the present disclosure, in the third direction, each third conductive contact in the third conductive contact combination has an average width W2, each fourth conductive contact in the fourth conductive contact combination has an average width W3, and the average width W2 of each third conductive contact is less than the average width W3 of each fourth conductive contact.

[0015] According to an example embodiment of the present disclosure, in the third direction Y, the spacing between each third conductive contact and its corresponding fourth conductive contact is the same.

[0016] According to an example embodiment of the present disclosure, in the third direction, each second conductive line in the third interconnection region has a length L3, there are at least two second conductive lines extending to the fourth interconnection region between adjacent second conductive lines in the third interconnection region, each second conductive line extending to the fourth interconnection region has a different length and is greater than the length L3, each second conductive line in the third interconnection region has a maximum spacing Dmax with its corresponding fourth conductive contact, and the sum of the maximum spacing Dmax and the length L3 is between the length values of the second conductive lines extending to the fourth interconnection region.

[0017] According to an example embodiment of the present disclosure, the number of rows of first word lines in the first memory cell array is less than the number of columns of first bit lines in the third interconnection region.

[0018] According to an example embodiment of the present disclosure, further comprising a plurality of third conductive lines, the plurality of third conductive lines including portions disposed in the first interconnection region and the second interconnection region and portions disposed in the third interconnection region and the fourth interconnection region, each third conductive line disposed in the first interconnection region and the second interconnection region is connected to a corresponding first conductive contact and a corresponding second conductive contact, respectively, and each third conductive line disposed in the third interconnection region and the fourth interconnection region is connected to a corresponding third conductive contact and a corresponding fourth conductive contact, respectively.

[0019] According to an example embodiment of the present disclosure, the semiconductor structure further comprises a second memory cell array, the second memory cell array comprising a plurality of rows of second word lines extending in the first direction, each second word line being isolated from each other, and each second word line being connected to a corresponding second conductive contact.

[0020] According to an example embodiment of the present disclosure, the semiconductor structure further comprises a second memory cell array, the second memory cell array comprising a plurality of rows of second bit lines extending in the third direction, each second bit line being isolated from each other, and each second bit line being connected to a corresponding fourth conductive contact.

[0021] The first conductive contacts in the semiconductor structure provided by the embodiments of the present disclosure are arranged at a relatively small pitch in the first interconnection region, and the second conductive contacts are arranged at a relatively large pitch in the second interconnection region. On the basis of ensuring good isolation between adjacent conductive contacts, a simpler interconnection mode can be arranged in the second interconnection region, for example, only a single contact pad is arranged to be connected with the second conductive contacts to realize signal transmission in the second interconnection region, thereby increasing the signal density and simplifying the process flow. BRIEF DESCRIPTION OF DRAWINGS

[0022] The accompanying drawings, which are incorporated herein and constitute part of the specification, illustrate embodiments consistent with the present disclosure and, together with the description, serve to explain the principles of the present disclosure.

[0023] FIG. 1A is a simplified schematic plan view of a semiconductor structure provided by an embodiment of the present disclosure.

[0024] FIG. 1B is a cross-sectional view of a semiconductor structure provided by an embodiment of the present disclosure.

[0025] FIG. 2 is a simplified schematic plan view of a semiconductor structure provided by an embodiment of the present disclosure.

[0026] FIG. 3 is a simplified schematic plan view of a semiconductor structure provided by an embodiment of the present disclosure.

[0027] FIG. 4A is a simplified schematic plan view of a semiconductor structure provided by an embodiment of the present disclosure.

[0028] FIG. 4B is a cross-sectional view of a semiconductor structure provided by an embodiment of the present disclosure.

[0029] FIG. 5 is a simplified schematic plan view of a semiconductor structure provided by an embodiment of the present disclosure.

[0030] FIG. 6 is a simplified schematic plan view of a semiconductor structure provided by an embodiment of the present disclosure.

[0031] FIG. 7A is a cross-sectional view of a semiconductor structure provided by an embodiment of the present disclosure.

[0032] FIG. 7B is a cross-sectional view of a semiconductor structure provided by an embodiment of the present disclosure.

[0033] The above-described drawings have shown specific embodiments of the present disclosure, and more detailed descriptions will be given hereinafter. These drawings and written descriptions are not intended to limit the scope of the concept of the present disclosure in any way, but to illustrate the concept of the present disclosure to those skilled in the art by referring to specific embodiments. DETAILED DESCRIPTION

[0034] The technical solutions in the embodiments of the present disclosure will be described clearly and completely in the embodiments of the present disclosure in combination with the accompanying drawings. It can be understood that the specific embodiments described herein are only used to explain the related disclosure, and not to limit the disclosure. In addition, it should be noted that only the relevant parts are shown in the drawings for convenience of description. Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the present disclosure belongs. The terms used herein are only for the purpose of describing the embodiments of the present disclosure, and are not intended to limit the present disclosure. In the following description, "some embodiments" are described, which describe a subset of all possible embodiments, but it can be understood that "some embodiments" can be the same subset or different subset of all possible embodiments, and can be combined with each other without conflict. It should be noted that the terms "first", "second", "third" in the embodiments of the present disclosure are only used to distinguish similar objects, and do not represent a specific order of the objects. It can be understood that "first", "second", "third" can be interchanged in a specific order or sequence as allowed, so that the embodiments of the present disclosure described herein can be implemented in an order other than that illustrated or described.

[0035] The embodiments of the present disclosure will be described in detail below in combination with the accompanying drawings.

[0036] FIG. 1A is a simplified schematic plan view of a semiconductor structure 1 according to an embodiment of the present disclosure, and FIG. 1B is a cross-sectional view of the semiconductor structure 1 along the line A1-A2 in FIG. 1A. In combination with FIG. 1A and FIG. 1B, the semiconductor structure 1 includes a first memory cell array 10 in which a plurality of word lines are arranged in parallel, for example, a plurality of first word lines 110 arranged in parallel and extending in a first direction X. Each of the first word lines 110 is parallel to and isolated from each other. The semiconductor structure 1 further includes a first interconnection region 11 in which a plurality of conductive lines are arranged in parallel and extending in the first direction X, for example, a plurality of first conductive lines 120. Each of the first conductive lines 120 is parallel to each other in the first direction X and connected to each of the first word lines 110 in an odd row or an even row, respectively. That is, another row of the first word lines 110 not connected to each of the first conductive lines 120 is arranged between each of the first conductive lines 120. Each of the first conductive lines 120 can be connected to each of the first word lines 110, respectively, and FIG. 1A shows an example in which each of the first conductive lines 120 is connected to each of the first word lines 110 in an odd row or an even row. It should be noted that each of the first word lines 110 not connected to each of the first conductive lines 120 is connected by a conductive line arranged in another interconnection region. A first conductive contact combination FC is arranged in the first interconnection region 11, and the first conductive contact combination FC includes a combination of a plurality of conductive contacts arranged corresponding to each of the first conductive lines 120, for example, a combination of a first conductive contact 140, a first conductive contact 141, a first conductive contact 142, and a first conductive contact 143. These conductive contacts are numbered differently to indicate that they are connected to different first conductive lines 120, respectively.

[0037] In the first direction X, each of the first conductive contacts has a spacing with an adjacent first conductive contact, for example, a spacing between the first conductive contact 140 and the first conductive contact 141, a spacing between the first conductive contact 141 and the first conductive contact 142, and a spacing between the first conductive contact 142 and the first conductive contact 143. The spacing between each of the first conductive contacts can be substantially the same or different, and has a minimum spacing, for example, a minimum spacing D0. In FIG. 1A, the first conductive contact 142 and the first conductive contact 143 have a minimum spacing D0, and the minimum spacing D0 can also be the spacing between other adjacent first conductive contacts. The value of the minimum spacing D0 is greater than 0 and less than the length of the extension of each of the first conductive lines 120 in the first direction X. The spacing between these first conductive contacts refers to the spacing between the center points of each of the first conductive contacts, and can also refer to the spacing between the same edges of each of the first conductive contacts or the spacing between the opposite edges of each of the first conductive contacts.

[0038] The semiconductor structure 1 comprises a second interconnection region 20 disposed adjacent to the first memory cell array 10 and the first interconnection region 11 in the first direction X, and a plurality of second conductive contact combinations SC are disposed in the second interconnection region 20, each of the second conductive contact combinations SC comprises a plurality of second conductive contacts disposed corresponding to each of the first conductive contacts, for example, a second conductive contact 201 corresponding to the first conductive contact 140, a second conductive contact 202 corresponding to the first conductive contact 141, a second conductive contact 203 corresponding to the first conductive contact 142, and a second conductive contact 204 corresponding to the first conductive contact 143. Each of the second conductive contacts is isolated from each other by a dielectric layer (not shown in the figure).

[0039] In the first direction X, each of the adjacent second conductive contacts is spaced apart, for example, the second conductive contact 201 and the second conductive contact 202 have a spacing therebetween, the second conductive contact 202 and the third conductive contact 203 have a spacing therebetween, and the second conductive contact 203 and the second conductive contact 204 have a spacing therebetween. The spacing between each of the adjacent second conductive contacts can be substantially the same or different, and has a minimum spacing, for example, the minimum spacing D1, in FIG. 1A, the second conductive contact 201 and the second conductive contact 202 have the minimum spacing D1 therebetween, and the minimum spacing D1 can also be the spacing between other adjacent second conductive contacts. The value of the minimum spacing D1 is greater than 0 and less than the length of the second interconnection region 20 extending in the first direction X. The spacing between each of the second conductive contacts refers to the spacing between the center points of each of the second conductive contacts, and can also refer to the spacing between the same edges of each of the second conductive contacts or the spacing between the opposite edges of each of the adjacent second conductive contacts. The minimum spacing D0 between each of the first conductive contacts is less than the minimum spacing D1 between each of the second conductive contacts.

[0040] Continuing to refer to FIGS. 1A and 1B, a plurality of first contact pads 210 are also disposed in the second interconnection region 20, and each of the second conductive contacts is connected to a corresponding one of the first contact pads 210 along a second direction Z. Each of the second conductive contacts has a corresponding length in the second direction Z, and the lengths of each of the second conductive contacts can be substantially the same or different, and has a minimum length. For example, the second conductive contact 201 has the minimum length L1.

[0041] Each of the first conductive contacts extends to a corresponding one of the first conductive lines 120 along a second direction Z, and the second direction Z is perpendicular to the first direction X, each of the first conductive contacts has a corresponding length in the second direction Z, and the lengths of each of the first conductive contacts can be substantially the same or different, and has a minimum length, for example, the first conductive contact 140 has the minimum length L0. Each of the second conductive contacts extends to a corresponding one of the first contact pads 210 along the second direction Z, and the minimum length L0 is less than the minimum length L1.

[0042] In the above embodiments, each first conductive contact in the first conductive contact combination FC is arranged in the first interconnection region 11 with a relatively small pitch, and each second conductive contact in the second conductive contact combination SC is arranged in the second interconnection region 20 with a relatively large pitch. On the basis of ensuring good isolation between adjacent conductive contacts, a simpler interconnection mode can be arranged in the second interconnection region 20, for example, only a single contact pad 210 is arranged to connect each second conductive contact to realize signal transmission in the second interconnection region 20, thereby increasing the signal density and simplifying the process flow.

[0043] The first interconnection region 11 can be located above or below the first memory cell array 10. In some embodiments, the first interconnection region 11 is located above or below the edge portion of the first memory cell array 10, i.e., the first interconnection region 11 is a region corresponding to the end of each first word line 110. The total number of rows of the first word lines 110 in the first memory cell array 10 can be an even number, for example, 512 rows, 1024 rows, or more.

[0044] In the second direction Z, the projection of each first conductive line 120 partially overlaps the projection of each first word line 110 to which it is connected, and the projection of each first word line 110 is located within the projection of each first conductive line 120. In the second direction Z, each second conductive contact overlaps the projection of each first contact pad 210 to which it is connected, and the projection of each second conductive contact is located within the projection of each first contact pad 210.

[0045] Continuing to refer to FIG. 1B, in the second direction Z, each first conductive line 120 is connected to each first word line 110 to which it corresponds through the contact plug 130, forming a connection channel between each first conductive line 120 and each first word line 110; and the contact plug 220 is further arranged on each first contact pad 210, forming a channel connecting the second conductive 210 in a direction away from the second conductive contact combination SC.

[0046] Referring back to FIGS. 1A and IB, the first memory cell array 10 is also provided with a plurality of columns of first bit lines 111, each column of first bit lines 111 extends along the third direction Y and is spaced apart from each other in the first direction X, the first direction X is perpendicular to the third direction Y, each column of first bit lines 111 extends in the second direction Z and the extension length thereof is not more than the extension length of each contact plug 130 in the second direction Z, the second direction Z is perpendicular to the third direction Y. The plurality of columns of first bit lines 111 and the plurality of rows of first word lines 110 are perpendicular to each other or have a certain angle. FIG. 1A takes an example in which the first bit lines 111 and the first word lines are perpendicular to each other, but is not limited thereto. In some embodiments, each first bit line 111 is closer to the first conductive contact combination FC than each first word line 110. The total number of columns of first bit lines 111 in the first memory cell array 10 can be an even number, for example, 512 columns, 1024 columns or more.

[0047] Referring back to FIG. IB, the first memory cell array 10 is also provided with a plurality of spaced-apart active regions 112 extending along the second direction Z, each active region 112 is connected to each column of first bit lines 111 at one end thereof in the second direction Z, and is connected to a capacitor array at the other end thereof in the second direction Z, the capacitor array includes a lower electrode 152, an upper electrode 150 and a dielectric layer 152 disposed between the upper and lower electrodes, for storing electric charges. In other embodiments, the capacitor array can also be other types of capacitor storage arrays. Each row of first word lines 110 simultaneously surrounds part of the sidewalls of a plurality of active regions 112 in the first direction X, thereby forming a memory for reading and storing data by storing and detecting electric charges in the capacitor array, such as a DRAM memory using vertical channel transistors. The first conductive contact combination FC is connected to each first word line 110 for controlling the opening and closing of the electron flow channel in the active region 112 between each column of first bit lines 111 and the capacitor array, and the second conductive contact combination SC is connected to each second conductive line 210 for transmitting the current signal in the second interconnection region 20.

[0048] In some embodiments of the present disclosure, as shown in FIG. 2, which is a simplified schematic plan view of the semiconductor structure 1, each first conductive contact in the semiconductor structure 1 has a corresponding width in the first direction X, the widths of each first conductive contact can be substantially the same or different, and these first conductive contacts have an average width, for example, W0. Each second conductive contact also has a corresponding width in the first direction X, the widths of each second conductive contact can be substantially the same or different, and these second conductive contacts have an average width, for example, W1, the average width W0 of each first conductive contact is less than the average width W1 of each second conductive contact.

[0049] Referring to FIG. 1A-1B, FIG. 2, and FIG. 3, which is a simplified schematic plan view of the semiconductor structure 1, in some embodiments of the present disclosure, the first conductive contact combination FC further comprises a first conductive contact 144, a first conductive contact 145, and a first conductive contact 146, and the second conductive contact combination SC further comprises a second conductive contact 205, a second conductive contact 206, and a second conductive contact 207. There are more first conductive contacts in the first conductive contact combination FC and more second conductive contacts in the second conductive contact combination SC, and the number of the first conductive contacts and the second conductive contacts is not limited to the number shown in the figure. The first conductive contacts in the first conductive contact combination FC can be divided into a first column first conductive contact combination FCC and a second column first conductive contact combination SCC according to the arrangement manner, the first column conductive contact combination FCC comprises a plurality of first conductive contacts arranged along the third direction Y, and each first conductive contact in the first column first conductive contact combination FCC corresponds to each first conductive line 120 in an odd row, such as the first conductive contact 140, the first conductive contact 142, the first conductive contact 144, and the first conductive contact 146. The second column conductive contact combination SCC comprises a plurality of first conductive contacts arranged along the third direction Y, and each first conductive contact in the second column first conductive contact combination SCC corresponds to each first conductive line 120 in an even row, such as the first conductive contact 141, the first conductive contact 143, and the first conductive contact 145. Each first conductive contact in the first column first conductive contact combination FCC and each first conductive contact in the second column first conductive contact combination SCC are staggered arranged in the first direction X with a minimum spacing D0.

[0050] Continuing to refer to FIG. 3, in some embodiments, at least one first conductive contact in the first column first conductive contact combination FCC has a maximum spacing with the second conductive contact corresponding thereto, for example, the first conductive contact 142 has a maximum spacing D2 with the second conductive contact 203, and the combination of the first conductive contact 142, the second conductive contact 203, and the space region between the first conductive contact 142 and the second conductive contact 203 is regarded as a first reference row, at this time, two first conductive contacts 141 and 143 in the second column first conductive contact combination SCC are arranged adjacent to the two sides of the first reference row, the first conductive contact 141 has a maximum spacing with the second conductive contact 202 corresponding thereto, and the first conductive contact 143 has a maximum spacing with the second conductive contact 204 corresponding thereto, and the two maximum spacings are both smaller than the maximum spacing D2.

[0051] In some embodiments, each of the first conductive contacts and each of the second conductive contacts disposed adjacent to the first reference row form a first reference row and a second reference row, respectively, for example, as shown in FIG. 3, the first conductive contact 141 and the second conductive contact 202 form the first reference row, and the first conductive contact 143 and the second conductive contact 204 form the second reference row, the first conductive contact and the second conductive contact in the first reference row have a maximum spacing D3 therebetween, the first conductive contact and the second conductive contact in the second reference row have a maximum spacing D4 therebetween, D3 is greater than D4, and both D3 and D4 are less than D2.

[0052] Continuing to refer to FIG. 3, in some embodiments, at least one of the first conductive contacts and its corresponding second conductive contact in the second column of first conductive contact combinations SCC have a maximum spacing therebetween, for example, the first conductive contact 145 and the second conductive contact 206 have a maximum spacing D5 therebetween, the first conductive contact 145, the second conductive contact 206, and the space region therebetween are considered as a second reference row, and two first conductive contacts 144 and 146 in the first column of first conductive contact combinations FCC are disposed adjacent to both sides of the second reference row, the first conductive contact 144 and its corresponding second conductive contact 205 have a maximum spacing therebetween, and the first conductive contact 146 and its corresponding second conductive contact 207 have a maximum spacing therebetween, both of which are less than the maximum spacing D5.

[0053] In some embodiments, each of the first conductive contacts and each of the second conductive contacts disposed adjacent to the second reference row form a third reference row and a fourth reference row, respectively, for example, as shown in FIG. 3, the first conductive contact 144 and the second conductive contact 205 form the third reference row, and the first conductive contact 146 and the second conductive contact 207 form the fourth reference row, the first conductive contact and the second conductive contact in the third reference row have a maximum spacing D6 therebetween, the first conductive contact and the second conductive contact in the fourth reference row have a maximum spacing D7 therebetween, D6 is greater than D7, and both D6 and D7 are less than D5.

[0054] The first reference row, the second reference row, and each of the reference rows in the above embodiments refer to a virtual row formed by a corresponding set of the first conductive contacts and the second conductive contacts along the first direction X, and are used to mark the positions of the corresponding first conductive contacts and the second conductive contacts.

[0055] In the above embodiments, the conductive contacts in the first interconnection region 11 and the second interconnection region 20 are arranged such that the first column of the first conductive contacts with the largest pitch and the corresponding second conductive contacts are the first reference row, the second column of the first conductive contacts with the largest pitch and the corresponding second conductive contacts are the second reference row, the second column of the first conductive contacts and the first column of the first conductive contacts and the corresponding second conductive contacts are arranged on the two sides adjacent to the first reference row and the second reference row respectively to form the reference rows, and the pitch between the conductive contacts in the reference rows is controlled to maximize the space utilization in the first interconnection region 11 and the second interconnection region 20, avoid short circuit between the conductive contacts, and generate parasitic capacitance.

[0056] The semiconductor structure 1 provided by the embodiments of the present disclosure further includes a plurality of conductive contacts connected to the columns of the first bit lines 111 in the third direction Y, as shown in FIG. 4A and FIG. 4B. FIG. 4A is a simplified schematic plan view of the semiconductor structure 1 provided by the embodiments of the present disclosure, and FIG. 4B is a cross-sectional view obtained by taking the B1-B2 line in FIG. 4A as a section. In the third direction Y, the semiconductor structure 1 further includes a third interconnection region 12, and the third interconnection region 12 includes a plurality of columns of the first bit lines 111 isolated from each other and parallel in the third direction Y. A fourth interconnection region 30 is arranged adjacent to the first memory cell array 10 and the third interconnection region in the third direction Y, and the columns of the bit lines in the first memory cell array 10 do not extend to the fourth interconnection region 30.

[0057] The third interconnection region 12 includes a plurality of second conductive lines 121 extending in the third direction Y, and the first conductive lines 121 are arranged corresponding to the odd-numbered columns or even-numbered columns of the first bit lines 111 and connected to each other. Each of the second conductive lines 121 extends in the third direction Y and is arranged spaced apart in the first direction X, wherein part of the second conductive lines 121 do not extend beyond the third interconnection region 12 in the third direction Y, and part of the second conductive lines 121 extend from the third interconnection region 12 to the fourth interconnection region 30 in the third direction Y. The second conductive lines 121 and the first conductive lines 120 together can constitute the first layer of conductive lines of the semiconductor structure 1, which means that the second conductive lines 121 and the first conductive lines 120 are conductive lines formed in different regions by the same conductive line manufacturing process.

[0058] Referring back to FIGS. 4A and 4B, the semiconductor structure 1 further includes a third conductive contact assembly TR including a plurality of third conductive contacts, such as third conductive contacts 160-165, each third conductive contact is disposed corresponding to each second conductive line 121, some of the third conductive contacts are disposed in the third interconnection region 12, and some of the third conductive contacts are disposed in the fourth interconnection region 30, such as the third conductive contacts 160 and 163 disposed in the third interconnection region 12, and the other third conductive contacts disposed in the fourth interconnection region 30. The fourth interconnection region further includes a fourth conductive contact assembly FR including a plurality of fourth conductive contacts, such as fourth conductive contacts 301-306, each fourth conductive contact is disposed corresponding to each third conductive contact in the third direction Y and electrically connected to each other.

[0059] Referring back to FIGS. 4A and 4B, the second conductive line 121 is connected to the corresponding first word line 111 through the contact plug 131, and the third conductive contact 160 is directly connected to the second conductive line 121. The fourth conductive contact 301 corresponding to the third conductive contact 160 extends to the second contact pad 211 disposed corresponding to the fourth conductive contact 301 in the second direction Z, and the second contact pad 211 is a conductive line disposed in the fourth interconnection region 30, which together with each first contact pad 210 disposed in the second interconnection region 20 can form a same layer conductive line of the semiconductor structure 1, which represents that the first contact pad 210 and the second contact pad 211 are formed by the same connection pad preparation process and are located in different regions.

[0060] In some embodiments, the third interconnection region 12 is a region where the end of each first bit line 111 in the third direction Y is located, the projection of each first conductive line 121 and the end of the corresponding first bit line 111 in the second direction Z has an overlapping region, the projection of each third conductive contact and each first conductive line 121 in the second direction Z also has an overlapping region, and the projection of each third conductive contact is located within the projection of each first conductive line 121.

[0061] Referring back to FIG. 5, FIG. 5 is a simplified schematic plan view of the semiconductor structure 1, each third conductive contact in the semiconductor structure 1 has a corresponding width in the third direction Y, the width of each third conductive contact can be substantially the same or different, and these third conductive contacts have an average width, such as W2. Each fourth conductive contact also has a corresponding width in the third direction Y, the width of each fourth conductive contact can be substantially the same or different, and these fourth conductive contacts have an average width, such as W3, and the average width W2 of each third conductive contact is less than the average width W3 of each fourth conductive contact.

[0062] Continuing to refer to FIG. 6, FIG. 6 is a simplified schematic plan view of the semiconductor structure 1, in the third direction Y, each third conductive contact is disposed adjacent to a same end of each second conductive line 121, for example, can be an end of each second conductive line 121 adjacent to or extending to the fourth interconnection region 30. In the third direction Y, each third conductive contact has a spacing with its corresponding fourth conductive contact, the spacings are the same or substantially the same, for example, the spacing D8 between the third conductive contact 161 and the fourth conductive contact 302.

[0063] In some embodiments, the spacings between each third conductive contact and its corresponding fourth conductive contact can also be partially the same or all different, the spacings between each third conductive contact and its corresponding fourth conductive contact in the embodiments of the present disclosure are not limited thereto.

[0064] In the third direction Y, at least two second conductive lines 121 extending from the third interconnection region 12 to the fourth interconnection region 30 are disposed between adjacent second conductive lines 121 in the third interconnection region 12. In the embodiments of the present disclosure, taking an example that two second conductive lines 121 extending from the third interconnection region 12 to the fourth interconnection region 30 are disposed between two adjacent second conductive lines 121 in the third interconnection region 12 as an example, as shown in FIG. 6, the second conductive line 121 corresponding to the third conductive contact 163 is disposed in the third interconnection region 12 and does not extend from the third interconnection region 12 to the fourth interconnection region 30, and has a length L3. Another third conductive contact adjacent to the third conductive contact 163 and located in the third interconnection region 12 is the third conductive contact 160. The third conductive contact 160 and the third conductive contact 163 are further provided with the third conductive contact 161 and the third conductive contact 162, the length of the second conductive line 121 corresponding to the third conductive contact 161 in the third direction Y is L4, and the length of the second conductive line 121 corresponding to the third conductive contact 162 in the third direction Y is L5, L4 is less than L5 and greater than L3.

[0065] In some embodiments, each second conductive line 121 disposed in the third interconnection region 12 has a maximum spacing with its corresponding fourth conductive contact, for example, as shown in FIG. 6, taking the fourth contact pad 304 and the second conductive line 121 corresponding thereto as an example. The spacing between the end edge of the second conductive line 121 corresponding to the third conductive contact 163 located in the third interconnection region 12 and its corresponding fourth conductive contact 304 away from the end edge of the third conductive contact 163 is the maximum spacing Dmax, the sum of Dmax and L3 is between L4 and L5.

[0066] In the above embodiments, each third conductive contact has a portion arranged in the third interconnection region and a portion arranged in the fourth interconnection region, thereby effectively avoiding short circuit between adjacent third conductive contacts or other factors affecting electrical properties, while the fourth interconnection region adjacent to the third interconnection region is arranged outside the third interconnection region, and the fourth conductive contacts in the fourth interconnection region maintain a predetermined distance from the third conductive contacts, so that the space utilization of the third interconnection region and the fourth interconnection region is maximized, short circuit between the conductive contacts and parasitic capacitance are avoided, and a design idea and practice for further increasing device density or wiring density are provided, which can further improve the integration of the semiconductor structure.

[0067] In some embodiments, the number of rows of first word lines in the first memory cell array 10 is less than the number of columns of first bit lines, for example, the first memory cell array 10 includes 512 first word lines and 1024 first bit lines.

[0068] Referring back to FIGS. 1A-1B and FIGS. 4A and 4B, the semiconductor structure 1 further includes a plurality of third conductive lines 122, including a portion of the third conductive lines 122 arranged in the first interconnection region 11 and the second interconnection region 20, and a portion of the third conductive lines 122 arranged in the third interconnection region 12 and the fourth interconnection region 30. Each third conductive line 122 arranged in the first interconnection region 11 is arranged corresponding to and connected to each first conductive contact, and each third conductive line 122 arranged in the second interconnection region 20 is arranged corresponding to and connected to each second conductive contact. Each third conductive line 122 arranged in the third interconnection region 12 and the fourth interconnection region 30 extends from the third interconnection region 12 to the fourth interconnection region 30, and is connected to the corresponding third conductive contact and fourth conductive contact, that is, each third conductive contact is interconnected with each corresponding fourth conductive contact via each third conductive line 122 extending in the third interconnection region 12 and the fourth interconnection region 30.

[0069] In some embodiments, each third conductive line 122 arranged in the first interconnection region 11 has the same or substantially the same width in the first direction X, and the projection area of each third conductive line 122 in the first interconnection region 11 in the second direction Z is greater than the projection area of each corresponding first conductive contact, and the projection of each first conductive contact is located within the projection of each third conductive line 122.

[0070] In some embodiments, each third conductive line 122 arranged in the second interconnection region 20 has the same or substantially the same width in the first direction X, and the projection area of each third conductive line 122 in the first interconnection region 11 in the second direction Z is greater than the projection area of each corresponding second conductive contact, and the projection of each second conductive contact is located within the projection of each third conductive line 122.

[0071] In some embodiments, the third conductive lines 122 located in the first interconnection region 11 can have the same or different sizes as the third conductive lines 122 located in the second interconnection region 20. FIG. 1A and FIG. 1B show an example in which the third conductive lines 122 located in the first interconnection region 12 have different sizes from the third conductive lines 122 located in the second interconnection region 20.

[0072] In some embodiments, the third conductive lines 122 corresponding to the third conductive contacts and the fourth conductive contacts have the same or substantially the same extension length in the third direction Y, and in the second direction Z, the projections of the third conductive contacts and the fourth conductive contacts are located within the projections of the corresponding third conductive lines 122.

[0073] Referring to FIG. 7A and FIG. 7B, FIG. 7A is a cross-sectional view of the semiconductor structure 1 along a section parallel to the second direction Z, and FIG. 7B is a cross-sectional view of the semiconductor structure 1 along a section parallel to the second direction Z. The semiconductor structure 1 further includes a second memory cell array 10', which has a similar structure to the first memory cell array 10, for example, including a plurality of rows of second word lines 110' arranged in parallel along the first direction X and a plurality of rows of second bit lines 111' arranged in parallel along the third direction Y.

[0074] Referring to FIG. 7A, in some embodiments, an interconnection region 11' is further provided below the second word lines 110', and the interconnection region 11' is connected to the second word lines 110' in the odd-numbered rows or the even-numbered rows of the second memory cell array 10'. An interconnection channel is formed between the interconnection region 11' and the second interconnection region 20, and the interconnection channel is connected to the corresponding first word line 110 in the first memory cell array 10, for example, a connection channel formed by the first contact pad 210 connected to the second conductive contact 201 and the contact plug 220, so as to form a connection channel for the second word lines 110' in the second memory cell array 10' in the second interconnection region 20.

[0075] Referring to FIG. 7B, in some embodiments, an interconnection region 12' is further provided below the second memory cell array 10', and the interconnection region 12' is connected to the second bit lines 111' in the odd-numbered columns or the even-numbered columns of the second memory cell array 10'. An interconnection channel is formed between the interconnection region 12' and the second interconnection region 30, and the interconnection channel is connected to the corresponding first bit line 111 in the first memory cell array 10, for example, a connection channel formed by the second contact pad 211 connected to the fourth conductive contact 301 and the contact plug 320, so as to realize the interconnection between the first bit line 111 and the second bit line 110'.

[0076] In some embodiments, the first contact pad 210 and the second contact pad 211 can be formed in the same process. In some embodiments, the first contact pad 210 and the second contact pad 211 are located between the capacitor array and the first word line 110, and the top surfaces of the second interconnection region 20 and the fourth interconnection region 30 are higher than the top surface of the capacitor array. By arranging the first contact pad 210 and the second contact pad 211, the second conductive contacts and the fourth conductive contacts can be prevented from extending for a long length in the second interconnection region 20 or the fourth interconnection region 30, and the process difficulty is further reduced. In other embodiments, only the second conductive contacts and the fourth conductive contacts extending in the second direction Z can be arranged in the second interconnection region 20 and the fourth interconnection region 30.

[0077] In some embodiments, the first memory cell array 10 and the second memory cell array 10' have a bonding surface formed by using a direct bonding or hybrid bonding process, and the bonding surface is used to realize the connection relationship between the word lines and the bit lines in the first memory cell array 10 and the second memory cell array 10'.

[0078] In some embodiments, the semiconductor structure 1 further includes a logic cell array (not shown in the figure), which has a portion connected to each second conductive line 122 in the first interconnection region 11, a portion connected to each second conductive line 122 in the second interconnection region 20, and a portion connected to each second conductive line 122 in the third interconnection region 12 and the fourth interconnection region 30, so as to realize corresponding operations on the first word lines 110 and the first bit lines 111 in the first memory cell array 10 and the second word lines 110' and the second bit lines 111' in the second memory cell array 10'.

[0079] In the above embodiments, the first memory cell array 10 and the second memory cell array 10' can be a memory cell array composed of DRAM memory cells, NAND memory cells or other memory cells, and the logic cell array can be any suitable digital, analog and / or mixed signal circuit structure for facilitating the operation of the memory structure.

[0080] It can be understood by those skilled in the art that the above embodiments are specific embodiments for implementing the present disclosure, and various changes can be made in form and details in actual applications without departing from the spirit and scope of the embodiments of the present disclosure. Any person skilled in the art can make various modifications and changes without departing from the spirit and scope of the embodiments of the present disclosure, and therefore the protection scope of the embodiments of the present disclosure should be subject to the scope defined by the claims.

Claims

1. A semiconductor structure, comprising: a first memory cell array, the first memory array comprising a plurality of rows of first word lines extending in a first direction, each of the first word lines being isolated from each other; a first interconnection region comprising a plurality of first conductive lines extending in the first direction, each of the first conductive lines being disposed corresponding to each of the first word lines of odd rows or even rows and connected to each other; a first conductive contact assembly disposed in the first interconnection region, the first conductive contact assembly comprising a plurality of first conductive contacts, each of the first conductive contacts being disposed corresponding to each of the first conductive lines, and each of the first conductive contacts extending in a second direction to connect to each of the first conductive lines; a second interconnection region disposed adjacent to the first memory cell array and the first interconnection region in the first direction, the second interconnection region being provided with a second conductive contact assembly comprising a plurality of second conductive contacts, each of the second conductive contacts being disposed corresponding to each of the first conductive contacts and isolated from each other; a plurality of first contact pads being disposed in the second interconnection region, each of the second conductive contacts extending in the second direction to connect to each of the first contact pads; wherein a minimum spacing D0 is provided between each of the first conductive contacts adjacent in the first direction, a minimum spacing D1 is provided between each of the second conductive contacts adjacent in the first direction, the minimum spacing D0 is smaller than the minimum spacing D1, in the second direction, each of the first conductive contacts has a minimum length L0, each of the second conductive contacts has a minimum length L1, the minimum length L0 is smaller than the minimum length L1.

2. The semiconductor structure of claim 1, wherein, In the first direction, each of the first conductive contacts in the first conductive contact assembly has an average width W0, each of the second conductive contacts in the second conductive contact assembly has an average width W1, the average width W0 of each of the first conductive contacts is smaller than the average width W1 of each of the second conductive contacts.

3. The semiconductor structure of claim 1, wherein, The first conductive contact assembly comprises a first column of first conductive contact assemblies and a second column of first conductive contact assemblies arranged in a third direction, each of the first conductive contacts in the first column of first conductive contact assemblies connects to each of the first conductive lines of odd rows respectively, each of the first conductive contacts in the second column of first conductive contact assemblies connects to each of the first conductive lines of even rows respectively, wherein in the first direction, a maximum spacing D2 is provided between at least one of the first conductive contacts in the first column of first conductive contact assemblies and a corresponding one of the second conductive contacts in the second conductive contact assembly, the first conductive contact and the second conductive contact having the maximum spacing D2 form a first reference row, each of the first conductive contacts in the second column of first conductive contact assemblies disposed adjacent to the first reference row has a maximum spacing smaller than the maximum spacing D2 from each of the second conductive contacts disposed corresponding thereto.

4. The semiconductor structure of claim 3, wherein, Each of the first conductive contacts and each of the second conductive contacts arranged adjacent to the first reference row forms a first reference row and a second reference row respectively, the first conductive contacts and the second conductive contacts in the first reference row have a maximum spacing D3 therebetween, the first conductive contacts and the second conductive contacts in the second reference row have a maximum spacing D4 therebetween, the maximum spacing D3 is greater than the maximum spacing D4, and the maximum spacing D3 and the maximum spacing D4 are both less than the maximum spacing D2.

5. The semiconductor structure of claim 3, wherein, In the first direction, at least one of the first conductive contacts and the corresponding one of the second conductive contacts in the second column of the first conductive contact combination and the second conductive contact combination have a maximum spacing D5 therebetween, the first conductive contacts and the second conductive contacts having the maximum spacing D5 form a second reference row, and each of the first conductive contacts in the first column of the first conductive contact combination arranged adjacent to the second reference row and each of the second conductive contacts arranged adjacent thereto have a maximum spacing less than the maximum spacing D5 therebetween.

6. The semiconductor structure of claim 5, wherein, Each of the first conductive contacts and each of the second conductive contacts arranged adjacent to the second reference row forms a third reference row and a fourth reference row respectively, the first conductive contacts and the second conductive contacts in the third reference row have a maximum spacing D6 therebetween, the first conductive contacts and the second conductive contacts in the fourth reference row have a maximum spacing D7 therebetween, the maximum spacing D6 is greater than the maximum spacing D7, and the maximum spacing D6 and the maximum spacing D7 are both less than the maximum spacing D5.

7. The semiconductor structure of claim 1, wherein, The first memory cell array further includes a plurality of columns of first bit lines extending in a third direction, each of the first bit lines being isolated from each other; a third interconnection region including a plurality of second conductive lines extending in the third direction, each of the second conductive lines being arranged corresponding to each of the first bit lines of the odd columns or the even columns and being connected to each other; a fourth interconnection region arranged adjacent to the first memory cell array and the third interconnection region in the third direction, part of the second conductive lines being arranged in the third interconnection region, and part of the second conductive lines being extended from the third interconnection region to the fourth interconnection region; a third conductive contact combination including a plurality of third conductive contacts, each of the third conductive contacts including a plurality of third conductive contacts arranged in the third interconnection region and a plurality of third conductive contacts arranged in the fourth interconnection region, each of the third conductive contacts being connected to the corresponding first conductive line; the third interconnection region is provided with a fourth conductive contact combination including a plurality of fourth conductive contacts, each of the fourth conductive contacts being arranged corresponding to each of the third conductive contacts and being connected to each other.

8. The semiconductor structure of claim 7, wherein, In the third direction, each of the third conductive contacts in the third conductive contact combination has an average width W2, each of the fourth conductive contacts in the fourth conductive contact combination has an average width W3, and the average width W2 of each of the third conductive contacts is less than the average width W3 of each of the fourth conductive contacts.

9. The semiconductor structure of claim 7, wherein, In the third direction Y, the spacing between each of the third conductive contacts and its corresponding fourth conductive contact is the same.

10. The semiconductor structure of claim 7, wherein, In the third direction, each of the second conductive lines in the third interconnection region has a length L3, and between adjacent second conductive lines in the third interconnection region, there are at least two second conductive lines extending to the fourth interconnection region, each of the second conductive lines extending to the fourth interconnection region has a different length and is greater than the length L3, each of the second conductive lines in the third interconnection region and its corresponding fourth conductive contact have a maximum spacing Dmax, and the sum of the maximum spacing Dmax and the length L3 is between the length values of the second conductive lines extending to the fourth interconnection region.

11. The semiconductor structure of claim 7, wherein, The number of rows of the first word lines in the first memory cell array is less than the number of columns of the first bit lines in the third interconnection region.

12. The semiconductor structure of claim 7, wherein, The semiconductor structure further includes a plurality of third conductive lines, the plurality of third conductive lines including portions disposed in the first interconnection region and the second interconnection region and portions disposed in the third interconnection region and the fourth interconnection region, each of the third conductive lines disposed in the first interconnection region and the second interconnection region is connected to a corresponding first conductive contact and second conductive contact, respectively. Each of the third conductive lines disposed in the third interconnection region and the fourth interconnection region is connected to a corresponding third conductive contact and fourth conductive contact, respectively.

13. The semiconductor structure of claim 1, wherein, The semiconductor structure further includes a second memory cell array, the second memory cell array including a plurality of rows of second word lines isolated from each other and extending in the first direction, each of the second word lines being connected to a corresponding second conductive contact.

14. The semiconductor structure of claim 7, wherein, The semiconductor structure further includes a second memory cell array, the second memory cell array including a plurality of rows of second bit lines isolated from each other and extending in the third direction, each of the second bit lines being connected to a corresponding fourth conductive contact.

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