Semiconductor structure and integrated assembly

Abstract

Provided in the embodiments of the present disclosure are a semiconductor structure and an integrated assembly. The semiconductor structure comprises: a first surface and a second surface that are opposite to each other; a first connection pad and a second connection pad that are arranged on the first surface; a third connection pad, a fourth connection pad and a fifth connection pad that are arranged on the second surface; and a memory cell region provided between the first surface and the second surface and containing a first connection part and, arranged in a first direction, a first semiconductor device and a second semiconductor device. The first connection pad and the fourth connection pad are connected to the first semiconductor device; the second connection pad and the fifth connection pad are connected to the second semiconductor device; the first connection part is connected to at least one of the first semiconductor device and the second semiconductor device; the first connection part is connected to the third connection pad. The semiconductor structure provided in the embodiments of the present disclosure has higher integration density.

Description

Semiconductor structure and integrated assembly

[0001] The present disclosure claims priority to a Chinese patent application No. 202411267637.7, filed on September 10, 2024, entitled “Semiconductor structure and integrated assembly”, the entire content of which is incorporated herein by reference. TECHNICAL FIELD

[0002] Embodiments of the present disclosure relate to the field of semiconductor technology, and in particular, to a semiconductor structure and integrated assembly. BACKGROUND

[0003] Memory is used to store data in modern computing architectures, and dynamic random access memory (DRAM) has the advantages of simple structure, low cost and high speed, and is widely used in personal computers, servers and various electronic devices as main memory.

[0004] As data continues to grow rapidly, the density of DRAM is slowing down, resulting in a growing gap between memory demand and DRAM capacity. Increasing the integration by increasing the packaging density to obtain higher storage capacity has become an important goal in the current integrated circuit manufacturing, and memory with tight packaging is urgently needed to be developed. SUMMARY

[0005] Embodiments of the present disclosure provide a semiconductor structure with higher integration.

[0006] The problems to be solved by the technical spirits of the present disclosure are not limited to the above-mentioned problems, and other problems not mentioned will be clearly understood by those skilled in the art from the following description.

[0007] According to an example embodiment of the present disclosure, a semiconductor structure is provided, comprising: opposite first and second surfaces; a first connection pad and a second connection pad disposed on the first surface; a third connection pad, a fourth connection pad and a fifth connection pad disposed on the second surface; a memory cell region disposed between the first and second surfaces, the memory cell region comprising first and second semiconductor devices arranged along a first direction, the first connection pad and the fourth connection pad connecting the first semiconductor device, the second connection pad and the fifth connection pad connecting the second semiconductor device, the memory cell region further comprising a first connection portion connected to at least one of the first and second semiconductor devices, the first connection portion connecting the third connection pad.

[0008] According to an example embodiment of the present disclosure, in a direction parallel to the first surface, a maximum width of at least one of the first and second connection pads is greater than a maximum width of at least one of the third, fourth and fifth connection pads.

[0009] According to an example embodiment of the present disclosure, the minimum spacing between the first connection pad and the second connection pad in a direction parallel to the first surface is greater than the minimum spacing between the third connection pad, the fourth connection pad, and the fifth connection pad.

[0010] According to an example embodiment of the present disclosure, the semiconductor structure further comprises: an interconnection layer disposed adjacent to the first surface; a wiring layer disposed adjacent to the second surface; the first connection pad and the second connection pad are connected to the first semiconductor device and the second semiconductor device, respectively, through the interconnection layer, the third connection pad is connected to the first connection portion through the wiring layer, the fourth connection pad and the fifth connection pad are connected to the first semiconductor device and the second semiconductor device, respectively, through the wiring layer, and the metal density of the wiring layer is greater than the metal density of the interconnection layer.

[0011] According to an example embodiment of the present disclosure, the semiconductor structure further comprises a second connection portion connected to the first semiconductor device and a third connection portion connected to the second semiconductor device, the first connection pad and the fourth connection pad are connected to the second connection portion, the second connection pad and the fifth connection pad are connected to the third connection portion, the second connection portion, the third connection portion, and the first connection portion are isolated from each other, and the wiring layer comprises a first wiring layer, and the first connection portion, the second connection portion, and the third connection portion are connected to the first wiring layer.

[0012] According to an example embodiment of the present disclosure, a sixth connection pad is further disposed on the first surface, a seventh connection pad is further disposed on the second surface, and the sixth connection pad is connected to the seventh connection pad.

[0013] According to an example embodiment of the present disclosure, the semiconductor structure further comprises a fourth connection portion, the fourth connection portion is located in the memory cell region and in a region between the first semiconductor device and the second semiconductor device, an eighth connection pad is further disposed on the first surface, a ninth connection pad is further disposed on the second surface, and the fourth connection portion is connected to the eighth connection pad and the ninth connection pad.

[0014] According to an example embodiment of the present disclosure, the wiring layer further comprises a second wiring layer, and the fourth connection portion is connected to the second wiring layer.

[0015] Another semiconductor structure is provided according to an example embodiment of the present disclosure, comprising: opposite first and second surfaces; first and second connection pads disposed on the first surface; third, fourth, and fifth connection pads disposed on the second surface; a memory cell region disposed between the first and second surfaces, the memory cell region comprising a first memory cell array and a second memory cell array spaced apart, the first memory cell array comprising a plurality of first semiconductor devices arranged along a first direction, the second memory cell array comprising a plurality of second semiconductor devices arranged along the first direction; the first and fourth connection pads connecting the first semiconductor devices, the second and fifth connection pads connecting the second semiconductor devices, the memory cell region further comprising a first connection portion connected to at least one of the first semiconductor devices and the second semiconductor devices, the third connection pad connecting the first connection portion.

[0016] According to an example embodiment of the present disclosure, the first memory cell array comprises a second connection portion, the second memory cell array comprises a third connection portion, the second connection portion connecting the first semiconductor devices, the third connection portion connecting the second semiconductor devices, the first and fourth connection pads connecting the second connection portion, the second and fifth connection pads connecting the third connection portion.

[0017] According to an example embodiment of the present disclosure, the plurality of first semiconductor devices arranged along the first direction form a plurality of first sub-columns, each first sub-column comprising a first sub-column connection portion connecting a plurality of the first semiconductor devices along the first direction, the plurality of second semiconductor devices arranged along the first direction form a plurality of second sub-columns, each second sub-column comprising a second sub-column connection portion connecting a plurality of the second semiconductor devices along the first direction, the first and fourth connection pads are connected to the first sub-column connection portions through the second connection portion, the second and fifth connection pads are connected to the second sub-column connection portions through the third connection portion, the first sub-column connection portions and the second sub-column connection portions are arranged in extension along the first direction, the first sub-column connection portions and the second sub-column connection portions are isolated from each other, the first memory cell array further comprises a plurality of first semiconductor devices arranged along a second direction, the second memory cell array further comprises a plurality of second semiconductor devices arranged along the second direction, the plurality of first semiconductor devices arranged along the second direction form a plurality of first sub-rows, the plurality of second semiconductor devices arranged along the second direction form a plurality of second sub-rows, each first sub-row comprising a first sub-row connection portion connecting a plurality of the first semiconductor devices along the second direction, each second sub-row comprising a second sub-row connection portion connecting a plurality of the second semiconductor devices along the second direction, the first sub-row connection portions and the second sub-row connection portions are arranged in extension along the second direction, the first connection portion is connected to at least one of the first sub-row connection portions and the second sub-row connection portions.

[0018] According to an example embodiment of the present disclosure, the first storage unit array includes a plurality of first sub-column connection portions and a plurality of first sub-row connection portions, the number of the first sub-column connection portions is greater than the number of the first sub-row connection portions, the second storage unit array includes a plurality of second sub-column connection portions and a plurality of second sub-row connection portions, the number of the second sub-column connection portions is greater than the number of the second sub-row connection portions.

[0019] According to an example embodiment of the present disclosure, the storage unit region further includes a third sub-column connection portion extending along the first direction, the third sub-column connection portion extends from the first storage unit array to the second storage unit array, the third sub-column connection portion connects the plurality of first semiconductor devices and the plurality of second semiconductor devices extending along the first direction.

[0020] According to an example embodiment of the present disclosure, the first semiconductor device and the second semiconductor device each include a gate and a drain, the first sub-row connection portion connects the gate of the first semiconductor device, the second sub-row connection portion connects the gate of the second semiconductor device, the first sub-column connection portion connects the drain of the first semiconductor device, the second sub-column connection portion connects the drain of the second semiconductor device, and the third sub-column connection portion connects the drains of the first semiconductor device and the second semiconductor device.

[0021] According to an example embodiment of the present disclosure, the first surface is further provided with a sixth connection pad, the second surface is further provided with a seventh connection pad, and the sixth connection pad connects the seventh connection pad.

[0022] According to an example embodiment of the present disclosure, an integrated assembly is provided, including: a first semiconductor structure, the first semiconductor structure including a first surface, the first surface being provided with a first connection pad and a second connection pad, the first semiconductor structure further including a storage unit region, the storage unit region being disposed below the first surface, the storage unit region including a first semiconductor device and a second semiconductor device, the first connection pad connecting the first semiconductor device, the second connection pad connecting the second semiconductor device, and a first connection portion being between the first semiconductor device and the second semiconductor device; a second semiconductor structure, the second semiconductor structure having a first bonding surface bonded to the first surface of the first semiconductor structure, the second semiconductor structure including a third semiconductor device and a fourth semiconductor device, the third semiconductor device and the first semiconductor device being connected by the first bonding surface and the first connection pad, the fourth semiconductor device and the second semiconductor device being connected by the first bonding surface and the second connection pad, the second semiconductor structure further having a common connection portion, the common connection portion connecting at least the third semiconductor device or the fourth semiconductor device; the first semiconductor structure further including a second surface, the second surface being provided with a third connection pad, a fourth connection pad, a fifth connection pad, and a sixth connection pad, the third connection pad connecting the first connection portion, the fourth connection pad connecting the first connection pad, the fifth connection pad connecting the second connection pad, and the sixth connection pad connecting the common connection portion.

[0023] According to an example embodiment of the present disclosure, the first semiconductor structure further comprises an interconnection layer between the first surface and the second surface and disposed adjacent to the first surface, the second semiconductor structure further comprises a connection layer disposed adjacent to the first bonding surface, and the third semiconductor device and the fourth semiconductor device are interconnected with the first semiconductor device and the second semiconductor device through the connection layer.

[0024] According to an example embodiment of the present disclosure, a third semiconductor structure is further included, one surface of the third semiconductor structure is bonded to the second surface of the first semiconductor structure, the third semiconductor structure comprises a fifth semiconductor device, the first semiconductor structure further comprises a wiring layer disposed adjacent to the second surface, the third semiconductor structure comprises a trace layer disposed adjacent to the second surface, and the first semiconductor device, the second semiconductor device, the third semiconductor device, and the fourth semiconductor device are interconnected with the fifth semiconductor device through the trace layer.

[0025] The first surface and the second surface of the semiconductor structure provided by the embodiments of the present disclosure are both provided with connection channels connected with the first semiconductor device and the second semiconductor device, through which the semiconductor devices in the memory cell array can be more flexibly laid out and designed, the area of the memory cell region is further reduced, and a more compact semiconductor structure is provided. BRIEF DESCRIPTION OF DRAWINGS

[0026] The accompanying drawings, which are incorporated herein and form part of the specification, illustrate embodiments consistent with the present disclosure and, together with the description, further serve to explain the principles of the present disclosure.

[0027] FIG. 1 is a schematic diagram of a semiconductor structure according to some embodiments of the present disclosure;

[0028] FIG. 2 is a schematic diagram of a semiconductor structure according to some embodiments of the present disclosure;

[0029] FIG. 3 is a schematic diagram of a semiconductor structure according to some embodiments of the present disclosure;

[0030] FIG. 4 is a schematic diagram of a semiconductor structure according to some embodiments of the present disclosure;

[0031] FIG. 5 is a schematic diagram of a semiconductor structure according to some embodiments of the present disclosure;

[0032] FIG. 6 is a schematic diagram of another semiconductor structure according to some embodiments of the present disclosure;

[0033] FIG. 7 is a schematic diagram of an integrated assembly according to some embodiments of the present disclosure;

[0034] The above figures have shown the specific embodiments of the present disclosure, which will be described in more detail hereinafter. These figures and the written description are not intended to limit the scope of the present disclosure in any way, but to illustrate the concept of the present disclosure to those skilled in the art by referring to specific embodiments. DETAILED DESCRIPTION

[0035] The technical solutions in the embodiments of the present disclosure will be described clearly and completely in combination with the drawings in the embodiments of the present disclosure. It can be understood that the specific embodiments described herein are only used to explain the concept of the present disclosure, and not to limit the present disclosure. In addition, it should be noted that only the relevant parts are shown in the drawings for convenience of description. Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the art to which the present disclosure belongs. The terms used herein are only for the purpose of describing the embodiments of the present disclosure, and are not intended to limit the present disclosure. In the following description, "some embodiments" are described, which describe a subset of all possible embodiments, but it can be understood that "some embodiments" can be the same subset or different subset of all possible embodiments, and can be combined with each other without conflict. It should be noted that the terms "first", "second", "third" used in the present disclosure are only used to distinguish similar objects, and do not represent a specific order of the objects. It can be understood that "first", "second", "third" can be interchanged in a specific order or sequence as allowed, so that the embodiments of the present disclosure described herein can be implemented in an order other than that illustrated or described.

[0036] The embodiments of the present disclosure will be described in detail below in combination with the drawings.

[0037] Figure 1 provides a semiconductor structure 1a, which includes opposite first and second surfaces A and B, the first surface A is provided with a first connection pad 110 and a second connection pad 120, and the second surface B is provided with a third connection pad 210, a fourth connection pad 220 and a fifth connection pad 230.

[0038] The first surface A and the second surface B can be upper and lower surfaces of the semiconductor structure la for bonding with other semiconductor structures, or can be independent upper and lower surfaces of the semiconductor structure la. The first connection pad 110 and the second connection pad 120 can have portions extending below the first surface A and surface portions exposed to the first surface A, and the third connection pad 210, the fourth connection pad 220, and the fifth connection pad 230 can have portions extending below the second surface B and surface portions exposed to the second surface B. In some embodiments, the first connection pad 110 and the second connection pad 120 can be connection pads for bonding with other semiconductor structures, and the third connection pad 210, the fourth connection pad 220, and the fifth connection pad 230 can be connection pads for bonding with other semiconductor structures.

[0039] In some embodiments, the first connection pad 110, the second connection pad 120, the third connection pad 210, the fourth connection pad 220, and the fifth connection pad 230 can be conductive connection pads of the same material type, for example, all being conductive pads containing copper, aluminum, or the like metal or alloy thereof. In other embodiments, the first connection pad 110 and the second connection pad 120 can be conductive pads of the same material type, and the third connection pad 210, the fourth connection pad 220, and the fifth connection pad 230 can be conductive pads of the same material type, but the first connection pad 110 is different from the third connection pad 210, for example, the first connection pad 110 is a conductive pad containing copper, and the third connection pad 210 is a conductive pad containing aluminum.

[0040] In some embodiments, the first connection pad 110, the second connection pad 120, the third connection pad 210, the fourth connection pad 220, and the fifth connection pad 230 are functional connection pads, and the first surface A and the second surface B are further provided with non-functional connection pads, the non-functional connection pads extending below the first surface A and the second surface B to a depth less than the extension depth of each functional connection pad, as shown in FIG. 1. In some embodiments, the non-functional connection pads can be provided only on one surface of the semiconductor structure la, for example, only on the second surface B, and the first surface A is provided with functional connection pads only. In some embodiments, the functional connection pads and the non-functional connection pads are uniformly distributed on each surface.

[0041] In some embodiments, the first connection pad 110 and the second connection pad 120 can have the same or substantially the same width along a cross-section taken in a direction parallel to the first surface; in some embodiments, the first connection pad 110 and the second connection pad 120 can have different widths, for example, the first connection pad 110 can have a larger width than the second connection pad 120, and the second connection pad 120 can also have a larger width than the first connection pad 110. Similarly, the third connection pad 210, the fourth connection pad 220 and the fifth connection pad 230 can also have the same or different widths. In some embodiments, at least one of the first connection pad 110 and the second connection pad 120 has a maximum width that is larger than a maximum width of at least one of the third connection pad 210, the fourth connection pad 220 and the fifth connection pad 230.

[0042] In some embodiments, along a cross-section taken in a direction parallel to the first surface, the first connection pad 110 and the second connection pad 120 have a minimum spacing between each other, and the third connection pad 210, the fourth connection pad 220 and the fifth connection pad 230 have a minimum spacing between each other, and the minimum spacing between the first connection pad 110 and the second connection pad 120 is larger than the minimum spacing between the third connection pad 210, the fourth connection pad 220 and the fifth connection pad 230.

[0043] In some embodiments, the minimum spacing between the first connection pad 110 and the second connection pad 120 includes the width of the first connection pad 110 and the distance between the outer edge of the first connection pad 110 and the outer edge of the second connection pad 120. In other embodiments, the minimum spacing between the first connection pad 110 and the second connection pad 120 is the distance between the outer edge of the first connection pad 110 and the outer edge of the second connection pad 120.

[0044] The semiconductor structure 1a further includes a memory cell region 3 disposed between the first surface A and the second surface B, the memory cell region 3 including first semiconductor devices 310 and second semiconductor devices 320 arranged along a first direction, which can be parallel to the first surface A or perpendicular to the first surface A. The first semiconductor devices 310 and the second semiconductor devices 320 are memory devices, for example, DRAM memory cells or NAND memory cells.

[0045] The first connection part 30 is used to connect at least one of the first semiconductor device 310 and the second semiconductor device 320. For example, in some embodiments, the first connection part 30 connects both the first semiconductor device 310 and the second semiconductor device 320, i.e., the first connection part 30 can be a common connection part between the first semiconductor device 310 and the second semiconductor device 320, as shown in FIG. 1. In this case, the first semiconductor device 310 and the second semiconductor device 320 are connected to the third connection pad 210 via the first connection part 30. In some embodiments, the first direction is a direction perpendicular to the first connection part.

[0046] In some embodiments, the first connection part 30 can also separately connect the first semiconductor device 310 or separately connect the second semiconductor device 320, as shown in FIG. 2, which shows a semiconductor structure la in which the first connection part 30 separately connects the first semiconductor device 310, and the second semiconductor device 320 is separately connected by another connection part 30'. In this case, the first semiconductor device 310 is connected to the third connection pad 210 via the first connection part 30, and the second semiconductor device 320 is connected to another connection pad 210' on the second surface B via the other connection part 30'.

[0047] The region between the first semiconductor device 310 and the second semiconductor device 320 is a region provided with an insulating medium layer, and no semiconductor device can be provided in this region. The first connection part 30 can be located in the region between the first semiconductor device 310 and the second semiconductor device 320, or can be located on one side of the first semiconductor device 310 or the second semiconductor device 320. The first connection part 30 and the other connection part 30' can be located on one side of the first semiconductor device 310 or the second semiconductor device 320, respectively, or can be located between the first semiconductor device 310 and the second semiconductor device 320. The first semiconductor device 310 also has an end connected to the first connection pad 110 and the fourth connection pad 220, and the second semiconductor device 320 also has an end connected to the second connection pad 120 and the fifth connection pad 230. In the semiconductor structure la, the first semiconductor device 310 and the second semiconductor device 320 form connection channels through the respective connection pads provided on the first surface A and the first surface B, respectively. The additional connection channels can more flexibly layout and design the first semiconductor device 310 and the second semiconductor device 320, thereby reducing the area of the memory cell region and providing a more compact semiconductor structure.

[0048] In some embodiments, the first connection portion 30 is disposed relatively closer to the second surface B, see FIG. 3. Unlike FIGS. 1 and 2, in the semiconductor structure la shown in FIG. 3, the first connection portion 30 is disposed relatively closer to the second surface B than the first connection portion 30 in FIGS. 1 and 2. The first connection portion 30 connects both the first semiconductor device 310 and the second semiconductor device 320 and is located in the region of the memory cell area 3 near the bottom.

[0049] In some embodiments, the first semiconductor device 310 and the second semiconductor device 320 can be DRAM memory device cells. FIGS. 1-3 show schematic diagrams of structures of the same type of DRAM memory device cell for the first semiconductor device 310 and the second semiconductor device 320. The basic unit includes a transistor and a capacitor. The transistor in the first semiconductor device 310 includes a source 3102 and a drain 3101 arranged in a vertical direction, with a channel region between the source 3102 and the drain 3101, and a gate 3103 disposed around the channel region on the periphery of the channel region. Similarly, the transistor in the second semiconductor device 320 includes a source 3202 and a drain 3201 arranged in a vertical direction, with a channel region between the source 3202 and the drain 3201, and a gate 3203 disposed around the channel region on the periphery of the channel region. The capacitor in the first semiconductor device 310 includes an electrode portion 3104 connected to the source 3102, and the capacitor in the second semiconductor device 320 also includes an electrode portion 3204 connected to the source 3202. The first semiconductor device 310 further includes an electrode portion 3105, and the electrode portion 3104 and the electrode portion 3105 constitute the upper and lower electrodes of the capacitor in the first semiconductor device 310. The second semiconductor device 320 further includes an electrode portion 3205, and the electrode portion 3204 and the electrode portion 3205 constitute the upper and lower electrodes of the capacitor in the second semiconductor device 320. In some embodiments, as shown in FIG. 1, the first connection portion 30 connects the gate 3103 of the first semiconductor device 310 and the gate 3203 of the second semiconductor device 320. In some embodiments, as shown in FIG. 2, the first connection portion 30 connects the gate 3103 of the first semiconductor device 310, and the connection portion 30’ connects the gate 3203 of the second semiconductor device 320. In some embodiments, as shown in FIG. 3, the first connection portion 30 connects the drain 3101 of the first semiconductor device 310 and the drain 3201 of the second semiconductor device 320. In some embodiments, the connection portion connected to the gate can be referred to as a word line, and the connection portion connected to the drain can be referred to as a bit line.

[0050] Continuing to refer to FIGS. 1-3, in some embodiments, the semiconductor structure la further comprises an interconnection layer 1 disposed adjacent to the first surface A and a wiring layer 2 disposed adjacent to the second surface B. The first connection pad 110 and the second connection pad 120 are connected to the first semiconductor device 310 and the second semiconductor device 320, respectively, through the interconnection layer 1, the fourth connection pad 220 and the fifth connection pad 230 are connected to the first semiconductor device 310 and the second semiconductor device 320, respectively, through the wiring layer 2, and the third connection pad 210 is connected to the first connection portion 30 through the wiring layer. The interconnection layer 1 is composed of at least one layer of conductive interconnection line, and the wiring layer 2 is composed of at least one layer of conductive wiring layer, for example, the interconnection layer 1 can include two layers of conductive interconnection lines, each layer of conductive interconnection line is interconnected through an interlayer via, and the conductive interconnection line is interconnected with the first connection pad 110 and the second connection pad 120 through an interlayer via; the wiring layer 2 can include two or more layers of conductive wiring layers, for example, four layers of conductive wiring layers, each layer of conductive wiring layer is interconnected through an interlayer via, and the third connection pad 210, the fourth connection pad 220 and the fifth connection pad 230 are interconnected with the conductive wiring layer through an interlayer via. In some embodiments, the metal density in the wiring layer 2 is greater than the metal density in the interconnection layer 1. The metal density refers to the volume ratio or mass ratio of the metal component in a specific volume in the specific volume, that is, the metal density of the interconnection layer refers to the volume ratio or mass ratio of the metal interconnection in the interconnection layer, and the metal density of the wiring layer refers to the volume ratio or mass ratio of the metal wiring in the wiring layer. In these embodiments, by respectively disposing the interconnection layer and the wiring layer with different metal densities on the opposite sides of the memory cell region, not only can the interconnection density requirements on different surfaces be met, but also the warping of the semiconductor structure can be improved, so that the deformation between the middle portion and the edge portion of the first surface and the second surface of the semiconductor structure is reduced, and subsequent packaging integration is utilized.

[0051] In embodiments of the present disclosure, there is no obvious distinction between the interconnection layer 1, the memory cell region 3 and the wiring layer 3, and there can be overlapping regions between any two of them, and the present disclosure is not limited to the structure shown in FIGS. 1-3.

[0052] Continuing to refer to FIGS. 1-3, the semiconductor structure la further includes a second connection portion 31 connecting one end of the first semiconductor device 310 and a third connection portion 32 connecting one end of the second semiconductor device 320, and the first connection portion 30 connecting the other ends of the first semiconductor device 310 and the second semiconductor device 320. The second connection portion 31 can be a common connection portion of one end of the first semiconductor device 310, and the third connection portion 32 can be a common connection portion of one end of the second semiconductor device 320. In some embodiments, as shown in FIG. 1, the first connection portion 30 simultaneously connects the gate of the first semiconductor device 310 and the gate of the second semiconductor device 320, the second connection portion 31 connects the drain 3101 of the first semiconductor device 310, and the third connection portion 32 connects the drain 3201 of the second semiconductor device 320; in some embodiments, as shown in FIG. 2, the first connection portion 30 connects the gate 3103 of the first semiconductor device 310, the second connection portion 31 connects the drain 3101 of the first semiconductor device 310, and the third connection portion 32 connects the drain 3201 of the second semiconductor device 320; in some embodiments, as shown in FIG. 3, the first connection portion 30 simultaneously connects the drain 3101 of the first semiconductor device 310 and the drain 3201 of the second semiconductor device 320, the second connection portion 31 connects the gate 3103 of the first semiconductor device 310, and the third connection portion 32 connects the gate 3203 of the second semiconductor device 320, at this time, the first connection portion 30 is arranged more adjacent to the first surface B than the second connection portion 31 and the third connection portion 32. The connection relationship between each connection portion and each semiconductor device is not limited thereto, and in other embodiments, other connection manners can also be used. In some embodiments, the first direction is a direction parallel to the second connection portion 31 and the third connection portion 32.

[0053] The first connection portion 30, the second connection portion 31, and the third connection portion 32 are isolated from each other, that is, an insulating medium layer is arranged between each connection portion to prevent short-circuiting between each connection portion. The second connection portion 31 is connected with the first connection pad 110 to realize the connection of the first semiconductor device 310 and the first connection pad 110, and the third connection portion 32 is connected with the second connection pad 120 to realize the connection of the second semiconductor device 320 and the second connection pad 120.

[0054] In some embodiments, the second connection portion 31 is interconnected with the first connection pad 110 through an interconnection structure 34, and the third connection portion 32 is interconnected with the second connection pad 120 through an interconnection structure 35. The interconnection structure 34 and the interconnection structure 35 can be a conductive structure vertically penetrating the storage unit region 3, or can be a conductive structure interconnected through a plurality of layers of wiring.

[0055] With continued reference to FIGS. 1-3, the wiring layer 2 further includes a first wiring layer 21 disposed adjacent to the memory cell region 3, and the first connection portion 30, the second connection portion 31, and the third connection portion 32 are connected to the first wiring layer 21. The first wiring layer 21 is interconnected with each of the connection portions through interlayer vias. In some embodiments, the height of the interlayer via connecting between the first wiring layer 21 and the first connection portion 30 is greater than the height of the interlayer via connecting between the first wiring layer 21 and the second connection portion 31 or the third connection portion 32.

[0056] In some embodiments, the second connection portion 31 and the third connection portion 32 have different lengths in a direction parallel to the first surface A.

[0057] With continued reference to FIGS. 1-3, in some embodiments, a sixth connection pad 130 is further disposed on the first surface A, and a seventh connection pad 240 is further disposed on the second surface B, and the sixth connection pad 130 and the seventh connection pad 240 are connected. In some embodiments, the sixth connection pad 130 and the seventh connection pad 240 are connected through an interconnection structure 36 that penetrates the memory cell region 3. In some embodiments, the interconnection structure 36 can be a multi-layer metal wire disposed in the memory cell region 3. In some embodiments, the interconnection structure 36 is connected to the first wiring layer 21, and the seventh connection pad 240 is connected to the interconnection structure 36 via the first wiring layer 21.

[0058] With continued reference to FIGS. 1-3, in some embodiments, the memory cell region 3 further has a fourth connection portion 33 located in a region between the first semiconductor device 310 and the second semiconductor device 320. The region between the first semiconductor device 310 and the second semiconductor device 320 can be a region provided with an insulating medium layer, and the region does not contain semiconductor devices. In some embodiments, the fourth connection portion 33 is disposed more adjacent to the interconnection layer 1 than the first connection portion 30, and in other embodiments, the top surface of the fourth connection portion 33 is higher than the top surfaces of the source 3102 of the first semiconductor device 310 and the source 3202 of the second semiconductor device 320, but lower than the top surfaces of the electrode portion 3104 and the electrode portion 3204. In other embodiments, the top surface of the fourth connection portion 33 is not higher than the top surfaces of the source 3102 of the first semiconductor device 310 and the source 3202 of the second semiconductor device 320.

[0059] In some embodiments, the electrode portion 3104 of the first semiconductor device 310 and / or the electrode portion 3204 of the second semiconductor device 320 can be directly connected or interconnected by a contact plug between the source 3102 of the first semiconductor device 310 and / or the source 3202 of the second semiconductor device 320. In some embodiments, the material of the electrode portion 3104 of the first semiconductor device 310 and / or the electrode portion 3204 of the second semiconductor device 320 includes polysilicon, metal (e.g., tungsten (W), copper (Cu), aluminum (Al), etc.), metal compound (e.g., titanium nitride (TiN), tantalum nitride (TaN), etc.), or silicide (e.g., cobalt silicide, nickel silicide, etc.). The material of the source 3102 of the first semiconductor device 310 and / or the source 3202 of the second semiconductor device 320 includes polysilicon, doped single-crystal silicon, or metal silicide, etc.

[0060] In some embodiments, the fourth connection portion 33 is formed in the same process step as the electrode portion 3104 of the first semiconductor device 310 and / or the electrode portion 3204 of the second semiconductor device 320, and is isolated from each other. In some embodiments, the fourth connection portion 33 has the same material as the electrode portion 3104 and the electrode portion 3204.

[0061] In some embodiments, the fourth connection portion 33 is formed in the same process step as the source 3102 of the first semiconductor device 310 and / or the source 3202 of the second semiconductor device 320, and is isolated from each other. In some embodiments, the fourth connection portion 33 has the same material as the source 3102 and the source 3202, for example, a silicon-containing metal compound.

[0062] In some embodiments, the fourth connection portion 33 can be formed in the process step of forming the contact plug.

[0063] In some embodiments, the first surface A is further provided with an eighth connection pad 140, and the second surface B is further provided with a ninth connection pad 250, the eighth connection pad 140 and the ninth connection pad 250 are connected with the fourth connection portion 33, thereby forming a path from the first surface A to the second surface B. In some embodiments, as shown in FIG. 1 and FIG. 2, the fourth connection portion 33 is connected with the eighth connection pad 140 and the ninth connection pad 250 through the interconnection structure 39. In some embodiments, as shown in FIG. 3, since FIG. 3 adopts a different wiring design from FIG. 1 and FIG. 2, the interconnection structure 39 connecting the fourth connection portion 33 and the ninth connection pad 250 is not shown in this cross-section.

[0064] In these embodiments, by providing the fourth connection portion in the region between the first semiconductor device and the second semiconductor device, the process of forming the connection channel between the eighth connection pad 140 and the ninth connection pad 250 can be simplified, the process difficulty can be reduced, and the yield can be improved.

[0065] The first semiconductor device 310 and the second semiconductor device 320 also include a connection portion 37 and a connection portion 38, respectively, which can be located above the first semiconductor device 310 and the second semiconductor device 320, respectively, and connected to the electrode portion 3105 in the first semiconductor device 310 and the electrode portion 3205 in the second semiconductor device 320, respectively, and can be connected to or not connected to each other. In some embodiments, the fourth connection portion 33 is not connected to the connection portion 37 or the connection portion 38, and in other embodiments, the fourth connection portion is connected to the first semiconductor device 310 and the second semiconductor device 320 through the connection portion 37 and the connection portion 38, respectively, or connected to the first semiconductor device 310 and the second semiconductor device 320 through the connection portion 37 and the connection portion 38 at the same time.

[0066] In some embodiments, the semiconductor structure 1a further includes a fifth connection portion 40, as shown in FIG. 4, which is disposed more adjacent to the interconnection layer 1 relative to the fourth connection portion 40, and the fifth connection portion 40 is connected to the fourth connection portion 33 through the interconnection structure 39, i.e., the conductive channel formed between the eighth connection pad 140 and the ninth connection pad 250 includes the fourth connection portion 33 and the fifth connection portion 40. In some embodiments, the fifth connection portion 40 can be not connected to the connection portion 37 and the connection portion 38, can be connected to the connection portion 37 and the connection portion 38 individually, and can be connected to the connection portion 37 and the connection portion 38 at the same time. The fifth connection portion 40 can be located in the region between the connection portion 37 and the connection portion 38, and the fifth connection portion 40 can be prepared by the same metal process as the connection portion 37 and the connection portion 38.

[0067] In some embodiments, the wiring layer 2 further includes a second wiring layer 22, which is disposed more adjacent to the second surface B relative to the first wiring layer 21. The fourth connection portion 33 is connected to the second wiring layer 22 through the interconnection structure 39. The fourth connection portion 33 can be directly connected to the second wiring layer 22 through the interconnection structure 39, or connected to the second wiring layer 22 through the first wiring layer 21.

[0068] The first wiring layer 21 and the second wiring layer 22 can be conductive layers disposed in an insulating medium layer, and the signal transmission between the first wiring layer 21 and the second wiring layer 22 is realized through the via structure at a specific position. In some embodiments, the first wiring layer 21 and the second wiring layer 22 are formed by a metal processing process, such as a damascene process. The first wiring layer 21 and the second wiring layer 22 can be one or a combination of copper, copper alloy, tungsten, tungsten alloy, aluminum, aluminum alloy, etc.

[0069] The wiring layer 2 further includes other conductive wiring layers disposed between the second wiring layer 22 and the second surface B, and the number of the other conductive wiring layers can be 1, 2, 3, 4, or another number.

[0070] In some embodiments, the semiconductor structure 1a includes a plurality of first semiconductor devices 310 and a plurality of second semiconductor devices 320 in the memory cell region, in combination with FIGS. 1-4 and FIG. 5, the plurality of first semiconductor devices 310 form a first memory cell array 4, and the plurality of second semiconductor devices 320 form a second memory cell array 5, the first memory cell array 4 and the second memory cell array 5 are arranged in a spaced manner. The first memory cell array 4 includes a plurality of first semiconductor devices 310 arranged in a first direction and a plurality of first semiconductor devices 310 arranged in a second direction, and the second memory cell array 5 includes a plurality of second semiconductor devices 320 arranged in the first direction and a plurality of second semiconductor devices 320 arranged in the second direction. The first direction and the second direction are perpendicular to each other, and the first direction and the second direction can both be parallel to the first surface A and the second surface B.

[0071] In some embodiments, the first memory cell array 4 includes a first connection portion 30 connected to the plurality of first semiconductor devices 310, and the first connection portion 30 is connected to one end of the plurality of first semiconductor devices in the second direction. In the first direction, the plurality of first semiconductor devices 310 in the first memory cell array 4 have a second connection portion 31 connecting one end of the plurality of first semiconductor devices 310 in the first direction. Similarly, in the second memory cell array 5, one end of the plurality of second semiconductor devices 320 in the second direction is connected to another connection portion 30', and one end of the plurality of second semiconductor devices 320 in the first direction is connected to a third connection portion 32.

[0072] In some embodiments, referring to FIG. 3, the first connection portion 30 can also be connected to one end of the plurality of first semiconductor devices 310 in the first direction and one end of the plurality of second semiconductor devices 320 in the first direction at the same time, and at this time, the second connection portion 31 and the third connection portion 33 are connected to the plurality of first semiconductor devices 310 in the second direction and the plurality of second semiconductor devices 320 in the second direction, respectively. The connection relationship between the first connection portion 30, the second connection portion 31, and the third connection portion 32 and the semiconductor devices in each memory cell array is not limited to the case shown in FIG. 5.

[0073] In the above embodiments, the plurality of first semiconductor devices 310 and the plurality of second semiconductor devices 320 form connection channels extending to the second surface B through the first connection portions 30 and the third connection pads 210 and the connection portions 30' and the connection pads 210', respectively, and also form connection channels extending from the first surface A to the second surface B through the second connection portions 31 and the third connection portions 32, respectively, for example, the second connection portion 31 is connected to the first connection pad 110 in the first surface A and the fourth connection pad 220 in the second surface B, establishing a connection channel of the first semiconductor device 310 extending between the first surface A and the second surface B, the third connection portion 32 is connected to the second connection pad 120 in the first surface A and the fifth connection pad 230 in the second surface B, establishing a connection channel of the second semiconductor device 320 extending between the first surface A and the second surface B, through this design, the semiconductor devices in the memory cell array can be more flexible in layout and design, further reducing the area of the memory cell region, and providing a more compact semiconductor structure.

[0074] Continuing to refer to FIG. 5, in the first memory cell array 4, the plurality of first semiconductor devices 310 arranged in the first direction form a plurality of first sub-columns 42, the plurality of first semiconductor devices 310 in each first sub-column 42 have the same end connected to a first sub-column connection portion 43, and the second connection portion 31 is connected to the first sub-column connection portion 43 to achieve the connection between the second connection portion 31 and the first semiconductor device 310. In the second memory cell array 5, the plurality of second semiconductor devices 320 arranged in the first direction form a plurality of second sub-columns 52, the plurality of second semiconductor devices 320 in each second sub-column 52 have the same end connected to a second sub-column connection portion 53, and the third connection portion 32 is connected to the second sub-column connection portion 53 to achieve the connection between the third connection portion 32 and the second semiconductor device 320. In some embodiments, the first sub-column connection portions 43 and the second sub-column connection portions 53 are isolated from each other. The second connection portions 31 and the second connection portions 32 can be respectively arranged on the same side of the first memory cell array 4 and the second memory cell array 5, or can be respectively arranged on different sides of the first memory cell array 4 and the second memory cell array 5. The second connection portions 31 and the second connection portions 32 can be respectively integrally formed with the first sub-column connection portions 43 and the second sub-column connection portions 53, or can be connection structures formed by a separate process and connected to the first sub-column connection portions 43 and the second sub-column connection portions 53. In some embodiments, the second connection portions 31 and the second connection portions 32 can be respectively the end regions of the first sub-column connection portions 43 and the second sub-column connection portions 53.

[0075] The plurality of first semiconductor devices 310 arranged along the second direction forms a plurality of first sub-rows 44, and the same end of each first semiconductor device 310 in each first sub-row 44 is connected to a first sub-row connection part 45. In the second memory cell array 5, the plurality of second semiconductor devices 320 arranged along the second direction forms a plurality of second sub-rows 54, and the same end of each second semiconductor device 320 in each second sub-row 54 is connected to a second sub-row connection part 55. The first connection part 30 is connected to at least one of the first sub-row connection part 45 or the second sub-row connection part 55. In some embodiments, the first connection part 30 can be a structure integrally formed with the first sub-row connection part 45 and the second sub-row connection part 55, or a connection structure connected to the first sub-row connection part 45 and / or the second sub-row connection part 55 by a separate process. In some embodiments, the first connection part can be a terminal region of the first sub-row connection part 45 and / or the second sub-row connection part 55.

[0076] In some embodiments, the first memory cell array 4 includes a plurality of first sub-column connection parts 43 and a plurality of first sub-row connection parts 45, and the number of the first sub-column connection parts 43 is greater than the number of the first sub-row connection parts 45. In some embodiments, the number of the first sub-column connection parts 43 in the first memory cell array 4 can be greater than twice the number of the first sub-row connection parts 45. The second memory cell array 5 includes a plurality of second sub-column connection parts 53 and a plurality of second sub-row connection parts 55, and the number of the second sub-column connection parts 53 is greater than the number of the second sub-row connection parts 55. In some embodiments, the number of the first sub-column connection parts 43 in the first memory cell array 4 can be greater than twice the number of the first sub-row connection parts 45.

[0077] In some embodiments, at least one first sub-column connection part 43 extends in the first direction for a length less than the length that at least one first sub-row connection part 45 extends in the second direction; similarly, at least one second sub-column connection part 53 extends in the first direction for a length less than the length that at least one second sub-row connection part 55 extends in the second direction.

[0078] In some embodiments, the first memory cell array 4 and the second memory cell array 5 further include a third sub-column connection part 60 extending along the first direction and extending from the first memory cell array 4 to the second memory cell array 5, and the third sub-column connection part 60 connects the same end of the plurality of first semiconductor devices 310 and the plurality of second semiconductor devices 320 extending along the first direction. In some embodiments, the third sub-column connection part 60 is spaced apart from the first sub-column connection part 43 and the second sub-column connection part 53 along the second direction.

[0079] In some embodiments, the first surface A and / or the second surface B further has a connection pad connected with the third sub-column connection part 60, forming a transmission channel extending one end of the plurality of first semiconductor devices and the plurality of second semiconductor devices extending in the first direction to the surface of the semiconductor structure.

[0080] In some embodiments, the first sub-column connection part 43 and the second sub-column connection part 53 and the third sub-column connection part 60 are respectively connected with the same end of the first semiconductor device 310 and the second semiconductor device 320, and the first sub-row connection part 45 and the second sub-row connection part 55 are respectively connected with the same other end of the first semiconductor device 310 and the second semiconductor device 320.

[0081] In some embodiments, referring to the description of FIG. 1 to FIG. 4, the first semiconductor device 310 and the second semiconductor device 320 each include a gate and a drain, the first sub-column connection part 43 is connected with the drain of the plurality of first semiconductor devices 310 in the first direction in the first storage unit array 4, and the second sub-column connection part 53 is connected with the drain of the plurality of second semiconductor devices 320 in the first direction in the second storage unit array 5; the first sub-row connection part 45 is connected with the gate of the plurality of first semiconductor devices 310 in the second direction in the first storage unit array 4, and the second sub-row connection part 55 is connected with the gate of the plurality of second semiconductor devices 320 in the second direction in the second storage unit array 5. The third sub-column connection part 60 is connected with the drain of the plurality of first semiconductor devices 310 and the plurality of second semiconductor devices 320 in the first direction in the first storage unit array 4 and the second storage unit array 5.

[0082] In some embodiments, each sub-column connection part can also be connected with the gate of each semiconductor device, and each sub-row connection part can also be connected with the drain of each semiconductor device.

[0083] In some embodiments, continuing to refer to FIG. 5, the first surface A and the second surface B are respectively provided with a sixth connection pad 130 and a seventh connection pad 240, and the sixth connection pad 130 and the seventh connection pad 240 have an interconnection structure extending through the storage unit region 3 therebetween.

[0084] In some embodiments, referring to Figs. 1-4, each first semiconductor device 310 in the first memory cell array 4 also has an electrode portion 3104, each semiconductor device 310 also has a source, the electrode portion 3104 is connected to the source of each semiconductor device, and each semiconductor device also has an electrode portion 3105 (not shown in Fig. 5) connected to each other; each second semiconductor device 320 in the second memory cell array 5 has an electrode portion 3204, each semiconductor device 320 also has a source, the electrode portion 3204 is connected to the source of each semiconductor device, and each semiconductor device also has an electrode portion 3205 (not shown in Fig. 5) connected to each other. The connection relationship between the electrode portion 3105 and the electrode portion 3205 of each semiconductor device in the semiconductor structure shown in Fig. 5 can be referred to the description of Figs. 1-4, and will not be repeated here.

[0085] In the above embodiments, the number of the first memory cell array 4 and the second memory cell array 5 can be multiple, and each memory cell array can be a minimum aggregation unit of the semiconductor device array, for example, a MAT (Memory Array Tile).

[0086] In some embodiments, the semiconductor structure 1a further includes an interconnection layer 1 and a wiring layer 2, the interconnection layer 1 is arranged adjacent to the first surface A, the wiring layer 2 is arranged adjacent to the second surface B, and the memory cell region 3 is arranged between the interconnection layer 1 and the wiring layer 2. The interconnection layer 1 and the wiring layer 2 in the semiconductor structure 1a shown in Fig. 5 can be referred to the description of Figs. 1-4, and will not be repeated here.

[0087] The embodiments of the present disclosure further provide an integrated assembly, referring to FIG. 7, the integrated assembly comprises a first semiconductor structure 1a and a second semiconductor structure 1b. The first semiconductor structure 1a can refer to the aforementioned semiconductor structure 1a and the structure shown in FIG. 1-5. The second semiconductor structure 1b can refer to the structure shown in FIG. 6. The second semiconductor structure 1b has a first bonding surface C, which can be an exposed surface of the second semiconductor structure 1b, for bonding with the first semiconductor structure 1a. The second semiconductor structure 1b further comprises a memory cell region, which has a third semiconductor device 710 and a fourth semiconductor device 720. The third semiconductor device 710 and the fourth semiconductor device 720 can be the same semiconductor device in the same memory cell array, or can be the same semiconductor device in different memory cell arrays, for example, both are DRAM memory cells. The third semiconductor device 710 comprises a drain 7101, a source 7102, and a gate 7103 between the source and the drain. The third semiconductor device 710 further comprises an electrode part 7104 connected to the source 7102 and an electrode part 7105, which constitute two electrodes of a capacitor. Similarly, the fourth semiconductor device 720 comprises a drain 7201, a source 7202, and a gate 7203 between the drain 7201 and the source 7207. The fourth semiconductor device 720 further comprises an electrode part 7204 connected to the source 7202 and an electrode part 7205, which constitute two electrodes of a capacitor.

[0088] The second semiconductor structure 1b further comprises a connection part 71 connected to the third semiconductor device 710 and a connection part 72 connected to the fourth semiconductor device 720. In some embodiments, the connection part 71 is connected to the drain 7101 of the third semiconductor device 710 and the connection part 72 is connected to the drain 7201 of the fourth semiconductor device 720. In other embodiments, the connection part 71 is connected to the gate of the third semiconductor device 710 and the connection part 72 is connected to the gate of the fourth semiconductor device 720. The second semiconductor structure 1b further comprises a common connection part 70 connected to the third semiconductor device 710 and / or the fourth semiconductor device 720. In some embodiments, the common connection part 70 is connected to the gate of the third semiconductor device 710 and / or the fourth semiconductor device 720. In other embodiments, the common connection part 70 can also be connected to the drain of the third semiconductor device 710 and / or the fourth semiconductor device 720. The second semiconductor structure 1b further comprises a connection part 77 connected to the third semiconductor device 710 and a connection part 78 connected to the fourth semiconductor device 720. In some embodiments, the connection part 77 is connected to the electrode part 7105 of the third semiconductor device 710 and the connection part 78 is connected to the electrode part 7205 of the fourth semiconductor device 720. In some embodiments, the connection part 77 and the connection part 78 can be connected to each other.

[0089] The second semiconductor structure 1b further comprises a first bonding surface C, which can be an exposed surface of the second semiconductor structure 1b. The first bonding surface C is provided with a plurality of connection pads for bonding connection with the connection pads in the first surface A of the first semiconductor structure 1a. A connection layer 6 is further provided between the first bonding surface C and the third semiconductor device 710 and the fourth semiconductor device 720. The connection layer 6 comprises at least one metal interconnection layer for establishing connection paths between the connection pads in the first bonding surface C and the third semiconductor device 710 and the fourth semiconductor device 720. In some embodiments, the number of metal interconnection layers in the connection layer 6 is the same as the number of conductive interconnection lines in the interconnection layer 1 in the first semiconductor structure 1a, for example, both are two layers. In some embodiments, the first bonding surface C is further provided with non-electrically connected virtual connection pads. The first bonding surface C can be a surface for hybrid bonding or fusion bonding.

[0090] The connection relationship between the connection pads in the second semiconductor structure 1b and the third semiconductor device 710 and the fourth semiconductor device 720 and the connection relationship between the first semiconductor structure 1a and the second semiconductor structure 1b will be described in brief below in connection with FIG. 6 and FIG. 7.

[0091] In the second semiconductor structure 1b, the connection pad 610 is connected with one connection part 71 of the third semiconductor device 710, the connection pad 620 is connected with one connection part 72 of the fourth semiconductor device 720, and the connection pad 630 is connected with the connection part 70 for realizing the connection between one end of the third semiconductor device 710 and / or one end of the fourth semiconductor device 720 and the connection pad 630. The first bonding surface C further includes a connection pad 640, which is connected with the connection part 77 and / or the connection part 78.

[0092] After the first bonding surface C and the first surface A are bonded, the connection pad 610 and the first connection pad 110 are bonded with each other, the connection pad 620 and the second connection pad 120 are bonded with each other, and the connection pad 640 and the eighth connection pad 140 are bonded with each other, thereby forming a signal transmission channel between the first semiconductor device 310 and the third semiconductor device 710 and a signal transmission channel between the second semiconductor device 320 and the fourth semiconductor device 720 between the first semiconductor structure 1a and the second semiconductor structure 1b. In some embodiments, the signal transmission channels include a connection channel between the drain of the first semiconductor device 310 and the drain of the third semiconductor device 710, such as the channel between the connection pad 610 and the first connection pad 110, and a connection channel between the drain of the second semiconductor device 320 and the drain of the fourth semiconductor device 720, such as the channel between the connection pad 620 and the second connection pad 120. The signal transmission channels further include a channel between the connection pad 640 and the eighth connection pad 140, which can be a connection channel between the electrode part 3105 of the first semiconductor device 310 and / or the electrode part 3205 of the second semiconductor device 320 and the electrode part 7105 of the third semiconductor device 710 and / or the electrode part 7205 of the fourth semiconductor device 720.

[0093] After the first bonding surface C and the first surface A are bonded, the connection pad 630 and the sixth connection pad 130 are bonded with each other, thereby forming a signal transmission channel between the first semiconductor structure 1a and the second semiconductor structure 1b. In some embodiments, the signal transmission channels can be signal transmission channels of the gate of the third semiconductor device 710 and / or the gate of the fourth semiconductor device 720.

[0094] The integrated assembly provided by the embodiments of the present disclosure further includes a third semiconductor structure 1c bonded to the second surface B of the first semiconductor structure 1a, and the bonding between the first semiconductor structure 1a and the third semiconductor structure 1c adopts hybrid bonding or fusion bonding. Please continue to refer to FIG. 7, the third semiconductor structure 1c includes a fifth semiconductor device 810, and a wiring layer 7 is arranged above the fifth semiconductor device 810, the wiring layer 7 is arranged between the second surface B and the fifth semiconductor device 810, and is used to connect the fifth semiconductor device 810 with each connection pad on the second surface B, so as to establish a signal transmission channel between the third semiconductor structure and the first semiconductor structure and the second semiconductor structure, and realize the interconnection between each semiconductor device.

[0095] In some embodiments, the wiring layer 7 includes multiple layers of metal wires, and the number of layers of the metal wires in the wiring layer 7 is greater than the number of layers of the conductive wiring layers in the wiring layer of the first semiconductor structure.

[0096] In some embodiments, the first semiconductor device, the second semiconductor device, the third semiconductor device and the fourth semiconductor device are the same semiconductor device, for example, are all DRAM memory devices, and the fifth semiconductor device is different from the first semiconductor device, and the fifth semiconductor device can be a logic device. In some embodiments, the first semiconductor structure and the second semiconductor structure can be a memory structure composed of DRAM memory cells, NAND memory cells or other memory cells, and the first semiconductor structure and the second semiconductor structure include an array of memory cells that can use transistors as switching and selection devices, and the third semiconductor structure can be any suitable digital, analog and / or mixed-signal circuit structure for facilitating operation of the memory structure.

[0097] It should be noted that the first semiconductor structure 1a in FIG. 7 takes the first semiconductor structure shown in FIG. 1 as an example, and the first semiconductor structure can also be the first semiconductor structure shown in FIGS. 2-4, and the connection relationship with the second semiconductor structure and the third semiconductor structure is clear to those skilled in the art after reading the foregoing description.

[0098] Those skilled in the art can understand that the above-mentioned embodiments are specific embodiments for implementing the present disclosure, and in actual application, various changes can be made in form and detail without departing from the spirit and scope of the embodiments of the present disclosure. Any person skilled in the art can make various modifications and modifications without departing from the spirit and scope of the embodiments of the present disclosure, therefore the protection scope of the embodiments of the present disclosure should be subject to the range defined by the claims.

Claims

1. A semiconductor structure, comprising: opposite first and second surfaces (A, B); a first connection pad (110) and a second connection pad (120) disposed on the first surface (A); a third connection pad (210), a fourth connection pad (220) and a fifth connection pad (230) disposed on the second surface (B); a memory cell region (3) disposed between the first and second surfaces (A, B), the memory cell region (3) comprising a first semiconductor device (310) and a second semiconductor device (320) arranged along a first direction, the first connection pad (110) and the fourth connection pad (220) connecting the first semiconductor device (310), the second connection pad (120) and the fifth connection pad (230) connecting the second semiconductor device (320), the memory cell region (3) further comprising a first connection portion (30) connected to at least one of the first and second semiconductor devices (310, 320), the first connection portion (30) connecting the third connection pad (210); in a direction parallel to the first surface, a maximum width of at least one of the first and second connection pads is greater than a maximum width of at least one of the third, fourth and fifth connection pads; in the direction parallel to the first surface, a minimum spacing between the first and second connection pads is greater than a minimum spacing between the third, fourth and fifth connection pads. The semiconductor structure further comprises: an interconnection layer disposed adjacent to the first surface; a wiring layer disposed adjacent to the second surface; the first and second connection pads are connected to the first and second semiconductor devices, respectively, through the interconnection layer, the third connection pad is connected to the first connection portion through the wiring layer, the fourth and fifth connection pads are connected to the first and second semiconductor devices, respectively, through the wiring layer, a metal density of the wiring layer is greater than a metal density of the interconnection layer. The semiconductor structure further comprises a second connection portion connected to the first semiconductor device and a third connection portion connected to the second semiconductor device, the first and fourth connection pads are connected to the second connection portion, the second and fifth connection pads are connected to the third connection portion, the second and third connection portions and the first connection portion are isolated from each other, the wiring layer comprises a first wiring layer, the first, second and third connection portions are connected to the first wiring layer. A sixth connection pad is further disposed on the first surface, a seventh connection pad is further disposed on the second surface, the sixth connection pad is connected to the seventh connection pad. ​ 2. The semiconductor structure of claim 1, wherein, ​ 3. The semiconductor structure of claim 1, wherein, ​ 4. The semiconductor structure of claim 1, wherein, ​ ​ ​ ​ 5. The semiconductor structure of claim 4, wherein, ​ 6. The semiconductor structure of claim 1, wherein, ​ 7. The semiconductor structure of claim 4, wherein, The semiconductor structure further has a fourth connection portion located in the memory cell region and in a region between the first semiconductor device and the second semiconductor device, the first surface is further provided with an eighth connection pad, the second surface is further provided with a ninth connection pad, and the fourth connection portion connects the eighth connection pad and the ninth connection pad.

8. The semiconductor structure of claim 7, wherein, The wiring layer further includes a second wiring layer, and the fourth connection portion is connected to the second wiring layer.

9. A semiconductor structure, comprising: opposite first and second surfaces; a first connection pad and a second connection pad provided on the first surface; a third connection pad, a fourth connection pad, and a fifth connection pad provided on the second surface; a memory cell region provided between the first and second surfaces, including a first memory cell array and a second memory cell array arranged in an interval, the first memory cell array including a plurality of first semiconductor devices arranged in a first direction, and the second memory cell array including a plurality of second semiconductor devices arranged in the first direction; the first connection pad and the fourth connection pad connecting the first semiconductor devices, the second connection pad and the fifth connection pad connecting the second semiconductor devices, the memory cell region further including a first connection portion connected to at least one of the first semiconductor devices and the second semiconductor devices, and the third connection pad connecting the first connection portion.

10. The semiconductor structure of claim 9, wherein, The first memory cell array includes a second connection portion, the second memory cell array includes a third connection portion, the second connection portion connects the first semiconductor devices, the third connection portion connects the second semiconductor devices, the first connection pad and the fourth connection pad connect the second connection portion, and the second connection pad and the fifth connection pad connect the third connection portion.

11. The semiconductor structure of claim 10, wherein, The first semiconductor devices arranged along the first direction form a plurality of first sub-columns, each of the first sub-columns comprising a first sub-column connection portion connecting a plurality of the first semiconductor devices in the first direction, the second semiconductor devices arranged along the first direction form a plurality of second sub-columns, each of the second sub-columns comprising a second sub-column connection portion connecting a plurality of the second semiconductor devices in the first direction, the first connection pad and the fourth connection pad are connected to the first sub-column connection portion through the second connection portion, the second connection pad and the fifth connection pad are connected to the second sub-column connection portion through the third connection portion, the first sub-column connection portion and the second sub-column connection portion are arranged in an extending manner along the first direction, the first sub-column connection portion and the second sub-column connection portion are isolated from each other, the first memory cell array further comprises a plurality of the first semiconductor devices arranged along a second direction, the second memory cell array further comprises a plurality of the second semiconductor devices arranged along the second direction, the plurality of the first semiconductor devices arranged along the second direction form a plurality of first sub-rows, the plurality of the second semiconductor devices arranged along the second direction form a plurality of second sub-rows, each of the first sub-rows comprises a first sub-row connection portion connecting a plurality of the first semiconductor devices in the second direction, each of the second sub-rows comprises a second sub-row connection portion connecting a plurality of the second semiconductor devices in the second direction, the first sub-row connection portion and the second sub-row connection portion are arranged in an extending manner along the second direction, and the first connection portion is connected to at least one of the first sub-row connection portion and the second sub-row connection portion.

12. The semiconductor structure of claim 11, wherein, The first memory cell array comprises a plurality of first sub-column connection portions and a plurality of first sub-row connection portions, the number of the first sub-column connection portions is greater than the number of the first sub-row connection portions, the second memory cell array comprises a plurality of second sub-column connection portions and a plurality of second sub-row connection portions, the number of the second sub-column connection portions is greater than the number of the second sub-row connection portions.

13. The semiconductor structure of claim 11, wherein, The memory cell region further comprises a third sub-column connection portion extending along the first direction, the third sub-column connection portion extends from the first memory cell array to the second memory cell array, and the third sub-column connection portion connects a plurality of the first semiconductor devices and a plurality of the second semiconductor devices extending along the first direction.

14. The semiconductor structure of claim 13, wherein, The first semiconductor devices and the second semiconductor devices each comprise a gate and a drain, the first sub-row connection portion connects the gate of the first semiconductor device, the second sub-row connection portion connects the gate of the second semiconductor device, the first sub-column connection portion connects the drain of the first semiconductor device, the second sub-column connection portion connects the drain of the second semiconductor device, and the third sub-column connection portion connects the drain of the first semiconductor device and the drain of the second semiconductor device.

15. The semiconductor structure of claim 9, wherein, The first surface is further provided with a sixth connection pad, the second surface is further provided with a seventh connection pad, and the sixth connection pad is connected to the seventh connection pad.

16. An integrated assembly comprising: A first semiconductor structure includes a first surface provided with a first connection pad and a second connection pad, and a memory cell region disposed below the first surface, the memory cell region including a first semiconductor device and a second semiconductor device, the first connection pad connecting the first semiconductor device, and the second connection pad connecting the second semiconductor device, and a first connection portion between the first semiconductor device and the second semiconductor device; A second semiconductor structure includes a first bonding surface bonded to the first surface of the first semiconductor structure, and a third semiconductor device and a fourth semiconductor device, the third semiconductor device and the first semiconductor device being connected by the first bonding surface and the first connection pad, and the fourth semiconductor device and the second semiconductor device being connected by the first bonding surface and the second connection pad, and a common connection portion connecting at least one of the third semiconductor device or the fourth semiconductor device. The first semiconductor structure further includes a second surface provided with a third connection pad, a fourth connection pad, and a fifth connection pad and a sixth connection pad, the third connection pad connecting the first connection portion, the fourth connection pad connecting the first connection pad, the fifth connection pad connecting the second connection pad, and the sixth connection pad connecting the common connection portion.

17. The assembly of claim 16, wherein, The first semiconductor structure further includes an interconnection layer between the first surface and the second surface, and disposed adjacent to the first surface, and the second semiconductor structure further includes a connection layer disposed adjacent to the first bonding surface, and the third semiconductor device and the fourth semiconductor device are interconnected with the first semiconductor device and the second semiconductor device by the connection layer.

18. The assembly of claim 16, wherein, The first semiconductor structure further includes a wiring layer disposed adjacent to the second surface, and the third semiconductor structure includes a routing layer disposed adjacent to the second surface, and the first semiconductor device, the second semiconductor device, the third semiconductor device, and the fourth semiconductor device are interconnected with the fifth semiconductor device by the routing layer.

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