Semiconductor device, method for manufacturing semiconductor device, and electronic device

Abstract

The present application relates to the technical field of semiconductors. Provided are a semiconductor device, an electronic device, and a method for manufacturing a semiconductor device. The semiconductor device comprises a P-type transistor, the P-type transistor comprising a first electrode, a second electrode and a channel, and the first electrode comprising boron. In addition, the semiconductor device further comprises a first film layer and a barrier layer. The first film layer is located on the first electrode, the first film layer comprising boron, and the boron content of the first film layer being greater than the boron content of the first electrode. The barrier layer is stacked between the first electrode and the first film layer, and the barrier layer is used for suppressing diffusion of boron in the first film layer into a substrate, for example, the barrier layer is used for suppressing diffusion of boron in the first film layer into the channel of the P-type transistor. In this way, the hole mobility of channel layers can be improved, thus improving driving circuits comprising P-type transistors.

Description

Semiconductor device, method for manufacturing semiconductor device, and electronic device

[0001] The present application claims priority to the Chinese patent application No. 202411279253.7, filed on September 11, 2024, and entitled "Semiconductor device, method for manufacturing semiconductor device, and electronic device", the content of which is incorporated herein by reference in its entirety. TECHNICAL FIELD

[0002] The present application relates to the technical field of semiconductor technology, and in particular to a semiconductor device, a semiconductor device packaging structure, an electronic device, and a method for manufacturing a semiconductor device. BACKGROUND

[0003] With the development of integrated circuits, for example, embedded source-drain epitaxial silicon germanium is a core technology in the current 45nm and below process.

[0004] Embedded source-drain epitaxial silicon germanium can be understood as opening a trench in a substrate, epitaxially growing silicon germanium in the trench, and forming source and drain. This technology uses the stress generated by the lattice mismatch between germanium Ge and silicon Si to improve hole mobility. Since the lattice constant of Ge is about 4% larger than that of Si, it will produce a lateral compressive stress on the channel, reducing the Si lattice constant in the channel and reducing the effective mass of holes, thereby achieving the purpose of improving the mobility of holes.

[0005] However, when manufacturing a transistor using this technology, some substances will diffuse into the channel, causing short channel effects and affecting device performance. SUMMARY

[0006] The present application provides a semiconductor device, a semiconductor device packaging structure, an electronic device comprising the semiconductor device packaging structure, and a method for manufacturing a semiconductor device. The main purpose is to suppress the short channel effect of P-type transistors, improve carrier mobility, and improve device performance.

[0007] To achieve the above purpose, the embodiments of the present application adopt the following technical solutions:

[0008] In a first aspect, the present application provides a semiconductor device, for example, the semiconductor device can include a storage circuit, a logic circuit, or a digital circuit, etc.

[0009] The semiconductor device comprises a substrate and a P-type transistor, the P-type transistor comprising a first electrode, a second electrode, a channel and a gate electrode, the first electrode, the second electrode and the channel of the P-type transistor being in the substrate, the channel being between the first electrode and the second electrode, the gate electrode being on the channel, the first electrode comprising boron; in addition, the semiconductor device further comprises a first film layer and a barrier layer, the first film layer being on the first electrode, the first film layer comprising boron, the content of boron in the first film layer being greater than the content of boron in the first electrode; the barrier layer being stacked between the first electrode and the first film layer, the surface of the substrate comprising a first region located at the periphery of the first electrode, the first region can correspond to the channel of the P-type transistor, at least part of the first region being covered by the barrier layer, the barrier layer being used to inhibit the diffusion of boron in the first film layer into the substrate, for example, the barrier layer is used to inhibit the diffusion of boron in the first film layer into the channel of the P-type transistor.

[0010] In the semiconductor device provided by the application, the first film layer is on the first electrode of the P-type transistor, and the first film layer has a high content of boron. The first film layer can be used to reduce the resistance in the circuit and optimize the performance of the device. However, in some process preparation processes, after the first film layer with high-concentration boron is prepared, the boron in the first film layer may diffuse into the channel of the P-type transistor, causing a short channel effect. In the application, the barrier layer is added between the first film layer and the first electrode, and at least part of the first region at the periphery of the first electrode is covered by the barrier layer, that is, at least part of the channel surrounding the periphery of the first electrode is covered by the barrier layer. The barrier layer can be used to inhibit the diffusion of boron in the first film layer into the channel, so that the short channel effect can be inhibited, the hole mobility can be improved, and the performance of the device can be optimized.

[0011] In an implementable manner, the first film layer and the first electrode further comprise silicon, and the barrier layer comprises pure silicon; or the barrier layer comprises silicon and boron, the content of boron in the barrier layer is less than the content of boron in the first film layer, and the content of silicon in the barrier layer is greater than the content of silicon in the first film layer; and the content of boron in the barrier layer is less than the content of boron in the first electrode, and the content of silicon in the barrier layer is greater than the content of silicon in the first electrode.

[0012] In some structures, pure silicon is used as the barrier layer. High-concentration silicon can be used to inhibit the diffusion of high-concentration boron in the first film layer into the channel of the transistor. In other structures, a barrier layer containing silicon and boron is used. Because the content of silicon in the barrier layer is greater than the content of boron in the first film layer and the first electrode, and the content of boron in the barrier layer is less than the content of boron in the first film layer and the first electrode, the diffusion of high-concentration boron in the first film layer into the channel of the transistor can be effectively inhibited.

[0013] In addition, the barrier layer is prepared by using pure silicon or a material containing silicon and boron. The process is easy to implement, compatible with the preparation process of the P-type transistor, does not increase the process, and has a relatively low manufacturing cost.

[0014] In an implementation, the first electrode includes: an embedded portion in the substrate, and a protruding portion protruding from the surface of the substrate, the first region surrounding the protruding portion; the circumferential surface of the protruding portion and the surface away from the substrate are covered by the barrier layer; the barrier layer on the circumferential surface of the protruding portion extends to the first region and covers the first region.

[0015] Since the barrier layer on the circumferential surface of the protruding portion extends to the first region on the surface of the substrate, the first region corresponds to the channel of the transistor, that is, part of the channel in the substrate is covered by the barrier layer, so that the diffusion of high-concentration boron in the first film layer into the channel can be inhibited.

[0016] In an implementation, the circumferential surface of the protruding portion near the gate is inclined away from the gate.

[0017] In this way, the first electrode can be prepared by epitaxial growth technology, and the preparation process is simple and easy to implement.

[0018] In an implementation, the thickness dimension of the barrier layer on the first region on the surface of the substrate is greater than the thickness dimension of the barrier layer on the first electrode.

[0019] In the implementation structure, the thickness dimension of the barrier layer on the surface of the substrate is greater than the thickness dimension of the barrier layer on the first electrode, so that the diffusion of boron in the first film layer into the channel can be inhibited.

[0020] In an implementation, the first film layer and the first region are separated by the barrier layer.

[0021] It can be understood that the first film layer stacked on the barrier layer does not contact the first region of the substrate.

[0022] For example, when the first film layer is prepared, the first film layer is prepared on the surface of the barrier layer by using a deposition process, and the first film layer cannot extend to the surface of the substrate, so as to avoid the diffusion of boron in the first film layer into the channel in the substrate.

[0023] In an implementation, the first electrode further includes silicon and germanium, and the first electrode includes: a first sub-electrode layer and a second sub-electrode layer stacked, the first sub-electrode layer being closer to the channel than the second sub-electrode layer; the content of germanium in the second sub-electrode layer is greater than the content of germanium in the first sub-electrode layer; and the content of boron in the second sub-electrode layer is greater than the content of boron in the first sub-electrode layer.

[0024] The first sub-electrode layer can be considered as a buffer layer, and the second sub-electrode layer can be considered as a stress applying layer. By the buffer layer, the stress value applied to the channel by the second sub-electrode layer can be increased, and the drive current of the P-type transistor is further improved.

[0025] In an implementable manner, the barrier layer comprises silicon and boron, the boron content in the barrier layer is less than the boron content in the second sub-electrode layer, and the silicon content in the barrier layer is greater than the silicon content in the second sub-electrode layer.

[0026] When the barrier layer comprises silicon and boron, by the boron content in the barrier layer being less than the boron content in the second sub-electrode layer and the silicon content in the barrier layer being greater than the silicon content in the second sub-electrode layer, the barrier layer can have the effect of inhibiting the diffusion of boron in the first film layer to the channel.

[0027] In an implementable manner, in the direction from the bottom surface to the top surface of the first pole, the radial dimension of the first pole first increases and then decreases.

[0028] In some implementable processes, a trench can be formed in the substrate, in the direction from the bottom surface to the opening of the trench, the radial dimension of the trench first increases and then decreases, such a trench structure can be referred to as a sigma trench, and the first pole is filled in the sigma trench, so that the first pole comprising germanium silicon of the structure can apply stress to the channel.

[0029] In an implementable manner, the semiconductor device further comprises: a first gate side wall and a second gate side wall, the first gate side wall and the second gate side wall are sequentially stacked on the peripheral side surface of the gate; the peripheral side surface of the first film layer and the peripheral side surface of the barrier layer both contact the second gate side wall.

[0030] In an example, the materials of the first gate side wall and the second gate side wall can be the same or different.

[0031] In a second aspect, the application also provides a semiconductor device packaging structure, which comprises a substrate and the semiconductor device in any of the above-mentioned implementable manners, and the semiconductor device is arranged on the substrate.

[0032] In the semiconductor device packaging structure provided by the application, the semiconductor device integrated on the substrate can inhibit the diffusion of boron in the first film layer to the channel by adding the barrier layer between the first film layer and the first pole, and at least part of the first region in the periphery of the first pole is covered by the barrier layer, that is, the channel is covered by the barrier layer. By using the barrier layer, the diffusion of boron in the first film layer to the channel can be inhibited, so that the short channel effect can be inhibited, the hole mobility can be improved, the device performance can be optimized, and the use performance of the semiconductor device packaging structure can be improved.

[0033] In a third aspect, the application also provides an electronic device, which comprises a circuit board and the semiconductor device packaging structure in any of the above-mentioned implementable manners, and the semiconductor device packaging structure is arranged on the circuit board.

[0034] The electronic device provided in the present application contains the semiconductor device in any of the above-mentioned implementation manners, and includes a barrier layer arranged between the first film layer and the first electrode. The barrier layer can inhibit the diffusion of boron in the first film layer to the channel, so that the short channel effect can be inhibited, the hole mobility can be improved, and the device performance can be optimized.

[0035] In a fourth aspect, the present application also provides a preparation method of a semiconductor device, which includes:

[0036] A trench is formed in an electrode region of the substrate, and the electrode region is used to form the first electrode of the P-type transistor.

[0037] The first electrode of the P-type transistor is formed in the trench, and the first electrode includes boron.

[0038] A barrier layer is prepared on the first electrode, and at least part of the region of the substrate surface and located at the periphery of the first electrode is covered by the barrier layer.

[0039] A first film layer is prepared on the barrier layer, the first film layer includes boron, the content of boron in the first film layer is greater than that in the first electrode, and the barrier layer is used to inhibit the diffusion of boron in the first film layer to the channel of the P-type transistor.

[0040] When the P-type transistor in the semiconductor device is prepared by using the method, the barrier layer is prepared before the first film layer containing high content of boron is prepared, and the region of the corresponding channel of the substrate is covered by the barrier layer. Therefore, after the first film layer is prepared, the high content of boron in the first film layer will not diffuse to the channel, and the short channel effect in the channel can be inhibited.

[0041] In an implementable manner, before the trench is formed in the electrode region of the substrate used to form the first electrode of the P-type transistor, the preparation method further includes:

[0042] The first mask layer includes silicon oxide, and the surface of the electrode region of the substrate is covered by the first mask layer. The second mask layer is located on the side of the first mask layer away from the substrate.

[0043] After the trench is formed in the electrode region of the substrate used to form the first electrode of the P-type transistor, the preparation method further includes:

[0044] The part of the first mask layer close to the trench is cleaned away, so that the surface of the substrate close to the trench is exposed.

[0045] For example, after the trench is formed, the inner wall surface of the trench will generate silicon oxide due to natural oxidation, and then the silicon oxide in the trench needs to be cleaned. In the cleaning process, the part of the first mask layer of the silicon oxide layer will also be cleaned away.

[0046] In an implementable manner, the cleaning of the inner wall surface of the trench includes:

[0047] The inner wall of the trench is cleaned by using a gas containing ammonia and hydrogen fluoride, so that the silicon oxide on the inner wall of the trench is cleaned, and the silicon oxide close to the trench of the first mask layer is cleaned.

[0048] In an implementable manner, the first electrode of the P-type transistor formed in the trench comprises:

[0049] A first sub-electrode layer is prepared in the trench;

[0050] A second sub-electrode layer is prepared on the first sub-electrode layer, the content of germanium in the second sub-electrode layer is greater than that in the first sub-electrode layer, and the content of boron in the second sub-electrode layer is greater than that in the first sub-electrode layer.

[0051] The first sub-electrode layer can be regarded as a buffer layer, and the second sub-electrode layer can be regarded as a stress applying layer. The buffer layer can increase the stress value applied to the channel by the second sub-electrode layer, further improve the carrier mobility of the channel, and improve the drive current of the P-type transistor. BRIEF DESCRIPTION OF DRAWINGS

[0052] FIG. 1 is a partial structure diagram of an electronic device according to an embodiment of the present application;

[0053] FIG. 2 is a partial structure diagram of a semiconductor device according to an embodiment of the present application;

[0054] FIG. 3 is a partial structure diagram of a P-type transistor in a semiconductor device according to an embodiment of the present application;

[0055] FIG. 4 is a top view of a first electrode of a P-type transistor in a semiconductor device according to an embodiment of the present application;

[0056] FIGS. 5 to 14 are process structure diagrams corresponding to partial steps in a preparation process of a semiconductor device according to an embodiment of the present application;

[0057] FIG. 15 is a structure diagram of a semiconductor device according to an embodiment of the present application;

[0058] FIG. 16 is a structure diagram of a semiconductor device according to an embodiment of the present application;

[0059] FIG. 17 is a structure diagram of a trench for filling a first electrode of a P-type transistor according to an embodiment of the present application;

[0060] FIG. 18 is a flow chart of a preparation method of a semiconductor device according to an embodiment of the present application.

[0061] Reference signs: 100-circuit board; 200-substrate; 300-semiconductor device; 400-electric connection structure; 11-first electrode; 12-second electrode; 13-channel; 14-gate; 15-first film layer; 16-barrier layer; 17-first gate sidewall; 18-second gate sidewall; 111-first sub-electrode layer; 112-second sub-electrode layer; 11A-embedded part; 11B-protruding part; 20-silicon oxide layer; 21-polysilicon hard mask layer; 22-hard mask silicon oxide layer; 23-hard mask silicon nitride layer; 24-trench; 25-notch. DETAILED DESCRIPTION

[0062] The following describes various embodiments of the present application in combination with the accompanying drawings in the embodiments of the present application.

[0063] The technical solution of the present application can be applied to various electronic devices using semiconductor devices. For example, the electronic device in the embodiments of the present application can be a (mobile phone), a tablet computer (pad), a notebook computer, a smart home, a smart wearable device (for example, a smart watch, a smart bracelet, smart glasses, a smart helmet), a virtual reality (VR) electronic device, an augmented reality (AR) electronic device, and the like. The electronic device can also be a handheld device with wireless communication function, a computing device, or other processing device connected to a wireless modem, a vehicle-mounted device, an electronic device in a 5G network or an electronic device in a future evolved public land mobile network (PLMN), and the like. The embodiments of the present application are not limited thereto.

[0064] As shown in FIG. 1, the above-mentioned electronic device can include a circuit board 100, such as a printed circuit board (PCB), on which a semiconductor device packaging structure is arranged. The semiconductor device packaging structure can be electrically connected to the circuit board 100 through an electric connection structure 400, so that the semiconductor device packaging structure can realize signal interconnection with other chips or other electronic modules on the circuit board 100.

[0065] In alternative embodiments, the electric connection structure 400 can include a plurality of solder balls, such as a ball grid array (BGA), or a plurality of metal pillars.

[0066] In some examples, as shown in FIG. 1, the semiconductor device package structure includes a plurality of semiconductor devices 300, which are disposed on a substrate 200, such as a package substrate. The substrate 200 is disposed on a circuit board 100 through an electrical connection structure 400.

[0067] The semiconductor device 300 shown in FIG. 1 can be one chip or a plurality of chips stacked in three dimensions.

[0068] In some implementations, the semiconductor device 300 can include a memory, a logic circuit, a system on chip (SOC), and can also include an analog chip, a digital chip, etc.

[0069] In the semiconductor device shown above, a plurality of transistors can be included. For example, when the semiconductor device is a memory, the memory cell of the memory can be a 6T memory cell, or can be a 4T2C memory cell.

[0070] The plurality of transistors in the semiconductor device can include a plurality of electrically connected P-type transistors, or a plurality of electrically connected N-type transistors, or a plurality of electrically connected P-type transistors and N-type transistors.

[0071] For example, in a P-type transistor, the application of compressive stress along the channel length direction can cause the lattice constant of silicon in the channel to decrease, the hole effective mass to decrease, and thus the hole mobility to increase, thereby increasing the drive current of the P-type transistor and optimizing the circuit performance.

[0072] However, when a P-type transistor is prepared, substances in some film layer structures can diffuse into the channel of the P-type transistor, thereby causing a short channel effect and deteriorating the performance of the P-type transistor.

[0073] Embodiments of the present application provide some implementation manners in which compressive stress can be applied to the channel of a P-type transistor and some substances can be inhibited from diffusing into the channel. The specific implementation manners are described below.

[0074] FIG. 2 is a schematic diagram of a partial structure of a semiconductor device according to an embodiment of the present application. The semiconductor device includes a substrate and a plurality of transistors. In the example shown in FIG. 2, one P-type transistor (PMOS) and two N-type transistors (NMOS) are shown. FIG. 2 is one example, and of course more transistors can be included.

[0075] As shown in FIG. 2, the P-type transistor according to the example of the present application includes a first electrode 11, a second electrode 12, and a channel 13, and a gate electrode 14. For example, one of the first electrode 11 and the second electrode 12 can be a drain electrode, and the other can be a source electrode.

[0076] The first electrode 11, the second electrode 12 and the channel 13 are located in the substrate, the channel 13 is located between the first electrode 11 and the second electrode 12, and the gate 14 is located on the channel 13. For example, the gate 14 can be made by epitaxial growth technology.

[0077] In the P-type transistor of the examples of the present application, the first electrode 11 can include boron B, for example, can include silicon Si, germanium Ge and boron B, such as a SiGe material containing boron B. The second electrode 12 can also include silicon Si, germanium Ge and boron B, such as a SiGe material containing boron B.

[0078] Since the lattice constant of germanium Ge is larger than that of silicon Si by about 4%, it will generate a lateral compressive stress F on the channel 13 as shown in FIG. 2, which will reduce the Si lattice constant in the channel 13 and reduce the effective mass of holes, thereby achieving the purpose of improving the mobility of holes.

[0079] FIG. 3 shows a detailed structure diagram of the first electrode 11, the gate 14 and other film layers in the P-type transistor. At least part of the first electrode 11 is located in the substrate, and the P-type transistor further includes a first film layer 15 and a barrier layer 16, the first film layer 15 is located on the first electrode 11, and the barrier layer 16 is stacked between the first electrode 11 and the first film layer 15.

[0080] The first film layer 15 includes boron B, for example, includes silicon Si and boron B, the content of boron B in the first film layer 15 is greater than that in the first electrode 11, and the first film layer 15 is electrically coupled with the first electrode 11. Due to the higher content (or concentration) of boron B in the first film layer 15, the resistance of the circuit in which the P-type transistor is located can be effectively reduced by using the first film layer 15, and the performance of the circuit can be optimized.

[0081] In some examples of the present application, the content of boron B in the first film layer 15 is greater than that in the first electrode 11, which can be understood as follows: in the first film layer, the content of boron B = the number of boron B atoms / (the number of boron B atoms + the number of silicon Si atoms); in the first electrode, the content of boron B = the number of boron B atoms / (the number of boron B atoms + the number of silicon Si atoms + the number of germanium Ge atoms).

[0082] In some examples, the content of boron B in the first film layer 15 is greater than that in the first electrode 11, which can be understood as follows: the proportion of boron B atoms in the first film layer 15 is greater than that in the first electrode 11; or the concentration of boron B in the first film layer 15 is greater than that in the first electrode 11.

[0083] As shown in FIG. 3, the approximate range of the channel 13 of the P-type transistor is simply shown in the substrate by a dashed line frame. Of course, FIG. 3 is an example.

[0084] As shown in FIG. 3 and FIG. 4, FIG. 4 shows a top view of the first pole 11 and the first region in FIG. 3. The surface of the substrate includes the first region located at the periphery of the first pole 11, which can be understood as the first region circumferentially surrounds the first pole 11, see FIG. 3, and in the substrate, the position corresponding to the first region is the channel 13 of the P-type transistor. In the example of the present application, at least part of the first region is covered by the blocking layer 16.

[0085] At least part of the first region is covered by the blocking layer 16, which can be understood as part or all of the first region is covered by the blocking layer 16.

[0086] In addition, the blocking layer 16 is used to inhibit the diffusion of boron B in the first film layer 15 into the substrate, for example, the blocking layer 16 is used to inhibit the diffusion of boron B in the first film layer 15 into the channel 13 of the P-type transistor.

[0087] The blocking layer 16 can inhibit the diffusion of boron B in the first film layer 15 into the channel 13 of the P-type transistor, which can be understood as: in some structures, the blocking layer 16 can completely inhibit the diffusion of boron B in the first film layer 15 into the channel 13 of the P-type transistor, and there is basically no boron B in the channel 13; or, in other structures, the blocking layer 16 can have a strong inhibitory effect, and there will be a small amount of boron B in the channel 13, which basically will not cause short channel effect. The following explains how to make the structure shown in FIG. 3 and how to use the blocking layer 16 to inhibit the diffusion of boron B in the first film layer 15 into the substrate by combining with the drawings.

[0088] As shown in FIG. 5, the gate 14 and the first gate side wall 17 are made on the substrate, and the first gate side wall 17 is formed on the circumferential side of the gate 14.

[0089] For example, the substrate is a silicon substrate, which will naturally oxidize into a silicon oxide layer 20 on the surface of the substrate.

[0090] In some optional materials, the gate 14 can be selected from conductive materials, for example, metal materials. In optional embodiments, it can be one or more of TiN (titanium nitride), Ti (titanium), Au (gold), W (tungsten), Mo (molybdenum), In-Ti-O (ITO, indium tin oxide), Al (aluminum), Cu (copper), Ru (ruthenium), Ag (silver) and the like.

[0091] In some optional materials, the first gate side wall 17 can be selected from dielectric materials, for example, dielectric materials with high dielectric constant. For example, it can be silicon nitride.

[0092] The first gate side wall 17 can have a protective effect, which can control the distance from the channel when ion implantation is formed in the substrate, thereby inhibiting short channel effect.

[0093] In some alternative processes, as shown in FIG. 5, a polysilicon hard mask layer 21 having a certain thickness can be formed on top of the gate 14, which can protect the gate 14 as a sacrificial layer in subsequent processes.

[0094] As shown in FIG. 6, a hard mask silicon oxide layer 22 and a hard mask silicon nitride layer 23 are formed. For example, the hard mask silicon oxide layer 22 and the hard mask silicon nitride layer 23 can be formed by epitaxial growth.

[0095] The hard mask silicon oxide layer 22 can serve as a buffer layer for the hard mask silicon nitride layer 23 and the first sidewall 17, and can facilitate the formation of the hard mask silicon nitride layer 23. For example, the hard mask silicon oxide layer 22 can have a thickness of 1 nm to 6 nm, which can be formed by CVD.

[0096] In some processes, the hard mask silicon nitride layer 23 can have a thickness of 5 nm to 30 nm, which can be formed by furnace tube deposition.

[0097] As shown in FIG. 6, the silicon oxide layer on the surface of the substrate includes the naturally oxidized silicon oxide layer 20 shown in FIG. 5, and the hard mask silicon oxide layer 22 formed in FIG. 6.

[0098] As shown in FIG. 7, a trench 24 is formed in the substrate for forming a source / drain region of a P-type transistor. For example, the trench 24 can be formed by dry etching or wet etching.

[0099] For example, the dry etching can use at least one of chlorine, hydrogen chloride, hydrogen bromide, carbon tetrafluoride, nitrogen trifluoride, etc. The etching time can be 50 s to 150 s.

[0100] For another example, the wet etching can use tetramethylammonium hydroxide. The etching time can be 100 s to 400 s.

[0101] As shown in FIG. 7, when the trench 24 is etched, the hard mask silicon nitride layer 23 and the silicon oxide layer (including the hard mask silicon oxide layer 22 and the naturally oxidized silicon oxide layer 20) on the surface of the substrate can be etched away.

[0102] As shown in FIG. 8, after the trench 24 is etched as shown in FIG. 7, the inner wall surface of the trench 24 can be oxidized to form silicon oxide when the substrate is a silicon substrate, for example.

[0103] In order to improve the performance of the P-type transistor, the inner wall surface of the trench 24 can be cleaned to remove the silicon oxide adhered to the wall surface of the trench 24 before the source / drain electrode is formed in the trench 24.

[0104] As shown in FIG. 9, the inner wall surface of the trench 24 is cleaned.

[0105] In some alternative processes, a gas containing hydrogen fluoride (HF) and ammonia (NH3) can be used to remove the silicon oxide on the inner wall of the trench 24.

[0106] As shown in Fig. 9, when the silicon oxide on the inner wall of the trench 24 is removed, the side of the portion of the silicon oxide layer in contact with the substrate is exposed, and further, the silicon oxide layer at the bottom of the hard mask silicon nitride layer 23 and in contact with the substrate is also removed, so that a gap 25 shown in Fig. 9 is formed. The formation of the gap 25 exposes part of the substrate surface.

[0107] The exposed substrate can be the channel 13 of the P-type transistor, and if the method shown in Fig. 10 is used to continue to form the source and drain of the P-type transistor and the first film layer 15, some technical problems can occur.

[0108] As shown in Fig. 10, the first electrode 11 of the P-type transistor is formed in the trench 24, and the first film layer 15 is formed on the first electrode 11.

[0109] Since the first film layer 15 has a high content of boron B, the high content of boron B can diffuse into the substrate through the gap 25, such as into the channel 13 of the P-type transistor, causing a short channel effect and deteriorating the performance of the transistor.

[0110] In order to prevent the high content of boron B from diffusing into the substrate through the gap 25, the present application can use the method shown in Figs. 11 and 12.

[0111] As shown in Fig. 11, the first electrode 11 of the P-type transistor is formed in the trench 24, and the barrier layer 16 is formed on the first electrode 11.

[0112] The barrier layer 16 covers the surface of the substrate, that is, at least the exposed area of the substrate located at the periphery of the first electrode 11 (i.e., the first area in Figs. 3 and 4 described above) is covered by the barrier layer 16.

[0113] As shown in Fig. 12, the first film layer 15 is formed on the barrier layer 16.

[0114] Since the barrier layer 16 is formed before the first film layer 15 is formed, and the barrier layer 16 covers some areas of the substrate surface that are exposed, the high content of boron B in the first film layer 15 will not substantially diffuse into the substrate, and will not diffuse into the channel of the P-type transistor. Therefore, when the P-type transistor is formed according to the present application, as shown in Fig. 9, the channel of the substrate is not exposed due to the existence of the gap 25, and the boron B in the first film layer 15 does not diffuse into the channel of the P-type transistor.

[0115] In some processes, the polysilicon hard mask layer 21, the hard mask silicon oxide layer 22, and the hard mask silicon nitride layer 23 are removed to form a structure as shown in Fig. 13.

[0116] For example, the wet etching can adopt phosphoric acid treatment for 200s-500s to remove the hard mask silicon nitride layer 23 and the polysilicon hard mask layer 21; the wet etching adopts HF to remove the hard mask silicon oxide layer 22.

[0117] As shown in FIG. 14, the second gate sidewall 18 is formed on the side of the first gate sidewall 17.

[0118] In some optional materials, the second gate sidewall 18 can be selected from a dielectric material, such as a dielectric material with high dielectric constant. For example, the dielectric material can be silicon nitride.

[0119] The materials of the first gate sidewall 17 and the second gate sidewall 18 can be the same or different.

[0120] In the examples of the present application, the barrier layer 16 can be selected from a variety of materials.

[0121] For example, the barrier layer 16 can be selected from a metal. The barrier layer 16 made of metal can achieve electrical coupling between the first electrode 11 and the first film layer 15.

[0122] For another example, the barrier layer 16 is pure silicon (Pure Si). Pure silicon can be understood as the content of silicon being substantially close to 100%, or at least being more than 98%. In some structures, the barrier layer 16 covering the first electrode 11 can be relatively thin, so as to achieve electrical coupling between the first electrode 11 and the first film layer 15. For example, the thickness of the barrier layer 16 covering the first electrode 11 can be more than 2nm.

[0123] For another example, the barrier layer 16 includes silicon Si and boron B. The barrier layer 16 including silicon Si and boron B has electrical conductivity, and can achieve electrical coupling between the first electrode 11 and the first film layer 15.

[0124] When the barrier layer 16 includes silicon Si and boron B, the content of boron in the barrier layer 16 is less than the content of boron in the first film layer 15, and the content of silicon in the barrier layer 16 is greater than the content of silicon in the first film layer 15; and the content of boron in the barrier layer 16 is less than the content of boron in the first electrode 11, and the content of silicon in the barrier layer 16 is greater than the content of silicon in the first electrode 11.

[0125] In the example of the present application, in the barrier layer 16, the boron content = the number of boron atoms / (the number of boron atoms + the number of silicon atoms), the silicon content = the number of silicon atoms / (the number of boron atoms + the number of silicon atoms); in the first film layer, the boron content = the number of boron atoms / (the number of boron atoms + the number of silicon atoms), the silicon content = the number of silicon atoms / (the number of boron atoms + the number of silicon atoms); in the first electrode, the boron content = the number of boron atoms / (the number of boron atoms + the number of silicon atoms + the number of germanium atoms), the silicon content = the number of silicon atoms / (the number of boron atoms + the number of silicon atoms + the number of germanium atoms).

[0126] In some examples, the boron content in the barrier layer 16 is less than the boron content in the first film layer 15, which can be understood as: the proportion of boron atoms in the barrier layer 16 is less than the proportion of boron atoms in the first film layer 15, or the boron concentration in the barrier layer 16 is less than the boron concentration in the first film layer 15.

[0127] In some structures that can be implemented, as shown in FIG. 15, the first electrode 11 of the P-type transistor can include a first sub-electrode layer 111 and a second sub-electrode layer 112 stacked, and the first sub-electrode layer 111 is closer to the channel 13 of the P-type transistor than the second sub-electrode layer 112. In the preparation process, the first sub-electrode layer 111 can be prepared first, and then the second sub-electrode layer 112 can be prepared on the first sub-electrode layer 111.

[0128] In the first sub-electrode layer 111, silicon Si, germanium Ge and boron B are included; in the second sub-electrode layer 112, silicon Si, germanium Ge and boron B are included.

[0129] The germanium content in the second sub-electrode layer 112 is greater than the germanium content in the first sub-electrode layer 111, and the boron content in the second sub-electrode layer 112 is greater than the boron content in the first sub-electrode layer 111.

[0130] The germanium content in the first sub-electrode layer 111 is less than the germanium content in the second sub-electrode layer 112, and the boron content in the first sub-electrode layer 111 is less than the boron content in the second sub-electrode layer 112. The first sub-electrode layer 111 can be considered as a buffer layer, and the second sub-electrode layer 112 can be considered as a stress applying layer. By the buffer layer, the stress value applied by the second sub-electrode layer 112 to the channel can be increased, further improving the carrier mobility of the channel and improving the drive current of the P-type transistor. For example, the on-state current of the semiconductor device can be increased by 50%.

[0131] When the first electrode 11 as shown in Fig. 15 includes the stacked first sub-electrode layer 111 and the second sub-electrode layer 112, the barrier layer 16 includes silicon and boron, the boron B content in the barrier layer 16 is less than the boron content in the second sub-electrode layer 112, and the silicon content in the barrier layer 16 is greater than the silicon content in the second sub-electrode layer 112. In this way, the barrier layer 16 does not affect the function of the first electrode 11, and the barrier layer 16 can also play a role in inhibiting the diffusion of boron in the first film layer 15 to the channel.

[0132] As shown in Fig. 16, Fig. 16 shows another structure of a P-type transistor, and the first electrode 11 in this example can include an embedded portion 11A in the substrate and a protruding portion 11B protruding from the surface of the substrate. The circumferential side surface of the protruding portion 11B and the surface away from the substrate are covered by the barrier layer 16; and the barrier layer 16 located on the circumferential side surface of the protruding portion 11B extends to the surface of the substrate, such as extending to the first region of the substrate (the region surrounding the outer periphery of the protruding portion 11B), and the barrier layer 16 covers the first region.

[0133] In the process of making the first electrode 11 including the embedded portion 11A and the protruding portion 11B shown in Fig. 16, an epitaxial growth process can be used to make the embedded portion 11A and the protruding portion 11B.

[0134] Continuing to see Fig. 16, the protruding portion 11B of the first electrode 11 is inclined towards the direction away from the gate 14 near the circumferential side surface of the gate 14, so that the thickness dimension of the barrier layer 16 on the substrate is greater than the thickness dimension of the barrier layer 16 on the first electrode 11.

[0135] Continuing to see Fig. 16, the first film layer 15 stacked on the barrier layer 16 does not contact the surface of the substrate. The circumferential side surface of the first film layer 15 can be in contact with the second gate side wall 18, and the circumferential side surface of the barrier layer 16 can be in contact with the second gate side wall 18.

[0136] In other examples, other film layer structures can be provided between the circumferential side surface of the first film layer 15 and the second gate side wall 18, and other film layer structures can be provided between the circumferential side surface of the barrier layer 16 and the second gate side wall 18.

[0137] In some implementable ways, the shape of the trench for accommodating the first electrode 11 has various forms, such as a rectangular slot; or such as the trench structure shown in Fig. 17.

[0138] In the trench 24 structure shown in Fig. 17, from the bottom surface of the trench 24 to the opening direction (such as along the P direction), the radial dimension of the trench 24 (such as the dimension along the L direction) first increases and then decreases.

[0139] For example, the trench 24 has opposite first and second inner walls S1 and S2, and opposite third and fourth inner walls S3 and S4, the first and third inner walls S1 and S3 are connected, and the second and fourth inner walls S2 and S4 are connected, from the bottom surface to the opening direction (e.g., along the P direction) of the trench 24, the first and second inner walls S1 and S2 are inclined towards the outside of the trench 24, and the third and fourth inner walls S3 and S4 are inclined towards the inside of the trench 24. Such a trench structure can be referred to as a sigma-shaped trench, and the sigma-shaped trench shape is beneficial for the first electrode to apply stress to the channel of the germanium-silicon-on-insulator (GSOI) transistor, thereby improving the carrier mobility of the channel, for example, the on-state current of the semiconductor device can be increased by 50%.

[0140] In this way, the first electrode 11 formed has a radial (e.g., along the L direction of FIG. 17) dimension that first increases and then decreases from the bottom surface to the top surface direction (e.g., along the P direction of FIG. 17).

[0141] Based on the above-described semiconductor device with different structures and the corresponding manufacturing method, the semiconductor device can be manufactured according to the process flow diagram shown in FIG. 18.

[0142] Step S1: A trench is formed in the electrode region of the substrate, and the electrode region is used to form the first electrode of the P-type transistor.

[0143] The first electrode can be the source electrode or the drain electrode of the P-type transistor.

[0144] In some optional processes, dry etching or wet etching can be used to etch the trench in the source / drain region of the substrate.

[0145] For example, the trench can be a sigma-shaped trench, which is beneficial for the first electrode of the P-type transistor to apply stress to the channel.

[0146] In some processes, before forming the trench in the electrode region of the substrate, the manufacturing method can further include:

[0147] forming a gate of the P-type transistor on the substrate;

[0148] forming a first mask layer and a second mask layer, the first mask layer includes silicon oxide, the surface of the electrode region of the substrate is covered by the first mask layer, the second mask layer is located on the side of the first mask layer away from the substrate, and the surface and side of the gate are also covered by the first mask layer and the second mask layer, and the second mask layer can include silicon nitride.

[0149] In some structures, when the substrate is a silicon substrate, after the trench is formed in the electrode region of the substrate, the inner wall surface of the trench will be oxidized to form silicon oxide, and therefore, an epitaxy in situ pre-clean process can be used to remove the silicon oxide on the inner wall surface of the trench.

[0150] For example, a gas containing ammonia and hydrogen fluoride can be used to clean the inner wall surface of the trench, so that the silicon oxide on the inner wall surface of the trench is cleaned.

[0151] In addition, the part of the first mask layer of silicon oxide close to the trench is also cleaned, so that the surface of the substrate close to the trench is exposed.

[0152] Step S2: forming a first electrode of a P-type transistor in the trench, the first electrode comprising boron. For example, the first electrode comprises silicon, germanium and boron.

[0153] In the step S2, it can comprise: preparing a first sub-electrode layer in the trench; preparing a second sub-electrode layer on the first sub-electrode layer, the content of germanium in the second sub-electrode layer being greater than that in the first sub-electrode layer, and the content of boron in the second sub-electrode layer being greater than that in the first sub-electrode layer.

[0154] The first sub-electrode layer as a buffer layer can make the second sub-electrode layer better apply stress to the channel.

[0155] The first electrode is prepared by an epitaxial growth process, and the first electrode protrudes from the surface of the substrate to form a protruding part on the surface of the substrate.

[0156] Step S3: preparing a barrier layer on the first electrode, at least part of the area of the surface of the substrate outside the periphery of the first electrode being covered by the barrier layer.

[0157] In the case that the surface of the substrate has a protruding part, the barrier layer covers the protruding part, and the barrier layer extends from the circumferential surface of the protruding part to the surface of the substrate, so as to cover the surface of the substrate corresponding to the channel.

[0158] For example, the barrier layer is a pure silicon layer or a layer structure comprising silicon and germanium.

[0159] Step S4: preparing a first film layer on the barrier layer, the first film layer comprising boron, the content of boron in the first film layer being greater than that in the first electrode, and the barrier layer being used to inhibit the diffusion of boron in the first film layer into the channel of the P-type transistor. For example, the first film layer comprises silicon and boron.

[0160] When the P-type transistor in the semiconductor device is prepared by the method of the present application, although the area corresponding to the channel of the substrate is exposed when the silicon oxide on the inner wall surface of the trench is cleaned, the exposed area is covered by the barrier layer, and the diffusion of high content of boron in the subsequent first film layer into the channel is avoided.

[0161] In the description of the present specification, specific features, structures, materials or characteristics can be combined in any one or more embodiments or examples in a suitable manner.

[0162] The above description is only specific embodiments of the present application, but the protection scope of the present application is not limited thereto, any person skilled in the art can easily think of changes or replacements within the technical scope disclosed by the present application, which should be covered in the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. A semiconductor device, characterized by, Comprising: a substrate; a P-type transistor including a first electrode, a second electrode, a channel, and a gate electrode, the first electrode, the second electrode, and the channel being located in the substrate, the channel being located between the first electrode and the second electrode, the gate electrode being located on the channel, the first electrode including boron; a first film layer located on the first electrode, the first film layer including boron, a content of boron in the first film layer being greater than a content of boron in the first electrode; a barrier layer stacked between the first electrode and the first film layer, a surface of the substrate including a first region located at a periphery of the first electrode, at least a portion of the first region being covered by the barrier layer, the barrier layer being configured to inhibit diffusion of boron in the first film layer into the channel of the P-type transistor.

2. The semiconductor device according to claim 1, wherein the first film layer and the first electrode further including silicon; the barrier layer including pure silicon; or; the barrier layer including silicon and boron; a content of boron in the barrier layer being less than a content of boron in the first film layer, a content of silicon in the barrier layer being greater than a content of silicon in the first film layer; and, a content of boron in the barrier layer being less than a content of boron in the first electrode, a content of silicon in the barrier layer being greater than a content of silicon in the first electrode.

3. The semiconductor device according to claim 1 or 2, wherein the first electrode including an embedded portion located in the substrate, and a protruding portion protruding from a surface of the substrate, the first region surrounding the protruding portion; a circumferential surface of the protruding portion and a surface facing away from the substrate are both covered by the barrier layer; the barrier layer located at the circumferential surface of the protruding portion extends to the first region and covers the first region.

4. The semiconductor device according to claim 3, wherein a circumferential surface of the protruding portion close to the gate electrode is inclined away from the gate electrode.

5. The semiconductor device according to claim 3 or 4, wherein a thickness dimension of the barrier layer located on the first region is greater than a thickness dimension of the barrier layer located on the first electrode.

6. The semiconductor device according to any one of Claims 1-5, wherein the first film layer and the first region are isolated by the barrier layer.

7. The semiconductor device according to any one of Claims 1-6, wherein the first electrode further includes silicon and germanium; the first electrode includes a first sub-electrode layer and a second sub-electrode layer stacked, the first sub-electrode layer being closer to the channel than the second sub-electrode layer; a content of germanium in the second sub-electrode layer is greater than a content of germanium in the first sub-electrode layer; and, a content of boron in the second sub-electrode layer is greater than a content of boron in the first sub-electrode layer.

8. The semiconductor device of claim 7, wherein, the barrier layer includes silicon and boron, a content of boron in the barrier layer being less than a content of boron in the second sub-electrode layer, and a content of silicon in the barrier layer being greater than a content of silicon in the second sub-electrode layer.

9. The semiconductor device according to any one of claims 1-8, a radial dimension of the first electrode increases first and then decreases from a bottom surface to a top surface of the first electrode.

10. The semiconductor device according to any one of Claims 1-9, wherein the semiconductor device further includes a first gate sidewall and a second gate sidewall, the first gate sidewall and the second gate sidewall being stacked in sequence at a circumferential surface of the gate electrode; a circumferential surface of the first film layer and a circumferential surface of the barrier layer both contact the second gate sidewall.

11. A semiconductor device package structure, comprising: Comprising: the semiconductor device according to any one of claims 1-10; a substrate, the semiconductor device being disposed on the substrate.

12. An electronic device, comprising: Comprising: A circuit board; The semiconductor device package structure of claim 11, wherein the semiconductor device package structure is disposed on the circuit board. The semiconductor device package structure of claim 11, wherein the semiconductor device package structure is disposed on the circuit board.

13. A method of manufacturing a semiconductor device, characterized by, The manufacturing method comprises: forming a trench in an electrode region of a substrate, the electrode region being used to form a first electrode of a P-type transistor; forming the first electrode of the P-type transistor in the trench, the first electrode comprising boron; forming a barrier layer on the first electrode, at least a portion of a surface of the substrate outside a periphery of the first electrode being covered by the barrier layer; forming a first film layer on the barrier layer, the first film layer comprising boron, a content of boron in the first film layer being greater than a content of boron in the first electrode, the barrier layer being used to inhibit diffusion of boron in the first film layer into a channel of the P-type transistor.

14. The manufacturing method of the semiconductor device according to claim 13, wherein, before the trench is formed in the electrode region of the substrate, the manufacturing method further comprises: forming a first mask layer and a second mask layer, the first mask layer comprising silicon oxide, a surface of the electrode region of the substrate being covered by the first mask layer, the second mask layer being located on a side of the first mask layer facing away from the substrate; after the trench is formed in the electrode region of the substrate, the manufacturing method further comprises: cleaning an inner wall surface of the trench, a portion of the first mask layer close to the trench being cleaned away, so that a surface of the substrate close to the trench is exposed.

15. The method of producing a semiconductor device according to Claim 14, wherein The cleaning of the inner wall surface of the trench comprises: cleaning the inner wall surface of the trench using a gas containing ammonia and hydrogen fluoride, so that silicon oxide of the inner wall surface of the trench and silicon oxide of the portion of the first mask layer close to the trench are cleaned away.

16. The method of producing a semiconductor device according to any one of claims 13 to 15, wherein The forming of the first electrode of the P-type transistor in the trench comprises: forming a first sub-electrode layer in the trench; forming a second sub-electrode layer on the first sub-electrode layer, a content of germanium in the second sub-electrode layer being greater than a content of germanium in the first sub-electrode layer, and a content of boron in the second sub-electrode layer being greater than a content of boron in the first sub-electrode layer.

Images