Low noise amplifier, radio frequency circuit, and electronic device

Abstract

The present application relates to the field of radio frequency, and discloses a low noise amplifier, a radio frequency circuit, and an electronic device, which are used for preventing an LNA from generating harmonic signals in an off state. An input port in the LNA is electrically connected to a resistor and an input end of a gain circuit by means of an input match and a bias capacitor. A bias circuit is electrically connected to a first end of the resistor and an enable port. A cathode of a first diode is electrically connected to an anode of a second diode, and a cathode of the second diode and an anode of a third diode are grounded. An anode of the first diode and a cathode of the third diode are electrically connected to any end of the bias capacitor. A switch is connected in parallel to at least one of the first diode and the second diode. The enable port is used to input an enable signal or a disable signal. The enable signal controls the bias circuit to output a bias voltage and a bias current to the gain circuit and controls the switch to be turned off. The disable signal controls the bias circuit to stop outputting the bias voltage and the bias current to the gain circuit and controls the switch to be turned on.

Description

Low noise amplifier, radio frequency circuit and electronic device

[0001] The present application claims priority to the Chinese patent application No. 202411291736.9, filed on September 14, 2024, and entitled "Low noise amplifier, radio frequency circuit and electronic device", the entire content of which is incorporated herein by reference. TECHNICAL FIELD

[0002] The present application relates to the field of radio frequency, in particular to a low noise amplifier, a radio frequency circuit and an electronic device. BACKGROUND

[0003] The low noise amplifier (LNA) is one of the important components in the wireless communication system, which is used to amplify the power of the received radio frequency signal. Due to the coupling relationship between the transmitting antenna and the receiving antenna, even if the LNA is in the off state during the transmitting time slot, a part of the power will be coupled to the input end of the LNA through the transmitting channel, so that the LNA generates a harmonic signal, which will produce radiation, so that the radiated spurious emission (RSE) test exceeds the standard and cannot meet the regulatory requirements. SUMMARY

[0004] Embodiments of the present application provide a low noise amplifier, a radio frequency circuit and an electronic device, which are used to avoid the generation of harmonic signals by the LNA in the off state. In order to achieve the above-mentioned purpose, the embodiments of the present application adopt the following technical solutions:

[0005] In a first aspect, a low noise amplifier is provided, comprising: a gain circuit, a protection circuit, an input matching, an output matching, a bias circuit, a load network, an input port, an output port, an enable port, a degeneration inductor, a bias capacitor, a resistor; the protection circuit comprises a first diode, a second diode, a third diode, a switch; the input port is electrically connected to a first end of the input matching, a second end of the input matching is electrically connected to a first end of the bias capacitor, a second end of the bias capacitor is electrically connected to a second end of the resistor and an input end of the gain circuit; the bias circuit is electrically connected to a first end of the resistor, and the bias circuit is also electrically connected to the enable port; an output end of the gain circuit is electrically connected to the output port, the gain circuit is also electrically connected to a power supply through the load network, and the gain circuit is also grounded through the degeneration inductor; a cathode of the first diode is electrically connected to an anode of the second diode, a cathode of the second diode and an anode of the third diode are grounded; an anode of the first diode and a cathode of the third diode are electrically connected to the first end or the second end of the bias capacitor; the enable port is also electrically connected to a control end of the switch, the switch is in parallel with at least one of the first diode and the second diode; the enable port is used to input an enable signal or a disable signal, the enable signal is used to control the bias circuit to output a bias voltage and a bias current to the gain circuit, and control the switch to be turned off; the disable signal is used to control the bias circuit to stop outputting the bias voltage and the bias current to the gain circuit, and control the switch to be turned on.

[0006] The low noise amplifier provided by the embodiments of the present application is electrically connected to the protection circuit at the input end of the gain circuit, the cathode of the first diode in the protection circuit is electrically connected to the anode of the second diode, the cathode of the second diode and the anode of the third diode are grounded, the anode of the first diode and the cathode of the third diode are electrically connected to the input end of the gain circuit, and the switch is in parallel with at least one of the first diode and the second diode. The enable port is used to input an enable signal or a disable signal, the enable signal is used to control the bias circuit to output a bias voltage and a bias current to the gain circuit, and control the switch to be turned off; the disable signal is used to control the bias circuit to stop outputting the bias voltage and the bias current to the gain circuit, and control the switch to be turned on. If the enable port inputs the disable signal, the disable signal controls the bias circuit to stop outputting the bias voltage and the bias current to the gain circuit, so that the LNA is in a closed state. The disable signal controls the switch to be turned on, at least one of the first diode and the second diode is short-circuited, so as to reduce the turn-on voltage of the protection circuit, the protection circuit is more likely to discharge the smaller input power, and the generation of harmonic signals by the gain circuit is avoided, so that the generation of harmonic signals by the LNA in the closed state is also avoided.

[0007] In a possible implementation, the protection circuit further comprises an inverter, and the enable port is electrically connected to the control end of the switch through the inverter. The protection circuit comprising the inverter is applicable to a scenario in which the enable signal is high, the disable signal is low, and the switch is an N-type MOS tube, or a scenario in which the enable signal is low, the disable signal is high, and the switch is a P-type MOS tube.

[0008] In a possible implementation, the enable signal is high, the disable signal is low, and the switch is an N-type MOS tube. The protection circuit comprises the inverter.

[0009] In a possible implementation, the enable signal is low, the disable signal is high, and the switch is a P-type MOS tube. The protection circuit comprises the inverter.

[0010] In a possible implementation, the enable signal is high, the disable signal is low, and the switch is a P-type MOS tube. The protection circuit does not comprise the inverter.

[0011] In a possible implementation, the enable signal is low, the disable signal is high, and the switch is an N-type MOS tube. The protection circuit does not comprise the inverter.

[0012] In a possible implementation, the enable signal is high, the disable signal is low, and the switch is an N-type MOS tube. The protection circuit does not comprise the inverter.

[0013] In a possible implementation, the enable signal is low, the disable signal is high, and the switch is a P-type MOS tube. The protection circuit does not comprise the inverter.

[0014] The technical effects of the second aspect and the third aspect are referred to the technical effects of the first aspect and any of the implementations of the first aspect, which are not repeated here. BRIEF DESCRIPTION OF DRAWINGS

[0015] FIG. 1 is a schematic view of an appearance of an electronic device according to an embodiment of the present application;

[0016] FIG. 2 is a schematic view of a structure of an electronic device according to an embodiment of the present application;

[0017] FIG. 3 is a schematic view of a structure of a radio frequency circuit according to an embodiment of the present application;

[0018] FIG. 4 is a schematic view of a structure of a first LNA according to an embodiment of the present application;

[0019] FIG. 5 is a schematic view of a discharge path of a first input power according to an embodiment of the present application;

[0020] Fig. 6 is a structural schematic diagram of a second LNA provided by an embodiment of the present application;

[0021] Fig. 7 is a schematic diagram of a discharge path of a second input power provided by an embodiment of the present application;

[0022] Fig. 8 is a structural schematic diagram of a third LNA provided by an embodiment of the present application;

[0023] Fig. 9 is a schematic diagram of a discharge path of a third input power provided by an embodiment of the present application;

[0024] Fig. 10 is a structural schematic diagram of a fourth LNA provided by an embodiment of the present application;

[0025] Fig. 11 is a schematic diagram of a discharge path of a fourth input power provided by an embodiment of the present application;

[0026] Fig. 12 is a structural schematic diagram of a fifth LNA provided by an embodiment of the present application;

[0027] Fig. 13 is a schematic diagram of a discharge path of a fifth input power provided by an embodiment of the present application;

[0028] Fig. 14 is a structural schematic diagram of a sixth LNA provided by an embodiment of the present application;

[0029] Fig. 15 is a schematic diagram of a discharge path of a sixth input power provided by an embodiment of the present application;

[0030] Fig. 16 is a structural schematic diagram of a seventh LNA provided by an embodiment of the present application;

[0031] Fig. 17 is a schematic diagram of a discharge path of a seventh input power provided by an embodiment of the present application;

[0032] Fig. 18 is a structural schematic diagram of an eighth LNA provided by an embodiment of the present application;

[0033] Fig. 19 is a schematic diagram of a discharge path of an eighth input power provided by an embodiment of the present application;

[0034] Fig. 20 is a structural schematic diagram of a ninth LNA provided by an embodiment of the present application;

[0035] Fig. 21 is a schematic diagram of a discharge path of a ninth input power provided by an embodiment of the present application;

[0036] Fig. 22 is a structural schematic diagram of a tenth LNA provided by an embodiment of the present application;

[0037] Fig. 23 is a schematic diagram of a discharge path of a tenth input power provided by an embodiment of the present application;

[0038] FIG. 24 is a schematic view of a structure of an eleventh LNA according to an embodiment of the present application;

[0039] FIG. 25 is a schematic view of a discharge path of an eleventh input power according to an embodiment of the present application. DETAILED DESCRIPTION

[0040] Some concepts involved in the present application are described first.

[0041] The terms "first", "second", and the like in the embodiments of the present application are only used for the purpose of distinguishing the same type of features, and should not be understood as indicating relative importance, quantity, order, etc.

[0042] The terms "exemplary" or "for example" in the embodiments of the present application are used to represent that an embodiment or design scheme is an example, illustration or description. Any embodiment or design scheme described as "exemplary" or "for example" in the present application should not be interpreted as being more preferred or advantageous than other embodiments or design schemes. In fact, the terms "exemplary" or "for example" are used to present relevant concepts in a specific manner.

[0043] The terms "coupled" and "connected" in the embodiments of the present application should be interpreted in a broad sense, for example, can refer to a direct physical connection, or can refer to an indirect connection through electronic devices, for example, a connection through resistors, inductors, capacitors or other electronic devices.

[0044] As shown in FIG. 1, an embodiment of the present application provides an electronic device 101, which is an electronic device with a wireless communication function. The electronic device can be mobile or fixed. The electronic device can be deployed on land (for example, indoors or outdoors, handheld or vehicle-mounted, etc.), on water (for example, a ship, etc.), or in the air (for example, an airplane, a balloon, a satellite, etc.). The electronic device can be referred to as a user equipment (UE), an access terminal, a terminal unit, a subscriber unit, a terminal station, a mobile station (MS), a mobile terminal, a terminal agent, or a terminal device, etc. For example, the electronic device can be a mobile phone, a tablet computer, a notebook computer, a smart bracelet, a smart screen, a smart watch, a virtual reality (VR) device, an augmented reality (AR) device, a terminal in industrial control, a terminal in self driving, a terminal in remote medical, a terminal in smart grid, a terminal in transportation safety, a terminal in smart city, a terminal in smart home, etc. Embodiments of the present application do not limit the specific type and structure of the electronic device. A possible structure of the electronic device is described below.

[0045] As shown in FIG. 1A, the electronic device 101 can include a front camera 2931 and a display screen 294. As shown in FIG. 1B, the electronic device 101 can include a back camera 2932. The front camera 2931 and the back camera 2932 are used to take still images or dynamic videos (which can be collectively referred to as images). The display screen 294 is used to display images or receive touch operations of a user.

[0046] Taking a mobile phone as an example of an electronic device, FIG. 2 shows a possible structure of the electronic device 101. The electronic device 101 can include a processor 210, an external memory interface 220, an internal memory 221, a universal serial bus (USB) interface 230, a power management module 240, a battery 241, a wireless charging coil 242, an antenna 1, an antenna 2, a mobile communication module 250, a wireless communication module 260, an audio module 270, a speaker 270A, a receiver 270B, a microphone 270C, a headset interface 270D, a sensor module 280, a key 290, a motor 291, an indicator 292, a camera 293, a display screen 294, and a subscriber identification module (SIM) card interface 295, etc. Optionally, in some embodiments, an audio digital signal processor (ADSP) 243 is further included.

[0047] It can be understood that the structure shown in the embodiments of the present application does not constitute a specific limitation on the electronic device 101. In other embodiments of the present application, the electronic device 101 can include more or fewer components than shown, or combine certain components, or split certain components, or different arrangement of components. The components shown can be implemented in hardware, software, or a combination of software and hardware.

[0048] The processor 210 can include one or more processing units, for example: the processor 210 can be a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), a system on chip (SoC), a central processing unit (CPU), an application processor (AP), a network processor (NP), a digital signal processor (DSP), a micro controller unit (MCU), a programmable logic device (PLD), a modem processor, a graphics processing unit (GPU), an image signal processor (ISP), a controller, a video codec, and a neural-network processing unit (NPU), etc. Different processing units can be independent devices or integrated in one or more processors. For example, the processor 210 can be an application processor (AP). Alternatively, the above processor 210 can be integrated in a system on chip (SoC). Alternatively, the above processor 210 can be integrated in an integrated circuit (IC) chip. The processor 210 can include an analog front end (AFE) and a micro-controller unit (MCU) in the IC chip.

[0049] The processor 210 executes the antenna feeding control method provided by the embodiments of the present application by executing programs and computer instructions stored in the internal memory 221.

[0050] The processor 210 can also be provided with a memory for storing computer instructions and data. In some embodiments, the memory in the processor 210 is a cache memory. The memory can store computer instructions or data that have just been used or are recycled by the processor 210. If the processor 210 needs to use the computer instructions or data again, it can directly call from the memory. This avoids repeated access and reduces the waiting time of the processor 210, thus improving the efficiency of the system.

[0051] In some embodiments, the processor 210 can include one or more interfaces. The interfaces can include an inter-integrated circuit (I2C) interface, an inter-integrated circuit sound (I2S) interface, a pulse code modulation (PCM) interface, a universal asynchronous receiver / transmitter (UART) interface, a mobile industry processor interface (MIPI), a general-purpose input / output (GPIO) interface, a subscriber identity module (SIM) interface, and / or a USB interface, etc.

[0052] The ADSP 243 can be coupled with the audio module 270 and the sensor module 280, and can be used to process audio signals and also process sensor data. The ADSP 243 can remain active while the processor is in a sleep state, thereby reducing power consumption of the electronic device.

[0053] It can be understood that the interface connection relationship between the modules shown in the embodiments of the present application is only illustrative and does not constitute a structural limitation of the electronic device 101. In some other embodiments of the present application, the electronic device 101 can also use different interface connection modes or a combination of multiple interface connection modes in the above embodiments.

[0054] The external memory interface 220 can be used to connect an external storage card, such as a micro SanDisk (Micro SD) card, to expand the storage capacity of the electronic device 101. The external storage card communicates with the processor 210 through the external memory interface 220 to realize a data storage function. For example, music, video, and other files are saved in the external storage card.

[0055] The internal memory 221 can be used to store computer executable program codes including computer instructions. The processor 210 performs various functional applications and data processing of the electronic device 101 by executing the computer instructions stored in the internal memory 221. In addition, the internal memory 221 can include a high-speed random access memory, and can further include a non-volatile memory such as at least one of a magnetic disk storage device, a flash memory device, a universal flash storage (UFS), etc.

[0056] The memory to which embodiments of the present application are directed can be a volatile memory or a non-volatile memory, or can include both volatile and non-volatile memories. Among them, the non-volatile memory can be a read-only memory (ROM), a programmable ROM (PROM), an erasable PROM (EPROM), an electrically EPROM (EEPROM), or a flash memory. The volatile memory can be a random access memory (RAM) used as an external cache. By way of example and not limitation, many forms of RAM can be used, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDR SDRAM), enhanced SDRAM (ESDRAM), synchlink DRAM (SLDRAM), and direct rambus RAM (DR RAM). It should be noted that the memory of the system and method described herein is intended to include, but not be limited to, these and any other suitable types of memory.

[0057] The electronic device 101 can implement an audio function through an audio module 270, a speaker 270A, a receiver 270B, a microphone 270C, a headset jack 270D, and an application processor, etc. For example, music playback, recording, etc.

[0058] The audio module 270 is configured to convert digital audio information into an analog audio signal output, and to convert an analog audio input into a digital audio signal. In some embodiments, the audio module 270 can be disposed in the processor 210, or some functional modules of the audio module 270 can be disposed in the processor 210. The speaker 270A, also referred to as a "loudspeaker", is configured to convert an audio electrical signal into a sound signal. The receiver 270B, also referred to as a "earpiece", is configured to convert an audio electrical signal into a sound signal. The microphone 270C, also referred to as a "microphone", "microphone", is configured to convert a sound signal into an electrical signal. The electronic device 101 can be provided with at least one microphone 270C. The earphone interface 270D is configured to connect a wired earphone. The earphone interface 270D can be a USB interface 230, or a 3.5mm open mobile terminal platform (OMTP) standard interface, a cellular telecommunications industry association of the USA (CTIA) standard interface.

[0059] The keys 290 include a power key, a volume key, and the like. The keys 290 can be mechanical keys. Alternatively, the keys 290 can be touch keys. The electronic device 101 can receive a key input, and generate a key signal input related to user settings and function control of the electronic device 101. The motor 291 can generate a vibration prompt. The motor 291 can be used for incoming call vibration prompts, and can also be used for touch vibration feedback. The indicator 292 can be an indicator light, and can be used to indicate a charging state, a power change, and can also be used to indicate a message, a missed call, a notification, and the like. The SIM card interface 295 is configured to connect a SIM card. The SIM card can be inserted into or removed from the SIM card interface 295 to achieve contact and separation with the electronic device 101. The electronic device 101 can support one or N SIM card interfaces, N being a positive integer greater than 1. The SIM card interface 295 can support a Nano SIM card, a Micro SIM card, a SIM card, and the like. In some embodiments, the electronic device 101 uses an embedded SIM (eSIM) card, which can be embedded in the electronic device 101 and cannot be separated from the electronic device 101.

[0060] The electronic device 101 can implement a photographing function through an ISP, a camera 293, a video codec, a GPU, a display 294, and an application processor, etc. The ISP is used to process data fed back by the camera 293. In some embodiments, the ISP can be disposed in the camera 293. The camera 293 is used to capture a still image or a video. In some embodiments, the electronic device 101 can include 1 or N cameras 293, where N is a positive integer greater than 1, such as the front camera 2931 and the back camera 2932 shown in FIG. 1.

[0061] The electronic device 101 can implement a display function through a GPU, a display 294, and an application processor, etc. The GPU is a microprocessor for image processing, which is connected to the display 294 and the application processor. The GPU is used to perform mathematical and geometric calculations for graphics rendering. The processor 210 can include one or more GPUs that execute computer instructions to generate or change display information.

[0062] The sensor module 280 can include a pressure sensor, a gyro sensor, a barometric sensor, a magnetic sensor, an acceleration sensor, a distance sensor, a proximity light sensor, a fingerprint sensor, a temperature sensor, a touch sensor, an ambient light sensor, an angle sensor, etc. When the display 294 is a folding screen, the angle sensor can detect the folding angle of the display 294, and the folding angle ranges from 0 to 180 degrees.

[0063] The battery 241 can include one or more batteries to power the load. The power management module 240 is used to receive charging input from a charger. The charger can be a wireless charger, such as a wireless charging base, another electronic device 101 with a reverse wireless charging function, etc. The power management module 240 can receive wireless charging input through the wireless charging coil 242 of the electronic device. The charger can also be a wired charger, for example, the power management module 240 can receive charging input from a wired charger through the USB interface 230. The power management module 240 is also called a charging chip.

[0064] The power management module 240 can supply power to the electronic device while charging the battery 241. The power management module 240 receives input from the battery 241 to power the processor 210, the internal memory 221, the external memory interface 220, the display 294, the camera 293, and the wireless communication module 260, etc. The power management module 240 can also be used to monitor parameters such as the capacity, voltage, battery cycle count, and battery health state (leakage, impedance) of the battery 241. In other embodiments, the power management module 240 can also be disposed in the processor 210.

[0065] The display screen 294 is configured to display images, videos, and the like. The display screen 294 includes a display panel. In some embodiments, the electronic device 101 can include one or more display screens 294.

[0066] The wireless communication function of the electronic device 101 can be implemented by the antenna 1, the antenna 2, the mobile communication module 250, the wireless communication module 260, a modem processor, and the like.

[0067] The antenna 1 and the antenna 2 are configured to transmit and receive electromagnetic wave signals. Each antenna in the electronic device 101 can be configured to cover a single or multiple communication bands. Different antennas can also be multiplexed to improve the utilization of the antennas. For example, the antenna 1 can be multiplexed as a diversity antenna for wireless local area networks. In some other embodiments, the antennas can be used in combination with a tuning switch.

[0068] The mobile communication module 250 (also referred to as a cellular communication module) can provide a solution for wireless communication including 2G / 3G / 4G / 5G, and the like, applied to the electronic device 101. The wireless communication module 260 (including a satellite communication module) can provide a solution for wireless communication including wireless local area networks (WLAN) (such as wireless fidelity (Wi-Fi) networks), Bluetooth (BT), global navigation satellite system (GNSS) (such as Beidou satellite communication), satellite network communication (such as Tianhong satellite communication, Xingwang satellite communication), frequency modulation (FM), near field communication (NFC), infrared technology (IR), and the like, applied to the electronic device 101. In some embodiments, the antenna 1 of the electronic device 101 is coupled with the mobile communication module 250, and the antenna 2 is coupled with the wireless communication module 260, so that the electronic device 101 can communicate with a network and other devices through wireless communication technology. The mobile communication module 250 and the wireless communication module 260 can be collectively referred to as a radio frequency circuit.

[0069] As shown in FIG. 3, the radio frequency circuit 30 can include a baseband chip 31, a radio frequency integrated circuit (RFIC) 32, and a radio frequency front-end circuit 33. The baseband chip 31 and the RFIC 32 can also be integrated with the processor 210 in a SoC. The radio frequency front-end circuit 33 includes a power amplifier (PA) 331, an LNA 332, and can also include filters, antenna switches, couplers, etc., which are not limited by the present application. The branch where the PA 331 is located is a transmitting channel, and the branch where the LNA 332 is located is a receiving channel.

[0070] The baseband chip 31 is configured to convert data from the processor 210 into a baseband signal, including modulating and demodulating the baseband signal, digital filtering, equalization processing, etc. The baseband chip 31 is also configured to control various devices in the radio frequency front-end circuit 33 through a control signal. The RFIC 32 is configured to convert the baseband signal from the baseband chip 31 into a radio frequency signal, which is amplified in power by the PA 331 and then transmitted from the first antenna 341. The LNA 332 is configured to amplify the radio frequency signal received from the second antenna 342 in power and then send it to the RFIC 32, which converts the radio frequency signal into a baseband signal and sends it to the baseband chip 31. The baseband chip 31 converts the baseband signal into data and sends it to the processor 210.

[0071] As shown in FIG. 4, the LNA includes a gain circuit 401, a protection circuit 402, an input matching 403, an output matching 404, a bias circuit 405, a load network 406, an input port IN, an output port OUT, a degeneration inductor L, a bias capacitor C, and a resistor R. The protection circuit 402 includes diodes D1, D2, D3, and D4.

[0072] The input port IN is configured to be electrically connected to the second antenna 342 in FIG. 3. The input port IN is electrically connected to a first end of the input matching 403, a second end of the input matching 403 is electrically connected to a first end of the bias capacitor C, a second end of the bias capacitor C is electrically connected to a second end of the resistor R and an input end of the gain circuit 401. The bias circuit 405 is electrically connected to a first end of the resistor R. An output end of the gain circuit 401 is electrically connected to the output port OUT through the output matching 404, and the output port OUT is configured to be electrically connected to the RFIC 32 in FIG. 3. The gain circuit 401 is also electrically connected to a power supply through the load network 406, and the gain circuit 401 is also grounded through the degeneration inductor L.

[0073] In the protection circuit 402, the anode of diode D1 and the cathode of diode D3 are electrically connected to the first end of the bias capacitor C, the cathode of diode D1 is electrically connected to the anode of diode D2, the anode of diode D3 is electrically connected to the cathode of diode D4, the cathode of diode D2 and the anode of diode D4 are grounded.

[0074] The degeneration inductance L and the input matching 403 are used for matching the noise figure and the gain of the LNA. The load network 406 is used for supplying power to the gain circuit 401 and preventing the reverse flow of radio frequency signals into the power supply. The bias circuit 405 is used for outputting bias voltage and bias current to the gain circuit 401. The output matching 404 is used for matching impedance. The bias capacitor C is used for isolating direct current signals and conducting alternating current signals. The resistor R is used for current limiting.

[0075] The protection circuit 402 is used for electrostatic discharge protection of the LNA. The voltage of static electricity has both positive voltage and negative voltage, so the diode D1 and the diode D2 in series in the protection circuit 402 are used for conducting the positive voltage of static electricity, and the diode D3 and the diode D4 in series are used for conducting the negative voltage of static electricity, so as to be able to discharge the bidirectional static voltage. The electrostatic discharge protection refers to avoiding the static electricity accumulated in the process of using the electronic device to be too large to burn the gain circuit 401 of the LNA. When the absolute value of the input static voltage of the LNA is large, any set of diodes in series is turned on, the protection circuit 402 grounds the input port IN, so as to discharge the static electricity.

[0076] Since the parasitic capacitance of the diodes in series will affect the performance of the input matching 403 when the LNA is working, the number of diodes in series in each set in the protection circuit 402 is usually greater than or equal to 2, which causes the turn-on voltage of the protection circuit 402 to be at least 2*Vdiode, Vdiode is the turn-on voltage of the diode (for example, 0.7V), and the corresponding input power of the input port IN is greater than 10dBm. When the input power of the input port IN is less than 10dBm, the diode cannot be turned on, the protection circuit 402 cannot discharge the input power and thus cannot play a protection role.

[0077] As shown in FIG. 5, taking the radio frequency signal of the n79 frequency band as an example, in the transmitting time slot, the PA 331 performs power amplification on the radio frequency signal, so that the power of the radio frequency signal radiated through the first antenna 341 is 20dBm. Assuming that the isolation between the first antenna 341 and the second antenna 342 is 15dB, although the LNA 332 is in the off state in the transmitting time slot, because of the coupling relationship between the first antenna 341 and the second antenna 342, the power of the radio frequency signal coupled to the second antenna 342 is 5dBm, that is, the power of the radio frequency signal coupled to the input end of the LNA 332 in the transmitting channel is 5dBm. As explained in FIG. 4, when the input power is less than 10dBm, the protection circuit in the LNA will not bleed the input power and thus cannot play a protection role. The PN junction in the gain circuit 401 of the LNA is a nonlinear device, so that even if the LNA is in the off state, the input power of the gain circuit 401 will generate harmonic signals, which will generate radiation, so that the radiated spurious emission (RSE) test exceeds the standard and cannot meet the regulatory requirements.

[0078] To this end, as shown in FIGS. 6-25, the embodiment of the present application provides another LNA, which comprises: a gain circuit 401, a protection circuit 402, an input matching 403, an output matching 404, a bias circuit 405, a load network 406, an input port IN, an output port OUT, an enable port EN, a degeneration inductor L, a bias capacitor C, and a resistor R. The protection circuit 402 comprises a diode D1, a diode D2, a diode D3, and a switch K. The switch K can be a metal-oxide-semiconductor field-effect transistor (MOS) tube. Optionally, as shown in FIGS. 16-25, the protection circuit 402 further comprises an inverter INV.

[0079] The input port IN is electrically connected to a first end of the input matching 403, a second end of the input matching 403 is electrically connected to a first end of the bias capacitor C, a second end of the bias capacitor C is electrically connected to a second end of the resistor R and an input end of the gain circuit 401. The bias circuit 405 is electrically connected to a first end of the resistor R and is also electrically connected to the enable port EN. An output end of the gain circuit 401 is electrically connected to the output port OUT, the gain circuit 401 is further electrically connected to a power supply through the load network 406, and the gain circuit 401 is further grounded through the degeneration inductor L.

[0080] In the protection circuit 402, as shown in FIGS. 6-25, the cathode of the diode D1 is electrically connected with the anode of the diode D2, and the cathode of the diode D2 and the anode of the diode D3 are grounded. As shown in FIGS. 6-11 and 16-21, the anode of the diode D1 and the cathode of the diode D3 are electrically connected with the first end of the bias capacitor C; or as shown in FIGS. 12-15 and 22-25, the anode of the diode D1 and the cathode of the diode D3 are electrically connected with the second end of the bias capacitor C. The anode of the diode D1 and the cathode of the diode D3 are electrically connected with the first end of the bias capacitor C, and the protection circuit 402 can not only provide electrostatic discharge protection for the gain circuit 401, but also provide electrostatic discharge protection for the bias capacitor C.

[0081] Since the power of the radio frequency signal inputted by the input port IN of the LNA is only positive, when the input power is large, the diode D1 and the diode D2 are turned on, and the diode D3 is always not turned on because it is reversely connected between the input port IN and the ground. Therefore, only at least one of the switch K and the diode D1, the diode D2 needs to be connected in parallel, so that at least one of the diode D1, the diode D2 is short-circuited when the switch K is turned on, so as to reduce the turn-on voltage of the protection circuit 402, without requiring the switch K to be connected in parallel with the diode D3. In this way, even if the input power of the LNA in the off state is small (for example, 5 dBm), the input port IN of the LNA can be grounded through the diode D1 or the diode D2, or directly grounded through the switch K, so that the input power can be discharged to the ground even when the input power is small, avoiding the generation of harmonic signals by the gain circuit 401.

[0082] For example, in FIGS. 6, 7, 12, 13, 16, 17, 22, 23, the switch K is connected in parallel with the diode D1, and the diode D1 is short-circuited when the switch K is turned on, and the turn-on voltage of the protection circuit 402 is equal to the turn-on voltage Vdiode of the diode D2. In FIGS. 8, 9, 14, 15, 18, 19, 24, 25, the switch K is connected in parallel with the diode D2, and the diode D2 is short-circuited when the switch K is turned on, and the turn-on voltage of the protection circuit 402 is equal to the turn-on voltage Vdiode of the diode D1. In FIGS. 10, 11, 20, 21, the switch K is connected in parallel with the diode D1 and the diode D2, and the diode D1 and the diode D2 are short-circuited when the switch K is turned on, and the turn-on voltage of the protection circuit 402 is 0 V. All of them are less than the corresponding turn-on voltage 2*Vdiode when the input power is 10 dBm, and it is easier to discharge the smaller input power, avoiding the generation of harmonic signals by the gain circuit 401.

[0083] The enable port EN can be electrically connected with the baseband chip 31 in FIG. 3. The baseband chip 31 can send a control signal (including an enable signal or a disable signal) to the enable port EN of the LNA. The enable signal is used to control the bias circuit 405 to output a bias voltage and a bias current to the gain circuit 401, so that the LNA is in an operating state. The enable signal is also used to control the switch K to be off. The disable signal is used to control the bias circuit 405 to stop outputting the bias voltage and the bias current to the gain circuit 401, so that the LNA is in a closed state. The disable signal is also used to control the switch K to be on.

[0084] The enable signal is high, the disable signal is low, the switch K is an N-type MOS tube, and the protection circuit 402 includes an inverter INV. Alternatively, the enable signal is high, the disable signal is low, the switch K is a P-type MOS tube, and the protection circuit 402 does not include the inverter INV. Alternatively, the enable signal is low, the disable signal is high, the switch K is a P-type MOS tube, and the protection circuit 402 includes the inverter INV. Alternatively, the enable signal is low, the disable signal is high, the switch K is an N-type MOS tube, and the protection circuit 402 does not include the inverter INV. As shown in FIGS. 6-15, when the protection circuit 402 does not include the inverter INV, the enable port EN is electrically connected with the control end of the switch K. As shown in FIGS. 16-25, when the protection circuit 402 includes the inverter INV, the input end of the inverter INV is electrically connected with the enable port EN, and the output end of the inverter INV is electrically connected with the control end of the switch K, that is, the enable port EN is electrically connected with the control end of the switch K through the inverter INV.

[0085] Taking the enable signal as high, the disable signal as low, the switch K as an N-type MOS tube, and the protection circuit 402 as including the inverter INV as an example, the working principle of the protection circuit 402 is as follows:

[0086] When the baseband chip 31 sends the enable signal to the enable port EN of the LNA, the bias circuit 405 outputs the bias voltage and the bias current to the gain circuit 401, so that the LNA is in an operating state. If the enable signal is high, the disable signal is low, the switch K is an N-type MOS tube, and the protection circuit 402 includes the inverter INV, the enable signal is inverted to low by the inverter INV, and the switch K of the N-type MOS tube is turned off. At this time, the protection circuit 402 can still play a role in electrostatic discharge protection, that is, when the absolute value of the input static voltage is large (greater than 2*Vdiode), the diode D1 and the diode D2 are turned on, or the diode D3 is turned on, and the static electricity is discharged through the diode D1 and the diode D2, or through the diode D3.

[0087] When the baseband chip 31 sends a disable signal to the enable port EN of the LNA, the bias circuit 405 stops outputting the bias voltage and the bias current to the gain circuit 401, so that the LNA is in the off state. If the enable signal is high level, the disable signal is low level, the switch K is an N-type MOS tube, and the protection circuit 402 includes an inverter INV, then the low level disable signal is inverted to high level by the inverter INV, and the switch K controlled by the N-type MOS tube is turned on. At this time, the switch K shorts the diode in parallel with the switch K. For example, in FIGS. 6, 7, 12, 13, 16, 17, 22, and 23, the switch K shorts the diode D1, and the input power is discharged through the switch K and the diode D2. In FIGS. 8, 9, 14, 15, 18, 19, 24, and 25, the switch K shorts the diode D2, and the input power is discharged through the switch K and the diode D1. In FIGS. 10, 11, 20, and 21, the switch K shorts the diodes D1 and D2, and the input power is discharged through the switch K. All of them can avoid the gain circuit 401 generating harmonic signals.

[0088] For example, the enable signal is high level, the disable signal is low level, the switch K is a P-type MOS tube, and the protection circuit 402 does not include an inverter INV. The working principle of the protection circuit 402 is as follows:

[0089] When the baseband chip 31 sends an enable signal to the enable port EN of the LNA, the bias circuit 405 outputs the bias voltage and the bias current to the gain circuit 401, so that the LNA is in the working state. If the enable signal is high level, the disable signal is low level, the switch K is a P-type MOS tube, and the protection circuit 402 does not include an inverter INV, then the high level enable signal controls the switch K of the P-type MOS tube to be turned off. At this time, the protection circuit 402 can still play a role in electrostatic discharge protection, that is, when the absolute value of the input static voltage is large (greater than 2*Vdiode), the diode D1, the diode D2, or the diode D3 is turned on, and the static electricity is discharged to ground through the diode D1 and the diode D2, or through the diode D3.

[0090] When the baseband chip 31 sends a disable signal to the enable port EN of the LNA, the bias circuit 405 stops outputting the bias voltage and the bias current to the gain circuit 401, so that the LNA is in the off state. If the enable signal is high level, the disable signal is low level, the switch K is a P-type MOS tube, and the protection circuit 402 does not include an inverter INV, then the low level disable signal controls the switch K of the P-type MOS tube to be turned on. At this time, the switch K shorts the diode in parallel with the switch K. For example, in FIGS. 6, 7, 12, 13, 16, 17, 22, and 23, the switch K shorts the diode D1, and the input power is discharged through the switch K and the diode D2. In FIGS. 8, 9, 14, 15, 18, 19, 24, and 25, the switch K shorts the diode D2, and the input power is discharged through the switch K and the diode D1. In FIGS. 10, 11, 20, and 21, the switch K shorts the diodes D1 and D2, and the input power is discharged through the switch K. All of them can avoid the gain circuit 401 generating harmonic signals.

[0091] Taking the example that the enable signal is low level, the disable signal is high level, the switch K is a P-type MOS tube, and the protection circuit 402 includes an inverter INV, the working principle of the protection circuit 402 is as follows:

[0092] When the baseband chip 31 sends an enable signal to the enable port EN of the LNA, the bias circuit 405 outputs the bias voltage and the bias current to the gain circuit 401, so that the LNA is in the working state. If the enable signal is low level, the disable signal is high level, the switch K is a P-type MOS tube, and the protection circuit 402 includes an inverter INV, then the low level enable signal is inverted to high level by the inverter INV, and the switch K of the P-type MOS tube is turned off. At this time, the protection circuit 402 can still play a function of electrostatic discharge protection, that is, when the absolute value of the input static voltage is large, the diode D1 and the diode D2 are turned on, or the diode D3 is turned on, and the static electricity is discharged to ground through the diode D1 and the diode D2, or through the diode D3.

[0093] When the baseband chip 31 sends a disable signal to the enable port EN of the LNA, the bias circuit 405 stops outputting the bias voltage and the bias current to the gain circuit 401, so that the LNA is in the off state. If the enable signal is low and the disable signal is high, the switch K is a P-type MOS tube, and the protection circuit 402 includes an inverter INV, then the high level disable signal is inverted to low level by the inverter INV, and the switch K controlled by the P-type MOS tube is turned on. At this time, the switch K shorts the diode in parallel with the switch K. For example, in FIGS. 6, 7, 12, 13, 16, 17, 22, and 23, the switch K shorts the diode D1, and the input power is discharged through the switch K and the diode D2. In FIGS. 8, 9, 14, 15, 18, 19, 24, and 25, the switch K shorts the diode D2, and the input power is discharged through the switch K and the diode D1. In FIGS. 10, 11, 20, and 21, the switch K shorts the diodes D1 and D2, and the input power is discharged through the switch K. All of them can avoid the gain circuit 401 generating harmonic signals.

[0094] For example, the enable signal is low, the disable signal is high, the switch K is an N-type MOS tube, and the protection circuit 402 does not include an inverter INV. The working principle of the protection circuit 402 is as follows:

[0095] When the baseband chip 31 sends an enable signal to the enable port EN of the LNA, the bias circuit 405 outputs the bias voltage and the bias current to the gain circuit 401, so that the LNA is in the working state. If the enable signal is low and the disable signal is high, the switch K is an N-type MOS tube, and the protection circuit 402 does not include an inverter INV, then the low level enable signal controls the switch K of the N-type MOS tube to turn off. At this time, the protection circuit 402 can still play a role in electrostatic discharge protection, that is, when the absolute value of the input static voltage is large when the LNA is in the working state, the diode D1 and the diode D2 are turned on, or the diode D3 is turned on, and the static electricity is discharged to ground through the diode D1 and the diode D2, or through the diode D3.

[0096] When the baseband chip 31 sends a disable signal to the enable port EN of the LNA, the bias circuit 405 stops outputting the bias voltage and the bias current to the gain circuit 401, so that the LNA is in the off state. If the enable signal is low and the disable signal is high, the switch K is an N-type MOS tube, and the protection circuit 402 does not include an inverter INV, then the high-level disable signal controls the switch K of the N-type MOS tube to be turned on. At this time, the switch K shorts the diode connected in parallel with the switch K. For example, the switch K shorts the diode D1 in FIGS. 6, 7, 12, 13, 16, 17, 22, and 23, and the input power is discharged through the switch K and the diode D2. The switch K shorts the diode D2 in FIGS. 8, 9, 14, 15, 18, 19, 24, and 25, and the input power is discharged through the switch K and the diode D1. The switch K shorts the diodes D1 and D2 in FIGS. 10, 11, 20, and 21, and the input power is discharged through the switch K. All of them can avoid the gain circuit 401 generating harmonic signals.

[0097] The low noise amplifier, the radio frequency circuit and the electronic device provided by the embodiments of the present application, the low noise amplifier provided by the embodiments of the present application, the input end of the gain circuit is electrically connected with the protection circuit, the cathode of the first diode in the protection circuit is electrically connected with the anode of the second diode, the cathode of the second diode and the anode of the third diode are grounded; the anode of the first diode and the cathode of the third diode are electrically connected with the input end of the gain circuit, and the switch is connected in parallel with at least one of the first diode and the second diode. The enable port is used for inputting an enable signal or a disable signal, the enable signal is used for controlling the bias circuit to output the bias voltage and the bias current to the gain circuit, and controlling the switch to be turned off; the disable signal is used for controlling the bias circuit to stop outputting the bias voltage and the bias current to the gain circuit, and controlling the switch to be turned on. If the disable signal is inputted to the enable port, the disable signal controls the bias circuit to stop outputting the bias voltage and the bias current to the gain circuit, so that the LNA is in the off state. The disable signal controls the switch to be turned on, and at least one of the first diode and the second diode is shorted, so as to reduce the turn-on voltage of the protection circuit, the protection circuit is more likely to discharge the smaller input power, and the generation of the harmonic signal by the gain circuit is avoided, and the generation of the harmonic signal by the LNA in the off state is also avoided.

[0098] The above merely provides the specific implementation of the present application, but the protection scope of the present application is not limited to this, any person skilled in the art can easily think of the changes or replacements within the technical range disclosed by the present application, which should be covered in the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. A low noise amplifier characterized by, Comprising: a gain circuit, a protection circuit, an input matching, an output matching, a bias circuit, a load network, an input port, an output port, an enable port, a degeneration inductor, a bias capacitor, a resistor; the protection circuit comprises a first diode, a second diode, a third diode, a switch; the input port is electrically connected with a first end of the input matching, a second end of the input matching is electrically connected with a first end of the bias capacitor, a second end of the bias capacitor is electrically connected with a second end of the resistor and an input end of the gain circuit; the bias circuit is electrically connected with a first end of the resistor, and the bias circuit is also electrically connected with the enable port; an output end of the gain circuit is electrically connected with the output port, and the gain circuit is also electrically connected to a power supply through the load network, and the gain circuit is also grounded through the degeneration inductor; a cathode of the first diode is electrically connected with an anode of the second diode, a cathode of the second diode and an anode of the third diode are grounded; an anode of the first diode and a cathode of the third diode are electrically connected with the first end or the second end of the bias capacitor; the enable port is also electrically connected with a control end of the switch, and the switch is in parallel with at least one of the first diode and the second diode; the enable port is used for inputting an enable signal or a disable signal, the enable signal is used for controlling the bias circuit to output a bias voltage and a bias current to the gain circuit, and controlling the switch to be turned off; the disable signal is used for controlling the bias circuit to stop outputting the bias voltage and the bias current to the gain circuit, and controlling the switch to be turned on.

2. The low noise amplifier of claim 1, wherein, The protection circuit further comprises an inverter, and the enable port is electrically connected with the control end of the switch through the inverter.

3. The low noise amplifier of claim 2, wherein, The enable signal is high level, the disable signal is low level, and the switch is an N-type MOS tube.

4. The low noise amplifier of claim 2, wherein, The enable signal is low level, the disable signal is high level, and the switch is a P-type MOS tube.

5. The low noise amplifier of claim 1, wherein, The enable signal is high level, the disable signal is low level, and the switch is a P-type MOS tube.

6. The low noise amplifier of claim 1, wherein, The enable signal is low level, the disable signal is high level, and the switch is an N-type MOS tube.

7. A radio frequency circuit, characterized by Comprising a baseband chip, a radio frequency integrated circuit and a low noise amplifier as claimed in any one of claims 1-6, the baseband chip is electrically connected with the radio frequency integrated circuit and the low noise amplifier, and the radio frequency integrated circuit and the low noise amplifier are electrically connected.

8. An electronic device, comprising: Comprising a radio frequency circuit as claimed in claim 7 and an antenna, the radio frequency circuit is electrically connected with the antenna.

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