Memory cell, memory array and control method therefor, memory device and manufacturing method therefor

Abstract

A memory cell, a memory array and a control method therefor, a memory device and a manufacturing method therefor. The memory cell comprises: device pillars, gate structures circumferentially surrounding the device pillars, storage capacitors located on the sides of the device pillars close to first ends, and an interconnection platform located on the side of the device pillars close to second ends. The area of the memory cell is small, which can effectively improve the storage density of the memory array comprising the memory cell; the interconnection platform electrically connected to the second ends of the device pillars can provide a basis for subsequent formation of bit lines, thereby effectively reducing the process difficulty of forming bit lines.

Description

Memory cell, memory array and control method thereof, memory device and manufacturing method thereof

[0001] The present application claims priority to the Chinese patent application No. 202411294655.4, filed on September 13, 2024, and titled "Memory cell, memory array and control method thereof, memory device and manufacturing method thereof", the content of which is incorporated herein by reference in its entirety. TECHNICAL FIELD

[0002] The present application relates to the field of semiconductor manufacturing, and in particular to a memory cell, a memory array and a control method thereof, a memory device and a manufacturing method thereof. BACKGROUND

[0003] With the rapid development of semiconductor manufacturing technology, semiconductor devices are developing towards higher component density and higher integration. For a memory device, the requirements for storage density and read-write speed of the memory device are becoming higher and higher.

[0004] In order to improve integration and reduce cost, the size of the memory cell is continuously reduced, and the circuit density inside the memory device is increasingly large. The reduction of the size of the memory cell and the increase of the circuit density inside the memory device continuously increase the difficulty of further increasing the storage density and the difficulty of further improving the read-write speed. SUMMARY

[0005] The problem solved by the present application is how to further improve the storage density and the read-write speed of the memory device.

[0006] To solve the above problems, the present application provides a memory cell, comprising:

[0007] a device column having a first end and a second end opposite to each other along an axial direction of the device column; a gate structure surrounding the device column in a circumferential direction; a storage capacitor located on a side of the device column close to the first end along the axial direction of the device column, the storage capacitor being electrically connected to the first end of the device column; and an interconnection platform located on a side of the device column close to the second end along the axial direction of the device column, the interconnection platform being electrically connected to the second end of the device column.

[0008] Optionally, the material of the interconnection platform is the same as the material of the device column.

[0009] Optionally, the interconnection platform is integrally connected to the device column.

[0010] Optionally, the extension direction of the interconnection platform is perpendicular to the extension direction of the gate structure.

[0011] Optionally, in a plane perpendicular to the axial direction of the device pillar, the size of the projection of the interconnection platform in the direction of vertical extension is smaller than the size of the projection of the device pillar in the same direction.

[0012] Optionally, in a plane perpendicular to the axial direction of the device pillar, the geometric center of the projection of the interconnection platform does not coincide with the geometric center of the projection of the device pillar.

[0013] Optionally, one side of the interconnection platform is tangent to the side of the device pillar.

[0014] Optionally, the device pillar is cylindrical, and the storage capacitor is cylindrical.

[0015] Optionally, the gate structure comprises a gate electrode and a gate dielectric layer, and the gate dielectric layer is located between the gate electrode and the device pillar.

[0016] Optionally, in the axial direction of the device pillar, at least one side of the gate dielectric layer extends beyond the gate electrode.

[0017] Optionally, the material of the gate electrode is one of polysilicon or metal; and the material of the gate dielectric layer is oxide.

[0018] Optionally, the storage capacitor is located on the end surface of the first end.

[0019] Correspondingly, the application also provides a storage array, comprising:

[0020] A storage unit, which is the storage unit of the application, and in a plane perpendicular to the axial direction of the device pillar, a plurality of the storage units are arranged in an array.

[0021] Optionally, the storage units of adjacent rows are staggered in the row direction; and the storage units of adjacent columns are staggered in the column direction.

[0022] Optionally, the interconnection platforms of the storage units in the same column are integrally connected.

[0023] Optionally, in a plane perpendicular to the axial direction of the device pillar, in the storage units of adjacent columns, the offset directions of the geometric centers of the projections of the interconnection platforms relative to the geometric centers of the projections of the corresponding device pillars are opposite.

[0024] Optionally, the gate electrodes of the gate structures of the storage units in the same row are integrally connected.

[0025] Optionally, the application further comprises a bit line, which is located on the side of the interconnection platform away from the device pillar in the axial direction of the device pillar, and in a plane perpendicular to the axial direction of the device pillar, the bit line extends in the column direction; and the storage units in the same column are connected to the same bit line.

[0026] Optionally, a projection of the bit line overlaps a projection of the interconnection platform in a plane perpendicular to an axial direction of the device pillar.

[0027] Optionally, the bit line is located on a surface of the interconnection platform away from the device pillar.

[0028] Optionally, a material of the bit line and a material of the interconnection platform are mutually melted at an interface.

[0029] Optionally, at least a portion of a material of the bit line near a side of the interconnection platform is a metal silicide.

[0030] Optionally, storage units of adjacent columns are connected to 2 adjacent bit lines alternately.

[0031] Optionally, the memory array further comprises a word line extending in a row direction in a plane perpendicular to an axial direction of the device pillar; and storage units in a same row are connected to a same word line.

[0032] In addition, the application further provides a control method of a memory array, the memory array being the memory array of the application; the control method comprising: loading a first voltage to a bit line while loading a second voltage to an adjacent bit line, the second voltage being different from the first voltage.

[0033] Optionally, the memory array comprises a first bit line, a second bit line, a third bit line, …, an nth bit line arranged in sequence, wherein n is the number of bit lines; the step of loading a first voltage to a bit line while loading a second voltage to an adjacent bit line comprises: loading the first voltage to the 2p-1th bit line while loading the second voltage to the 2pth bit line, wherein p is an integer greater than 0.

[0034] Optionally, in the step of loading the first voltage to the 2p-1th bit line while loading the second voltage to the 2pth bit line, the first voltage is loaded to all the 2p-1th bit lines while the second voltage is loaded to all the 2pth bit lines.

[0035] Optionally, the step of loading a first voltage to a bit line while loading a second voltage to an adjacent bit line further comprises: loading the first voltage to the 2qth bit line while loading the second voltage to the 2q-1th bit line, wherein q is an integer greater than 0.

[0036] Optionally, in the step of loading the first voltage to the 2qth bit line while loading the second voltage to the 2q-1th bit line, the first voltage is loaded to all the 2qth bit lines while the second voltage is loaded to all the 2q-1th bit lines.

[0037] Optionally, the second voltage is a default voltage.

[0038] Correspondingly, the application also provides a storage device, comprising:

[0039] a storage array, which is the storage array of the application; a controller, which is adapted to load a first voltage to a bit line and load a second voltage to an adjacent bit line at the same time, wherein the second voltage is not equal to the first voltage.

[0040] Optionally, the storage array comprises a first bit line, a second bit line, a third bit line, …, an nth bit line arranged in sequence, wherein n is the number of the bit lines; the controller is adapted to load a first voltage to the 2p-1th bit line and load a second voltage to the 2pth bit line at the same time, wherein p is an integer greater than 0.

[0041] Optionally, the controller loads the first voltage to all the 2p-1th bit lines and loads the second voltage to all the 2pth bit lines at the same time.

[0042] Optionally, the controller is further adapted to load the first voltage to the 2qth bit line and load the second voltage to the 2q-1th bit line at the same time, wherein q is an integer greater than 0.

[0043] Optionally, the controller loads the first voltage to all the 2qth bit lines and loads the second voltage to all the 2q-1th bit lines at the same time.

[0044] Optionally, the second voltage is a default voltage.

[0045] In addition, the application also provides a manufacturing method of a storage device, comprising:

[0046] forming a device column, which has a first end and a second end along the axial direction of the device column; forming a gate structure which circumferentially surrounds the device column; forming a storage capacitor on the side of the device column close to the first end along the axial direction of the device column, wherein the storage capacitor is electrically connected to the first end; forming an interconnection platform, which is located on the side of the device column close to the second end along the axial direction of the device column, wherein the interconnection platform is electrically connected to the second end of the device column.

[0047] Optionally, the step of forming the device column comprises: providing a substrate; etching the substrate to form a substrate and a to-be-etched platform which protrudes from the front surface of the substrate; etching the to-be-etched platform to form a prefabricated platform and a device column which protrudes from the first surface of the prefabricated platform.

[0048] Optionally, in the step of etching the substrate to form a substrate and a to-be-etched platform which protrudes from the front surface of the substrate, there are discrete openings between adjacent to-be-etched platforms; after etching the substrate to form a substrate and a to-be-etched platform which protrudes from the front surface of the substrate and before etching the to-be-etched platform, the discrete openings are filled with a medium material.

[0049] Optionally, in the step of forming the device column, the device column protrudes from a first surface of a pre-preparation platform, and the pre-preparation platform protrudes from a front surface of a substrate; the step of forming the interconnection platform comprises: removing the substrate to expose the pre-preparation platform; and etching the pre-preparation platform to form the interconnection platform.

[0050] Optionally, the step of removing the substrate to expose the pre-preparation platform comprises: removing the substrate along a back surface of the substrate to expose a second surface of the pre-preparation platform, the back surface of the substrate being opposite to the front surface of the substrate, and the second surface of the pre-preparation platform being opposite to the first surface of the pre-preparation platform; and the step of etching the pre-preparation platform to form the interconnection platform comprises: etching the pre-preparation platform through the second surface of the pre-preparation platform to form the interconnection platform.

[0051] Optionally, the step of etching the pre-preparation platform to form the interconnection platform comprises: thinning the pre-preparation platform through the second surface of the pre-preparation platform; and forming a second opening penetrating through the thickness of the thinned pre-preparation platform to form the interconnection platform in the row direction.

[0052] Optionally, in the step of forming the second opening penetrating through the thickness of the thinned pre-preparation platform, the second opening penetrating through the thickness of the thinned pre-preparation platform is formed in a self-aligned manner.

[0053] Optionally, before the step of forming the second opening penetrating through the thickness of the thinned pre-preparation platform, a medium material filled in the discrete opening protrudes from the second surface of the thinned pre-preparation platform; and the step of forming the second opening penetrating through the thickness of the thinned pre-preparation platform comprises: forming a linear layer on the thinned pre-preparation platform and the medium material filled in the discrete opening; etching the linear layer to expose part of the surface of the thinned pre-preparation platform; and etching the exposed thinned pre-preparation platform to form the second opening.

[0054] Optionally, the method further comprises: forming a bit line on a side of the interconnection platform away from the device column along the axial direction of the device column, and the bit line is electrically connected to the interconnection platform.

[0055] Optionally, in the step of forming the bit line on the side of the interconnection platform away from the device column along the axial direction of the device column, the bit line is formed on the side of the interconnection platform away from the device column along the axial direction of the device column in a self-aligned manner.

[0056] Optionally, the step of forming the bit line on the side of the interconnection platform away from the device column along the axial direction of the device column comprises: forming a precursor metal layer on the surface of the interconnection platform; and performing annealing treatment to make the precursor metal layer and the interconnection platform react with each other to form the bit line.

[0057] Compared with the prior art, the technical scheme of the present application has the following advantages:

[0058] In the technical scheme, the gate structure surrounds the device column in the axial direction, and the storage capacitor is located on one side of the first end of the device column in the axial direction and connected with the first segment. The gate structure fully surrounds the device column, which can effectively ensure the control ability of the gate structure on the channel. In the storage unit, the channel in the device column extends in the axial direction. In the plane perpendicular to the axial direction of the device column, the area of the storage unit is small, which can effectively improve the storage density of the storage array including the storage unit. The interconnection platform electrically connected with the second end of the device column can provide a basis for the formation of subsequent bit lines, which can effectively reduce the process difficulty of the formation of the bit lines.

[0059] In the optional technical scheme, the interconnection platform is integrally connected with the device column, the material of the bit line and the material of the interconnection platform are mutually fused at the interface, and at least part of the material of the bit line near the side of the interconnection platform is a metal silicide. The bit line is a bit line formed through a self-alignment process. In the formation process of the bit line, the use of photolithography process can be effectively reduced, the process difficulty of the formation of the bit line can be effectively reduced, the influence of overlay accuracy on performance can be effectively avoided, the improvement of the device manufacturing yield is facilitated, and the improvement of the device performance is facilitated.

[0060] In the optional technical scheme, in the storage array, the storage units of adjacent rows are arranged in the column direction. The storage units of adjacent rows are arranged in the column direction, the storage units are densely packed in the plane perpendicular to the axial direction of the device column, the distribution density of the storage units can be effectively improved, the storage density is improved, a hardware basis for the odd-even interval operation mode is provided, the storage density is improved as much as possible, the area waste is reduced, and the read-write speed and the storage density can be considered.

[0061] In the optional technical scheme, the storage units of adjacent columns are connected with the bit lines adjacent in the row direction, a first voltage is loaded to one bit line, a second voltage is loaded to the adjacent bit line at the same time, and the second voltage is not equal to the first voltage. When the storage device works, the adjacent bit lines load unequal voltages, one bit line loads a first voltage to read out and write in data, and the adjacent bit line loads a second voltage to shield the coupling capacitance. The odd-even interval operation mode of the bit line can effectively shield the coupling effect between the bit lines, and the read-write operation speed can be effectively ensured.

[0062] In the optional technical scheme, the second voltage is a default voltage, that is, the second voltage is Vcc / 2. Without making great changes to the circuit inside the storage device, the technical scheme can be implemented, and the implementation process difficulty can be effectively reduced. BRIEF DESCRIPTION OF DRAWINGS

[0063] FIG. 1 is a circuit structure schematic diagram of a storage array.

[0064] Fig. 2 is a perspective structural schematic diagram of some embodiments of the storage array of the present application;

[0065] Fig. 3 is a top structural schematic diagram of some embodiments of the storage array of the present application in the direction of A in Fig. 2;

[0066] Fig. 4 is a sectional structural schematic diagram of some embodiments of the storage array of the present application in the position of the line B1B2 in Fig. 3;

[0067] Fig. 5 is a sectional structural schematic diagram of some embodiments of the storage array of the present application in the position of the line C1C2 in Fig. 3;

[0068] Fig. 6 is a circuit structural schematic diagram of some embodiments of the storage array of the present application;

[0069] Figs. 7 to 35 are structural schematic diagrams of the intermediate structures in each step of some embodiments of the manufacturing method of the storage device of the present application. DETAILED DESCRIPTION

[0070] As known from the background art, with the iteration of the storage device technology, the storage density of the storage device is required to be higher and higher, and it is more and more difficult to further improve the storage density of the storage device.

[0071] Moreover, with the improvement of the storage density, the size of each component in the storage device is required to be higher and higher, and each component is continuously reduced in size, and the distance between each component is continuously reduced. This results in the coupling between the storage units being stronger and stronger, and the coupling capacitance between the adjacent bit lines in the storage device being larger and larger.

[0072] Specifically, as shown in Fig. 1, in the storage array of the storage device, the storage units 11 are arranged in a rectangular array, and the row direction and the column direction of the storage array are perpendicular to each other. In the storage array, the bit lines BL extend along the column direction and are arranged in parallel along the row direction; the word lines WL extend along the row direction and are arranged in parallel along the column direction. The storage units 11 located in the same row are connected to the same word line WL; the storage units 11 located in the same column are connected to the same bit line BL.

[0073] When a word line WL loads a working voltage, all the storage units 11 located in the same row are enabled to work, i.e., all the bit lines BL can load a working voltage to make the storage units 11 in the whole row start to work at the same time. Since the distance between the adjacent bit lines BL is small, the coupling between the adjacent bit lines BL is strong, thereby affecting the sense margin of the storage device and affecting the further improvement of the read / write speed.

[0074] To solve the technical problem, the present application provides a storage unit, comprising:

[0075] a device column having a first end and a second end opposite to each other along an axial direction of the device column; a gate structure surrounding the device column along a circumferential direction and separated from the first end and the second end along the axial direction of the device column; a storage capacitor located on a side of the device column close to the first end along the axial direction of the device column and electrically connected to the first end of the device column; and an interconnection platform located on a side of the device column close to the second end along the axial direction of the device column and electrically connected to the second end of the device column.

[0076] In the storage unit, the gate structure surrounds the device column along the axial direction, and the storage capacitor is located on a side of the device column close to the first end along the axial direction and connected to the first end. The gate structure fully surrounds the device column, which can effectively ensure the control ability of the gate structure on the channel. In the storage unit, the channel in the device column extends along the axial direction. In a plane perpendicular to the axial direction of the device column, the area of the storage unit is small, which can effectively improve the storage density of the storage array including the storage unit. The interconnection platform electrically connected to the second end of the device column can provide a basis for the formation of subsequent bit lines, which can effectively reduce the process difficulty of the formation of the bit lines.

[0077] In order to make the above-mentioned purposes, features and advantages of the present application more obvious and easy to understand, the specific embodiments of the present application will be described in detail below with reference to the accompanying drawings.

[0078] Referring to FIGS. 2 to 5, the structural schematic diagram of an embodiment of the storage array of the present application is shown.

[0079] Among them, FIG. 2 is a perspective structural schematic diagram of an embodiment of the storage array of the present application; FIG. 3 is a top view structural schematic diagram of FIG. 2 along the A direction; FIG. 4 is a cross-sectional structural schematic diagram of FIG. 3 along the B1B2 line position; and FIG. 5 is a cross-sectional structural schematic diagram of FIG. 3 along the C1C2 line position.

[0080] The storage array includes storage units 101 arranged in a regular array.

[0081] The storage unit 101 comprises: a device pillar 110, the device pillar 110 having a first end (not shown in the figure) and a second end (not shown in the figure) opposite to each other along the axial direction of the device pillar 110; a gate structure 120, the gate structure 120 being circumferentially arranged around the device pillar 110; a storage capacitor 130, the storage capacitor 130 being arranged on the side of the device pillar 110 close to the first end along the axial direction of the device pillar 110, and the storage capacitor 130 being electrically connected to the first end of the device pillar 110; and an interconnection platform 140, the interconnection platform 140 being arranged on the side of the device pillar 110 close to the second end along the axial direction of the device pillar 110, and the interconnection platform 140 being electrically connected to the second end of the device pillar 110.

[0082] In the array plane parallel to the storage array, the area of the storage unit 101 is small, and the storage density of the storage array is large; and the storage unit 101 is a gate all around (GAA) storage unit, the control ability of the gate structure 120 to the channel is strong, and the performance of the storage array can be effectively ensured.

[0083] The interconnection platform 140 is integrally connected to the device pillar 110, can provide a basis for forming a bit line through a self-alignment process, can effectively reduce the use of a photolithography process in the process of forming a bit line, and can effectively reduce the process difficulty of forming a bit line.

[0084] The specific technical solutions of the embodiments of the storage array and the storage unit of the present application will be described in detail below with reference to the accompanying drawings.

[0085] The storage array comprises: storage units 101 arranged in a regular array. The storage unit 101 comprises a device pillar 110, a gate structure 120, and a storage capacitor 130.

[0086] The device pillar 110 is used to form a switching device to control the opening and closing of the storage unit 101.

[0087] Specifically, the material of the device pillar 110 is silicon. For example, the material of the device pillar 110 can be selected from single crystal silicon, polycrystalline silicon, or amorphous silicon. In other embodiments of the present application, the material of the device pillar can also be other semiconductor materials; for example, the material of the device pillar can also be germanium, gallium arsenide, or other group IV semiconductors or group III-V semiconductors, and the material of the device pillar can even be group II-VI semiconductors. The material of the device pillar can be selected from any suitable material for forming a switching device.

[0088] The device pillar 110 has an axial direction along which the device pillar 110 extends; along the axial direction of the device pillar 110, the device pillar 110 has a first end and a second end, wherein the first end is adapted to be connected to the storage capacitor 130; and the second end is adapted to be connected to a bit line BL.

[0089] As shown in FIGS. 2-5, in some embodiments of the present application, the device pillar 110 is cylindrical. The device pillar 110 is arranged in a cylindrical shape to minimize sharp corner structures and avoid excessive concentration of electric field, which can affect the performance of the storage unit. In a plane perpendicular to the axial direction of the device pillar 110, the end faces of the first end and the second end of the device pillar 110 are both circular.

[0090] The gate structure 120 is adapted to control the conduction and cutoff of the channel of the switching device formed by the device pillar 110.

[0091] The device pillar 110 also has a circumferential direction around the axial direction thereof; the gate structure 120 surrounds the device pillar 110 along the circumferential direction; in the storage unit, the channel in the device pillar 110 extends along a direction perpendicular to the axial direction of the device pillar 110; and the storage unit 101 is a gate all around (GAA) storage unit, the control ability of the gate structure 120 over the channel is strong, which can effectively ensure the performance of the storage array.

[0092] In some embodiments of the present application, the gate structure 120 includes a gate electrode 122 and a gate dielectric layer 121, and the gate dielectric layer 121 is located between the gate electrode 122 and the device pillar 110. The gate electrode 122 is adapted to be electrically connected to an external circuit, and the gate dielectric layer 121 is adapted to achieve electrical insulation between the gate electrode 122 and the device pillar 110.

[0093] In some embodiments, the gate structure 120 is one of a polysilicon gate structure and a metal gate structure. In some example embodiments, the material of the gate electrode 122 is one of polysilicon and metal; and the material of the gate dielectric layer 121 is an oxide, for example, the oxide can be silicon oxide or a high-K gate dielectric layer.

[0094] In some embodiments of the present application, in a plane perpendicular to the axial direction of the device pillar 110, the gate structure 120 extends along a predetermined direction. The extension direction of the gate structure 120 is perpendicular to the axial direction of the device pillar 110. For example, as shown in FIGS. 2-5, the gate structure 120 extends along a first direction x.

[0095] In some embodiments, at least one side of the gate dielectric layer 121 extends beyond the gate electrode 122 along the axial direction of the device pillar 110. As shown in FIGS. 2-5, both sides of the gate dielectric layer 121 extend beyond the gate electrode 122 along the axial direction of the device pillar 110; the size of the gate dielectric layer 121 along the axial direction of the device pillar 110 is greater than the size of the gate electrode 122 along the axial direction of the device pillar 110, and the gate electrode 122 is located on the surface of the gate dielectric layer 121.

[0096] The storage capacitor 130 is adapted to store data.

[0097] Along the axial direction of the device pillar 110, the storage capacitor 130 is located on one side of the first end of the device pillar 110. The device pillar 110 and the storage capacitor 130 are stacked along the axial direction of the device pillar 110; in the plane perpendicular to the axial direction of the device pillar 110, the projection area of the storage unit is small.

[0098] In some embodiments of the present application, the storage capacitor 130 is located on the end surface of the first end of the device pillar 110; the surface of the storage capacitor 130 facing the device pillar 110 directly contacts the end surface of the first end of the device pillar 110 to achieve electrical connection between the storage capacitor 130 and the device pillar 110.

[0099] As shown in FIGS. 2-5, in some embodiments of the present application, the storage capacitor 130 is cylindrical. The storage capacitor 130 is set to be cylindrical to minimize sharp corner structures and avoid excessive concentration of electric field to cause sharp tip discharge and affect the performance of the storage unit.

[0100] With reference to FIGS. 2-5, the interconnection platform 140 electrically connected to the second end of the device pillar 110 is adapted to achieve electrical connection between the device pillar 110 and the bit line BL. The interconnection platform 140 can also provide a process basis for the formation of the bit line BL, so that the bit line BL can be formed in a self-alignment manner to reduce the difficulty of the formation process of the bit line BL.

[0101] In some embodiments of the present application, the material of the interconnection platform 140 is the same as the material of the device pillar 110. In some example embodiments, the material of the device pillar 110 is silicon, and the material of the interconnection platform 140 is also silicon. In other embodiments, when the device pillar 140 is of other materials, the interconnection platform 140 can also be of other materials.

[0102] In some embodiments, the interconnection platform 140 is integrally connected with the device pillar 110. There is no obvious boundary between the interconnection platform 140 and the device pillar 110, and the interconnection platform 140 and the device pillar 110 can be formed by etching the same bulk material.

[0103] In some embodiments of the application, the extension direction of the interconnection platform 140 is perpendicular to the extension direction of the gate structure 120. The extension direction of the interconnection platform 140 is also perpendicular to the axial direction of the device pillar 110. Both the interconnection platform 140 and the gate structure extend in a plane perpendicular to the axial direction of the device pillar 110. For example, as shown in FIGS. 2-5, the gate structure 120 extends along a first direction x, and the interconnection platform 140 extends along a second direction y.

[0104] In some embodiments of the application, in the plane perpendicular to the axial direction of the device pillar 110, the size of the projection of the interconnection platform 140 in the direction perpendicular to the extension direction is smaller than the size of the projection of the device pillar 110 in the same direction. Specifically, in the plane perpendicular to the axial direction of the device pillar 110, the width of the interconnection platform 140 is smaller than the diameter of the device pillar 110. This can achieve close arrangement of the memory cells 101 while separating the interconnection platforms 140 of the memory cells 101 in adjacent columns, and can achieve separation of the bit lines BL while ensuring storage density.

[0105] As shown in FIGS. 2-5, the interconnection platform 140 extends along the second direction y, and in the plane perpendicular to the axial direction of the device pillar 110, the size of the interconnection platform 140 along the first direction x is smaller than the size of the device pillar 110 along the first direction x.

[0106] In some embodiments of the application, in the plane perpendicular to the axial direction of the device pillar 110, the geometric center of the projection of the interconnection platform 140 does not coincide with the geometric center of the projection of the device pillar 110. Specifically, in a memory cell 101, in the plane perpendicular to the axial direction of the device pillar 110, the interconnection platform 140 is biased to one side of the device pillar 110 along the first direction x.

[0107] As shown in FIGS. 2-5, in a memory cell 101, in the plane perpendicular to the axial direction of the device pillar 110, the geometric center of the projection of the interconnection platform 140 is located on one side of the geometric center of the projection of the device pillar 110 along the first direction x.

[0108] In some embodiments of the application, one side of the interconnection platform 140 is tangent to the side of the device pillar 110. In a memory cell 101, in the plane perpendicular to the axial direction of the device pillar 110, the projection of the interconnection platform 140 and the projection of the device pillar 110 have tangent edges.

[0109] Specifically, one side of the two sides of the interconnection platform 140 arranged opposite along the first direction x is tangent to the side of the device pillar 110. As shown in FIG. 3, in a storage unit 101, the projection of the interconnection platform 140 in a plane perpendicular to the axial direction of the device pillar 101 is tangent to the projection of the device pillar 110 along one of the two edges of the first direction.

[0110] With reference to FIG. 2 and FIG. 3 to FIG. 5, the storage array has an array plane, and a plurality of storage units 110 in the storage array are regularly arranged in a row direction and a column direction in the array plane.

[0111] It should be noted that in FIG. 2 to FIG. 5, the first direction x and the second direction y are parallel to the array plane, and the first direction x and the second direction y are perpendicular to each other; the third direction z is perpendicular to the array plane. The first direction x is the row direction, and the second direction z is the column direction.

[0112] It should be further noted that in some embodiments as shown in FIG. 2 to FIG. 5, the row direction and the column direction are perpendicular to each other; in other embodiments of the present application, the row direction and the column direction can also intersect but not be perpendicular.

[0113] As shown in FIG. 2 to FIG. 5, in some embodiments, the device pillar 110 is perpendicular to the array plane of the storage array; the axial direction of the device pillar 110 is perpendicular to the array plane; the array plane is a plane perpendicular to the axial direction of the device pillar 110; the projection area of the storage unit in the array plane of the storage array is small; and the storage density of the storage array is large.

[0114] It should be noted that the axial direction of the device pillar 110 is perpendicular to the array plane; the array plane is a plane perpendicular to the axial direction of the device pillar 110; and the circumferential direction of the device pillar 110 is parallel to the array plane. The gate structure 120 extends in a plane perpendicular to the axial direction of the device pillar 110, and the gate structure 120 extends in a plane parallel to the array plane.

[0115] In some embodiments of the present application, the gate electrode 122 of the gate structure 120 is integrally connected in the storage unit 101 adjacent along the extension direction of the gate structure; and the gate electrode 120 of the gate structure 120 is separated in the storage unit 101 adjacent along the direction perpendicular to the extension direction of the gate structure.

[0116] In some embodiments, the storage units 101 are arranged in an array, and the gate structures 120 of the storage units 101 extend along a row direction, and the gate electrodes 122 of the gate structures 120 of the storage units 101 adjacent in the row direction are integrally connected, so that the switching devices of the storage units 101 in the same row are simultaneously turned on under row selection; and the gate electrodes 122 of the gate structures 120 of the storage units 101 adjacent in a column direction are separated, so that the switching devices of the storage units 101 are independently operated under row and column selection.

[0117] As shown in FIGS. 2-5, in some embodiments, the gate structures 120 extend along a first direction x; the gate electrodes 122 of the gate structures 120 of the storage units 101 adjacent in the first direction x are integrally connected; and the gate electrodes 122 of the gate structures 120 of the storage units 101 adjacent in a second direction y are separated.

[0118] In some embodiments, the gate electrodes 122 of the gate structures 120 of the storage units 101 in the same row are integrally connected. Specifically, the gate electrodes 122 are in the shape of long strips; in the array plane, the gate electrodes 122 extend along the row direction (i.e., the first direction x) and across the range in which the device pillars 110 are distributed; and each device pillar 110 and the gate electrode 122 have a gate dielectric layer 121 therebetween.

[0119] With reference to FIG. 6, in some embodiments of the present application, the storage units 101 in adjacent rows are staggered in the row direction; and the storage units 101 in adjacent columns are staggered in the column direction. In the column direction, a storage unit 101 is located between two adjacent storage units 101 in adjacent rows; and in the row direction, a storage unit 101 is located between two adjacent storage units 101 in adjacent columns. In the storage array, the storage units 101 are arranged in a hexagonal close-packed manner; the arrangement density of the storage units 101 is higher, and the storage density of the storage array is higher.

[0120] As shown in FIG. 3, in the second direction y, a storage unit 101 is located between two adjacent storage units 101 in adjacent rows; and in the first direction x, a storage unit 101 is located between two adjacent storage units 101 in adjacent columns.

[0121] Specifically, the storage units have a first row, a second row, …, and an mth row arranged in sequence in the column direction, where m is the number of rows of the storage units in the storage array; the storage units have a first column, a second column, …, and an nth column arranged in sequence in the row direction, where n is the number of columns of the storage units in the storage array; the storage units in the ith row are staggered with the storage units in the (i+1)th row in the row direction; and the storage units in the jth column are staggered with the storage units in the (j+1)th column in the column direction, where i is an integer greater than or equal to 1 and less than or equal to m, and j is an integer greater than or equal to 1 and less than or equal to n.

[0122] As shown in FIG. 3 and FIG. 6, the storage units 101b and 101d are located in the same row, and the storage units 101a and 101c are located in a row adjacent to the row in which the storage units 101b and 101d are located; along the row direction, the storage units 101a and 101c are located between the storage units 101b and 101d. The storage units 101a and 101c are located in the same column, and the storage units 101b and 101d are located in a column adjacent to the column in which the storage units 101a and 101c are located; along the column direction, the storage units 101b and 101d are located between the storage units 101a and 101c.

[0123] In some embodiments, the interconnection platforms 140 of the storage units 101 in the same column are integrally connected. In a storage unit 101, the interconnection platform 140 extends in the array plane along the column direction; as shown in FIG. 2 and FIG. 3, in the array plane, the interconnection platforms 140 in the storage units 101 extend along the second direction y; the interconnection platforms of the storage units 101 arranged along the second direction y are integrally connected.

[0124] In addition, in some embodiments as shown in FIG. 3, the storage units 101 in adjacent rows are staggered along the row direction, and the storage units 101 in adjacent rows are in different columns; the storage units 101 in alternate rows are in the same column; the interconnection platforms 140 of the storage units 101 in alternate rows are integrally connected.

[0125] In some embodiments, the interconnection platforms 140 of the storage units 101 in the same row are separated. The interconnection platforms 140 of the storage units 101 in the same row are arranged in parallel with each other; as shown in FIG. 2 and FIG. 3, in the array plane, the interconnection platforms 140 in the storage units 101 are arranged in parallel along the first direction x.

[0126] In some embodiments, in a plane perpendicular to the axial direction of the device pillars 110, in the storage units 101 in adjacent columns, the geometric centers of the projections of the interconnection platforms 140 are offset in opposite directions relative to the geometric centers of the projections of the corresponding device pillars 110.

[0127] Specifically, in the array plane, the interconnection platforms 140 of two adjacent columns of storage units 101 are offset in different directions relative to the corresponding device pillars 110. For example, in the array plane, the interconnection platforms 140 of one column of storage units 101 are offset to one side relative to the corresponding device pillars 110 along the first direction x; the interconnection platforms 140 of the adjacent column of storage units 101 are offset to the other side relative to the corresponding device pillars 110 along the first direction x.

[0128] As shown in FIGS. 3-5, the interconnection platform 140 of the memory cell 101a is biased to one side of the device pillar 110 of the memory cell 101a along the first direction x; the memory cell 101b is adjacent to the memory cell 101a along the row direction, and the interconnection platform 140 of the memory cell 101b is biased to the other side of the device pillar 110 of the memory cell 101b along the first direction x.

[0129] With continued reference to FIGS. 3-6, in some embodiments of the present application, the memory array further comprises a bit line BL (as shown by the solid and dashed lines extending along the column direction in FIG. 6) located on the side of the interconnection platform 140 away from the device pillar 110 along the axial direction of the device pillar 110, and the bit line BL extends along the column direction in the plane perpendicular to the axial direction of the device pillar 110; the memory cells 101 in the same column are connected to the same bit line BL.

[0130] The bit line BL is electrically connected to the second end of the device pillar 110 through the interconnection platform 140 to implement the operation of data in the memory cell.

[0131] In some embodiments, the bit line BL is located on the surface of the side of the interconnection platform 140 away from the device pillar 110. The bit line BL is directly located on the surface of the side of the interconnection platform 140 away from the device pillar 110, i.e., the surface of the bit line BL close to the device pillar 110 is in contact with the surface of the interconnection platform 140 away from the device pillar 110.

[0132] In some embodiments, at least the portion of the material of the bit line BL close to the side of the interconnection platform 140 is a metal silicide. The bit line BL is formed by a self-alignment process, i.e., formed by metalizing the portion of the material of the interconnection platform 140 away from the device pillar 110; the material of the interconnection platform 140 is silicon, and the material of the bit line BL is metal silicide.

[0133] In some embodiments, the material of the bit line BL and the material of the interconnection platform 140 are inter-melted at the interface. The bit line BL is formed by a self-alignment process, i.e., formed by metalizing the portion of the material of the interconnection platform 140 away from the device pillar 110; during the self-alignment process, the metal material diffuses to the material of the bit line BL, so that the two materials are inter-melted at the interface to form the bit line BL; the material of the bit line BL and the material of the interconnection platform 140 are inter-melted at the interface, and there is no obvious boundary between them.

[0134] In some embodiments, a projection of the bit line BL overlaps with a projection of the interconnection platform 140 in a plane perpendicular to the axial direction of the device pillar 110. The bit line BL is formed by a self-alignment process; the size and position of the interconnection platform 140 determine the size and position of the bit line BL in the plane perpendicular to the axial direction of the device pillar 110; the position of the bit line BL coincides with the position of the interconnection platform 140, and the size of the bit line BL is the same as the size of the interconnection platform 140 everywhere.

[0135] In some embodiments, the storage units in the same column are connected to the same bit line BL. In a plane perpendicular to the axial direction of the device pillar 110, the bit line BL extends in the column direction (i.e., the second direction y in FIG. 3) and is arranged in sequence in the row direction (i.e., the first direction x in FIG. 3); in the column direction, the bit line BL spans multiple rows of the storage units and is connected to all of the multiple rows of the storage units. Specifically, the storage unit has n bit lines BL, which are the 1st bit line, the 2nd bit line, …, and the nth bit line, and n bit lines correspond to n rows of storage units in sequence one by one.

[0136] In some embodiments, the storage units in adjacent columns are staggered in the column direction; in a plane perpendicular to the axial direction of the device pillar 110, the bit line BL extends in the column direction; and the storage units in adjacent columns are connected to adjacent two bit lines BL in a staggered manner.

[0137] Specifically, the storage units in the odd rows (or even rows) in the a-th column are connected to the a-th bit line (as shown by the solid line in FIG. 6), and the storage units in the even rows (or odd rows) in the a+1-th column are connected to the a+1-th bit line (as shown by the dashed line in FIG. 6), where a is an integer greater than or equal to 1 and less than or equal to n-1.

[0138] As shown in FIG. 6, in some embodiments of the application, the storage array further includes a word line WL (as shown by the dashed and solid lines extending in the row direction in FIG. 6), which extends in the row direction in a plane perpendicular to the axial direction of the device pillar 110; and the storage units in the same row are connected to the same word line WL.

[0139] In a plane perpendicular to the axial direction of the device pillar 110 (i.e., the array plane of the storage array), the word line WL extends in the row direction (i.e., the first direction x in FIG. 3) and is arranged in sequence in the column direction (i.e., the second direction y in FIG. 3); in the row direction, the word line WL spans multiple columns of the storage units and is connected to all of the multiple columns of the storage units.

[0140] Specifically, the storage unit has m word lines WL, which are the 1st word line, the 2nd word line, …, and the mth word line, and m word lines correspond to m rows of storage units in sequence one by one.

[0141] As shown in FIG. 2 to FIG. 5, one word line WL is connected with the gate structures of the storage units in the same row. Specifically, in the gate structure 120 of the storage units in the same row, the gate electrodes 122 extend along the row direction and are integrally connected; one word line WL is connected with the storage units in the same row through the integrally connected gate electrodes 122.

[0142] In some embodiments, the storage units in adjacent rows are staggered along the row direction; in the plane perpendicular to the axial direction of the device pillar 110, the word lines WL extend along the row direction; the storage units in adjacent rows are connected with two adjacent word lines WL alternately.

[0143] Specifically, the storage units in the odd columns (or even columns) in the bth row are connected with the bth word line (as shown by the solid line extending along the row direction in FIG. 6), and the storage units in the even columns (or odd columns) in the b+1th row are connected with the b+1th word line (as shown by the dashed line extending along the row direction in FIG. 6), where b is an integer greater than or equal to 1 and less than or equal to m-1.

[0144] Correspondingly, the application also provides a control method of a storage array.

[0145] In combination with reference to FIG. 6, the storage device comprises a storage array, which is the storage array of the application; the control method comprises: loading a first voltage to one bit line while loading a second voltage to an adjacent bit line, the second voltage being different from the first voltage.

[0146] As shown in FIG. 2 to FIG. 5, the storage array is the storage array of the application. The specific technical solutions of the storage array are reasonable and refer to the foregoing storage array of the application, which will not be described herein again.

[0147] In the control method, different voltages are loaded to adjacent bit lines at the same time, so that the two adjacent bit lines BL play different roles: one of the bit lines BL is used to operate the connected storage unit 101 (for example, one of the read operation, write operation and erase operation), and the other bit line BL is used to shield the coupling effect of other bit lines BL.

[0148] The first voltage is suitable for operating the loaded storage unit 101, and the first voltage is the operating voltage for operating the connected storage unit 101, which is determined based on the operation of the storage unit 101.

[0149] In some embodiments of the example, the first voltage is a read voltage in the read operation; in some embodiments of the example, the first voltage is a write voltage in the write operation; and in some embodiments of the example, the first voltage is an erase voltage in the erase operation.

[0150] Specifically, the read voltage is suitable for reading data stored in the connected memory cell; the write voltage is suitable for writing data into the connected memory cell; and the erase voltage is suitable for erasing data stored in the connected memory cell.

[0151] The second voltage is suitable for avoiding adjacent bit lines from being in a floating state so that the loaded bit line BL can play a role of shielding coupling.

[0152] In some embodiments, the second voltage is a default voltage. By setting the second voltage as a default voltage, the adjacent bit lines can be avoided from being in a floating state without introducing a new voltage and without making great changes to the circuit, so that the generation and loading of the second voltage can be realized and the process difficulty can be effectively reduced.

[0153] For example, the second voltage is half of the voltage (Vcc) of the access circuit, Vcc / 2. In other embodiments of the present application, the second voltage can also be other fixed voltage values to avoid the loaded bit line from being in a floating state.

[0154] In some embodiments, the memory array includes a first bit line, a second bit line, a third bit line,..., and an nth bit line arranged in sequence, where n is the number of bit lines; and the step of loading the first voltage to a bit line and loading the second voltage to an adjacent bit line includes: loading the first voltage to the 2p-1th bit line and loading the second voltage to the 2pth bit line, where p is an integer greater than 0.

[0155] Specifically, the first voltage is loaded to the 2p-1th bit line (as shown by the solid line extending along the column direction in FIG. 6) to operate the connected memory cell 101; and the second voltage is loaded to the 2pth bit line (as shown by the dashed line extending along the column direction in FIG. 6) to shield the coupling effect of the surrounding other bit lines BL.

[0156] With reference to FIG. 6, in some specific embodiments, in the step of loading the first voltage to the 2p-1th bit line and loading the second voltage to the 2pth bit line, the first voltage is loaded to all the 2p-1th bit lines and the second voltage is loaded to all the 2pth bit lines.

[0157] Meanwhile, all the 2p-1 bit lines are loaded with the first voltage to operate the corresponding connected memory cells 101, and meanwhile, all the 2p bit lines are loaded with the second voltage, so that the bit lines loaded with the first voltage (as shown by the solid lines extending along the column direction in Fig. 6) are spaced from the bit lines loaded with the second voltage (as shown by the dashed lines extending along the column direction in Fig. 6), and the bit lines loaded with the second voltage are arranged between the adjacent bit lines loaded with the first voltage, thereby effectively reducing or even eliminating the coupling between the adjacent bit lines loaded with the first voltage.

[0158] In addition, in some embodiments, the step of loading the first voltage to one bit line and loading the second voltage to the adjacent bit line further comprises: loading the first voltage to the 2q bit line and loading the second voltage to the 2q-1 bit line, wherein q is an integer greater than 0.

[0159] Specifically, the first voltage is loaded to the 2q-1 bit line (as shown by the dashed lines extending along the column direction in Fig. 6) to operate the connected memory cells 101, and meanwhile, the second voltage is loaded to the 2q bit line (as shown by the solid lines extending along the column direction in Fig. 6) to shield the coupling effect of the surrounding other bit lines BL.

[0160] In some specific embodiments, in the step of loading the first voltage to the 2q bit line and loading the second voltage to the 2q-1 bit line, the first voltage is loaded to all the 2q bit lines and the second voltage is loaded to all the 2q-1 bit lines, so that the bit lines loaded with the first voltage (as shown by the dashed lines extending along the column direction in Fig. 6) are spaced from the bit lines loaded with the second voltage (as shown by the solid lines extending along the column direction in Fig. 6), and the bit lines loaded with the second voltage are arranged between the adjacent bit lines loaded with the first voltage.

[0161] The first voltage is loaded to all the odd bit lines and the second voltage is loaded to all the even bit lines, and the second voltage is loaded to all the even bit lines and the first voltage is loaded to all the odd bit lines, so that the bit lines are in the odd-even interval operation mode when the storage device is in operation, thereby effectively shielding the coupling effect between the bit lines and effectively ensuring the speed of read and write operation.

[0162] In some embodiments of the application, the storage array further has a plurality of word lines WL (as shown by the solid lines or dashed lines extending along the row direction in Fig. 6), and specifically, the storage array further comprises a first word line, a second word line, …, and an mth word line arranged in sequence, wherein m is the number of word lines; and the control method further comprises: loading a working voltage to one word line.

[0163] The working voltage is loaded to one word line to realize the row selection of the memory cells 101.

[0164] Specifically, the time for loading the working voltage to the word line WL is not later than the time for loading the first voltage to the bit line and loading the second voltage to the adjacent bit line: in some embodiments, the working voltage is loaded to the word line WL at the same time as the first voltage is loaded to the bit line and the second voltage is loaded to the adjacent bit line; in other embodiments, the working voltage is loaded to the word line WL after the first voltage is loaded to the bit line and the second voltage is loaded to the adjacent bit line.

[0165] In some embodiments, in the storage array, the storage units of adjacent rows are alternately connected to the adjacent two word lines WL, and the storage units of adjacent columns are alternately connected to the adjacent two bit lines BL.

[0166] When the working voltage is loaded to the second c-1 word line (as shown by a solid line in Fig. 6) to open the connected storage unit, the first voltage is loaded to all the second p-1 bit lines to make all the second p-1 bit lines work, and the second voltage is loaded to the second p bit lines between the working second p-1 bit lines to play a metal shielding role; when the working voltage is loaded to the second c word line (as shown by a dashed line in Fig. 6) to open the connected storage unit, the first voltage is loaded to all the second q bit lines to make all the second q bit lines work, and the second voltage is loaded to the second q-1 bit lines between the working second q bit lines to play a metal shielding role.

[0167] Correspondingly, the application also provides a storage device.

[0168] Referring to Fig. 6, a circuit structure schematic diagram of an embodiment of the storage device of the application is shown.

[0169] The storage device comprises: a storage array, which is the storage array of the application; and a controller, which is adapted to load the first voltage to a bit line at the same time as loading the second voltage to the adjacent bit line, and the second voltage is not equal to the first voltage.

[0170] As shown in Figs. 2 to 5, the storage array is the storage array of the application. The specific technical solutions of the storage array are reasonable and are described above, and the application will not be described here.

[0171] It should be noted that in some embodiments, the controller is adapted to perform each step of the control method of the application. The specific technical solutions of the controller can be referred to the embodiments of the control method described above.

[0172] The controller is connected to the bit line BL and loads the voltage to the bit line BL to make the bit line BL work.

[0173] Specifically, the controller loads different voltages to adjacent bit lines BL at the same time, so that the adjacent two bit lines BL play different roles: one of the bit lines BL is used to operate the connected memory cell 101 (for example, one of read operation, write operation and erase operation), and the other bit line BL is used to shield the coupling effect of other bit lines BL.

[0174] The first voltage is suitable for operating the loaded memory cell 101, and the first voltage is an operating voltage for operating the connected memory cell 101, and the first voltage is determined based on the operation of the memory cell 101.

[0175] In some embodiments of the example, the first voltage is a read voltage during read operation; in some embodiments of the example, the first voltage is a write voltage during write operation; and in some embodiments of the example, the first voltage is an erase voltage during erase operation.

[0176] Specifically, the read voltage is suitable for reading the data stored in the connected memory cell; the write voltage is suitable for writing data into the connected memory cell; and the erase voltage is suitable for erasing the data stored in the connected memory cell.

[0177] The second voltage is suitable for avoiding the adjacent bit line BL from being in a floating state so that the loaded bit line BL can play a role in shielding coupling.

[0178] In some embodiments, the second voltage is a default voltage. By setting the second voltage as a default voltage, the adjacent bit line BL can be avoided from being in a floating state without introducing a new voltage, without making large changes to the circuit to generate and load the second voltage, and the process difficulty can be effectively reduced.

[0179] For example, the second voltage is half of the voltage (Vcc) of the access circuit, Vcc / 2. In other embodiments of the application, the second voltage can also be other fixed voltage values to avoid the loaded bit line from being in a floating state.

[0180] With reference to FIG. 6, the controller controls in a way that the bit lines BL are operated in an odd-even interval manner.

[0181] In some embodiments of the application, the memory array includes a first bit line, a second bit line, a third bit line, …, and an nth bit line arranged in sequence, where n is the number of bit lines; the controller loads the first voltage to the (2p-1)th bit line and loads the second voltage to the (2p)th bit line, where p is an integer greater than 0.

[0182] As shown in Fig. 6, specifically, the controller comprises a first control element 141 connected to the bit lines BL; the first control element 141 loads a first voltage to the 2p-1 bit lines to operate the connected memory cells 101, and loads a second voltage to the 2p bit lines to shield the coupling effect of the surrounding bit lines BL.

[0183] In some embodiments, the controller loads the first voltage to all the 2p-1 bit lines and loads the second voltage to all the 2p bit lines. When operating the connected memory cells 101, the first voltage is loaded to all the 2p-1 bit lines, and the second voltage is loaded to all the 2p bit lines. The bit lines loaded with the first voltage (shown as solid lines extending along the column direction in Fig. 6) are spaced apart from the bit lines loaded with the second voltage (shown as dashed lines extending along the column direction in Fig. 6), and the bit lines loaded with the second voltage are arranged between the adjacent bit lines loaded with the first voltage, which can effectively reduce or even eliminate the coupling between the adjacent bit lines loaded with the first voltage.

[0184] For example, as shown in Fig. 6, the controller has a first control element 141 connected to a plurality of the bit lines BL; the first control element 141 loads the first voltage to all the 2p-1 bit lines and loads the second voltage to all the 2p bit lines at the same time.

[0185] In addition, in some embodiments, the controller loads the first voltage to the 2q bit lines and loads the second voltage to the 2q-1 bit lines, where q is an integer greater than 0. Specifically, as shown in some embodiments in Fig. 6, the first control element 141 loads the first voltage to the 2q-1 bit lines to operate the connected memory cells 101, and loads the second voltage to the 2q bit lines to shield the coupling effect of the surrounding bit lines BL.

[0186] In corresponding embodiments, the controller loads the first voltage to all the 2q bit lines and loads the second voltage to all the 2q-1 bit lines, which also makes the bit lines loaded with the first voltage (shown as dashed lines extending along the column direction in Fig. 6) spaced apart from the bit lines loaded with the second voltage (shown as solid lines extending along the column direction in Fig. 6), and the bit lines loaded with the second voltage are arranged between the adjacent bit lines loaded with the first voltage.

[0187] The controller loads a first voltage to all odd-numbered bit lines and a second voltage to even-numbered bit lines; the controller loads the second voltage to all even-numbered bit lines and the first voltage to odd-numbered bit lines; when the memory device is working, the bit lines are in an odd-even interval working mode, so as to effectively shield the coupling effect between the bit lines and effectively ensure the speed of read and write operations.

[0188] With continuous reference to FIG. 6, in some embodiments of the present application, the memory array further has a plurality of word lines WL (as shown by solid lines or dashed lines extending along the row direction in FIG. 6). Specifically, the memory array further includes a first word line, a second word line, …, and an mth word line arranged in sequence, where m is the number of word lines; the controller loads a working voltage to the word lines.

[0189] As shown in FIG. 6, specifically, the controller further includes a second control element 142 connected with the word lines WL; the second control element 142 loads a working voltage to a word line to open the connected memory cells, so as to perform row selection on the memory cells 101.

[0190] Specifically, the second control element 142 loads a working voltage to a word line WL no later than the time when the first control element 141 loads a first voltage to a bit line BL and a second voltage to an adjacent bit line BL; in some embodiments, the second control element 142 loads a working voltage to a word line WL at the same time when the first control element 141 loads a first voltage to a bit line and a second voltage to an adjacent bit line; in other embodiments, the second control element 142 loads a working voltage to a word line WL, and then the first control element 141 loads a first voltage to a bit line and a second voltage to an adjacent bit line.

[0191] In some embodiments, in the memory array, the memory cells of adjacent rows are alternately connected with two adjacent word lines WL; and the memory cells of adjacent columns are alternately connected with two adjacent bit lines BL.

[0192] When the memory array is working, a working voltage is loaded to the 2c-1th word line (as shown by a solid line in FIG. 6) to open the connected memory cells, a first voltage is loaded to all 2p-1th bit lines to make all 2p-1th bit lines work, and a second voltage is loaded to the 2pth bit lines between the working 2p-1th bit lines to play a metal shielding role; a working voltage is loaded to the 2cth word line (as shown by a dashed line in FIG. 6) to open the connected memory cells, a first voltage is loaded to all 2qth bit lines to make all 2qth bit lines work, and a second voltage is loaded to the 2q-1th bit lines between the working 2qth bit lines to play a metal shielding role.

[0193] Further, the application also provides a manufacturing method of the storage device.

[0194] It should be noted that the manufacturing method is suitable for manufacturing the storage device of the application. The specific embodiments of the manufacturing method can refer to the embodiments of the storage device described above.

[0195] Referring to FIGS. 7 to 35, structural schematic diagrams of intermediate structures in respective steps of some embodiments of the manufacturing method of the storage device of the application are shown.

[0196] Referring to FIG. 7, refer to FIGS. 8 to 13, wherein FIG. 8 is a structural schematic diagram of the top view of FIG. 7 along the direction of A1; FIG. 9 is a structural schematic diagram of the cross section of FIG. 8 along the line of B1B2; FIG. 11 is a structural schematic diagram of the top view of FIG. 10 along the direction of A2; FIG. 12 is a structural schematic diagram of the cross section of FIG. 11 along the line of C1C2; and FIG. 13 is a structural schematic diagram of the cross section of FIG. 11 along the line of D1D2.

[0197] First, a device pillar 110 is formed, which has a second end and a first end opposite to each other along the axial direction of the device pillar 110.

[0198] The device pillar 110 is used to form a switching device to control the opening and closing of the storage unit.

[0199] In some embodiments of the application, the step of forming the device pillar 110 comprises: providing a substrate; etching the substrate to form a substrate 102 and a to-be-etched platform 109 protruding from the front surface of the substrate 102, as shown in FIGS. 7 to 9; etching the to-be-etched platform 109 to form a pre-preparation platform 108 and a device pillar 110 protruding from the surface of the pre-preparation platform 108, as shown in FIGS. 10 to 13.

[0200] The substrate is used to provide a process basis and mechanical support.

[0201] Specifically, the material of the substrate is silicon. For example, the material of the substrate can be selected from single crystal silicon, polycrystalline silicon or amorphous silicon. In other embodiments of the application, the material of the substrate can also be other semiconductor materials. For example, the material of the substrate can be germanium, silicon germanium or other group IV semiconductor materials; the material of the substrate can be gallium arsenide or other group III-V semiconductor materials; or even, the material of the substrate can be group II-VI semiconductor materials. The material of the substrate can be selected from any suitable material for forming a switching device.

[0202] The substrate 102 is suitable for providing mechanical support during the process; and the to-be-etched platform 109 is used to form the pre-preparation platform 108 and the device pillar 110.

[0203] The substrate 102 and the to-be-etched platform 109 are etched from the base, and the material of the substrate 102 and the device column 110 corresponds to the material of the base. In some example embodiments, the material of the base is silicon, and the material of the substrate 102 and the to-be-etched platform 109 is also silicon.

[0204] In the step of etching the base, the base with a partial thickness is etched, and the base with a remaining thickness after etching is suitable to form the substrate 102, and the base with a remaining thickness after etching is suitable to form the to-be-etched platform 109.

[0205] As shown in FIGS. 7-9, in some embodiments, in the step of etching the base to form the substrate 102 and the to-be-etched platform 109 protruding from the front surface of the substrate 102, there are separate openings 107 between adjacent to-be-etched platforms 109. Specifically, in the step of etching the base, the adjacent to-be-etched platforms 109 and the substrate 102 enclose the separate openings 107, and the separate openings 107 extend along the second direction y.

[0206] In some embodiments, in the step of etching the base, a plurality of separate openings 107 and a plurality of to-be-etched platforms 109 are formed; the plurality of separate openings 107 are arranged in parallel along the first direction x, and the plurality of to-be-etched platforms 109 are arranged in parallel along the first direction x.

[0207] It should be noted that, as shown in FIGS. 7-9, the first direction x and the second direction y are both parallel to the front surface of the substrate 102 and perpendicular to each other. In other embodiments of the present application, the first direction x and the second direction y can also intersect but not be perpendicular to each other.

[0208] In some embodiments, after forming the substrate 102 and the to-be-etched platform 109 protruding from the front surface of the substrate 102, the separate openings 107 are filled. Specifically, the separate openings 107 can be filled with a dielectric material to achieve insulation between adjacent to-be-etched platforms 109 and provide a good process surface for subsequent processes.

[0209] In some embodiments, after forming the to-be-etched platform 109, as shown in FIGS. 10-13, the to-be-etched platform 109 is patterned to form a pre-prepared platform 108 and a device column 110 protruding from the surface of the pre-prepared platform 108.

[0210] The pre-prepared platform 108 is suitable to provide a process basis for the formation of a subsequent interconnection platform; and the device column 110 is suitable to form a switching device.

[0211] In some embodiments, the step of etching the to-be-etched table 109 comprises: forming a patterned layer (not shown in the figures) on the surface of the to-be-etched table 109; and etching a partial thickness of the to-be-etched table 109 to form the prefabricated table 108 and the device column 110, with the patterned layer as a mask.

[0212] The patterned layer can be a patterned photoresist layer, which can be formed by exposing and developing a spin-coated photoresist; or the patterned layer can be a hard mask layer, which can be formed by etching a deposited mask material layer.

[0213] It should be noted that the device columns 110 of adjacent rows are shown in dashed lines in FIGS. 12 and 13.

[0214] The prefabricated table 108 and the device column 110 are both etched from the to-be-etched table 109, and the materials of the prefabricated table 108 and the device column 110 correspond to the material of the to-be-etched table 109. In some example embodiments, the material of the to-be-etched table 109 is silicon, the prefabricated table 108 and the device column 110 are integrally connected, there is no obvious boundary between the prefabricated table 108 and the device column 110, and the materials of the prefabricated table 108 and the device column 110 are both silicon.

[0215] The prefabricated table 108 protrudes from the front surface of the substrate 102; the device column 110 protrudes from the first surface of the prefabricated table 108, and the first surface faces away from the substrate 102; and the axial direction of the device column 110 is a third direction z perpendicular to the front surface of the substrate 102. For example, the axial direction of a cylindrical device column 110 is parallel to the generatrix direction of the cylindrical device column 110, and the generatrix direction of the device column 110 is perpendicular to the front surface of the substrate 102.

[0216] The device column 110 protrudes from the first surface of the prefabricated table 108, the first end and the second end of the device column 110 are two ends opposite in the axial direction, the end surface of the second end is connected to the first surface of the prefabricated table 108, and the first end is away from the prefabricated table 108.

[0217] As shown in FIGS. 10 to 13, in a plane perpendicular to the axial direction of the device column 110, the prefabricated table 108 extends in a second direction y. The extension direction of the prefabricated table 108 is consistent with the extension direction of the formed bit line BL, so that the subsequently formed bit line BL can be connected to the device columns 110 of a plurality of memory cells 101. In addition, at least one side of the prefabricated table 108 in a first direction x has a dielectric material filling the discrete openings 107 (as shown in FIGS. 7 to 9), so as to achieve separation from adjacent prefabricated tables 108.

[0218] As shown in FIG. 10 to FIG. 13, along the first direction x, the device pillar 110 is biased to one side of the pre-prepared platform 108. The interconnection platform 140 is biased to one side of the device pillar 110 along the first direction x; in one of the memory cells 101, the geometric center of the projection of the interconnection platform 140 does not overlap with the geometric center of the projection of the device pillar 110 in the plane perpendicular to the axial direction of the device pillar 101; in one of the memory cells 101, the geometric center of the projection of the interconnection platform 140 is located on one side of the geometric center of the projection of the device pillar 110 along the first direction in the plane perpendicular to the axial direction of the device pillar 101.

[0219] In some embodiments of the examples, the pre-prepared platform 108 has a side surface tangent to the side surface of the device pillar 110. In one of the memory cells 101, the projection of the interconnection platform 140 has a tangent side with the projection of the device pillar 110 in the plane perpendicular to the axial direction of the device pillar 101.

[0220] Specifically, among the two side surfaces of the pre-prepared platform 108 arranged opposite to each other along the first direction x, one side surface is tangent to the side surface of the device pillar 110; in one of the memory cells 101, one of the two sides of the projection of the interconnection platform 140 along the first direction is tangent to the projection of the device pillar 110 in the plane perpendicular to the axial direction of the device pillar 101.

[0221] As shown in FIG. 10 to FIG. 13, in some embodiments, in the step of forming the device pillar 110, a plurality of device pillars 110 are formed, and the plurality of device pillars 110 are arranged in a regular array in a plane parallel to the front surface of the substrate 102.

[0222] The array plane of the plurality of device pillars 110 arranged in a regular array is parallel to the front surface of the substrate 102; it can be seen that the first direction x and the second direction y are both parallel to the array plane; the third direction z is perpendicular to the array plane; the axial direction of the device pillar 110 is perpendicular to the array plane. For example, the first direction x is the row direction of the plurality of device pillars 110 arranged in a regular array, and the second direction y is the column direction of the plurality of device pillars 110 arranged in a regular array.

[0223] It should be noted that in the array plane, the arrangement mode of the device pillar 110 is consistent with the arrangement mode of the memory cell 101, and the arrangement mode of the device pillar 110 can refer to the foregoing embodiments of the memory array.

[0224] As shown in FIG. 11, in some embodiments of the present application, the device pillars 110 of adjacent rows are staggered along the row direction; the device pillars 110 of adjacent columns are staggered along the column direction, so that the plurality of device pillars 110 are densely arranged in a hexagonal shape.

[0225] Specifically, the plurality of device pillars 110 arranged in a regular array has a first row, a second row, …, and an mth row arranged in sequence along a column direction, where m is the number of rows of the device pillars 110; the plurality of device pillars 110 arranged in a regular array has a first column, a second column, …, and an nth column arranged in sequence along a row direction, where n is the number of columns of the device pillars 110; the device pillars 110 of the ith row are staggered along the row direction with the device pillars 110 of the (i+1)th row; the device pillars 110 of the jth column are staggered along the column direction with the device pillars 110 of the (j+1)th column, where i is an integer greater than or equal to 1 and less than or equal to m, and j is an integer greater than or equal to 1 and less than or equal to n.

[0226] As shown in FIG. 11, the device pillar 110b and the device pillar 110d are located in the same row, and the device pillar 110a and the device pillar 110c are located in a row adjacent to the row in which the device pillar 110b and the device pillar 110d are located; along the row direction, the device pillar 110a and the device pillar 110c are located between the device pillar 110b and the device pillar 110d. The device pillar 110a and the device pillar 110c are located in the same column, and the device pillar 110b and the device pillar 110d are located in a column adjacent to the column in which the device pillar 110a and the device pillar 110c are located; along the column direction, the device pillar 110b and the device pillar 110d are located between the device pillar 110a and the device pillar 110c.

[0227] In some embodiments, the prefabricated platforms 108 of the storage units 101 adjacent along the column direction are integrally connected. As shown in FIG. 11, the second direction y is the row direction; the prefabricated platforms 108 of the storage units 101 adjacent along the second direction y are integrally connected; and the prefabricated platforms 108 of the plurality of storage units 101 arranged along the second direction y are sequentially connected, so that the prefabricated platform extends from one side to the other side of the column direction of one column of the device pillars 110.

[0228] In some embodiments, the device pillars 110 adjacent along the row direction are biased to the same side of the corresponding prefabricated platform 108 along the row direction, and the device pillars 110 adjacent along the column direction are biased to different sides of the corresponding prefabricated platform 108 along the row direction.

[0229] Specifically, as shown in FIG. 11, the device pillar 110a is biased to one side of the corresponding prefabricated platform 108; the device pillar 110b is adjacent to the device pillar 110a along the first direction x (i.e., the row direction), and the device pillar 110b is biased to the same side of the corresponding prefabricated platform 108 along the first direction x (i.e., the row direction); the device pillar 110c is adjacent to the device pillar 110a along the second direction y (i.e., the column direction), and the device pillar 110b is biased to the other side of the corresponding prefabricated platform 108 along the row direction along the first direction x (i.e., the row direction).

[0230] In some embodiments of the example, the sidewalls of the device pillars 110 adjacent in the row direction are tangent to the sidewalls of the respective pre-fabricated lands 108 on the same side of the pre-fabricated lands 108 in the row direction; and the sidewalls of the device pillars 110 adjacent in the column direction are tangent to the sidewalls of the respective pre-fabricated lands 108 on different sides of the pre-fabricated lands 108 in the row direction.

[0231] Specifically, as shown in FIG. 11, the device pillar 110a and the device pillar 110b are adjacent in the first direction x (i.e., the row direction), and the sidewall of the device pillar 110a and the sidewall of the device pillar 110b are tangent to the sidewalls of the respective pre-fabricated lands 108 on the same side of the pre-fabricated lands 108 in the row direction; and the device pillar 110a and the device pillar 110c are adjacent in the second direction y (i.e., the column direction), and the sidewall of the device pillar 110a and the sidewall of the device pillar 110c are tangent to the sidewalls of the respective pre-fabricated lands 108 on different sides of the pre-fabricated lands 108 in the row direction.

[0232] In some embodiments of the example, there are two columns of the device pillars 110 on the extended pre-fabricated land 108, and the two columns of the device pillars 110 are respectively offset to the two sides of the pre-fabricated land 108 in the row direction. Specifically, in a plane perpendicular to the axial direction of the device pillars 101, the geometric centers of the projections of the two columns of the device pillars 110 are arranged in two columns on the two sides of the geometric center of the projection of the interconnect land 140 in the row direction.

[0233] In some embodiments, the two columns of the device pillars 110 are respectively tangent to the two sidewalls of the pre-fabricated land 108 in the row direction. Specifically, on the extended pre-fabricated land 108, the sidewalls of one column of the device pillars 110 are respectively tangent to one sidewall of the extended pre-fabricated land 108, and the sidewalls of the other column of the device pillars 110 are respectively tangent to the other sidewall of the extended pre-fabricated land 108.

[0234] Specifically, as shown in FIG. 11, the device pillar 110a, the device pillar 110b, the device pillar 110c, and the device pillar 110e are located on the same extended pre-fabricated land 108; wherein the device pillar 110a and the device pillar 110c are arranged in a column in the second direction y, and the device pillar 110b and the device pillar 110e are arranged in a column in the second direction y; the sidewall of the device pillar 110a and the sidewall of the device pillar 110c are both tangent to one sidewall of the pre-fabricated land 108; and the sidewall of the device pillar 110b and the sidewall of the device pillar 110e are both tangent to the other sidewall of the pre-fabricated land 108.

[0235] Reference is made to FIGS. 14-22. FIG. 15 is a cross-sectional structural schematic view of a corresponding position of FIG. 12; FIG. 16 is a cross-sectional structural schematic view of a corresponding position of FIG. 13; FIG. 17 is a cross-sectional structural schematic view of a corresponding position of FIG. 12; FIG. 18 is a cross-sectional structural schematic view of a corresponding position of FIG. 13; FIG. 20 is a top structural schematic view of FIG. 19 along a direction A3; FIG. 21 is a cross-sectional structural schematic view of FIG. 20 along a line C3-C4 position; and FIG. 22 is a cross-sectional structural schematic view of FIG. 20 along a line D3-D4 position.

[0236] After the device pillar 110 is formed, a gate structure 120 is formed to surround the device pillar 110 in a circumferential direction.

[0237] The circumferential direction of the device pillar 110 is in a plane perpendicular to an axial direction of the device pillar 110, the axial direction of the device pillar 110 is perpendicular to a front surface of the substrate 102, the circumferential direction of the device pillar 110 is parallel to the front surface of the substrate 102, and the circumferential direction of the device pillar 110 is parallel to an array plane of a plurality of device pillars 110 arranged in a regular array.

[0238] The gate structure 120 surrounds the device pillar 110 in a plane parallel to the array plane. The storage unit is a gate all around (GAA) storage unit, the gate structure 120 has a strong control ability on a channel, and can effectively ensure the performance of the storage array; the channel in the device pillar 110 extends along a third direction z perpendicular to the array plane of the plurality of device pillars 110 arranged in a regular array; and the area of the formed storage unit in the array plane is small, which can effectively improve the storage density.

[0239] In some embodiments of the present application, the step of forming the gate structure 120 to surround the device pillar 110 in the circumferential direction includes: forming a gate dielectric layer 121 to surround the device pillar 110 in the circumferential direction; and forming a gate electrode 122 on the gate dielectric layer 121.

[0240] In some embodiments, the gate structure 120 is one of a polysilicon gate structure and a metal gate structure. In some example embodiments, the material of the gate electrode 122 is one of polysilicon and metal; and the material of the gate dielectric layer 121 is an oxide, for example, the oxide can be silicon oxide or a high-K gate dielectric layer.

[0241] It should be noted that in the step of forming the gate structure 120, the corresponding material is patterned based on the shape and distribution mode of the gate structure 120; and the shape and distribution mode of the formed gate structure 120 can refer to the foregoing embodiments.

[0242] In some embodiments of the present application, the gate structure 120 extends along a predetermined direction in a plane parallel to the substrate 102. The axis of the device pillar 110 is perpendicular to the array plane of the regularly arrayed device pillars 110, and the gate structure 120 extends along the predetermined direction in the array plane of the regularly arrayed device pillars 110.

[0243] As shown in FIGS. 19 and 20, the gate electrode 122 is in a strip shape. In the array plane of the regularly arrayed device pillars 110, the gate electrode 122 extends along the row direction (i.e., the first direction x) and across the range of the device pillars 110. The gate dielectric layer 121 is between each device pillar 110 and the gate electrode 122.

[0244] In some embodiments, at least one side of the gate dielectric layer 121 extends beyond the gate electrode 122 along the axis of the device pillar 110. As shown in FIG. 19, both sides of the gate dielectric layer 121 extend beyond the gate electrode 122 along the axis of the device pillar 110. In the third direction z, the size of the gate dielectric layer 121 is greater than the size of the gate electrode 122, and the gate electrode 122 is only on the surface of the gate dielectric layer 121.

[0245] It should be noted that the gate structure 120 surrounds the middle position of the device pillar 110 and is separated from the first end and the second end of the device pillar 110 along the axis of the device pillar 110. As shown in FIGS. 14-18, the manufacturing method further comprises: forming a first dielectric layer (shown in FIGS. 17 and 18 as filled with a semi-transparent diagonal line) on the sidewall of the device pillar 110 close to the pre-prepared platform 108 before forming the gate structure 120 after forming the device pillar 110; and as shown in FIGS. 19-22, the gate structure 120 is formed on the first dielectric layer in the step of forming the gate structure 120.

[0246] The first dielectric layer is used to achieve electrical insulation between adjacent device pillars 110. Specifically, the material of the first dielectric layer is a dielectric material. For example, the material of the first dielectric layer can be a dielectric material such as silicon oxide, a low-K dielectric material, or even an ultra-low-K dielectric material.

[0247] For example, the step of forming the first dielectric layer comprises: forming a dielectric material on the substrate as shown in FIGS. 14-16, the dielectric material filling between adjacent device pillars; and removing part of the thickness of the dielectric material to expose the end surface of the first end of the device pillar 110 as shown in FIGS. 17-18, thereby forming the first dielectric layer.

[0248] In addition, as shown in some embodiments of FIG. 21 and FIG. 22, the manufacturing method further comprises: after forming the gate structure 120, forming a second dielectric layer (shown in FIG. 21 and FIG. 22 filled with a semi-transparent diagonal line) on the side of the gate structure 120 away from the prefabricated platform 108, filling between adjacent device pillars 110.

[0249] The second dielectric layer is used to achieve electrical insulation between adjacent device pillars 110; moreover, the top surface of the second dielectric layer is flush with the end surface of the first end of the device pillar 110, which can also provide a good process operation surface for subsequent processes.

[0250] Specifically, the material of the second dielectric layer is a dielectric material; for example, the material of the second dielectric layer can be a dielectric material such as silicon oxide, and the second dielectric layer can also be a low-K dielectric material or even an ultra-low-K dielectric material.

[0251] For example, the step of forming the second dielectric layer includes: forming a dielectric material on the gate structure 120, the dielectric material filling between adjacent device pillars 110; removing part of the thickness of the dielectric material to expose the end surface of the first end of the device pillar 110, forming the second dielectric layer.

[0252] It should be noted that FIG. 19 and FIG. 20 omit the first dielectric layer and the second dielectric layer, and only show part of the structure to show clearly.

[0253] Referring to FIG. 23, after forming the gate structure 120, a storage capacitor 130 is formed on the side of the device pillar 110 along the axial direction of the device pillar 110 towards the first end, and the storage capacitor 130 is electrically connected to the first end.

[0254] The device pillar 110 and the storage capacitor 130 are stacked along a third direction z perpendicular to the front surface of the substrate 102; the device pillar 110 is located between the storage capacitor 130 and the substrate 102.

[0255] In some specific embodiments, in the step of forming the storage capacitor 130, the storage capacitor 130 is formed on the end surface of the first end of the device pillar 110. The surface of the storage capacitor 130 towards the device pillar 110 directly contacts the end surface of the first end of the device pillar 110, to achieve electrical connection between the storage capacitor 130 and the device pillar 110.

[0256] It should be noted that, as shown in FIG. 23, in some embodiments, the manufacturing method further includes: after forming the storage capacitor 130, forming a third dielectric layer (shown in FIG. 23 as filled with a semi-transparent diagonal line), which is located on the side of the second dielectric layer away from the gate structure 120 and fills between adjacent storage capacitors 130.

[0257] The third dielectric layer is used to achieve electrical insulation between adjacent storage capacitors 130; and the top surface of the third dielectric layer is flush with the end surface of the storage capacitor 130, and the third dielectric layer can also provide a good operating surface for subsequent processes.

[0258] Specifically, the material of the third dielectric layer is a dielectric material; for example, the material of the third dielectric layer can be a dielectric material such as silicon oxide, and the third dielectric layer can also be a low-K dielectric material or even an ultra-low-K dielectric material.

[0259] For example, the step of forming the third dielectric layer includes: forming a dielectric material on the second dielectric layer, which fills between adjacent storage capacitors 130; and removing part of the thickness of the dielectric material to expose the end surface of the storage capacitor 130, thereby forming the third dielectric layer.

[0260] Referring to FIGS. 24-35, FIGS. 25, 28, 31 and 34 are cross-sectional structural schematic diagrams of corresponding positions of FIG. 21, and FIGS. 26, 29, 32 and 35 are cross-sectional structural schematic diagrams of corresponding positions of FIG. 22.

[0261] After forming the storage capacitor 130, an interconnection platform 140 is formed, which is located on the side of the device column 110 close to the second end along the axial direction of the device column 110, and the interconnection platform 140 is electrically connected to the second end of the device column 110.

[0262] It should be noted that FIGS. 24, 27, 30 and 33 omit the first dielectric layer, the second dielectric layer and the third dielectric layer, and only show part of the structure to show clearly.

[0263] In some embodiments of the application, the step of forming the interconnection platform 140 includes: as shown in FIGS. 24-29, removing the substrate 102 to expose the pre-preparation platform 108; and as shown in FIGS. 30-35, etching the pre-preparation platform 108 to form the interconnection platform 140.

[0264] Specifically, before the step of forming the interconnection platform 140, the substrate 102 is removed to expose the pre-preparation platform 108, thereby providing a basis for the formation of the interconnection platform 140.

[0265] In some embodiments, the step of removing the substrate 102 to expose the pre-fabricated land 108 includes: removing the substrate 102 along a back surface of the substrate 102 to expose a second surface of the pre-fabricated land 108, the back surface of the substrate 108 being opposite to a front surface of the substrate 102, the second surface of the pre-fabricated land 108 being opposite to the first surface of the pre-fabricated land 108.

[0266] In addition, the step of removing the substrate 102 further includes: after forming the storage capacitor 130, reversing the structure to expose a back surface of the substrate 102, as shown in FIGS. 24-26, the back surface of the substrate 102 being opposite to a front surface of the substrate 102; and after reversing the structure, removing the substrate 102 along the back surface of the substrate 102, as shown in FIGS. 27-29.

[0267] Specifically, the step of removing the substrate 102 along the back surface of the substrate 102 includes: thinning the substrate 102 by grinding; and etching the thinned substrate 102 until the second surface of the pre-fabricated land 108 is exposed, the second surface of the pre-fabricated land 108 being opposite to the first surface.

[0268] Furthermore, the pre-fabricated land 108 has a dielectric material filling the discrete opening 107 (as shown in FIGS. 7-9) on at least one side of the pre-fabricated land 108 along the first direction x; and the step of removing the substrate 102 along the back surface of the substrate 102 also exposes the dielectric material filling the discrete opening 107, a surface of the exposed dielectric material filling the discrete opening 107 being flush with the exposed second surface of the pre-fabricated land 108.

[0269] In some embodiments, the step of etching the pre-fabricated land 108 to form the interconnection land 140 includes: etching the pre-fabricated land 108 through the second surface of the pre-fabricated land 108 to form the interconnection land 140.

[0270] In some specific embodiments, the step of etching the pre-fabricated land 108 to form the interconnection land 140 includes: thinning the pre-fabricated land 108 through the second surface of the pre-fabricated land 108, as shown in FIGS. 30-32; and forming a second opening through the thickness of the thinned pre-fabricated land 108 to form the interconnection land 140, as shown in FIGS. 33-35.

[0271] For example, in the step of thinning the pre-fabricated land 108 through the second surface of the pre-fabricated land 108, the pre-fabricated land 108 can be thinned through the second surface of the pre-fabricated land 108 by etching.

[0272] In some embodiments, in the step of thinning the preform platform 108, only the preform platform 108 is etched, and the medium material filling the discrete openings 107 is not etched. As shown in FIGS. 30-32, after the preform platform 108 is thinned, the medium material filling the discrete openings 107 protrudes from the second surface of the thinned preform platform 108.

[0273] In some embodiments, in the step of forming the second openings penetrating the thickness of the thinned preform platform 108, the second openings penetrating the thickness of the thinned preform platform 108 are formed by a self-alignment method. Specifically, the second openings can be formed by a linear layer formation and a punch process.

[0274] As shown in FIGS. 30-32, in the step of thinning the preform platform 108, only the preform platform 108 is thinned, and the medium material filling the discrete openings 107 is not etched. Specifically, before the step of forming the second openings penetrating the thickness of the thinned preform platform 108, the medium material filling the discrete openings 107 protrudes from the second surface of the thinned preform platform 108.

[0275] In an example, the step of forming the second openings penetrating the thickness of the thinned preform platform 108 includes: forming a linear layer (not shown in the figures) on the thinned preform platform 108 and the medium material filling the discrete openings 107; etching the linear layer to expose part of the surface of the thinned preform platform 108; and etching the exposed thinned preform platform 108 to form the second openings.

[0276] The medium material filling the discrete openings 107 protrudes from the thinned preform platform 108. In the step of forming the linear layer, the linear layer conformally covers the thinned preform platform 108 and the medium material filling the discrete openings 107. In the first direction x, the thickness of the linear layer at the middle of the preform platform 108 is less than the thickness of the linear layer near the medium material filling the discrete openings 107. In the step of etching the linear layer, the linear layer is etched by a maskless etching process to expose the surface at the middle of the thinned preform platform 108, i.e., without using a mask and without photolithography, only the entire linear layer is etched to expose the surface at the middle of the thinned preform platform 108, so that the second openings divide the preform platform 108 into two parts, and two interconnection platforms 140 are formed.

[0277] It should be noted that in at least one of the steps of etching the linear layer and etching the exposed thinned pre-platen 108, the etching is performed by a punch process. The punch process refers to an etching process with high anisotropic etching rate. Specifically, by adjusting the etching process parameters, such as bias, the etching rate in the vertical direction is greater than the etching rate in the horizontal direction. The punch process can make the etching rate in the horizontal direction as low as possible, and the difference between the etching rate in the vertical direction and the etching rate in the horizontal direction as large as possible.

[0278] Due to the thickness of the portion of the linear layer located at the middle position of the pre-platen 108 in the first direction x is less than the thickness of the portion of the linear layer close to the dielectric material filling the discrete opening 107, during the etching of the linear layer by the punch process, the portion of the linear layer located at the middle position of the pre-platen 108 is removed first, thereby exposing the surface of the middle position of the thinned pre-platen 108, and the portion of the linear layer close to the dielectric material filling the discrete opening 107 is only thinned, and the surface of the pre-platen 108 close to the dielectric material filling the discrete opening 107 is not exposed.

[0279] During the etching of the exposed thinned pre-platen 108 by the punch process, the exposed thinned pre-platen 108 is etched, and the pre-platen 108 close to the dielectric material filling the discrete opening 107 is protected by the remaining linear layer and is not etched, thereby forming a second opening and forming two interconnection platen 140.

[0280] The interconnection platen 140 is formed in a self-aligned manner, without the use of photolithography process and without the use of mask, which can effectively avoid the influence of photolithography alignment on yield and performance, effectively reduce the process cost and the manufacturing process difficulty of the interconnection platen 140, and improve the storage unit density while ensuring the manufacturing yield and device performance.

[0281] As shown in FIGS. 33-35, in some embodiments, the manufacturing method further comprises: after forming the second opening and forming the interconnection platen 140, forming a fourth dielectric layer (shown as sparse dots in FIGS. 33-35), which fills in the second opening.

[0282] The fourth dielectric layer is used to achieve electrical insulation between adjacent interconnection platen 140; and the surface of the fourth dielectric layer is flush with the surface of the interconnection platen 140, and the fourth dielectric layer can also provide a good operating surface for subsequent processes.

[0283] Specifically, the material of the fourth dielectric layer is a dielectric material; for example, the material of the fourth dielectric layer can be a dielectric material such as silicon oxide, and the fourth dielectric layer can also be a low-K dielectric material or even an ultra-low-K dielectric material.

[0284] For example, the step of forming the fourth dielectric layer includes: forming a dielectric material on the fourth dielectric layer, the dielectric material filling the second opening; removing part of the thickness of the dielectric material to expose the interconnection platform 140, thereby forming the fourth dielectric layer.

[0285] Referring to FIGS. 2-5, the manufacturing method further includes: forming a bit line BL on the side of the interconnection platform 140 away from the device pillar 110 along the axial direction of the device pillar 110, the bit line BL being electrically connected to the interconnection platform 140.

[0286] It should be noted that FIGS. 2 and 3 omit the first dielectric layer, the second dielectric layer, and the third dielectric layer, and only show part of the structure to show clarity.

[0287] In some embodiments of the present application, in the step of forming a bit line BL on the side of the interconnection platform 140 away from the device pillar 110 along the axial direction of the device pillar 110, the bit line BL is formed on the side of the interconnection platform 140 away from the device pillar 110 along the axial direction of the device pillar 110 in a self-aligned manner.

[0288] By forming the bit line BL in a self-aligned manner, the use of photolithography process is not required, and a mask is not required, which can effectively avoid the influence of photolithography alignment on yield and performance, can effectively reduce the process cost and the manufacturing process difficulty of the bit line BL, and can improve the storage unit density while ensuring the manufacturing yield and device performance.

[0289] In some embodiments, the step of forming a bit line on the side of the interconnection platform 140 away from the device pillar 110 along the axial direction of the device pillar 110 includes: forming a precursor metal layer (not shown in the figure) on the surface of the interconnection platform 140; and performing annealing treatment to make the precursor metal layer and the interconnection platform 140 react with each other to form the bit line BL.

[0290] In summary, in the storage unit, the gate structure surrounds the device column in the axial direction, the storage capacitor is located on the side of the first end of the device column in the axial direction and is connected with the first segment. The gate structure fully surrounds the device column, which can effectively ensure the control ability of the gate structure on the channel. In the storage unit, the channel in the device column extends in the axial direction. In the plane perpendicular to the axial direction of the device column, the area of the storage unit is small, which can effectively improve the storage density of the storage array including the storage unit. The interconnection platform electrically connected with the second end of the device column can provide a basis for the formation of the subsequent bit line, which can effectively reduce the process difficulty of the bit line formation.

[0291] In addition, the interconnection platform is integrally connected with the device column, the material of the bit line and the material of the interconnection platform are mutually melted at the interface, and at least part of the material of the bit line near the side of the interconnection platform is a metal silicide. The bit line is a bit line formed through a self-alignment process. In the formation process of the bit line, the use of the photolithography process can be effectively reduced, the process difficulty of the bit line formation can be effectively reduced, the influence of the overlay accuracy on the performance can be effectively avoided, which is beneficial to the improvement of the device manufacturing yield and the improvement of the device performance.

[0292] In addition, in the storage array, the storage units of adjacent rows are staggered in the column direction. By staggering the storage units of adjacent rows in the column direction, the storage units are densely packed in the plane perpendicular to the axial direction of the device column, which can effectively improve the distribution density of the storage units. Due to the improvement of the storage density, a hardware basis can be provided for the odd-even interval operation mode, the storage density can be improved as much as possible, the area waste can be reduced, and the read / write speed and the storage density can be balanced.

[0293] In addition, the storage units of adjacent columns are connected with the bit lines adjacent in the row direction; while a bit line is loaded with a first voltage, an adjacent bit line is loaded with a second voltage, and the second voltage is not equal to the first voltage. When the storage device is working, adjacent bit lines are loaded with unequal voltages, a bit line is loaded with a first voltage to read out or write in data, and an adjacent bit line is loaded with a second voltage to shield the coupling capacitance. The odd-even interval operation mode of the bit line can effectively shield the coupling effect between the bit lines and can effectively ensure the speed of the read / write operation.

[0294] Further, the second voltage is a default voltage, i.e., the second voltage is Vcc / 2. Without making great changes to the circuit inside the storage device, the present scheme can be implemented, which can effectively reduce the process difficulty.

[0295] Although the present application is disclosed as above, the present application is not limited to this. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present application, and the protection scope of the present application should be subject to the scope defined by the claims.

Claims

1. A memory cell, comprising: Comprising: a device pillar having a first end and a second end opposite to each other along an axial direction of the device pillar; a gate structure circumferentially surrounding the device pillar; a storage capacitor located on a side of the device pillar close to the first end along the axial direction of the device pillar, the storage capacitor being electrically connected to the first end of the device pillar; an interconnection platform located on a side of the device pillar close to the second end along the axial direction of the device pillar, the interconnection platform being electrically connected to the second end of the device pillar.

2. The memory cell of claim 1, wherein, The material of the interconnection platform is the same as that of the device pillar.

3. The memory cell of claim 1 or 2, wherein, The interconnection platform is integrally connected to the device pillar.

4. The memory cell of claim 1, wherein, The extending direction of the interconnection platform is perpendicular to the extending direction of the gate structure.

5. The memory cell of claim 1, wherein, In a plane perpendicular to the axial direction of the device pillar, the size of the projection of the interconnection platform in the direction perpendicular to the extending direction is smaller than the size of the projection of the device pillar in the same direction.

6. The memory cell of claim 1, wherein, In the plane perpendicular to the axial direction of the device pillar, the geometric center of the projection of the interconnection platform does not coincide with the geometric center of the projection of the device pillar.

7. The memory cell of claim 6, wherein, One side surface of the interconnection platform is tangent to a side surface of the device pillar.

8. The memory cell of claim 1, wherein, The device pillar is cylindrical, and the storage capacitor is cylindrical.

9. The memory cell of claim 1, wherein, The gate structure comprises a gate electrode and a gate dielectric layer, the gate dielectric layer being located between the gate electrode and the device pillar.

10. The memory cell of claim 9, wherein, At least one side of the gate dielectric layer extends beyond the gate electrode along the axial direction of the device pillar.

11. The memory cell of claim 9, wherein, The material of the gate electrode is one of polysilicon or metal; the material of the gate dielectric layer is oxide.

12. The memory cell of claim 1, wherein, The storage capacitor is located on the end surface of the first end.

13. A memory array comprising: Comprising: a storage unit as claimed in any one of claims 1 to 12, a plurality of the storage units being arranged in an array in a plane perpendicular to the axial direction of the device pillar.

14. The storage array of claim 13, wherein, The storage units of adjacent rows are staggered along the row direction. The storage units of adjacent columns are staggered along the column direction.

15. The storage array of claim 13 or 14, wherein, The interconnection platforms of the storage units in the same column are integrally connected.

16. The storage array of claim 13 or 14, wherein, In the plane perpendicular to the axial direction of the device pillar, the geometric centers of the projections of the interconnection platforms in adjacent columns are opposite in the direction of deviation relative to the geometric centers of the projections of the corresponding device pillars.

17. The storage array of claim 13 or 14, wherein, The gate electrodes of the gate structures of the storage units in the same row are integrally connected.

18. The storage array of claim 13 or 14, wherein, Further comprising: a bit line located on a side of the interconnection platform away from the device pillar along the axial direction of the device pillar, the bit line extending along the column direction in a plane perpendicular to the axial direction of the device pillar; The storage units in the same column are connected to the same bit line.

19. The storage array of claim 18, wherein, The projection of the bit line overlaps the projection of the interconnection platform in the plane perpendicular to the axial direction of the device pillar.

20. The storage array of claim 18, wherein, The bit line is located on the surface of the side of the interconnection platform away from the device pillar.

21. The storage array of claim 18, wherein, The material of the bit line and the material of the interconnection platform are mutually fused at the interface.

22. The storage array of claim 18, wherein, At least the part of the material of the bit line close to the interconnection platform is metal silicide.

23. The storage array of claim 18, wherein, The storage units of adjacent columns are connected to adjacent two bit lines in a staggered manner.

24. The storage array of claim 13 or 14, wherein, Further comprising: a word line extending along the row direction in a plane perpendicular to the axial direction of the device pillar; The storage units in the same row are connected to the same word line.

25. A method of controlling a memory array, the method comprising: the memory array being as claimed in any one of claims 13 to 24; the method comprising loading a first voltage onto a bit line while loading a second voltage onto an adjacent bit line, the second voltage being different from the first voltage.

26. The control method of claim 25, wherein the memory array comprises a first bit line, a second bit line, a third bit line, a fourth bit line, a fifth bit line, a sixth bit line, a seventh bit line, an eighth bit line, a ninth bit line, a tenth bit line, an eleventh bit line, a twelfth bit line, a thirteenth bit line, a fourteenth bit line, a fifteenth bit line, a sixteenth bit line, a seventeenth bit line, an eighteenth bit line, a nineteenth bit line, and a twentieth bit line, wherein the first bit line, the second bit line, the third bit line, the fourth bit line, the fifth bit line, the sixth bit line, the seventh bit line, the eighth bit line, the ninth bit line, the tenth bit line, the eleventh bit line, the twelfth bit line, the thirteenth bit line, the fourteenth bit line, the fifteenth bit line, the sixteenth bit line, the seventeenth bit line, the eighteenth bit line, the nineteenth bit line, and the twentieth bit line are arranged in sequence; the step of loading a first voltage onto a bit line while loading a second voltage onto an adjacent bit line comprises loading the first voltage onto the second bit line while loading the second voltage onto the first bit line.

27. The control method of claim 26, wherein the step of loading the first voltage onto the second bit line while loading the second voltage onto the first bit line comprises loading the first voltage onto all of the second bit line while loading the second voltage onto all of the first bit line.

28. The control method of claim 26, wherein the step of loading a first voltage onto a bit line while loading a second voltage onto an adjacent bit line further comprises loading the first voltage onto the twelfth bit line while loading the second voltage onto the eleventh bit line.

29. The control method of claim 28 wherein, the step of loading the first voltage onto the twelfth bit line while loading the second voltage onto the eleventh bit line comprises loading the first voltage onto all of the twelfth bit line while loading the second voltage onto all of the eleventh bit line.

30. The control method of claim 25, wherein the second voltage is a default voltage.

31. A memory device, comprising: comprising: a memory array, the memory array being as claimed in any one of claims 13 to 24; a controller adapted to load a first voltage onto a bit line while loading a second voltage onto an adjacent bit line, the second voltage being different from the first voltage.

32. The memory device of claim 31, wherein, the memory array comprises a first bit line, a second bit line, a third bit line, a fourth bit line, a fifth bit line, a sixth bit line, a seventh bit line, an eighth bit line, a ninth bit line, a tenth bit line, an eleventh bit line, a twelfth bit line, a thirteenth bit line, a fourteenth bit line, a fifteenth bit line, a sixteenth bit line, a seventeenth bit line, an eighteenth bit line, a nineteenth bit line, and a twentieth bit line, wherein the first bit line, the second bit line, the third bit line, the fourth bit line, the fifth bit line, the sixth bit line, the seventh bit line, the eighth bit line, the ninth bit line, the tenth bit line, the eleventh bit line, the twelfth bit line, the thirteenth bit line, the fourteenth bit line, the fifteenth bit line, the sixteenth bit line, the seventeenth bit line, the eighteenth bit line, the nineteenth bit line, and the twentieth bit line are arranged in sequence; the controller is adapted to load the first voltage onto the second bit line while loading the second voltage onto the first bit line.

33. The memory device of claim 32, wherein, the controller is adapted to load the first voltage onto all of the second bit line while loading the second voltage onto all of the first bit line.

34. The memory device of claim 31, wherein, the controller is further adapted to load the first voltage onto the twelfth bit line while loading the second voltage onto the eleventh bit line.

35. The memory device of claim 34, wherein, the controller is adapted to load the first voltage onto all of the twelfth bit line while loading the second voltage onto all of the eleventh bit line.

36. The memory device of claim 31, wherein, the second voltage is a default voltage.

37. A method for manufacturing a storage device, characterized by comprising: comprising: forming a device pillar, the device pillar having a first end and a second end opposite to each other along an axial direction of the device pillar; forming a gate structure surrounding the device pillar in a circumferential direction; forming a storage capacitor on a side of the device pillar close to the first end along the axial direction of the device pillar, the storage capacitor being electrically connected to the first end; forming an interconnection platform on a side of the device pillar close to the second end along the axial direction of the device pillar, the interconnection platform being electrically connected to the second end of the device pillar.

38. The production method according to claim 37, wherein the step of forming a device pillar comprises: providing a substrate; etching the substrate to form a substrate and a to-be-etched platform protruding from a front surface of the substrate; Etching the to-be-etched platform to form a prefabricated platform and a device column protruding from a first surface of the prefabricated platform.

39. The production method according to claim 38, wherein In the step of etching the substrate to form the substrate and the to-be-etched platform protruding from the front surface of the substrate, the to-be-etched platforms have discrete openings between adjacent to-be-etched platforms. After the step of etching the substrate to form the substrate and the to-be-etched platform protruding from the front surface of the substrate, before the step of etching the to-be-etched platform, the discrete openings are filled with a medium material.

40. The production method according to Claim 37, wherein In the step of forming the device column, the device column protrudes from a first surface of the prefabricated platform, and the prefabricated platform protrudes from the front surface of the substrate. The step of forming the interconnection platform includes: Removing the substrate to expose the prefabricated platform; Etching the prefabricated platform to form the interconnection platform.

41. The production method according to Claim 40, wherein The step of removing the substrate to expose the prefabricated platform includes: removing the substrate along the back surface of the substrate to expose the second surface of the prefabricated platform, the back surface of the substrate being opposite to the front surface of the substrate, and the second surface of the prefabricated platform being opposite to the first surface of the prefabricated platform; The step of etching the prefabricated platform to form the interconnection platform includes: etching the prefabricated platform through the second surface of the prefabricated platform to form the interconnection platform.

42. The production method according to claim 41, wherein The step of etching the prefabricated platform to form the interconnection platform includes: Thinning the prefabricated platform through the second surface of the prefabricated platform; Forming a second opening penetrating the thickness in the thinned prefabricated platform to form the interconnection platforms adjacent in the row direction.

43. The production method according to claim 42, wherein In the step of forming the second opening penetrating the thickness in the thinned prefabricated platform, the second opening penetrating the thickness in the thinned prefabricated platform is formed in a self-aligned manner.

44. The production method according to claim 42, wherein Before the step of forming the second opening penetrating the thickness in the thinned prefabricated platform, the medium material filled in the discrete openings protrudes from the second surface of the thinned prefabricated platform; The step of forming the second opening penetrating the thickness in the thinned prefabricated platform includes: forming a linear layer on the thinned prefabricated platform and the medium material filled in the discrete openings; Etching the linear layer to expose part of the surface of the thinned prefabricated platform; etching the exposed thinned prefabricated platform to form the second opening.

45. The manufacturing method according to Claim 37, wherein Further comprising: Forming a bit line on the side of the interconnection platform away from the device column along the axial direction of the device column, the bit line being electrically connected to the interconnection platform.

46. The production method described in claim 45, wherein In the step of forming the bit line on the side of the interconnection platform away from the device column along the axial direction of the device column, the bit line is formed on the side of the interconnection platform away from the device column along the axial direction of the device column in a self-aligned manner.

47. The production method according to Claim 45, wherein In the step of forming the bit line on the side of the interconnection platform away from the device column along the axial direction of the device column, the bit line is formed on the side of the interconnection platform away from the device column along the axial direction of the device column in a self-aligned manner. In the step of forming the bit line on the side of the interconnection platform away from the device column along the axial direction of the device column, the bit line is formed on the side of the interconnection platform away from the device column along the axial direction of the device column in a self-aligned manner. Forming a precursor metal layer on the surface of the interconnection platform; Performing annealing treatment to make the precursor metal layer and the interconnection platform react with each other to form the bit line.

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