Multi-stack layer for use in a field-effect transistor

Abstract

A multi-layer stack (110) for use in a field-effect transistor comprises multiple layers of aluminium gallium nitride (AlGaN) arranged in a stack from a base layer to a surface layer, wherein the base layer comprises an average aluminium content equal to a first predefined, non-zero value, and the surface layer comprises an average aluminium content equal to substantially zero, wherein the multiple layers of AlGaN comprise a first set of layers and a second set of layers, wherein respective layers of the first set are interposed with respective layers of the second set such that layers of the first and second sets alternate with one another, wherein an average aluminium content of the first set of layers decreases, in a direction from the base layer towards the surface layer, from the first predefined, non-zero value according to a first profile, wherein the first profile defines a first rate of reduction of average aluminium content, wherein an average aluminium content of the second set of layers decreases, in the direction towards the surface layer, from a second predefined, non-zero value that is higher than the first predefined, non-zero value, according to a second profile, wherein the second profile defines a second rate of reduction of average aluminium content.

Description

[0001] MULTI-STACK LAYER FOR USE IN A FIELD-EFFECT TRANSISTOR

[0002] TECHNICAL FIELD

[0003] The present disclosure relates, in general, to a multi-layer stack for use in a field-effect transistor. Aspects of the disclosure relate to a polarisation engineered normally-off aluminium gallium nitride (AlGaN) high electron mobility transistor (HEMT).

[0004] BACKGROUND

[0005] Gallium nitride (GaN) technology is being actively developed by leading semiconductor power manufacturers as a potential replacement for conventional silicon-based technologies in power applications. Wide bandgap materials, such as silicon carbide (SiC) and gallium nitride, offer significant advantages over traditional silicon due to their ability to withstand higher electric fields for a given drift region design. This characteristic enables the design of smaller power devices compared to their silicon counterparts. Additionally, wide bandgap materials exhibit lower device capacitance and can achieve higher switching frequencies, which translates into improved system performance, increased power density, and reduced overall weight and volume of power systems.

[0006] Over the past 15 to 20 years, intensive research and development efforts have been dedicated to advancing GaN technology as a potential replacement for silicon-based field-effect transistors (FETs). The use of GaN offers the opportunity for unprecedented performance improvements at both the device and system levels. Enhancement-mode GaN power FETs have now reached commercialization, and several leading semiconductor manufacturers have introduced products to the market.

[0007] However, existing approaches to GaN technology face significant challenges, including increased process complexity and high process costs, which hinder widespread adoption. Additionally, devices often exhibit low threshold voltages, which can limit their performance and reliability in power applications. Another critical issue is the large instability of devices due to incomplete dopant activation, leading to the generation of traps and defects within the gate module. These traps and defects can result in significant performance degradation, reduced device reliability, and increased operational variability, thus affecting the overall efficacy of GaN-based power devices.

[0008] SUMMARY

[0009] An objective of the present disclosure is to provide an efficient and effective implementation of normally-off GaN power technology.

[0010] The foregoing and other objectives are achieved by the features of the independent claims.

[0011] Further implementation forms are apparent from the dependent claims, the description and the Figures.

[0012] A first aspect of the present disclosure provides a multi-layer stack for use in a field-effect transistor, the multi-layer stack comprising multiple layers of aluminium gallium nitride (AlGaN) arranged in a stack from a base layer to a surface layer, wherein the base layer comprises an average aluminium content equal to a first predefined, non-zero value, and the surface layer comprises an average aluminium content equal to substantially zero, wherein the multiple layers of AlGaN comprise a first set of layers and a second set of layers, wherein respective layers of the first set are interposed with respective layers of the second set such that layers of the first and second sets alternate with one another, wherein an average aluminium content of the first set of layers decreases, in a direction from the base layer towards the surface layer, from the first predefined, non-zero value according to a first profile, wherein the first profile defines a first rate of reduction of average aluminium content, wherein an average aluminium content of the second set of layers decreases, in the direction towards the surface layer, from a second predefined, non-zero value that is higher than the first predefined, non-zero value, according to a second profile, wherein the second profile defines a second rate of reduction of average aluminium content.

[0013] Accordingly, a multi-layer stack offering several advantageous effects can be provided. The advantages of the proposed approach include compatibility with conventional industrial lateral GaN technology on silicon substrates, which allows the integration of existing manufacturing processes. The approach retains the use of high mobility two-dimensional electron gas (2DEG) channels, ensuring that the high-speed and high-frequency performance of GaN devices is maintained. This structure leverages a consolidated process already developed for mass production of lateral GaN power devices, facilitating scalability and cost-effectiveness. Unlike conventional approaches, the multi-layer stack eliminates the need for dopants, such as magnesium, to achieve normally-off operation, thus avoiding the need for complex activation annealing steps like rapid thermal processing (RTP) or furnace annealing, thereby reducing process complexity and cost. The absence of magnesium dopants also enhances overall device reliability, particularly gate reliability, by mitigating the negative effects associated with dopant activation and related defect formation. Additionally, this design enables a higher hole concentration in the gate region compared to traditional magnesium activation approaches, leading to a higher threshold voltage, and it can also be employed as a hole injector to improve dynamic effects, further enhancing the device's performance and operational stability.

[0014] The first predefined value may define an average aluminium content of between around 10% - 25%.

[0015] A thickness of respective layers of the multiple layers may be between around 5nm - 50nm.

[0016] The first predefined, non-zero, value may define an average aluminium content of around 15%.

[0017] The second predefined, non-zero, value may define an average aluminium content of around 1% - 5% more than that of the first predefined, non-zero, value.

[0018] At least one of the first rate of reduction and the second rate of reduction may define a rate of reduction of average aluminium content of around 1% - 15%.

[0019] A second aspect of the present disclosure provides a field-effect transistor, FET, comprising at least one multi-layer stack as described herein.

[0020] The field-effect transistor may further comprise a substrate, a nucleation layer formed over the substrate, a transition layer arranged between the nucleation layer and a gallium nitride (GaN) layer, wherein the GaN layer comprises a GaN buffer and a GaN channel layer, an AlGaN barrier layer formed over the GaN channel layer, and a first multi-layer stack arranged over at least a portion of the AlGaN barrier layer, wherein a gate terminal of the field-effect transistor is arranged on the surface layer of the first multi-layer stack.

[0021] The field-effect transistor may further comprise a second multi-layer stack arranged over at least a portion of the AlGaN barrier layer, wherein the second multi-layer stack is provided in spaced relation to the first multi-layer stack, and wherein a drain structure of the FET is arranged on or in close proximity to the second multi-layer stack.

[0022] A number of layers of the second multi-layer stack may be different to a number of layers of the first multi-layer stack.

[0023] The substrate may comprise a silicon substrate, and the nucleation layer may comprise aluminium nitride, AIN.

[0024] A third aspect of the present disclosure provides a method of fabricating a multi-layer stack for use in a field-effect transistor, the method comprising forming a base layer, wherein the base layer comprises an average aluminium content equal to a first predefined, non-zero value, forming multiple layers of aluminium gallium nitride (AlGaN) in a stack over the base layer, and forming a surface layer with an average aluminium content equal to substantially zero over the multiple layers of AlGaN, wherein the multiple layers of AlGaN comprise a first set of layers and a second set of layers, wherein respective layers of the first set of layers are interposed with respective layers of the second set of layers such that layers of the first and second sets alternate with one another, wherein an average aluminium content of the first set of layers decreases, in a direction towards the surface layer, from the first predefined, non-zero value according to a first profile, wherein the first profile defines a first rate of reduction of average aluminium content, wherein an average aluminium content of the second set of layers decreases, in the direction towards the surface layer, from a second predefined, non-zero value that is higher than the first predefined, non-zero value, according to a second profile, wherein the second profile defines a second rate of reduction of average aluminium content.

[0025] A fourth aspect of the present disclosure provides a method of fabricating a field-effect transistor, FET, comprising a multilayer stack as described herein, the method comprising providing a substrate, forming a nucleation layer over the substrate, forming a transition layer arranged between the nucleation layer and a gallium nitride, GaN, layer, wherein the GaN layer comprises a GaN buffer and a GaN channel layer, forming an AlGaN barrier layer over the GaN channel layer, forming or providing a first multi-layer stack over at least a portion of the AlGaN barrier layer, forming a gate terminal of the FET on the surface layer of the first multi-layer stack, and forming a source region and a drain region.

[0026] F orming the drain region may comprise forming a second multi-layer stack arranged over at least a portion of the AlGaN barrier layer, wherein the second multi-layer stack is provided in spaced relation to the first multi-layer stack, and wherein a drain structure of the FET is provided over or in close proximity to the second multi-layer stack.

[0027] A number of layers of the second multi-layer stack may be different to a number of layers of the first multi-layer stack.

[0028] These and other aspects of the invention will be apparent from the embodiments) described below.

[0029] BRIEF DESCRIPTION OF THE DRAWINGS

[0030] In order that the present invention may be more readily understood, embodiments of the invention will now be described, by way of example, with reference to the accompanying drawings, in which:

[0031] Figure 1 is a schematic representation of a field-effect transistor comprising a multi-layer stack according to an example;

[0032] Figure 2 is a schematic representation of the composition of multiple layers of aluminium gallium nitride according to an example;

[0033] Figure 3 is a schematic representation of a field-effect transistor comprising a multi-layer stack according to another example;

[0034] Figure 4 is a schematic representation of a field-effect transistor comprising a multi-layer stack according to yet another example;

[0035] F igure 5 is a flow chart of a method of fabricating a multi-layer stack for use in a field-effect transistor according to an example; and

[0036] Figure 6 is a flow chart of a method of fabricating field-effect transistor, FET, comprising a multi-layer stack according to an example. DETAILED DESCRIPTION

[0037] Example embodiments are described below in sufficient detail to enable those of ordinary skill in the art to embody and implement the systems and processes herein described. It is important to understand that embodiments can be provided in many alternate forms and should not be construed as limited to the examples set forth herein.

[0038] Accordingly, while embodiments can be modified in various ways and take on various alternative forms, specific embodiments thereof are shown in the drawings and described in detail below as examples. There is no intent to limit to the particular forms disclosed. On the contrary, all modifications, equivalents, and alternatives falling within the scope of the appended claims should be included. Elements of the example embodiments are consistently denoted by the same reference numerals throughout the drawings and detailed description where appropriate.

[0039] The terminology used herein to describe embodiments is not intended to limit the scope. The articles “a,” “an,” and ‘The” are singular in that they have a single referent, however the use of the singular form in the present document should not preclude the presence of more than one referent. In other words, elements referred to in the singular can number one or more, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises,” “comprising,” “includes,” and / or “including,” when used herein, specify the presence of stated features, items, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, items, steps, operations, elements, components, and / or groups thereof.

[0040] Unless otherwise defined, all terms (including technical and scientific terms) used herein are to be interpreted as is customary in the art. It will be further understood that terms in common usage should also be interpreted as is customary in the relevant art and not in an idealized or overly formal sense unless expressly so defined herein.

[0041] One key distinction between GaN technology and conventional silicon technology for power transistors lies in the fact that GaN is a lateral technology, meaning that the gate, source, and drain contacts are positioned on the same surface, and current flows laterally across the device, in contrast to the vertical current flow seen in conventional silicon power MOSFETs. This lateral configuration provides the significant advantage that device performance can be tailored by simply altering the lateral layout, offering greater design flexibility and enabling the monolithic integration of multiple components on a single chip.

[0042] A common approach in the industry, employed by most GaN manufacturers, is the pGaN approach, where an AlGaN barrier is grown on top of a GaN buffer layer. Due to the spontaneous and piezoelectric polarisation effects inherent to the GaN / AlGaN heterostructure, a high-density two-dimensional electron gas (2DEG) forms at the interface between the AlGaN barrier and the GaN channel, enhancing electron mobility. To achieve normally-off operation (i.e., a positive threshold voltage), a p-type doped GaN layer is introduced beneath the metal gate in the gate region only, thereby depleting the 2DEG in this region. This concept, known as the pGaN normally-off approach, is widely adopted due to its mature development and proven performance characteristics.

[0043] The pGaN approach offers several advantages: the lateral technology allows for the optimisation of device breakdown voltage and other electrical characteristics through layout modifications, and the monolithic integration of multiple functions on a single chip is feasible. The pGaN gate enables normally-off operation, a crucial safety feature for power devices, and its Schottky contact structure permits the use of standard gate-driving schemes, simplifying circuit design. Additionally, GaN on silicon epitaxy facilitates the use of cost-effective 6-inch and 8-inch silicon substrates, significantly reducing manufacturing costs compared to alternative wide bandgap substrates such as silicon carbide. There is a well-established trade-off between performance and reliability, allowing manufacturers to balance these factors to meet specific application requirements.

[0044] However, this technology also presents several challenges. The lateral configuration, while advantageous for integration and layout flexibility, is inherently less efficient in terms of area utilisation compared to vertical technology, potentially limiting the overall current-carrying capability per unit area. Devices based on the pGaN approach often exhibit large dynamic instabilities in threshold voltage and may have low static threshold voltages, impacting device stability during operation. Gate reliability remains a significant concern, as the use of dopants such as magnesium can lead to defect formation and degradation of gate performance over time, potentially causing failure in demanding applications. The process for dopant activation is technically challenging due to the precise control required over temperature, time, and atmospheric conditions to ensure proper incorporation of the dopants into the crystal lattice without inducing additional defects. This process is not only technically demanding but also time-consuming, often involving lengthy annealing steps that significantly increase production time and overall costs. Dynamic effects, such as current collapse and dynamic on-resistance (Rdson) variations, are commonly observed due to epitaxial defects and dislocations, which can degrade switching performance and efficiency. The presence of dynamic Rdson, which refers to the increase in on-state resistance during high-frequency switching, affects the overall efficiency of the power device. The limited degrees of freedom available for single-barrier AlGaN devices also constrain the optimisation of key parameters such as threshold voltage, electric field management, and overall device reliability, making it challenging to achieve desired performance levels while maintaining long-term stability.

[0045] According to an example, there is provided a new device scheme that allows to overcome most of the issues affecting the conventional single barrier GaN approaches that make use of field plates. Advantageously, the proposed approach eliminates the need for complex dopant activation schemes, such as rapid thermal processing or furnace annealing, which are commonly used in most pGaN approaches. This results in a simpler and more cost-effective process while also enhancing device performance. A high hole concentration of approximately l *1019cm ’ can be achieved in the gate region, significantly surpassing the lower hole concentrations of around l *1017cm ’ typically seen in conventional pGaN approaches due to the limited activation efficiency of magnesium dopants, which generally only achieve partial dopant activation of a few percent. The hole concentration in the proposed scheme can be adjusted by varying the stack composition, including the thickness and aluminium content of the layers within the gate region. The concept also enables the achievement of a higher threshold voltage (Vth) compared to standard pGaN approaches, where Vth values of approximately 1 V are commonly obtained. The polarisation-engineered layer can also be utilised in other parts of the device to locally reduce the maximum electric field, thereby enhancing device reliability. Additionally, the polarisation-engineered layer can serve as a hole injection layer in various regions of the device, contributing to reduced dynamic instabilities.

[0046] The present disclosure is described with reference to flow charts and / or block diagrams of the method, devices and systems according to examples of the present disclosure. Although the flow diagrams described above show a specific order of execution, the order of execution may differ from that which is depicted. Blocks described in relation to one flow chart may be combined with those of another flow chart. In some examples, some blocks of the flow diagrams may not be necessary and / or additional blocks may be added. It shall be understood that each flow and / or block in the flow charts and / or block diagrams, as well as combinations of the flows and / or diagrams in the flow charts and / or block diagrams can be realized by machine readable instructions.

[0047] Figure 1 is a schematic representation of a field-effect transistor comprising a multi-layer stack according to an example. The multi-layer stack 101 for use in a field-effect transistor 100 comprises multiple layers of aluminium gallium nitride (AlGaN), arranged in a stack from a base layer 102 to a surface layer 104. The base layer 102 comprises an average aluminium content equal to a first pre-defined, non-zero value. In contrast, the surface layer 104 comprises an average aluminium content equal to substantially zero.

[0048] In the example shown in Figure 1, the multi-layer stack 101 is shown to be used in a gate region of the transistor 100, but the invention is not limited thereto, as will be described in more detail in relation to the later figures. The field-effect transistor 100 may comprise, for example, a high electron mobility transistor (HEMT) or other types of field-effect transistors (FETs). Other FET types that the transistor 100 might comprise include metal-oxide-semiconductor FETs (MOSFETs) or junction FETs (JFETs).

[0049] To aid understanding of the sets of layers of the multiple layers of AlGaN, in addition to Figure 1, reference will be made also to Figure 2. Figure 2 is a schematic representation of the composition of multiple layers of aluminium gallium nitride according to an example. The multiple layers of AlGaN comprise a first set of layers 117 and a second set of layers 119. Respective layers of the first set of layers 117 are interposed with respective layers of the second set of layers 119, such that respective layers of the first set of layers 117 and the second set of layers 119 alternate with one another.

[0050] In one example, the first set of layers 117 may comprise the base layer 102, while the second set of layers 119 may comprise the surface layer 104; however, the invention is not limited thereto, and the first set of layers 117 may alternatively comprise the surface layer 104, or both the surface layer 104 and the base layer 102, while the second set of layers 119 may comprise the base layer 102, or both the base layer 102 and the surface layer 104.

[0051] As shown on the right side of Figure 2, an average aluminium content of the first set of layers 117 decreases in a direction from the base layer 104 towards the surface layer 104, while an average aluminium content of the second set of layers 119 decreases in a direction towards the surface layer 104. In particular, the average aluminium content of the first set of layers 117 decreases from the first pre-defined (non-zero) value according to a first profile, wherein the first profile defines a first rate of reduction of average aluminium content. The first predefined value may define an average aluminium content of between 10% to 25%. In a specific example, the first predefined value may define an average aluminium content of around 15%.

[0052] In contrast, the average aluminium content of the second set of layers 119 decreases from a second predefined (non-zero) value that is higher than the first pre-defined (non-zero) value according to a second profile, wherein the second profile defines a second rate of reduction of average aluminium content. The second predefined value may define an average aluminium content of around 1% to 5% more than that of the first predefined value. The first rate of reduction of average aluminium content and the second rate of reduction of average aluminium content may define a rate of reduction of average aluminium content of around 1% to 15%.

[0053] In other words, the multi-layer stack 101 comprises different layers of AlGaN having the average aluminium content decreasing from an initial value at the bottom of the stack 101 (i.e., base layer 102), down to zero at the top of the stack 101 (i.e., surface layer 104). While the average aluminium content is decreasing from the base layer 104 towards the surface layer 104, the specific aluminium content in each layer fluctuates, rising and falling between adjacent layers (i.e., between a layer of the first set of layers 117 and a layer of the second set of layers 119). This alternating pattern of Al content generates positive and negative polarisation charges at the various interfaces within the layer structure, which in turn influences the electric field distribution within the transistor device. As such, the performance of the transistor device 100 can be optimised.

[0054] Varying the stack composition enables a p-type gate module where, instead of relying on conventional external doping profiles such as magnesium doping, a novel polarisation-engineered gate concept is employed. This approach enables the achievement of very high hole concentrations, which are not feasible with conventional pGaN methods. Typically, the activation rate for p- type dopants in conventional schemes is only a few percent of the total implanted dose, limiting the maximum hole concentration in the p-type gate region to approximately P I O1’ cm3. In contrast, the proposed method allows for a maximum hole concentration exceeding P IO1’ cm3. Consequently, the threshold voltage attainable with this new concept is significantly higher than what can be achieved with current conventional pGaN approaches that use magnesium as the dopant.

[0055] The hole concentration in the multi-layer stack 101 can be adjusted by varying the composition of the stack, including the thickness and aluminium content of the layers within the gate region. A thickness of the layers of the multiple layers of the multi-layer stack 101 may be between 5 nanometres to 50 nanometres. Etching may be employed to selectively remove portions of the layers that make up the overall p-type-like layer, thereby allowing for precise modification of the layer's composition. Additionally, etching can be used to adjust the effective "doping" within the layer, thereby influencing its electrical properties and performance characteristics.

[0056] The field-effect transistor 100 may further comprise, in addition to the multi-layer stack 101, a substrate 103. The substrate 103 may serve as the foundational base of the transistor and could be composed of silicon, sapphire, or other suitable materials depending on the application. The nucleation layer 105 may be positioned directly above the substrate 103. The nucleation layer 105 may comprise a material such aluminium nitride or a similar compound, so as to facilitate the growth of high-quality epitaxial layers and ensure a good interface with the underlying substrate 103.

[0057] The transition layer 107 may be situated between the nucleation layer 105 and the gallium nitride (GaN) layer 109. The transition layer 107 might be designed to manage lattice mismatch issues, providing a smooth transition between the nucleation layer 105 and the subsequent GaN layer 109. The GaN layer 109 may comprise two distinct sub-layers: the GaN buffer 111 and the GaN channel layer 113. The GaN buffer 111 may act as a foundational layer, supporting the GaN channel layer 113 and reducing strain-related issues. The GaN channel layer 113 may comprise a region where the two-dimensional electron gas forms.

[0058] Above the GaN channel layer 113, an aluminium gallium nitride (AlGaN) barrier layer 115 may be formed. This layer may create a high-density two-dimensional electron gas at the interface with the GaN channel layer 113, thereby achieving operation of the transistor 100.

[0059] The multi-layer stack 101 may comprise a first multi-layer stack 101, arranged over at least a portion of the AlGaN barrier layer 115. The gate terminal 120 of the field-effect transistor 100 may be positioned on the surface layer 104 of the first multilayer stack, achieving high hole concentration in the gate region.

[0060] Figure 3 is a schematic representation of a field-effect transistor comprising a multi-layer stack according to another example. The field-effect transistor 300 of Figure 3 largely corresponds to the field-effect transistor 100 of Figure 1. Same reference numerals denote the same elements functioning likewise in Figures 1 and 3.

[0061] The difference between the field-effect transistor 300 of Figure 3 and the field-effect transistor 100 of Figure 1 is the presence of a second multi-layer stack 121. The second multi-layer stack 121 may be identical, or substantially identical, to the first multi-layer stack 101.

[0062] The second multi-layer stack 121 may be arranged in close proximity to a drain region 130 of the field-effect transistor 300. The primary rationale for positioning the second multi-layer stack 121 near the drain side is twofold: firstly, it facilitates the reduction of the electric field by depleting the two-dimensional electron gas at the AlGaN barrier 115 / GaN channel 113 interface, which helps to manage and mitigate high electric fields within the device; secondly, it enables hole injection into the GaN channel 113 and buffer 111, leading to improved dynamic behaviour of the device by enhancing its overall performance and stability during operation.

[0063] Figure 4 is a schematic representation of a field-effect transistor comprising a multi-layer stack according to yet another example. Same reference numerals denote the same elements functioning likewise in Figures 1, 3 and 4. The transistor 400 of Figure 4 largely corresponds to the transistor 300 of Figure 3. The main distinction between transistor 400 and transistor 300 lies in the composition of the second multi-layer stack 121 compared to the first multi-layer stack 101 used in the gate region 120. For instance, the second multi-layer stack 121 may employ fewer layers near the drain contact 130. This adjustment enables precise control over the extent of depletion induced by the polarisation-engineered stack on the two-dimensional electron gas (2DEG) channel beneath it. Consequently, this approach provides a higher degree of freedom in tailoring the device's performance to meet specific operational requirements.

[0064] Figure 5 is a flow chart of a method of fabricating a multi-layer stack for use in a field-effect transistor according to an example. The multi-layer stack to be fabricated may comprise the multi-layer stack 101 described herein. The method comprises, in block 501, forming a base layer, wherein the base layer comprises an average aluminium content equal to a first predefined, non-zero, value. In block 502, the method comprises forming multiple layers of aluminium gallium nitride, AlGaN, in a stack over the base layer. In block 503, the method comprises forming a surface layer with an average aluminium content equal to substantially zero over the multiple layers of AlGaN, wherein the multiple layers of AlGaN comprise a first set of layers and a second set of layers, wherein respective layers of the first set of layers are interposed with respective layers of the second set of layers such that respective layers of first and second sets of layers alternate with one another, wherein an average aluminium content of the first set of layers decreases, in a direction towards the surface layer, from the first predefined, non-zero, value according to a first profile, wherein the first profile defines a first rate of reduction of average aluminium content, wherein an average aluminium content of the second set of layers decreases, in the direction towards the surface layer, from a second predefined, non-zero, value that is higher than the first predefined, non-zero, value, according to a second profile, wherein the second profile defines a second rate of reduction of average aluminium content.

[0065] Figure 6 is a flow chart of a method of fabricating a field-effect transistor, FET, comprising a multi-layer stack according to an example. The field-effect transistor may comprise the field-effect transistor 100, 300, 400 described herein. In block 601 , the method comprises providing a substrate. In block 602, the method comprises forming a nucleation layer over the substrate. The method comprises, in block 603, forming a transition layer arranged between the nucleation layer and a gallium nitride, GaN, layer, wherein the GaN layer comprises a GaN buffer and a GaN channel layer. In block 604, the method comprises forming an AlGaN barrier layer over the GaN channel layer, while in block 605, the method comprises forming or providing a first multi-layer stack over at least a portion of the AlGaN barrier layer. In block 606, the method comprises forming a gate terminal of the FET on the surface layer of the first multi-layer stack, followed by forming a source region and a drain region in block 607.

[0066] The preceding description has been provided to enable others skilled in the art to best utilize various aspects of the exemplary embodiments disclosed herein. This exemplary description is not intended to be exhaustive or to be limited to any precise form disclosed. Many modifications and variations are possible without departing from the spirit and scope of the instant disclosure. The embodiments disclosed herein should be considered in all respects illustrative and not restrictive. Reference should be made to the appended claims and their equivalents in determining the scope of the instant disclosure.

Claims

CLAIMS1. A multi-layer stack (101) for use in a field-effect transistor (100), the multi-layer stack (101) comprising: multiple layers of aluminium gallium nitride, AlGaN, arranged in a stack from a base layer (102) to a surface layer (104), wherein the base layer (102) comprises an average aluminium content equal to a first predefined, non-zero, value, wherein the surface layer (104) comprises an average aluminium content equal to substantially zero, wherein the multiple layers of AlGaN comprise a first set of layers (117) and a second set of layers (119), wherein respective layers of the first set of layers (117) are interposed with respective layers of the second set of layers (119) such that respective layers of first and second sets of layers (117, 119) alternate with one another, wherein an average aluminium content of the first set of layers (117) decreases, in a direction from the base layer (104) towards the surface layer (104), from the first predefined, non-zero, value according to a first profile, wherein the first profile defines a first rate of reduction of average aluminium content, wherein an average aluminium content of the second set of layers (119) decreases, in the direction towards the surface layer (104), from a second predefined, non-zero, value that is higher than the first predefined, non-zero, value, according to a second profile, wherein the second profile defines a second rate of reduction of average aluminium content.

2. The multi-layer stack of claim 1, wherein the first predefined value defines an average aluminium content of between around 10% - 25%.

3. The multi-layer stack of claim 1 or 2, wherein a thickness of respective layers of the multiple layers is between around 5nm - 50nm.

4. The multi-layer stack of any preceding claim, wherein the first predefined, non-zero, value defines an average aluminium content of around 15%.

5. The multi-layer stack of any preceding claim, wherein the second predefined, non-zero, value defines an average aluminium content of around 1% - 5% more than that of the first predefined, non-zero, value.

6. The multi-layer stack of any preceding claim, wherein at least one of the first rate of reduction and the second rate of reduction define a rate of reduction of average aluminium content of around 1% - 15%.

7. A field-effect transistor, FET, (100) comprising at least one multi-layer stack (101) as claimed in any preceding claim.

8. The field-effect transistor of claim 7, further comprising:9a substrate (103); a nucleation layer (105) formed over the substrate (103); a transition layer (107) arranged between the nucleation layer (105) and a gallium nitride, GaN, layer (109), wherein the GaN layer (109) comprises a GaN buffer (111) and a GaN channel layer (113); an AlGaN barrier layer (115) formed over the GaN channel layer (113); and a first multi-layer stack (101) arranged over at least a portion of the AlGaN barrier layer (115), wherein a gate terminal (120) of the FET (100) is arranged on the surface layer (104) of the first multi-layer stack (101).

9. The field-effect transistor of claim 8, further comprising a second multi-layer stack (121) arranged over at least a portion of the AlGaN barrier layer (115), wherein the second multi-layer stack (121 ) is provided in spaced relation to the first multi-layer stack (101), and wherein a drain structure (130) of the FET (100) is arranged on or in close proximity to the second multi-layer stack (121).

10. The field-effect transistor of claim 9, wherein a number of layers of the second multi-layer stack (121) is different to a number of layers of the first multi-layer stack (101).

11. The field-effect transistor of any one of claims 8 to 10, wherein the substrate (103) comprises a silicon substrate, wherein the nucleation layer (105) comprises aluminium nitride, AIN.

12. A method of fabricating a multi-layer stack for use in a field-effect transistor, the method comprising: forming a base layer, wherein the base layer comprises an average aluminium content equal to a first predefined, non-zero, value (501); and forming multiple layers of aluminium gallium nitride, AlGaN, in a stack over the base layer (502); and forming a surface layer with an average aluminium content equal to substantially zero over the multiple layers of AlGaN (503), wherein the multiple layers of AlGaN comprise a first set of layers and a second set of layers, wherein respective layers of the first set of layers are interposed with respective layers of the second set of layers such that respective layers of first and second sets of layers alternate with one another, wherein an average aluminium content of the first set of layers decreases, in a direction towards the surface layer, from the first predefined, non-zero, value according to a first profile, wherein the first profile defines a first rate of reduction of average aluminium content, wherein an average aluminium content of the second set of layers decreases, in the direction towards the surface layer, from a second predefined, non-zero, value that is higher than the first predefined, non-zero, value, according to a second profile, wherein the second profile defines a second rate of reduction of average aluminium content.

13. A method of fabricating a field-effect transistor, FET, comprising a multi-layer stack as claimed in any of claims 1 to 6, the method comprising: providing a substrate (601); forming a nucleation layer over the substrate (602); forming a transition layer arranged between the nucleation layer and a gallium nitride, GaN, layer, wherein theGaN layer comprises a GaN buffer and a GaN channel layer (603); forming an AlGaN barrier layer over the GaN channel layer (604); forming or providing a first multi-layer stack over at least a portion of the AlGaN barrier layer (605); forming a gate terminal of the FET on the surface layer of the first multi-layer stack (606); and forming a source region and a drain region (607).

14. The method of claim 13, wherein forming the drain region comprises forming a second multi-layer stack arranged over at least a portion of the AlGaN barrier layer, wherein the second multi-layer stack is provided in spaced relation to the first multi-layer stack, and wherein a drain structure of the FET is provided over or in close proximity to the second multi-layer stack.

15. The method of claim 14, wherein a number of layers of the second multi-layer stack is different to a number of layers of the first multi-layer stack.

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