Interposer and semiconductor package

Abstract

The purpose of the present disclosure is to provide an interposer that prevents peeling between an inner layer structure and an outer layer structure.　To this end, an interposer disclosed herein comprises: an inner layer structure (7) including at least one inner layer wiring layer; a first outer layer structure (5) disposed on a first surface of the inner layer structure; and a second outer layer structure disposed on a second surface of the inner layer structure, wherein the first outer layer structure (5) and the second outer layer structure have higher rigidity than the inner layer structure (7). The interposer comprises: a filled part (21b) in which a portion of the first outer layer structure is filled from the first surface side of the inner layer structure toward the inside of the inner layer structure; and / or a filled part in which a portion of the second outer layer structure is filled from the second surface side of the inner layer structure toward the inside of the inner layer structure.

Description

Interposer and Semiconductor Package

[0001] The present invention relates to an interposer for mounting a semiconductor device and a semiconductor package in which a semiconductor device is mounted on the interposer.

[0002] In recent years, SiP (System In Package) has been put into practical use, in which a plurality of different types of semiconductor devices (semiconductor chips) are mounted on an interposer to form a single high-performance semiconductor package. According to this method, it is possible to obtain a "semiconductor package", which is a single high-performance semiconductor device, without increasing the process cost.

[0003] Further, as the semiconductor device mounted on the above SiP, HBM (High Bandwidth Memory), which is a stacked DRAM, tends to be widely used. Generally, HBM has a narrow pitch of about 55 μm for connection terminals, and it is necessary to form connection terminals of a similar degree on the interposer.

[0004] Further, the interposer as described above will be connected to FC-BGA. The CTE (Coefficient of Thermal Expansion) of FC-BGA is about 18 ppm / °C, which is high compared with the CTE of 3 ppm / °C of the semiconductor chip. Therefore, it is required that the interposer has a function of relaxing the CTE mismatch between the semiconductor chip and FC-BGA. Furthermore, for the convenience of assembly as a semiconductor package, it is desirable that after mounting the semiconductor device on the interposer, it can be mounted on FC-BGA. Therefore, the interposer needs to exist as a single entity independent of FC-BGA.

[0005] Patent Document 1 discloses a method for manufacturing a semiconductor package in order to suppress warping of an interposer, which includes the steps of: preparing a laminate having a plate-shaped first reinforcing member, a laminate for a first conductor pattern wiring substrate, and a plate-shaped second reinforcing member arranged on a second conductor pattern; heating the laminate to heat-cur the insulating layer; selectively removing a part of the first reinforcing member to form an opening for exposing the first conductor pattern; selectively removing a part of the second reinforcing member to form an opening 41 for exposing the second conductor pattern; and connecting a semiconductor element to the second conductor pattern exposed from the opening of the second reinforcing member.

[0006] Furthermore, Patent Document 2 discloses an interposer that enables quality checks of the interposer itself before mounting semiconductor devices and provides a SiP with a high yield, with the aim of providing an SiP with a high yield. The interposer comprises an inner layer structure including at least one inner layer wiring layer, a first outer layer structure disposed on the first surface of the inner layer structure and having higher rigidity than the inner layer structure, and a second outer layer structure disposed on the second surface of the inner layer structure and having higher rigidity than the inner layer structure. The inner layer wiring layer comprises wiring disposed on the surface of the first insulating resin layer and conductive members connected to the wiring and penetrating the first insulating resin layer, and the first outer layer structure and the second outer layer structure comprise a second insulating resin layer and conductive members penetrating the second insulating resin. In this interposer, terminals that can be connected to a semiconductor device and that can be electrically inspected are formed on the surface of the first outer layer structure and / or the second outer layer structure opposite to the surface connected to the inner layer structure.

[0007] International Publication No. 2013 / 065287, International Publication No. 2023 / 157624

[0008] However, the interposer shown in Patent Document 1 has a structure in which a resin composition is impregnated into a fibrous substrate, so the maximum diameter of the vias that can be formed is limited to 50 μm. In addition, the pitch between vias is limited to 130 μm, making it difficult to mount an HBM, which is a stacked DRAM.

[0009] Furthermore, conventional interposers such as fan-out packages and silicon interposers, and semiconductor packages using them, do not anticipate a process where the interposer itself is inspected before mounting the semiconductor device. Therefore, in conventional manufacturing methods, multiple chips are mounted on the interposer without the interposer itself being inspected or guaranteed. As a result, the yield of the semiconductor package is the sum of manufacturing defects in the interposer and chip mounting defects, and these cannot be separated.

[0010] Specifically, the manufacturing yield of SiP can be simply described by the following calculation formula (1): "Interposer yield" (YINTERPOSER): (value between 0 and 1) Geometric mean yield of semiconductor chip mounting ("Mounting yield" (YASSEMBRY): (value between 0 and 1) Number of semiconductor devices mounted on the SiP: N (integer greater than or equal to 1) Manufacturing yield of SiP (YTOTAL): (value between 0 and 1) Then the manufacturing yield of SiP is as follows: (YTOTAL) = (YINTERPOSER) × (YASSEMBRY)N ・・・・・(1)

[0011] As shown in equation (1), the manufacturing yield of a SiP is the interposer yield plus the geometric mean yield of chip mounting raised to the power of the number of chips. Here, if both the "interposer yield" (YINTERPOSER) and the "mounting yield" (YASSEMBRY) are 90%, and the SiP has 7 chips, then (YINTERPOSER) = (YASSEMBRY) = 90%, N = 7... (2) (YTOTAL) = 0.9 × 0.97 = 43.0%... (3) Thus, even if each process yield is 90%, the overall manufacturing yield of the SiP becomes extremely low, which is a problem.

[0012] In a SiP (System-in-Package) that combines multiple semiconductor devices into a single semiconductor package, even if each individual semiconductor device passes inspection, a single manufacturing defect or mounting defect in the interposer can lead to the discarding of the entire SiP (all multiple semiconductor devices). As a result, as the number of chips increases, the SiP manufacturing yield decreases exponentially, and the number of good chips that are discarded also increases.

[0013] Furthermore, in Patent Document 1, since the entire surface of the mounted semiconductor device is solidified with molding resin, there is a problem in that it becomes impossible to replace or repair individual semiconductor devices that have manufacturing defects. Electrical inspection before molding is necessary to enable repair, but because the interposer is thin, handling is difficult and it is difficult to perform the inspection.

[0014] Furthermore, in Patent Document 2, in order to manufacture a thin, self-supporting interposer, a fine wiring layer is formed in the inner layer, and a highly rigid insulating layer is placed on top of it as a reinforcing layer. However, in this case, a mismatch in the CTE (Coefficient of Thermal Expansion) between the fine wiring layer and the highly rigid insulating layer creates a risk of delamination between the two.

[0015] Therefore, the present invention aims to provide a self-supporting and repairable interposer that can also prevent delamination between the inner and outer layers.

[0016] To solve the above problems, one representative interposer of the present invention comprises an inner layer structure including at least one inner wiring layer, a first outer layer structure disposed on a first surface of the inner layer structure, and a second outer layer structure disposed on a second surface of the inner layer structure. Furthermore, the inner layer structure comprises a filling portion in which a part of the first outer layer structure is filled, extending from the first surface side toward the inside of the inner layer structure, and / or a filling portion in which a part of the second outer layer structure is filled, extending from the second surface side toward the inside of the inner layer structure.

[0017] According to the present invention, it is possible to provide an interposer capable of preventing delamination between the inner fine wiring layer and the reinforcing layer. Problems, configurations, and effects other than those described above will be revealed by the description of embodiments below.

[0018] Figure 1 is a cross-sectional view of the interposer and semiconductor package of the first embodiment. Figure 2 is a diagram showing the relationship between the total CTE and the CTE of the outer wiring layer. Figure 3 is a diagram showing the relationship between the manufacturing defect rate and thickness. Figure 4 is a diagram illustrating the manufacturing process of the interposer and semiconductor package of the first embodiment. Figure 5 is a diagram illustrating the manufacturing process of the interposer and semiconductor package of the first embodiment. Figure 6 is a diagram illustrating the manufacturing process of the interposer and semiconductor package of the first embodiment. Figure 7 is a diagram illustrating the manufacturing process of the interposer and semiconductor package of the first embodiment. Figure 8 is a diagram illustrating the manufacturing process of the interposer and semiconductor package of the first embodiment. Figure 9 is a diagram illustrating the manufacturing process of the semiconductor package of the first embodiment. Figure 10 is a diagram illustrating the manufacturing process of the semiconductor package of the first embodiment. Figure 11 is a plan view of the interposer of the first embodiment. Figure 12 is a diagram illustrating modification 1 of the interposer of the first embodiment. Figure 13 is a diagram illustrating modification 2 of the interposer of the first embodiment. Figure 14 illustrates a third modification (reverse tapered shape) of the interposer according to the first embodiment. Figure 15 illustrates a third modification (reverse tapered shape) of the interposer according to the first embodiment. Figure 16 illustrates a fourth modification of the interposer according to the first embodiment.

[0019] Embodiments of the present invention will be described below with reference to the drawings. However, the present invention is not limited by these embodiments. Furthermore, in the drawings, identical parts are denoted by the same reference numerals. The designations "first" and "second" do not particularly limit the order or configuration, but are defined for the convenience of explanation.

[0020] The positions, sizes, shapes, and ranges of the components shown in the drawings may not represent their actual positions, sizes, shapes, and ranges in order to facilitate understanding of the invention. Therefore, the present invention is not necessarily limited to the positions, sizes, shapes, and ranges disclosed in the drawings.

[0021] In this disclosure, "surface" may refer not only to the surface of the plate-like member, but also to the interface of a layer contained within the plate-like member that is substantially parallel to the surface of the plate-like member. Furthermore, "upper surface" and "lower surface" refer to the surface shown above or below when the plate-like member or a layer contained within the plate-like member is illustrated, and in the figure, the side with the tip of the Z-direction arrow is indicated as the upper surface, and the opposite side of the arrow is indicated as the lower surface. In addition, "upper surface" and "lower surface" may also be referred to as "first surface" and "second surface."

[0022] Furthermore, "side" refers to the surface or thickness of a layer within a plate-like member or a layer contained within a plate-like member. In addition, a part of the surface and the side together are sometimes called the "end." Furthermore, "upward" refers to the direction vertically upward when a plate-like member or layer is placed horizontally. In addition, "upward" and its opposite, "downward," are sometimes referred to as the "positive Z-axis direction" and the "negative Z-axis direction," respectively, and the horizontal direction is sometimes referred to as the "X-axis direction" and the "Y-axis direction."

[0023] Furthermore, "planar shape" and "planar view" refer to the shape of a surface or layer when viewed from above. In addition, "cross-sectional shape" and "cross-sectional view" refer to the shape of a plate-like member or layer when cut in a specific direction and viewed from the horizontal. Furthermore, "center" refers to the center of a surface or layer, excluding the periphery. And "direction of the center" refers to the direction from the periphery of a surface or layer toward the center of the planar shape of the surface or layer.

[0024] (First Embodiment) <Interposer Structure> Figure 1(a) is an example of a schematic cross-sectional view of the interposer 100 of the first embodiment of the present invention. Figure 1(b) is an enlarged schematic cross-sectional view of the interface between the first outer layer structure 5 and the inner layer structure 7 of the interposer 100 of the first embodiment of the present invention. Figure 1(c) is a schematic cross-sectional view of a semiconductor package 150 on which semiconductor devices 50 and 51 are mounted on the interposer 100 of the first embodiment. In this disclosure, the side on which the semiconductor devices 50 and 51 are mounted on the upper and lower surfaces of the interposer 100 is referred to as the "first surface side," and the other side on which the interposer 100 is connected to the motherboard or FC-BGA is referred to as the "second surface side."

[0025] In this embodiment, the second connection terminal 17 is located on the second surface side of the second outer layer structure 11. The second connection terminal 17 serves as a connection terminal to an FC-BGA board or motherboard. The interposer 100 in Figure 1(a) mainly consists of a first outer layer structure 5, an inner layer structure 7, and a second outer layer structure 11. The first outer layer structure 5 is located above the inner layer structure 7, i.e., in the positive Z-axis direction. The first outer layer structure 5 is formed of a second insulating resin layer 6, and the second insulating resin layer 6 has an external connection via 4 that penetrates the second insulating resin layer 6 in the Z-axis direction. The first connection terminal (solder) 16 may be placed on the exposed portion of the external connection via 4, or it may be omitted as appropriate.

[0026] The inner layer structure 7 is positioned between the first outer layer structure 5 and the second outer layer structure 11. The inner layer structure 7 comprises at least one inner wiring layer, which includes a first insulating resin layer 8, wiring 10 arranged on the surface of the first insulating resin layer, and a conductive member connected to the wiring 10 and penetrating the first insulating resin layer in the Z-axis direction. The conductive member penetrating the first insulating resin layer can also function as a via 9 of the inner wiring layer.

[0027] Figure 1(b) is an enlarged view of the interface between the first outer layer structure 5 and the inner layer structure 7 in Figure 1(a). An opening 21a (see Figures 5(i) and (j)) is provided in the first insulating resin layer 8 of the inner layer structure 7 on the side of the first outer layer structure 5, and the second insulating resin layer 6 of the first outer layer structure 5 is filled into the opening 21a to form a filled portion 21b. In other words, the joint interface between the first insulating layer on the first surface side of the inner layer structure and the second insulating layer of the outer layer structure is not a single plane, but rather an uneven structure in which the inner and outer layers intersect, due to the presence of the filled portion 21b. Since the first insulating resin layer 8 and the second insulating resin layer 6 have different coefficients of thermal expansion (CTE), differences occur in dimensional displacement due to temperature changes. The larger this difference, the greater the load on the joint surface between the first insulating resin layer 8 and the second insulating resin layer 6, which can cause delamination between the insulating layers. However, by forming the filled portion 21b, the joint area between the insulating layers increases, and the adhesion strength increases, thus suppressing delamination.

[0028] In Figure 1, the second outer layer structure 11 is positioned below the inner layer structure 7, that is, in the negative Z-axis direction. The second outer layer structure 11 is formed of a second insulating resin layer 12, and external connection vias 14 are formed in the second insulating resin layer 12, penetrating the second insulating resin layer 12 in the Z-axis direction. The external connection vias 14 penetrating the second insulating resin layer 12 connect to the outermost wiring layer of the inner layer structure 7 and can also function as pads for the external connection terminals of the second outer layer structure 11. Furthermore, external connection terminal pads 15 and second connection terminals (solder) 17 are arranged on the second surface side of the second outer layer structure 11.

[0029] Furthermore, it is desirable that the total thickness of the interposer 100 in the Z-axis direction, including the inner layer structure 7, the first outer layer structure 5, and the second outer layer structure 11, be 50 μm or more. In addition, the thickness of the first outer layer structure 5 and the second outer layer structure 11 of the interposer 100 in this embodiment is not limited to the thickness adopted in this embodiment, but if the first outer layer structure 5 and the second outer layer structure 11 have higher physical rigidity than the inner layer structure 7, it is desirable that the sum of the thicknesses of the first outer layer structure 5 and the second outer layer structure 11 is greater than that of the inner layer structure 7. That is, it is desirable that the first outer layer structure 5 and the second outer layer structure 11 be more than half of the total thickness of the interposer 100.

[0030] <Semiconductor Package Structure> Figure 1(c) shows a semiconductor package 150 in which semiconductor devices 50 and 51 are fixed to the first side of the interposer 100 described in Figure 1(a) by underfill 19 (encapsulating resin) and molding resin 20.

[0031] In addition, although the first connection terminal 16 and the second connection terminal 17 shown in Figure 1(c) are made of solder, the type and composition of solder are not limited in this embodiment, and known conductive materials can be used. Furthermore, although the first connection terminal 16 in Figures 1(a) and 1(c) is formed flush with the exposed portion of the external connection via 4 of the first outer layer structure 5, the positional relationship and shape of the first connection terminal 16 and the external connection via 4 are not limited to this. Similarly, although the second connection terminal 17 is formed to match the pad 15 of the external terminal on the external connection via 14 of the second outer layer structure 11, the structure is not necessarily limited to this.

[0032] <First insulating resin layer and second insulating resin layer> When the interposer 100 in the embodiment shown in Figure 1(a) is applied as an interposer for SiP that mounts multiple semiconductor devices, fine wiring with a wiring rule of at least L / S = 8 / 8 μm or less is required. For this reason, the thickness of the first insulating resin layer 8 constituting the inner layer structure 7 must be made thin, at least 25 μm or less. As a result, the inner layer structure 7 must have flexibility and lack physical rigidity, even if the inner layer wiring layer is a multilayer laminated circuit.

[0033] <CTE and Elastic Modulus of Outer Layer Structure> The second insulating resin layer constituting the first outer layer structure 5 and the second outer layer structure 11 is preferably selected from a non-photosensitive insulating resin containing a filler. Furthermore, it is even more preferable that the second insulating resin layer is a non-photosensitive resin layer containing a filler, and is selected from a prepreg, build-up resin, or mold resin with an elastic modulus of 5 GPa or more and a linear thermal expansion coefficient (CTE) of 20 ppm or less. The first insulating resin layer applicable to the inner layer structure 7 in this embodiment is a photosensitive insulating resin or a build-up resin, and the general material properties are low elasticity and high CTE materials with a CTE in the range of 20 ppm to 80 ppm / °C and an elastic modulus in the range of 1.5 to 10 GPa or less. For this reason, if the interposer is formed only from the above material, the CTE will be lower than that of FC-BGA (CTE 18 ppm / °C), making it difficult to realize an interposer that can perform a buffering function with the low CTE of semiconductor devices. In this embodiment, in this respect as well, by selecting a mold resin, prepreg, or build-up resin from which the CTE of the second insulating resin layer used in the first outer layer structure 5 and the second outer layer structure 11 is 20 ppm / °C or less and has a high modulus of elasticity of 5 GPa or more, it is possible to make the CTE of the entire interposer 15 to 30 ppm / °C or less, which is the CTE of FC-BGA.

[0034] When the CTE of the second insulating resin layer used in the first outer layer structure 5 and the second outer layer structure 11 is set to 20 ppm / °C or less, the effect of reducing the overall CTE of the interposer 100 is achieved, as will be explained below. Figure 2 shows the simulation results of the relationship between the overall CTE of the 50 μm thick interposer in this embodiment and the CTE and elastic modulus of the materials used in the first and second outer layer structures. The Y-axis shows the overall CTE of the interposer and the CTE of the first and second outer layer wiring layers. The simulation conditions are as follows. Note that the CTE and elastic modulus of the first and second outer layer wiring layers were calculated as equivalent factors.

[0035] - First outer layer structure thickness: 20 μm, copper wiring volume ratio fixed at 10%, CTE, elastic modulus as a factor - Second outer layer structure thickness: 20 μm, copper wiring volume ratio fixed at 30%, CTE, elastic modulus as a factor - Inner layer structure thickness: 10 μm, CTE: 65 ppm / °C, elastic modulus 2 GPa, copper wiring thickness 2 μm, copper wiring volume ratio 85%, total interposer thickness 50 μm

[0036] The results of the simulation performed under these conditions are shown in the graph in Figure 2. That is, as is clear from Figure 2, by using materials with a CTE of 20 ppm / °C or less for the first outer layer structure 5 and the second outer layer structure 11, the overall CTE of the interposer 100 can be made lower than that of the conventional FC-BGA substrate. It can also be seen that the more highly elastic the material used for the first outer layer structure 5 and the second outer layer structure 11, the greater the effect of reducing the overall CTE of the interposer. From these findings, it has been found that if the elastic modulus of the first outer layer structure 5 and the second outer layer structure 11 is 5 GPa or higher, the overall CTE of the interposer can be effectively reduced, and it is desirable to select materials with a CTE of 20 ppm / °C or less and an elastic modulus of 5 GPa or higher.

[0037] <Outer Layer Structure Configuration and Residual Copper Ratio> In the embodiment of the interposer 100 shown in Figure 1(a), the external connection vias 4 and 14, and pads 15 of the first outer layer structure 5 and the second outer layer structure 11 have the function of electrically connecting the wiring of the first connection terminal 16 and the second connection terminal 17 to the wiring of the inner layer structure 7. For this reason, the first outer layer structure 5 and the second outer layer structure 11 are basically formed with connection paths in the Z direction. On the other hand, in the inner layer structure 7, wiring suitable for miniaturization is used to realize wiring in the Z-axis direction and in a direction perpendicular to the Z-axis, i.e., in the horizontal direction. Although copper is basically used as the conductive material in the interposer in this embodiment, the CTE of copper is relatively high at 16 ppm / °C, so if the copper volume ratio is high in the first outer layer structure 5 and the second outer layer structure 11, it becomes difficult to lower the CTE of the entire interposer 100. For this reason, it is desirable that the residual copper ratio in the first outer layer structure 5 and the second outer layer structure 11 be 80% or less. More preferably, it should be 50% or less. Even more preferably, it should be 30% or less.

[0038] <Effects of the outer layer structure: Crack suppression> As described above, the inner layer structure 7 is difficult to strengthen physically by filling with fillers or glass cloth, and is physically weak (low tensile strength, low elongation). As a result, there is a concern that cracks may occur in the inner layer structure 7 due to temperature changes, leading to malfunctions such as disconnection of the wiring layer. In this regard, in the interposer 100 of this embodiment, the reliability of the inner layer structure 7, which has a fine wiring structure, can be increased by forming the first outer layer structure 5 and the second outer layer structure 11 over both entire surfaces of the inner layer structure 7. It has been found that if the first outer layer structure 5 and the second outer layer structure 11 are only partially formed on the upper and lower surfaces of the inner layer structure 7, cracks may occur in the inner layer structure 7 due to deformation or stress concentration. For this reason, the first outer layer structure 5 and the second outer layer structure 11 need to be formed over both entire surfaces of the inner layer structure 7. In this embodiment, the physical properties and specific materials used for the first outer layer structure 5 and the second outer layer structure 11 are not particularly specified, but it is preferable that the CTEs of the first outer layer structure 5 and the second outer layer structure 11 are similar.

[0039] <Effects of the outer layer structure: Mountability> According to this embodiment, arranging the first outer layer structure 5 and the second outer layer structure 11 on both sides of the inner layer structure 7 is also preferable from the viewpoint of the mountability of the semiconductor device. If the first outer layer structure 5 is not arranged on the upper surface of the inner layer structure 7, and only the second outer layer structure 11 is arranged on the lower surface of the inner layer structure 7, the interposer 100 will warp due to heating during mounting due to the difference in CTE of each material. Such warping is directly related to connection failure of the semiconductor device, so it is desirable to minimize it. In the interposer 100 according to this embodiment, the inner layer structure 7, which has a relatively high CTE and low modulus of elasticity, is sandwiched from both sides by the first outer layer structure 5 and the second outer layer structure 11, which are made of low CTE and high elasticity material, thereby effectively suppressing thermal deformation of the inner layer structure 7. For this reason, it is possible to sufficiently suppress warping of the interposer 100 even in the mounting process of the semiconductor devices 50 and 51.

[0040] <Configuration of the inner layer structure> The inner layer structure 7 shown in Figures 1(a) and (c) consists of a first insulating resin layer 8, wiring 10, vias 9 of the inner layer wiring layer penetrating the first insulating resin layer 8, and openings 21a formed in the first insulating resin layer 8. The thickness, number of layers, wiring layer pattern, via shape, via taper direction of the vias, number of vias, etc. of the components of the inner layer wiring layer in this embodiment are not limited by this embodiment. The inner layer structure 7 may consist of a single layer or multiple layers of inner layer wiring, and the number of layers and thickness are not limited by this embodiment. However, in this embodiment, when considering application to SiP in the interposer 100, it is preferable that the inner layer wiring layer consists of multiple layers.

[0041] <Wiring Rules for the Inner Wiring Layer> The wiring design rules for the wiring 10 in the inner wiring layer of the inner structure 7 shown in Figure 1(a) are preferably wiring design rules applicable to fine inter-chip connections. Preferably, L / S = 15 / 15 or less, more preferably 10 / 10 μm or less. Even more preferably, L / S = 8 / 8 μm or less. If L / S is 15 μm or more, it becomes equivalent to the wiring rules of conventional FC-BGA and is not suitable for mounting HBMs, etc.

[0042] <Insulating resin of the outer layer structure: non-photosensitive resin> The second insulating resin layer 12, which is a component of the first outer layer structure 5 and the second outer layer structure 11 in Fig. 1(a), can be selected from epoxy-phenol resin, epoxy-phenol ester resin, epoxy-cyanate resin, cyanate resin, benzocyclobutene, polyimide, polybenzoxazole, etc., as long as it is a non-photosensitive insulating resin. Furthermore, it may contain a filler or a glass cloth, but the content of the filler or the glass cloth is preferably such that it does not hinder the formation of fine wiring with L / S = 8 / 8 μm or less.

[0043] <Insulating resin layer of the inner layer structure: photosensitive resin> For the material of the first insulating resin layer 8, which is a component of the inner layer structure 7 in Fig. 1(a), known techniques such as benzocyclobutene, polyimide, polybenzoxazole, epoxy resin, epoxy acrylate, acrylate, etc. can be applied as long as it is a photosensitive insulating resin. When at least L / S = 8 / 8 μm or less fine wiring formation is required for the first insulating resin layer 8 in the present embodiment, it is desirable that it is a photosensitive insulating resin advantageous for fine wiring formation.

[0044] <Merit of the photosensitive resin of the first insulating resin layer of the inner layer structure> When the first insulating resin layer 8 is a photosensitive insulating resin, micro vias with a diameter of 20 μm or less can be formed with a photolithography position accuracy of ±3 μm or less. Therefore, it becomes possible to maximize the number of semiconductor devices mounted on the interposer and also maximize the number of connection vias. If it is a photosensitive insulating resin, it is advantageous in that the via formation time does not depend on the number of vias and can be formed in a batch.

[0045] <Insulating resin layer of the inner layer structure: non-photosensitive resin> A non-photosensitive insulating resin can also be used as the material of the first insulating resin layer 8. It can be selected from epoxy-phenol resin, epoxy-phenol ester resin, epoxy-cyanate resin, cyanate resin, benzocyclobutene, polyimide, polybenzoxazole, etc. Furthermore, it may contain a filler or a glass cloth

[0046] <Merits of the first insulating resin layer of the inner layer structure: non-photosensitive resin> When a non-photosensitive insulating resin is used for the inner layer structure, an insulating resin with a high elastic modulus can be selected, so that the interposer can be given high rigidity.

[0047] <Thickness of the insulating resin layer of the inner layer wiring layer> The thickness of the first insulating resin layer 8 is preferably 25 μm or less. The thickness of the first insulating resin layer 8 referred to here refers to the resin thickness between the upper and lower copper wiring patterns. When the thickness of the first insulating resin layer is 25 μm or more, it becomes difficult to form vias with a small diameter of 20 μm or less, and it becomes difficult to increase the wiring density. More preferably, the thickness of the first insulating resin layer is 15 μm or less. Even more preferably, it is 10 μm or less. The thickness of the first insulating resin layer 8 can be appropriately adjusted according to the applied wiring rules and circuit impedance matching.

[0048] <Via diameter of the inner layer wiring layer> The diameter of the via 9 in the inner layer wiring layer is preferably 40 μm or less. The diameter of the via 9 referred to here refers to the maximum diameter part. When the diameter of the via 9 is 40 μm or more, it hinders the high-density wiring. More preferably, the diameter is 30 μm or less. Even more preferably, it is preferably 20 μm or less because it can contribute to the high-density wiring.

[0049] <Thickness of the wiring layer of the inner layer wiring layer> The thickness of the wiring layer 10 is preferably 15 μm or less. More preferably, it is preferably 10 μm or less. Even more preferably, it is preferably 8 μm or less. When it is 15 μm or more, although it depends on the resist for photolithography used, it becomes difficult to form fine wiring with L / S = 15 / 15 μm or less The thickness of the wiring layer is preferably adjusted as appropriate according to the applied wiring rules and circuit impedance matching.

[0050] <Wiring Layer Material for Inner Wiring Layer> The material used for the wiring 10 may include elemental metals such as copper, aluminum, nickel, silver, gold, tungsten, iron, niobium, tantalum, titanium, and chromium, as well as their alloys or additive elements. Alternatively, it may be a layered structure of these various materials. Or, it may be a conductive paste containing these materials, or carbon, conductive resin, etc. For example, when forming a metal layer on the first insulating resin layer 8 by sputtering, it is common practice to form titanium, chromium, nickel, etc. as a single layer or alloy layer, and then form copper. It is also preferable to form a layer of electroless copper plating or electroless nickel plating on the upper surface of the first insulating resin layer 8. Electrolytic copper plating is generally preferred for the wiring 10 because it is simple, inexpensive, and desirable.

[0051] <Interposer Thickness> In this embodiment, the thickness of the interposer 100 is preferably at least 50 μm. As shown in Figure 3, if the thickness is less than 50 μm, sufficient rigidity cannot be obtained in the interposer 100 itself, and defects will occur very frequently in the subsequent external connection terminal formation process, electrical inspection process, and semiconductor device assembly process. According to this embodiment, since electrical inspection of the interposer alone is possible before mounting the semiconductor device, (YINTERPOSER) of the yield after manufacturing and inspection of the interposer as described in Equation 1 can be set to 100%. Therefore, it can contribute to improving the SiP manufacturing yield (YTOTAL).

[0052] (Outline of the manufacturing process) The general outline of the interposer manufacturing method in this embodiment consists of the following steps. First, a support substrate is prepared, and then the interposer can be obtained by the following steps: A first step of forming a second outer layer structure on the support substrate; a second step of forming an inner layer structure above the second outer layer structure; a third step of forming a first outer layer structure above the inner layer structure; a fourth step of separating the second outer layer structure from the support substrate; and a fifth step of forming an external connection opening 21 on the outermost layer of the second outer layer structure.

[0053] Once the formation of the first and second outer layers is complete, the interposer can achieve sufficient rigidity on its own, even without a support substrate. Therefore, in subsequent processes, the interposer or semiconductor package can be manufactured by peeling it off the support substrate. Because there is no support substrate, surface treatment, solder bump formation, and protruding electrode formation can be performed on the connection terminals exposed on both sides of the substrate. In this way, the first and second connection terminals can be formed on both sides of the interposer.

[0054] (Detailed explanation of manufacturing method) The following describes the details of the manufacturing method for interposers and semiconductor packages with reference to Figures 4 to 10.

[0055] <Preparation Process for Support Substrate> As shown in Figure 4(a), first, the support substrate 1 is prepared. The support substrate 1 can be, for example, a glass substrate on which a laser release layer is provided, and a metal layer 2 is provided on the laser release layer. The metal layer 2 may be formed by electroless plating or sputtering. Alternatively, a support substrate may be used in which a carrier copper foil is formed as the metal layer 2 via a prepreg on a CCL (Copper Clad Laminate) substrate. Here, the carrier copper foil has a three-layer structure of carrier copper foil - release layer - ultrathin copper foil, and is a copper foil that can be easily physically peeled off at the release layer interface. The type of support substrate is not limited to the above, and various known substrates can be used.

[0056] Figure 4(b) illustrates the process of forming the second outer layer structure 11. First, a prepreg and a carrier-equipped copper foil 13, which will become the second insulating resin layer 12 of the second outer layer structure 11, are formed on top of the support substrate 1 and the metal layer 2 by lamination press. In this embodiment, a carrier-equipped copper foil 13 with a thickness of 18 μm was used for the carrier copper foil 13b and a carrier-equipped copper foil 13a with a thickness of 3 μm, and the 3 μm thin copper foil 13a was placed on the prepreg side. A 60 μm thick prepreg was used.

[0057] Figure 4(c) shows the carrier copper foil 13b being peeled off from the carrier copper foil 13, and then external connection vias 14 being formed on the second outer layer structure 11 using a CO2 laser. After this, the laser aperture was desmeared, and then electroless copper plating with a thickness of 0.6 μm was formed on the via portion by electroless copper plating (not shown). In this embodiment, vias with a diameter of 60 μm were formed at a pitch of 150 μm.

[0058] Figure 4(d) shows the process of forming a photolithography resist layer on the second outer layer structure 11, then patterning to form a photolithography resist pattern 3, and finally forming wiring 10 by electrolytic copper plating. The thickness of the photolithography resist is determined appropriately in consideration of the height of the wiring to be formed. In this embodiment of the present invention, a dry film resist with a thickness of 25 μm was used, and an electrolytic copper plating layer with a thickness of 18 μm was formed.

[0059] Figure 4(e) shows the second outer layer structure 11 formed after the photolithography resist pattern 3 has been removed, and the thin copper foil 13a and electroless copper plating layer have been etched off. In this embodiment, wiring 10 with a diameter of 120 μm and a wiring thickness of 15 μm is formed on the second outer layer structure at a pitch of 150 μm.

[0060] Figure 5(f) shows the first insulating resin layer 8 of the inner layer structure 7 formed above the second outer layer structure 11, with vias 9 formed. In this embodiment, the first insulating resin layer 8 is formed with a thickness of 21 μm using a photosensitive insulating resin, and vias 9 with a diameter of 15 μm are formed.

[0061] Figure 5(g) shows a first insulating resin layer 8 on which a seed metal layer (not shown) is formed, followed by the formation of a photolithography resist pattern 3, and then the formation of vias 9 and wiring 10 of the inner wiring layer by electroplating. In this embodiment, a seed metal layer of Ti / Cu = 50 / 300 nm was formed by sputtering, and the photolithography resist thickness was 5 μm. As a result, a photolithography resist pattern 3 with L / S = 2 / 2 μm was formed, and then wiring 10 with a thickness of 2 μm was formed using electroplating.

[0062] Figure 5(h) shows the formation of an inner wiring layer consisting of a first insulating resin layer 8, vias 9, and wiring 10 after the resist pattern 3 for photolithography has been peeled off and the seed metal layer has been removed. Note that the wiring formation method and the insulating resin layer formation method are not limited to the method of this embodiment, and an appropriate formation method can be selected.

[0063] Figure 5(i) shows an inner layer structure 7 formed by repeating the process shown in Figures 5(f) to (h) three more times, in which four layers each of wiring 10 and first insulating resin layer 8 are laminated. The thickness of each first insulating resin layer 8 is 6 μm, the thickness of the outermost first insulating resin layer 8 is 8 μm, and the thickness of the wiring 10 is 2 μm. Subsequently, an opening 21a for forming a filling portion 21b is provided in the outermost first insulating resin layer 8, toward the center of the inner thickness of the inner layer structure. The diameter R of the opening 21a is limited by the ratio of the thickness of the insulating resin layer forming the opening (aspect ratio: insulating resin thickness / diameter R). The lower the aspect ratio, the wider the opening a becomes even with the same insulating resin thickness, and the lower the density of the openings a, thus reducing the design freedom. On the other hand, if the aspect ratio is high, the resolution during opening a formation decreases, increasing the risk of defects in opening a formation. Therefore, an aspect ratio of 0.3 to 8 is preferred, and more preferably 1 to 8 is desirable. Furthermore, if the distance between adjacent openings 21a (arrangement pitch: distance between adjacent openings a / diameter R of opening a) is increased, the arrangement density of openings a decreases, reducing the degree of design freedom. On the other hand, if the arrangement pitch is shortened, the thickness of the insulating resin between adjacent openings 21a becomes thinner, increasing the risk of the insulating resin cracking. For this reason, a pitch of 1.2 to 3 relative to the diameter R of the openings 21a is preferable, and more preferably 1.2 to 2.

[0064] Figure 5(j) shows the exposed surface of the inner layer structure 7 after being flattened by CMP (Chemical Mechanical Polishing). Flattening the surface can improve the resolution performance in subsequent photolithography processes, but this process is not mandatory and may be selected as appropriate. In this embodiment, as a result of the CMP process, the thickness of the inner layer structure 7 is 39 μm.

[0065] Figure 6(l) shows a substrate in which, after Figure 5(j), a metal layer 2 is formed on the entire surface of the inner layer structure 7 as shown in Figure 6(k), and a photolithography resist layer is formed on the metal layer 2, and a photolithography resist pattern 3 is formed by patterning. The thickness of the photolithography resist is appropriately determined in consideration of the height of the pads to be formed. In the embodiment of the present invention, a liquid photolithography resist of 70 μm was applied, and the resist pattern 3 was formed so that cylindrical pads with a pitch of 50 μm and a diameter of 25 μm could be formed as pads for the first connection terminals.

[0066] Figure 6(m) shows the results after the process in Figure 6(l), where external connection vias 4 are formed by electrolytic copper plating, followed by the removal of the resist pattern 3 and metal layer 2. In this embodiment, the average height of the external connection vias 4 formed by copper plating in the Z direction was 60 μm.

[0067] Figure 6(n) shows the formation of the second insulating resin layer 6, which forms the first outer layer structure 5. In this embodiment, the second insulating resin layer 6, which is made of a non-photosensitive resin, is preferably a non-photosensitive resin containing at least a filler, and is selected from prepregs, build-up resins, and molded resins with an elastic modulus of 5 GPa or more and a CTE of 20 ppm / °C or less. In this embodiment, the second insulating resin layer 6 was formed by vacuum lamination using a 70 μm thick film-like molded resin. At this time, the filling portion 21b is formed by filling the opening 21a with the second insulating resin layer 6. The type, thickness, and formation method of the non-photosensitive resin are not limited to the examples described in this embodiment, and it is possible to select appropriate materials and formation methods. Furthermore, by adding a step of roughening the opening 21a of the first insulating resin layer 8 before forming the second insulating resin layer 6, higher adhesion between the first insulating resin layer 8 and the second insulating resin layer 6 can be obtained, and the effect of reducing peeling can be obtained. As for roughening methods, wet treatment with potassium permanganate solution or dry treatment using plasma treatment can be appropriately selected.

[0068] Figure 7(o) shows the result after the process in Figure 6(n), where the second insulating resin layer 6 has been further ground down by 20 μm with a grinder to expose the external connection vias 4.

[0069] Figure 7(p) shows the step of removing the support substrate 1 after Figure 7(o).

[0070] Figure 7(q) shows the process of forming a photolithography resist pattern 3 on the second outer layer structure 11 after Figure 7(p).

[0071] Figure 7(r) shows the result after Figure 7(q), where a protective sheet is applied to the surface of the first outer layer structure 5 (not shown), pads 15 are formed by electrolytic copper plating, the photolithography resist pattern 3 and metal layer 2 are removed, and the protective sheet of the first outer layer structure 5 is further removed (not shown). As a result, an interposer 100 can be obtained in which the external connection vias 4 and pads 15 are exposed on the first outer layer structure 5. According to this embodiment, in the steps from Figure 7(p) onward, a first outer layer structure 5 and a second outer layer structure 11 selected from high-elasticity, low-CTE material are formed on both sides of the inner layer structure 7, forming an interposer 100 with a total thickness of 50 μm or more. The interposer formed in this way has the rigidity to be transported by itself. Furthermore, since the support has been removed from the interposer, both sides of the interposer are exposed, making it possible to form the first connection terminal 16 and the second connection terminal 17 on the front and back surfaces of the interposer.

[0072] Figure 8(s) shows the process of surface treatment on the external connection vias 4 (pads), which are external connection terminals of the first outer layer structure 5, and the pads 15 of the external connection terminals of the second outer layer structure 11. The type and thickness of these surface treatments can be any known method as appropriate. After the surface treatment, solder can be formed on both pad layers. For the solder formation method, any known method such as screen printing, ball mounting, electroplating, or filling with molten solder after forming a resist pattern for photolithography can be appropriately employed. In this embodiment, electroless Ni / Pd / Au was applied to both sides as a surface treatment, and solder was formed on both the front and back sides using the solder ball method. In this way, the interposer 100 of this embodiment can be obtained, in which the first connection terminal 16 and the second connection terminal 17 are formed on the first outer layer structure 5 and the second outer layer structure 11.

[0073] Figure 8(t) shows the process of performing an electrical inspection of the interposer 100 by simultaneously contacting the first connection terminal 16 and the second connection terminal 17 on both sides of the interposer 100 with an electrical inspection probe.

[0074] The specific electrical inspection and the manufacturing procedure utilizing the results are as follows: 1) A first inspection step in which electrical inspection of the interposer is performed from the connection terminals. 2) A first judgment step in which the quality of the interposer is determined based on the results of the first inspection step. 3) A temporary connection step in which semiconductor devices are mounted on the interposer that was judged to be "good" in the first judgment step. 4) A second inspection step in which electrical inspection is performed on the temporarily connected semiconductor packages. 5) A second judgment step in which the quality of the semiconductor packages is determined based on the results of the second inspection step. 6) A repair step in which the mounting of semiconductor devices that were judged to be "bad" in the second judgment step is repaired and / or replaced.

[0075] In addition to the above manufacturing procedure, the following steps may be performed: 7) A third inspection step in which an electrical inspection is performed on the semiconductor package after the repair step. 8) A third judgment step in which the quality of the semiconductor package is determined based on the results of the third inspection step. 9) A fixing step in which underfill is supplied to the gap between the semiconductor device and the interposer of the semiconductor package that was judged to be "good" in the third judgment step.

[0076] Figure 8(u) shows the process of cutting out individual interposers by dicing a panel raw material in which multiple interposers are continuously formed in a grid pattern along the A-A' section. In this way, the interposer 100 in this embodiment can be manufactured.

[0077] In the first embodiment described above, an opening 21a was formed in the first insulating resin layer 8, the outermost layer on the first face side of the inner layer structure 7, and the second insulating resin layer of the first outer layer structure was filled into it. However, instead of forming an opening 21a on the first face side of the inner layer structure 7, an opening similar to the opening 21a may be formed in the first insulating resin layer 8, the outermost layer on the second face side of the inner layer structure 7, and the second insulating resin layer of the second outer layer structure may be filled into it. Alternatively, openings may be formed on both the first and second face sides of the inner layer structure 7, and the second insulating resin layer may be filled from both sides. In other words, a filling portion may be provided from both the first and second face sides of the inner layer structure 7 toward the center of the inner thickness of the inner layer structure.

[0078] (Method for assembling semiconductor device) Next, with reference to Figure 9, a method for mounting a semiconductor device onto the interposer according to the present invention and manufacturing a semiconductor package will be described.

[0079] Figure 9(a) is a schematic cross-sectional view of the process of manufacturing a semiconductor package by mounting semiconductor devices 50 and 51 on an interposer. The interposer used in this embodiment has undergone electrical testing as a standalone unit and has been confirmed to be a good product.

[0080] For mounting semiconductor devices, known mounting techniques such as mass reflow and TCB (Thermal-Compression bonding) can be used. Using TCB makes it less likely for misalignment to occur during mounting of multiple semiconductor devices or during reflow, and CTE mismatch due to high-temperature heating of the interposer to occur. Furthermore, in this embodiment, it is desirable to use capillary underfill for the underfill process, rather than employing NCF (Non-Conductive Film) or NCP (Non-Conductive Paste). This is because, if a defect is found in a semiconductor device during subsequent electrical inspection, it is easy to replace the defective semiconductor device.

[0081] Next, Figure 9(b) shows an electrical inspection of the SiP as a semiconductor package in this embodiment. By making contact with the second connection terminal 17 and performing an electrical inspection, the "assembly yield (YASSEMBRY)" including the individually mounted semiconductor devices can be inspected, and assembly defects or defects in the semiconductor devices can be identified.

[0082] Figure 9(c) is a schematic cross-sectional view showing the process of partially removing a faulty or defective semiconductor device 52 identified in the previous process and replacing it with a good semiconductor device 53. In this embodiment, since the mounted semiconductor device is not fixed with mold resin or underfill, it is possible to partially correct faulty locations or defective semiconductor devices. After correction, the (YASSEMBRY) shown in equation (4) can be made to 100%. Therefore, according to the interposer in this embodiment, the total yield of SiP assembly (Y) can be increased regardless of the number of chips N to be integrated. TOTAL This can contribute to improving [the performance of the system]. The modification can be performed by reversing the process of TCB implementation.

[0083] Figure 10(d) shows a capillary underfill process in which underfill 19 is formed in a semiconductor package 150 according to this embodiment, on which multiple semiconductor devices are mounted, using an underfill supply device 56. After inspection and correction, the underfill 19 can be used to fix the semiconductor devices to the interposer in this embodiment.

[0084] Figure 10(e) is a schematic cross-sectional view showing the formation of a molding resin 20 on the semiconductor device. This molding resin fixing process is not necessarily required. Furthermore, any known and appropriate method can be used for fixing with the molding resin. The upper surface of the molding resin 20 may also be polished to expose the upper end of the semiconductor device.

[0085] Next, with reference to Figure 11, the placement of the filling portions 21b arranged within the plane of the interposer 100 will be described. Figure 11 is a plan view of the interposer 100 as seen from above of a first embodiment semiconductor package that has been sectionalized. The first connection terminal is located in the center, and the filling portions 21b are located at the corners of the rectangle, their periphery, and at the corners of the rectangle. The force that attempts to peel off due to the difference in the coefficient of thermal expansion between the first insulating resin layer and the second insulating resin layer becomes stronger as the distance from the center of the interposer 100 increases. For this reason, in this embodiment, it is effective to place the filling portions 21b in locations where the peeling force is large. That is, in the xy plane of the interposer 100, it is preferable to place them on the outer periphery of the interposer, and more preferably at the corners of the rectangular interposer. In other words, referring to Figure 8(u), the filling portions 21b are placed near the dicing lines when the interposer is sectionalized from the panel raw material.

[0086] <Modification 1> Next, Modification 1 will be described with reference to Figure 12. Figure 12 differs from the first embodiment in that the first insulating resin layer 8 of the inner layer structure 7 is filled into an opening formed in the second insulating resin layer 6 of the first outer layer structure 5, thereby forming a filled portion 22b. In the following description, the same or equivalent components as those in the first embodiment described above are denoted by the same reference numerals, and their descriptions are simplified or omitted. The manufacturing method for Modification 1 is the same as that of the first embodiment, but with an additional layer of the first insulating resin layer 8 added after the step in Figure 6(k), and a protruding filled portion 22b formed by photolithography. Then, from Figure 6(l) onward, the manufacturing method is the same as that of the first embodiment. In Modification 1, the opening 21a does not need to be formed in the step in Figure 5(i) in the manufacturing method of the first embodiment.

[0087] <Modification 2> Next, Modification 2 will be described with reference to Figure 13. Modification 2 differs from the first embodiment in that, as shown in Figure 13, the cross-sectional shape of the filling portion 21b in the xz plane is a tapered shape that widens upward. In the following description, the same or equivalent components as those in the first embodiment described above are denoted by the same reference numerals, and their descriptions are simplified or omitted. The manufacturing method for Modification 2 is the same as that of the first embodiment, with only the exposure conditions for the opening 21a in Figure 5(i) being different. By adjusting the exposure conditions appropriately to match the insulating resin, the opening 21a can be made tapered, and the structure of Modification 2 can be obtained by going through the process from Figure 6(k) onward. By making the cross-sectional shape of the filling portion 21b tapered, the bonding area between the first insulating resin layer 8 and the second insulating resin layer 6 is increased, thus providing an effect of suppressing peeling. Furthermore, in the modified example 2, as shown in Figure 14, the shape of the filling portion 21b in the first embodiment may be such that the area of ​​the filling portion 21b on the first surface (xy plane) of the inner layer structure 7 is smaller than the area on the bottom surface (xy plane) of the filling portion 21b. In this way, for example, by making the cross-sectional shape of the filling portion 21b on the xz plane an inverse taper shape that widens downwards, the outer layer structure 5 and the inner layer structure 7 can be more firmly fixed together, and peeling can be prevented. Note that in the description of the modified example 2 above, it was assumed that the filling portion 21b is formed near the first surface of the inner layer structure. When the filling portion 21b is formed near the second surface of the inner layer structure, naturally, the tapered shape will have a cross-sectional shape that widens downwards on the xz plane, and the inverse taper shape will have a cross-sectional shape that widens upwards on the xz plane.

[0088] <Modification 3> Next, Modification 3 will be described with reference to Figure 15. Modification 3 differs from the first embodiment in that the filling portion 21b is formed across multiple first insulating resin layers 8. In the following description, the same or equivalent components as those in the first embodiment described above are denoted by the same reference numerals, and their descriptions are simplified or omitted. The manufacturing method for Modification 3 is the same as that of the first embodiment, in which the opening 21a in Figure 5(i) is formed across multiple first insulating resin layers 8, and the filling portion 21b in the process of forming the second insulating resin layer 6 in Figure 5(n) is formed across multiple first insulating resin layers 8. As a result, the bonding area between the first insulating resin layer 8 and the second insulating resin layer 6 is increased, and the effect of suppressing peeling can be obtained.

[0089] <Modification 4> Next, Modification 4 will be described with reference to Figure 16. Modification 4 differs from the first embodiment in that a conductive member is arranged at the bottom of the filling portion 21b. In the following description, the same or equivalent components as those in the first embodiment described above are denoted by the same reference numerals, and their descriptions are simplified or omitted. In Modification 4, a metal layer with a higher elastic modulus than the insulating resin is preferred as the conductive member 23, and for example, copper can be used. By using copper, it can be formed simultaneously when forming the wiring 10 in the inner layer structure 7. By arranging the conductive member 23 with a higher elastic modulus than the insulating resin at the bottom of the filling portion 21b, the filling portion 21b can be fixed with a hard layer, and the effect of suppressing peeling of the first insulating resin layer 8 and the second insulating resin layer 6 can be obtained. Furthermore, in Modification 4, the material with a high elastic modulus formed at the bottom of the filling portion 21b is not limited to a conductive member. Instead of a conductive member, an insulator with a higher elastic modulus than other areas of the inner layer structure may be used.

[0090] Furthermore, the present invention can be appropriately combined or substituted in part or in whole with the above embodiments and modifications. Furthermore, the following embodiments can also be taken. Furthermore, these embodiments can also be combined. (Embodiment 1) An interposer comprising: an inner layer structure including at least one inner layer wiring layer; a first outer layer structure disposed on a first surface of the inner layer structure; and a second outer layer structure disposed on a second surface of the inner layer structure, wherein the first outer layer structure and the second outer layer structure have higher rigidity than the inner layer structure, and the inner layer structure has a filling portion in which a part of the first outer layer structure is filled from the first surface side toward the inside of the inner layer structure and / or a filling portion in which a part of the second outer layer structure is filled from the second surface side toward the inside of the inner layer structure.

[0091] (Aspect 2) An interposer according to the Interposer of Aspect 1, characterized in that the sum of the thicknesses of the first outer layer structure and the second outer layer structure is greater than 50% of the thickness of the interposer.

[0092] (Aspect 3) An interposer according to aspect 1 or 2, characterized in that the resin layers constituting the first outer layer structure and the second outer layer structure are non-photosensitive resins containing fillers.

[0093] (Aspect 4) An interposer according to any one of aspects 1 to 3, characterized in that the resin layer constituting the inner layer structure is a photosensitive resin.

[0094] (Aspect 5) An interposer according to any one of aspects 1 to 4, characterized in that the filling portion formed on the first surface and / or second surface of the inner layer structure penetrates at least one interior wiring layer constituting the inner layer structure.

[0095] (Aspect 6) An interposer according to any one of aspects 1 to 5, characterized in that a conductive member is arranged at the bottom of the filling portion formed in the inner layer structure.

[0096] (Aspect 7) An interposer according to any one of aspects 1 to 6, characterized in that an insulator with a higher modulus of elasticity than other areas of the inner layer structure is arranged at the bottom of the filling portion formed in the inner layer structure.

[0097] (Aspect 8) An interposer according to any one of aspects 1 to 7, characterized in that the filling portion formed in the inner layer structure is arranged on the outer periphery of the interposer.

[0098] (Aspect 9) An interposer according to any one of aspects 1 to 8, characterized in that the filling portion formed in the inner layer structure is arranged at the corner of the interposer.

[0099] (Aspect 10) An interposer according to any one of aspects 1 to 9, characterized in that the xz cross-sectional shape of the filling portion formed in the inner layer structure is tapered.

[0100] (Aspect 11) An interposer according to any one of aspects 1 to 9, characterized in that the xz cross-sectional shape of the filling portion formed in the inner layer structure is an inverse tapered shape.

[0101] (Aspect 12) An interposer comprising: an inner layer structure including at least one inner layer wiring layer; a first outer layer structure disposed on a first surface of the inner layer structure; and a second outer layer structure disposed on a second surface of the inner layer structure, wherein the first outer layer structure and the second outer layer structure have higher rigidity than the inner layer structure, and the inner layer structure has a filling portion in which a part of the inner layer structure is filled, extending from the first surface side toward the first outer layer structure and / or a filling portion in which a part of the inner layer structure is filled, extending from the second surface side toward the second outer layer structure.

[0102] (Aspect 13) A semiconductor package characterized by mounting a semiconductor element on an interposer according to any one of aspects 1 to 12.

[0103] 1: Support substrate, 2: Metal layer, 3: Resist pattern, 4: External connection via, 5: First outer layer structure, 6: Second insulating resin layer, 7: Inner layer structure, 8: First insulating resin layer, 9: Via, 10: Wiring, 11: Second outer layer structure, 12: Second insulating resin layer, 13: Carrier-equipped copper foil, 13a: Thin copper foil, 13b: Carrier copper foil, 14: External connection via, 15: Pad, 16: First connection terminal, 17: Second connection terminal, 18: Inspection probe, 19: Underfill, 20: Molding resin, 21a: Opening, 21b: Filling section, 23: Conductive member, 50, 51, 52, 53: Semiconductor device, 54: External connection electrode of semiconductor device, 55: Connection terminal of semiconductor device, 56: Underfill supply device, 100: Interposer, 150: Semiconductor package

Claims

1. An interposer comprising: an inner layer structure including at least one inner layer wiring layer; a first outer layer structure disposed on a first surface of the inner layer structure; and a second outer layer structure disposed on a second surface of the inner layer structure, wherein the first outer layer structure and the second outer layer structure have higher rigidity than the inner layer structure, and the inner layer structure has a filling portion in which a part of the first outer layer structure is filled, extending from the first surface side toward the inside of the inner layer structure, and / or a filling portion in which a part of the second outer layer structure is filled, extending from the second surface side toward the inside of the inner layer structure.

2. An interposer according to claim 1, characterized in that the sum of the thicknesses of the first outer layer structure and the second outer layer structure is greater than 50% of the thickness of the interposer.

3. An interposer according to claim 1, characterized in that the resin layers constituting the first outer layer structure and the second outer layer structure are non-photosensitive resins containing fillers.

4. An interposer according to claim 1, characterized in that the resin layer constituting the inner layer structure is a photosensitive resin.

5. An interposer according to claim 1, characterized in that the filling portion formed on the first surface and / or second surface of the inner layer structure penetrates at least one interior wiring layer constituting the inner layer structure.

6. An interposer according to claim 1, characterized in that a conductive member is disposed at the bottom of the filling portion formed in the inner layer structure.

7. An interposer according to claim 1, characterized in that an insulator with a higher modulus of elasticity than other regions of the inner layer structure is disposed at the bottom of the filling portion formed in the inner layer structure.

8. An interposer according to claim 1, characterized in that the filling portion formed in the inner layer structure is arranged on the outer periphery of the interposer.

9. An interposer according to claim 1, characterized in that the filling portion formed in the inner layer structure is arranged at the corner of the interposer.

10. An interposer according to claim 1, characterized in that the xz cross-sectional shape of the filling portion formed in the inner layer structure is tapered.

11. An interposer according to claim 1, characterized in that the xz cross-sectional shape of the filling portion formed in the inner layer structure is an inverse tapered shape.

12. An interposer comprising: an inner layer structure including at least one inner layer wiring layer; a first outer layer structure disposed on a first surface of the inner layer structure; and a second outer layer structure disposed on a second surface of the inner layer structure, wherein the first outer layer structure and the second outer layer structure have higher rigidity than the inner layer structure, and the inner layer structure has a filling portion in which a part of the inner layer structure is filled, extending from the first surface side toward the first outer layer structure and / or a filling portion in which a part of the inner layer structure is filled, extending from the second surface side toward the second outer layer structure.

13. A semiconductor package characterized by mounting a semiconductor element on an interposer according to any one of claims 1 to 12.

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