Semiconductor device

Abstract

This semiconductor device comprises: a chip having a main surface; a device structure formed on the main surface; a metal electrode covering the main surface; an alloy layer covering the metal electrode; and an organic insulating film covering the metal electrode with the alloy layer interposed therebetween.

Description

Semiconductor device Related application

[0001] This application corresponds to Japanese Patent Application No. 2024-159525 filed with the Japan Patent Office on September 13, 2024, and the entire disclosure of this application is herein incorporated by reference.

[0002] This disclosure relates to a semiconductor device

[0003] Patent Document 1 discloses a SiC semiconductor device including a first inorganic insulating film, a first main surface electrode covering the first inorganic insulating film and having an electrode sidewall on the first inorganic insulating film, a second inorganic insulating film having an inner covering portion covering the first main surface electrode so as to expose the electrode sidewall, and an organic insulating film covering the electrode sidewall.

[0004] International Publication No. 2021 / 26110

[0005] [Summary] One embodiment of this disclosure provides a semiconductor device including a chip having a main surface, a device structure formed on the main surface, a metal electrode covering the main surface, an alloy layer covering the metal electrode, and an organic insulating film covering the metal electrode with the alloy layer interposed therebetween.

[0006] Figure 1 is a plan view of a semiconductor device according to the first embodiment of the present disclosure. Figure 2 is a cross-sectional view taken along the line II-II shown in Figure 1. Figure 3A is a plan view showing an example of a metal electrode layout. Figure 3B is a plan view showing an example of an alloy layer layout. Figure 4 is a plan view showing an example of a first main surface layout of a chip. Figure 5 is an enlarged view of the area enclosed by the dashed line V in Figure 4. Figure 6 is a cross-sectional view taken along the line VI-VI shown in Figure 5. Figure 7 is a cross-sectional view taken along the line VII-VII shown in Figure 1. Figure 8 is a cross-sectional view taken along the line VIII-VIII shown in Figure 1. Figure 9 is a cross-sectional view taken along the line IX-IX shown in Figure 1. Figure 10 is a schematic diagram showing a SiC wafer used in the manufacture of the semiconductor device. Figure 11A is a cross-sectional view showing a method for manufacturing the semiconductor device. Figure 11B is a cross-sectional view showing a process after Figure 11A. Figure 11C is a cross-sectional view showing a process after Figure 11B. Figure 11D is a cross-sectional view showing a process after Figure 11C. Figure 11E is a cross-sectional view showing a process after Figure 11D. Figure 11F is a cross-sectional view showing a process after Figure 11E. Figure 11G is a cross-sectional view showing a process after Figure 11F. Figure 11H is a cross-sectional view showing a process after Figure 11G. Figure 11I is a cross-sectional view showing a process after Figure 11H. Figure 11J is a cross-sectional view showing a process after Figure 11I. Figure 12 is a cross-sectional view showing a first embodiment example of the alloy layer. Figure 13 is a cross-sectional view showing a second embodiment example of the alloy layer. Figure 14 is a cross-sectional view showing a third embodiment example of the alloy layer. Figure 15A is a plan view showing an example layout of a metal electrode according to the second embodiment of this disclosure. Figure 15B is a cross-sectional view along the XVB-XVB line shown in Figure 15A. Figure 16A is a plan view showing an example layout of a metal electrode according to the third embodiment of this disclosure. Figure 16B is a plan view showing an example layout of an alloy layer according to the third embodiment of this disclosure. Figure 17A is a plan view showing an example layout of a metal electrode according to the fourth embodiment of this disclosure. Figure 17B is a plan view showing an example of the layout of an alloy layer according to the fourth embodiment of this disclosure. Figure 18 is a cross-sectional view showing the main part of a semiconductor device according to the fourth embodiment of this disclosure. Figure 19A is a plan view showing an example of the layout of a metal electrode according to the fifth embodiment of this disclosure. Figure 19B is a plan view showing an example of the layout of an alloy layer according to the fifth embodiment of this disclosure.Figure 20 is a cross-sectional view along the line XX-XX shown in Figure 19A.

[0007] [Detailed Description] Next, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0008] The attached drawings are all schematic diagrams and not strictly accurate; the scale, proportions, angles, etc., do not necessarily match. Corresponding structures in the attached drawings are given the same reference numerals, and redundant explanations are omitted or simplified. For structures whose explanations are omitted or simplified, the explanation given before the omission or simplification applies.

[0009] Where the word "substantially" is used in this specification, it includes not only numerical values ​​(forms) that are approximately equal to the numerical value (form) being compared, but also numerical errors (form errors) within a range of ±10% from the numerical value (form) being compared. In the following descriptions, words such as "first," "second," and "third" are used, but these are symbols attached to the names of each structure to clarify the order of explanation and are not intended to limit the names of each structure.

[0010] In the following description, the conductivity type of a semiconductor (impurity) is indicated using "p-type" or "n-type," but "n-type" may be referred to as the "first conductivity type" and "p-type" as the "second conductivity type." Of course, "p-type" may also be referred to as the "first conductivity type" and "n-type" as the "second conductivity type." "n-type" is the conductivity type due to pentavalent elements, and "p-type" is the conductivity type due to trivalent elements. Unless otherwise specified, trivalent elements are at least one of boron, aluminum, gallium, and indium. Unless otherwise specified, pentavalent elements are at least one of nitrogen, phosphorus, arsenic, antimony, and bismuth.

[0011] Figure 1 is a plan view of a semiconductor device 1A according to the first embodiment of the present disclosure. Figure 2 is a cross-sectional view taken along the line II-II shown in Figure 1. Figure 3A is a plan view showing an example layout of the metal electrode 16. Figure 3B is a plan view showing an example layout of the alloy layer 39. Figure 4 is a plan view showing an example layout of the first main surface 3 of the chip 2. In Figure 3B, for ease of viewing, the reference numerals of the metal electrode 16 are shown in accordance with the reference numerals of each part of the alloy layer 39.

[0012] Semiconductor device 1A is a semiconductor switching device having an insulated gate type transistor structure Tr as an example of a device structure. The transistor structure Tr has a planar gate type vertical structure.

[0013] Referring to Figures 1 to 4, the semiconductor device 1A includes a chip 2 formed in a hexahedral shape (specifically, a rectangular parallelepiped shape). In this embodiment, the chip 2 includes a single crystal of a wide-bandgap semiconductor. In other words, the semiconductor device 1A is a "wide-bandgap semiconductor device". The chip 2 may also be referred to as a "semiconductor chip," "wide-bandgap semiconductor chip," etc.

[0014] Wide-bandgap semiconductors are semiconductors that have a bandgap greater than that of silicon (Si). Examples of wide-bandgap semiconductors include gallium nitride (GaN), silicon carbide (SiC), and diamond (C). In this configuration, chip 2 is a "SiC chip" containing a hexagonal SiC single crystal as an example of a wide-bandgap semiconductor. In other words, semiconductor device 1A is a "SiC semiconductor device".

[0015] Hexagonal SiC single crystals have multiple polytypes, including 2H (Hexagonal)-SiC single crystals, 4H-SiC single crystals, and 6H-SiC single crystals. In this embodiment, an example is shown in which chip 2 contains a 4H-SiC single crystal, but chip 2 may also contain other polytypes.

[0016] The chip 2 has a first main surface (main surface) 3 on one side, a second main surface 4 on the other side, and first to fourth side surfaces 5A to 5D connected to the first main surface 3 and the second main surface 4. The first main surface 3 and the second main surface 4 are formed in a rectangular shape in a plan view from the vertical direction Z (hereinafter simply referred to as "plan view"). The vertical direction Z is also the thickness direction of the chip 2 and the normal direction of the first main surface 3 (second main surface 4). The first main surface 3 and the second main surface 4 may be formed in a square or rectangular shape in a plan view.

[0017] The first main surface 3 and the second main surface 4 are preferably formed by the c-plane of the SiC single crystal. In this case, the first main surface 3 is preferably formed by the silicon plane ((0001) plane) of the SiC single crystal, and the second main surface 4 is preferably formed by the carbon plane ((000-1) plane) of the SiC single crystal. The first main surface 3 and the second main surface 4 may have an off-angle that is inclined at a predetermined angle in a predetermined off-direction with respect to the c-plane. The off-direction is preferably the a-axis direction ([11-20] direction) of the SiC single crystal. The off-angle may be greater than 0° and less than or equal to 10°. The off-angle is preferably 5° or less.

[0018] The first side surface 5A and the second side surface 5B extend in a first direction X along the first main surface 3 and face a second direction Y that intersects the first direction X along the first main surface 3. Specifically, the second direction Y is perpendicular to the first direction X. The third side surface 5C and the fourth side surface 5D extend in the second direction Y and face the first direction X.

[0019] In this embodiment, the first direction X is the a-axis direction ([11-20] direction) of the SiC single crystal, and the second direction Y is the m-axis direction ([1-100] direction) of the SiC single crystal. Alternatively, the first direction X may be the m-axis direction of the SiC single crystal, and the second direction Y may be the a-axis direction of the SiC single crystal.

[0020] The XY plane, which includes the first direction X and the second direction Y, forms a horizontal plane perpendicular to the vertical direction Z. Hereafter, the axis extending along the vertical direction Z may be referred to as the "vertical axis." Also below, the first direction X and the second direction Y may be referred to as the "horizontal direction." The horizontal direction is also the direction extending along the first principal plane 3.

[0021] The first to fourth sides 5A to 5D may have a length of 0.5 mm or more and 20 mm or less in a plan view. The length of the first to fourth sides 5A to 5D may be a value that falls within one of the following ranges: 0.5 mm or more and 1 mm or less, 1 mm or more and 2 mm or less, 2 mm or more and 5 mm or less, 5 mm or more and 10 mm or less, 10 mm or more and 15 mm or less, and 15 mm or more and 20 mm or less. The length of the first to fourth sides 5A to 5D may be 5 mm or more.

[0022] Referring to Figure 2, the semiconductor device 1A includes an n-type first semiconductor region 6 formed on the surface layer of the second main surface 4. A drain potential, which is a first potential (high potential), is applied to the first semiconductor region 6. The first semiconductor region 6 may also be referred to as the "base region (layer)", "semiconductor region (layer)", "drain region (layer)", etc.

[0023] The first semiconductor region 6 extends in layers along the second main surface 4 and is exposed from the second main surface 4 and the first to fourth side surfaces 5A to 5D. In this embodiment, the first semiconductor region 6 consists of an n-type semiconductor layer. Specifically, the first semiconductor region 6 consists of a substrate (SiC substrate) containing a SiC single crystal (semiconductor single crystal), and forms the second main surface 4 and the first to fourth side surfaces 5A to 5D. The first semiconductor region 6 (substrate) has the aforementioned off-direction and off-angle. The first semiconductor region 6 may have a thickness of 10 μm or more and 500 μm or less.

[0024] The semiconductor device 1A includes an n-type second semiconductor region 7 formed on the surface layer of the first main surface 3. The second semiconductor region 7 may also be referred to as a "semiconductor region (layer)," "drift region (layer)," etc. The second semiconductor region 7 has an n-type impurity concentration less than that of the first semiconductor region 6. In a cross-sectional view, the second semiconductor region 7 is formed in the region on the first main surface 3 side relative to the first semiconductor region 6 and is electrically connected to the first semiconductor region 6.

[0025] The second semiconductor region 7 extends in layers along the first main surface 3 and is exposed from the first main surface 3 and the first to fourth side surfaces 5A to 5D. In this configuration, the second semiconductor region 7 consists of an n-type semiconductor layer.

[0026] The second semiconductor region 7 consists of an epitaxial layer (SiC epitaxial layer) grown from the first semiconductor region 6. The second semiconductor region 7 has a lower end and an upper end. The lower end of the second semiconductor region 7 is the crystal growth starting point, and the upper end of the second semiconductor region 7 is the crystal growth ending point. The lower end of the second semiconductor region 7 is also the bottom of the second semiconductor region 7. Since the second semiconductor region 7 is grown continuously from the first semiconductor region 6, the lower end of the second semiconductor region 7 coincides with the upper end of the first semiconductor region 6.

[0027] The second semiconductor region 7 (epitaxial layer) has the aforementioned off-direction and off-angle. The thickness of the second semiconductor region 7 may be 5 μm or more and 15 μm or less. Preferably, the second semiconductor region 7 has a thickness less than the thickness of the first semiconductor region 6. The thickness of the second semiconductor region 7 may be greater than the thickness of the first semiconductor region 6.

[0028] The second semiconductor region 7 includes an n-type drift region 8. In this embodiment, the drift region 8 is formed by a part (n-type portion) of the second semiconductor region 7.

[0029] Referring to Figure 4, the semiconductor device 1A includes an active region 9 and an outer peripheral region 10 set on the first main surface 3 of the chip 2. Figures 1, 3A, 3B, and 4 are diagrams showing the layer structure formed on the active region 9 and the outer peripheral region 10, layer by layer. Of Figures 1, 3A, 3B, and 4, Figure 4 shows the lowest layer, Figure 3A shows a layer above Figure 4, Figure 3B shows a layer above Figure 3A, and Figure 1 shows a layer above Figure 3B.

[0030] The active region 9 includes the device structure (i.e., the transistor structure Tr) and is the region where the output current (drain current) is generated. The active region 9 may also be called the element region. In a plan view, the active region 9 is set in the inner part of the chip 2, spaced apart from the periphery of the chip 2 (first to fourth side surfaces 5A to 5D). In a plan view, the active region 9 is formed in a polygonal shape with sides parallel to the periphery of the chip 2. In this embodiment, the active region 9 is formed in a quadrilateral shape in a plan view. The active region 9 may also be formed in a polygonal shape with recesses along the gate pad electrodes 24, which will be described later, in a plan view. Preferably, the planar area of ​​the active region 9 is 50% to 90% of the planar area of ​​the first main surface 3.

[0031] The outer peripheral region 10 is a region that does not include the device structure (transistor structure Tr). In a plan view, the outer peripheral region 10 is located in the region between the periphery of the chip 2 and the active region 9. In a plan view, the outer peripheral region 10 extends in a band shape along the active region 9 and is set up as a polygonal ring (a quadrilateral ring in this form) surrounding the active region 9.

[0032] The semiconductor device 1A includes a plurality of planar electrode type gate structures 11 formed in the active region 9. The plurality of gate structures 11 are formed in the inner part of the first main surface 3, spaced apart from the periphery (first to fourth side surfaces 5A to 5D) of the first main surface 3, and are not formed in the outer peripheral region 10.

[0033] In this configuration, the multiple gate structures 11 are arranged at intervals in the second direction Y (m-axis direction) and each is formed in a strip-like shape extending in the first direction X (a-axis direction). In other words, the multiple gate structures 11 are arranged in a stripe-like shape extending in the first direction X (a-axis direction). The direction of extension of the multiple gate structures 11 coincides with the off-direction of the SiC single crystal.

[0034] The semiconductor device 1A includes a p-type outer well region 12 formed in the outer peripheral region 10. The outer well region 12 includes a first outer well region 13 and a plurality of second outer well regions 14.

[0035] Referring to Figure 4, the first outer well region 13 is a rectangular ring-shaped region demarcated by a thick solid line and a thick dashed line. The first outer well region 13 has a portion extending in a first direction X and a portion extending in a second direction Y. In this embodiment, the first outer well region 13 is formed as a polygonal ring (a rectangular ring in this embodiment) with four sides parallel to the periphery of the chip 2 in a plan view, and surrounds a plurality of gate structures 11.

[0036] The first outer well region 13 may have an edge portion that connects the portion extending in the first direction X and the portion extending in the second direction Y in an arc shape (preferably a quarter arc shape). In this embodiment, the first outer well region 13 is formed in the outer peripheral region 10 and surrounds the active region 9.

[0037] Each of the multiple second outer well regions 14 has a portion extending in a first direction X and a portion extending in a second direction Y. In this embodiment, each second outer well region 14 is formed as a polygonal ring (a quadrilateral ring in this embodiment) with four sides parallel to the periphery of the chip 2 in a plan view, and surrounds the first outer well region 13.

[0038] Each of the multiple second outer well regions 14 may have an edge portion that connects the portion extending in the first direction X and the portion extending in the second direction Y in an arc shape (preferably in a quarter arc shape). In this embodiment, the multiple second outer well regions 14 are arranged in the outer peripheral region 10 at a distance from the first outer well region 13.

[0039] Referring to Figure 2, the semiconductor device 1A includes an insulating interlayer film 15 formed on the first main surface 3. The interlayer film 15 may, for example, be formed over the entire first main surface 3. The interlayer film 15 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. It is preferable that the interlayer film 15 includes a silicon oxide film. The interlayer film 15 may be referred to as an "insulating film," "interlayer insulating film," "intermediate insulating film," etc.

[0040] Referring to FIGS. 2 and 3A, the semiconductor device 1A includes a metal electrode 16 disposed on the interlayer film 15. For the sake of clarity of the positional relationship of the metal electrode 16, the outline of the metal electrode 16 is indicated by a broken line in FIG. 1.

[0041] Referring to FIG. 3A, in this embodiment, the metal electrode 16 includes a source metal 17 and a gate metal 18.

[0042] The source metal 17 is a film physically and electrically separated from the gate metal 18. The source metal 17 is disposed at an interval from the gate metal 18 on the interlayer film 15. The source metal 17 is an electrode to which a source potential is applied from the outside. The source metal 17 may be referred to as a "first main surface electrode", a "source pad electrode", a "source metal electrode", a "first pad electrode", etc.

[0043] The source metal 17 includes a source pad electrode 19 and a source wiring 20 electrically connected to the source pad electrode 19.

[0044] The source pad electrode 19 is disposed on the first main surface 3 (FIG. 2). The source pad electrode is an example of a pad electrode. The source pad electrode 19 is a terminal electrode to which a source potential is applied from the outside and may be referred to as a "source electrode film", a "first pad electrode", a "first main surface electrode", a "first terminal electrode", etc. The source pad electrode is disposed on a portion of the interlayer film covering the active region 9 (FIG. 2).

[0045] In this embodiment, the source pad electrode 19 has a first pad portion 2, a second pad portion 22, and a third pad portion 23. The first pad portion 21 has a relatively large planar area and forms the main body of the source pad electrode 19. In this embodiment, the first pad portion 21 is formed in a polygonal shape (a square shape in this embodiment) having four sides parallel to the periphery of the chip 2 in plan view, and is unevenly distributed on the second side surface portion 5B side with respect to the central portion of the first main surface 3.

[0046] The second pad portion 22 has a flat area less than that of the first pad portion 21, and extends in a strip-like (square-shaped) manner from one end of the first direction X (the end on the third side surface 5C side) toward the first side surface 5A.

[0047] The third pad portion 23 has a flat area less than that of the first pad portion 21, and extends in a strip-like (square-shaped) manner from the other end of the first pad portion 21 in the first direction X (the end on the fourth side surface 5D side) toward the first side surface 5A. The third pad portion 23 faces the second pad portion 22 in the first direction X.

[0048] The flat area of ​​the third pad portion 23 may be approximately equal to the flat area of ​​the second pad portion 22. The flat area of ​​the third pad portion 23 may be larger than the flat area of ​​the second pad portion 22, or it may be smaller than the flat area of ​​the second pad portion 22. Either or both of the second pad portion 22 and the third pad portion 23 may be used as terminal portions for current monitoring.

[0049] The source pad electrode 19 does not necessarily have to have both the second pad portion 22 and the third pad portion 23 at the same time. The source pad electrode 19 may have only one of the second pad portion 22 and the third pad portion 23. The source pad electrode 19 may consist only of the first pad portion 21 and may not have either the second pad portion 22 or the third pad portion 23.

[0050] The source wiring 20 is arranged around the source pad electrode 19 on the interlayer film 15 (Figure 2). The source wiring 20 is an example of wiring. The source wiring 20 is supplied with the same potential (source potential) as the potential supplied to the source pad electrode 19. The source wiring 20 may also be referred to as "termination electrode (wiring)", "wiring", "first wiring", "finger electrode", "source finger", etc.

[0051] The source wiring 20 has a wiring width less than the electrode width of the source pad electrode 19 and is selectively routed on the interlayer film 15 (Figure 2). In this configuration, the source wiring 20 is led out from the source pad electrode 19 (first pad portion 21) to the second side surface 5B. The source wiring 20 is led out from the active region 9 to the outer peripheral region 10.

[0052] The source wiring 20 extends in a strip shape along the periphery of the first main surface 3 (the periphery of the active region 9). In this embodiment, the source wiring 20 is formed in a polygonal ring shape (a quadrilateral ring shape in this embodiment) having four sides parallel to the periphery of the chip 2 in a plan view, and surrounds the inner part of the first main surface 3 (active region 9). The source wiring 20 may have an edge portion that connects the portion extending in the first direction X and the portion extending in the second direction Y in an arc shape (preferably a quarter-circular arc shape). The source wiring 20 may be end-bound or endless.

[0053] Referring to Figure 3A, the gate metal 18 is an electrode to which a gate potential is applied from the outside. The gate metal 18 may also be called the "second main surface electrode," "gate pad electrode," "gate metal electrode," "second pad electrode," etc.

[0054] The gate metal 18 includes a gate pad electrode 24 and gate wiring 25 electrically connected to the gate pad electrode 24.

[0055] The gate pad electrode 24 is positioned on the first main surface 3. The gate pad electrode 24 is an example of a pad electrode. The gate pad electrode 24 is a terminal electrode to which a gate potential is applied from the outside. The gate pad electrode 24 may also be referred to as "gate pad," "gate electrode film," "second pad electrode," "second main surface electrode," "second terminal electrode," etc.

[0056] The gate pad electrode 24 is positioned at a distance from the source pad electrode 19 and on the portion of the interlayer film 15 that covers the active region 9. In this configuration, the gate pad electrode 24 is positioned in the region on the first side surface 5A side with respect to the first pad portion 21. The gate pad electrode 24 faces the first pad portion 21 in the second direction Y. The gate pad electrode 24 is interposed in the region between the second pad portion 22 and the third pad portion 23. The gate pad electrode 24 faces both the first pad portion 21 and the second pad portion 22 in the first direction X.

[0057] The gate pad electrode 24 is formed in a polygonal shape (a quadrilateral shape in this embodiment) having four sides parallel to the periphery of the chip 2 in a plan view. The gate pad electrode 24 has a planar area less than that of the source pad electrode 19. The gate pad electrode 24 has a planar area less than that of the first pad portion 21. The gate pad electrode 24 may have a planar area less than that of the first pad portion 21 (second pad portion 22).

[0058] The gate pad electrode 24 is located in a recess formed in the source pad electrode 19. The gate pad electrode 24 may be located in a region along the central part of any of the first to fourth side surfaces 5A to 5D. The gate pad electrode 24 may be located at any corner C of the tip 2 on the first main surface 3 in a plan view. The gate pad electrode 24 may be located in the central part of the first main surface 3 in a plan view. The gate pad electrode 24 may be located on the active region 9. In this embodiment, the gate pad electrode 24 is formed in a square shape in a plan view.

[0059] The gate wiring 25 is an example of wiring. The gate wiring 25 includes a plurality of finger wirings 26, 27 extending in a strip-like manner from the gate pad electrode 24 in different directions from each other. The plurality of finger wirings 26, 27 are arranged in a non-parallel positional relationship with each other. The plurality of finger wirings 26, 27 may include a first finger wiring 26 and a second finger wiring 27.

[0060] The first finger wiring 26 and the second finger wiring 27 extend from the gate pad electrode 24 in opposite directions along the periphery of the chip 2, and together surround the source pad electrode 19. The first finger wiring 26 and the second finger wiring 27 may also be referred to as gate periphery wiring.

[0061] In this configuration, the first finger wiring 26 and the second finger wiring 27 are each formed in a substantially U shape in plan view and have a corner C1 at a position corresponding to the corner C of the chip 2.

[0062] In this configuration, the first finger wiring 26 extends from the gate pad electrode 24 along the first side surface 5A, the third side surface 5C, and the second side surface 5B in that order, and has a first tip portion 28 in the middle of the second side surface 5B in the first direction X. The first finger wiring 26 may be referred to as, for example, "first outer peripheral wiring," "first outer peripheral electrode," "first outer peripheral finger wiring," or "first outer peripheral finger electrode."

[0063] The second finger wiring 27 extends from the gate pad electrode 24 along the first side surface 5A, the fourth side surface 5D, and the second side surface 5B in that order, and has a second tip portion 29 midway along the second side surface 5B in the first direction X. The first tip portion 28 and the second tip portion 29 face each other with space between them in the first direction X. The second finger wiring 27 may also be referred to as, for example, "second outer peripheral wiring," "second outer peripheral electrode," "second outer peripheral finger wiring," or "second outer peripheral finger electrode."

[0064] In this configuration, the finger wires 26 and 27 are directly connected to the gate pad electrode 24. However, the finger wires 26 and 27 do not need to be directly connected to the gate pad electrode 24 as long as they are electrically connected to the gate pad electrode 24.

[0065] Referring to Figures 1 and 2, the semiconductor device 1A includes an organic insulating film 30 that covers the interlayer film 15 on the first main surface 3 and selectively covers the metal electrode 16.

[0066] Referring to Figure 1, the organic insulating film 30 includes a gate pad opening 32 that exposes the inner portion of the gate pad electrode 24 as a gate pad (pad) 31. The organic insulating film 30 covers the periphery of the gate pad electrode 24 and the entire area of ​​the gate wiring 25. The gate pad opening 32 is formed in a rectangular shape in plan view.

[0067] The organic insulating film 30 includes a first source pad opening (pad opening) 34, a second source pad opening (pad opening) 36, and a third source pad opening (pad opening) 38. The organic insulating film 30 covers the peripheral edges of the first pad portion 21, the second pad portion 22, and the third pad portion 23. That is, the organic insulating film 30 covers the peripheral edges of the source pad electrode 19 and the peripheral edges of the pad portions 21, 22, and 23 in the central part of the source pad electrode 19.

[0068] The first source pad opening 34 exposes the inner portion of the electrode surface 70 (Figure 7) of the first pad portion 21 of the source pad electrode 19 as the first source pad (pad) 33. In a plan view, the first source pad opening 34 is formed in a polygonal shape along the periphery of the third pad portion 23. Preferably, the planar area of ​​the first source pad opening 34 is larger than the planar area of ​​the gate pad opening 32.

[0069] The second source pad opening 36 exposes the inner portion of the electrode surface of the second pad portion 22 as the second source pad (pad) 35. In a plan view, the second source pad opening 36 is formed in a rectangular shape along the periphery of the first pad portion 21. Preferably, the planar area of ​​the second source pad opening 36 is smaller than the planar area of ​​the gate pad opening 32.

[0070] The third source pad opening 38 includes a third source pad opening (pad opening) 38 that exposes the inner portion of the electrode surface of the third pad portion 23 as a third source pad (pad) 37. In a plan view, the third source pad opening 38 is formed in a rectangular shape along the periphery of the second pad portion 22. Preferably, the planar area of ​​the third source pad opening 38 is smaller than the planar area of ​​the gate pad opening 32.

[0071] The organic insulating film 30 may also be referred to as an "organic film," "resin film," etc. The organic insulating film 30 preferably contains a transparent resin or a light-transmitting resin. The organic insulating film 30 preferably contains a photosensitive resin. The photosensitive resin may be a negative type or a positive type. The organic insulating film 30 may contain at least one of a polyimide film (polyimide), a polyamide film (polyamide), and a polybenzoxazole film (polybenzoxazole). The organic insulating film 30 may be a polyimide film or a polyamide film. In this embodiment, the organic insulating film 30 contains a polyimide film.

[0072] The thickness T3 of the organic insulating film 30 (Figures 7 and 8) may be greater than the electrode thickness T2 of the metal electrode (Figures 7 to 9). Preferably, the thickness of the organic insulating film 30 is less than the thickness of the chip 2. The thickness of the organic insulating film 30 may be greater than or less than the thickness of the second semiconductor region 7.

[0073] Referring to Figures 1 and 2, the organic insulating film 30 is formed so as to span over the active region 9 and over the outer peripheral region 10. The organic insulating film 30 covers a portion of the source pad electrode 19 and a portion of the gate pad electrode 24. The organic insulating film 30 also covers the source wiring 20 and the gate wiring 25 (Figure 3A).

[0074] Referring to Figure 3B, the semiconductor device 1A includes an alloy layer 39 disposed between the metal electrode 16 and the organic insulating film 30. The alloy layer 39 includes a first pad alloy layer (pad alloy layer) 40, a first wiring alloy layer (wiring alloy layer) 41, a second pad alloy layer (pad alloy layer) 42, and a second wiring alloy layer (pad alloy layer) 43.

[0075] The first pad alloy layer 40 is positioned between the source pad electrode 19 and the organic insulating film 30. The first pad alloy layer 40 covers a portion of the electrode surface 70 (Figure 7) of the source pad electrode 19. The first pad alloy layer 40 has a first alloy opening 45, a second alloy opening 46, and a third alloy opening 47 formed therein. The first pad alloy layer 40 covers the peripheral edge of the first pad portion 21, the peripheral edge of the second pad portion 22, and the peripheral edge of the third pad portion 23.

[0076] The first alloy opening 45 exposes the inner portion of the electrode surface 70 (Figure 7) of the first pad portion 21 of the source pad electrode 19 as the first source pad 33. The second alloy opening 46 exposes the inner portion of the electrode surface of the second pad portion 22 of the source pad electrode 19 as the second source pad 35. The third alloy opening 47 exposes the inner portion of the third pad portion 23 of the electrode surface of the source pad electrode 19 as the third source pad 37.

[0077] The first wiring alloy layer 41 is formed on the surface of the source wiring 20. The first wiring alloy layer 41 covers the electrode surface 70 (Figures 8 and 9) and the side wall 71 (Figures 8 and 9) of the source wiring 20.

[0078] The second pad alloy layer 42 is formed on the surface of the gate pad electrode 24. The second pad alloy layer 42 covers a portion of the electrode surface of the gate pad electrode 24. A fourth alloy opening 48 is formed in the second pad alloy layer 42. The fourth alloy opening 48 exposes the inner portion of the electrode surface of the gate pad electrode 24 as the gate pad 31.

[0079] The second wiring alloy layer 43 is formed on the surface of the gate wiring 25 (first finger wiring 26 and second finger wiring 27). The second wiring alloy layer 43 covers the electrode surface 70 (Figure 9) and side wall 71 (Figure 9) of the gate wiring 25.

[0080] Referring to Figure 2, the semiconductor device 1A includes a drain electrode 44 that covers the second main surface 4. The drain electrode 44 is a terminal electrode to which a drain potential is applied from the outside. The drain electrode 44 may also be called a "third pad electrode," "third main surface electrode," "third terminal electrode," etc.

[0081] The drain electrode 44 is electrically connected to the first semiconductor region 6. The drain electrode 44 may cover the entire area of ​​the second main surface 4 so as to be continuous with the periphery of the second main surface 4 (first to fourth side surfaces 5A to 5D). The drain electrode 44 may partially cover the second main surface 4 so as to expose the periphery of the second main surface 4.

[0082] The breakdown voltage that can be applied between the source pad electrode 19 and the drain electrode 44 (between the first main surface 3 and the second main surface 4) may be 500V or more and 3000V or less. The breakdown voltage may have a value that falls within at least one of the following ranges: 500V or more and 750V or less, 750V or more and 1000V or less, 1000V or more and 1250V or less, 1250V or more and 1500V or less, 1500V or more and 1750V or less, 1750V or more and 2000V or less, 2000V or more and 2250V or less, 2250V or more and 2500V or less, 2500V or more and 2750V or more and 3000V or less.

[0083] Referring to Figures 2 and 4, semiconductor device 1A is a semiconductor switching device having an insulated gate type transistor structure Tr as an example of a device structure. The transistor structure Tr has a planar gate type vertical structure.

[0084] Figure 5 is an enlarged view of the area enclosed by the dashed line V in Figure 4. Figure 6 is a cross-sectional view along the line VI-VI shown in Figure 5.

[0085] Referring to Figures 5 and 6, the semiconductor device 1A includes a plurality of p-type body regions 50 formed on the surface layer of the first main surface 3 in the region where the transistor structure Tr (Figures 2 and 4) is formed (i.e., the active region 9) on the first main surface 3. In this embodiment, the plurality of body regions 50 are arranged at intervals in the second direction Y and each is formed in a strip shape extending in the first direction X. The plurality of body regions 50 are arranged in a stripe shape as a whole. The direction of extension of the plurality of body regions 50 coincides with the off-direction of the SiC single crystal. The plurality of body regions 50 may be formed at intervals in the second direction Y and each extends in a strip shape in the first direction X.

[0086] Each body region 50 provides a unit cell UC (Figures 5 to 7, etc.) of a planar gate type transistor structure Tr. Each unit cell UC comprises at least a body region 50 and a source region 51, described below, and may be the smallest unit that functions as an MIS transistor. Multiple body regions 50 may be, for example, 1 × 10 １５ cm －３ The above 1 x 10１８ cm －３ The following p-type impurity concentrations may be present as peak values.

[0087] The semiconductor device 1A includes one or more n-type source regions 51 formed on the surface of a plurality of body regions 50 in the transistor structure Tr (Figures 2 and 4) formation region (i.e., the active region 9) on the first main surface 3. In this embodiment, a plurality (two in this embodiment) of source regions 51 are formed at intervals on the surface of each body region 50. The plurality of source regions 51 have an n-type impurity concentration higher than the n-type impurity concentration of the drift region 8. The plurality of source regions 51 have a density of 1 × 10⁻¹⁶ １８ cm －３ The above 1 x 10 ２１ cm －３ The following n-type impurity concentrations may be present as peak values.

[0088] The multiple source regions 51 may each extend in a strip-like manner along the extending direction of the corresponding body region 50. Of course, the multiple source regions 51 may be formed at intervals along the extending direction of the corresponding body region 50. The multiple source regions 51 may be formed at intervals from the bottom of the corresponding body region 50 toward the first main surface 3, and at intervals from the periphery of the corresponding body region 50 toward the inward side.

[0089] Referring to Figure 6, the multiple source regions 51 define channel regions 52 along the first main surface 3 at the periphery of the body region 50.

[0090] Referring to Figures 5 and 6, the semiconductor device 1A includes one or more p-type body contact regions 53 formed on the surface of each of the multiple body regions 50. The body contact regions 53 may also be referred to as "back gate regions". In this configuration, one body contact region 53 is formed in the region between multiple adjacent source regions 51 on the surface of each body region 50.

[0091] The multiple body contact regions 53 may each extend in a strip-like manner along the extending direction of the corresponding body region 50. Of course, the multiple body contact regions 53 may be formed at intervals along the extending direction of the corresponding body region 50. The multiple body contact regions 53 are formed at intervals from the bottom of the corresponding body region 50 toward the first main surface 3, and at intervals from the peripheral edge of the corresponding body region 50 toward the inside.

[0092] As described above, the semiconductor device 1A includes a plurality of gate structures 11 in the active region 9. One gate structure 11 has a stacked structure including a gate insulating film 56 and a gate electrode 57. The gate structure 11 does not have an insulating sidewall structure (spacer) on the side of the gate electrode 57.

[0093] The gate insulating film 56 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. In this embodiment, the gate insulating film 56 has a single-layer structure made of a silicon oxide film. It is particularly preferable that the gate insulating film 56 includes a silicon oxide film made of the oxide of the chip 2. The gate insulating film 56 is formed to cover the entire area of ​​the transistor structure Tr (Figure 4) formation region (i.e., the active region 9) on the first main surface 3. The gate insulating film 56 is not formed in the area outside the transistor structure Tr formation region (i.e., the outer peripheral region 10) on the first main surface 3.

[0094] The multiple gate electrodes 57 may contain either or both of p-type conductive polysilicon and n-type conductive polysilicon. A gate potential is applied to the multiple gate electrodes 57 as a control potential.

[0095] In this embodiment, the multiple gate electrodes 57 are arranged at intervals in the second direction Y (m-axis direction) and are formed in a strip shape extending in the first direction X (a-axis direction). In this embodiment, the multiple gate electrodes 57 are arranged in a stripe shape extending in the a-axis direction (first direction X). The direction of extension of the multiple gate electrodes 57 coincides with the off-direction of the chip 2.

[0096] Referring to Figure 5, the multiple gate electrodes 57 are spaced apart on the first main surface 3 so as to overlap at least one channel region 52 in the stacking direction (vertical direction Z). The multiple gate electrodes 57 control the inversion and non-inversion of the channel (current path) within the body region 50 in response to the gate potential.

[0097] Referring to Figure 6, the interlayer film 15 has a plurality of source contact openings 58 that open directly above a plurality of body regions 50. The plurality of source contact openings 58 are formed in the region between a pair of gate electrodes 57 that face each other in the second direction Y. The plurality of source contact openings 58 penetrate the interlayer film 15 and the gate insulating film 56. The plurality of source contact openings 58 are spaced apart in the direction in which the pair of gate electrodes 57 face each other, i.e., in the second direction Y.

[0098] Figure 7 is a cross-sectional view along the line VII-VII shown in Figure 1. Figure 8 is a cross-sectional view along the line VIII-VIII shown in Figure 1. Figure 9 is a cross-sectional view along the line IX-IX shown in Figure 1.

[0099] Referring to Figures 8 and 9, the semiconductor device 1A includes an outer insulating film 62 formed on the first main surface 3 in the outer peripheral region 10. The outer insulating film 62 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. In this embodiment, the outer insulating film 62 has a single-layer structure made of a silicon oxide film. The outer insulating film 62 may also include a silicon oxide film made of the oxide of the chip 2. The outer insulating film 62 may be formed integrally with the gate insulating film 56.

[0100] Referring to Figures 8 and 9, the semiconductor device 1A includes a p-type outer contact region 60 formed on the surface layer of the first main surface 3 in the outer peripheral region 10. A source potential is applied to the outer contact region 60. The outer contact region 60 has a p-type impurity concentration higher than the n-type impurity concentration of the second semiconductor region 7. The p-type impurity concentration of the outer contact region 60 is higher than the p-type impurity concentration of the body region 50 and the first outer well region 13.

[0101] The outer contact region 60 is formed on the surface of the first outer well region 13. In other words, the outer contact region 60 is formed in the thickness range between the first main surface 3 and the bottom of the first outer well region 13.

[0102] In this embodiment, the outer contact region 60 is formed as a polygonal ring (a quadrangular ring in this embodiment) having four sides parallel to the periphery of the tip 2 in a plan view, and surrounds the inner portion (active region 9) of the first main surface 3. The outer contact region 60 may have an edge portion that connects the portion extending in the first direction X and the portion extending in the second direction Y in an arc shape (preferably a quarter-circular arc shape).

[0103] Referring to Figures 8 and 9, the semiconductor device 1A includes at least one (one in this embodiment) outer opening 61 formed in the interlayer film 15 in the outer peripheral region 10. The outer opening 61 penetrates the outer insulating film 62 and the interlayer film 15, exposing the outer contact region 60. In a plan view, the outer opening 61 extends in a strip shape along the outer contact region 60.

[0104] In this embodiment, the outer opening 61 is formed in a polygonal ring shape (specifically, a quadrilateral ring shape) that surrounds the inner portion (active region 9) of the first main surface 3 along the outer contact region 60 in a plan view. The outer opening 61 may have an opening end that is curved in an arc shape. The semiconductor device 1A may have a plurality of outer openings 61. In this case, the plurality of outer openings 61 may be formed at intervals along the outer contact region 60 so as to surround the inner portion (active region 9) of the first main surface 3.

[0105] Referring to Figures 5 to 9, the metal electrode 16 is formed from a metallic material containing aluminum (Al). The metal electrode 16 includes an Al-based metal film. The metal electrode 16 may include at least one of the following: a pure Al film (an Al film with a purity of 99% or more), an AlCu alloy film, an AlSi alloy film, and an AlSiCu alloy film. The metal electrode 16 has an electrode surface 70 and a side wall 71.

[0106] Referring to Figures 6 to 9, the metal electrode 16 has an electrode thickness T2. Preferably, the electrode thickness T2 is greater than the thickness of the interlayer film 15. The electrode thickness T2 may be, for example, greater than 0 μm and 4 μm or less. The electrode thickness T2 may have a value that falls within at least one of the following ranges: greater than 0 μm and 0.25 μm or less, 0.25 μm or more and 0.5 μm or less, 0.5 μm or more and 0.75 μm or less, 0.75 μm or more and 1 μm or less, 1 μm or more and 1.25 μm or less, 1.25 μm or more and 1.5 μm or less, 1.5 μm or more and 1.75 μm or less, 1.75 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, 2.5 μm or more and 3 μm or less, 3 μm or more and 3.5 μm or less, and 3.5 μm or more and 4 μm or less.

[0107] The alloy layer 39 is formed on the surface of the metal electrode 16. The alloy layer 39 directly covers both the electrode surface 70 and the side wall 71 of the metal electrode 16. The metal electrode 16 is directly covered by the alloy layer 39, and the metal electrode 16 is covered by the organic insulating film 30 with the alloy layer 39 in between. In this embodiment, the alloy layer 39 may include a TiAl alloy layer 80 (Figure 12).

[0108] Referring to Figures 6 to 9, the alloy layer 39 has a layer thickness T1. Preferably, the layer thickness T1 is greater than the thickness of the interlayer film 15. The layer thickness T1 may be, for example, greater than 10 Å and 500 Å or less. The layer thickness T1 may have a value that falls within at least one of the following ranges: greater than 10 Å and 50 Å or less, 50 Å to 100 Å, 100 Å to 150 Å, 150 Å to 200 Å, 200 Å to 250 Å, 250 Å to 300 Å, 300 Å to 350 Å, 350 Å to 400 Å, 400 Å to 450 Å, and 450 Å to 500 Å.

[0109] The thickness ratio (T1 / T2) of the alloy layer 39 thickness T1 to the electrode thickness T2 of the metal electrode 16 may be greater than 0 and 1 / 100 or less. The thickness ratio (T1 / T2) may have a value that falls within at least one of the following ranges: 1 / 5000 or more and 1 / 3000 or less, 1 / 3000 or more and 1 / 1000 or less, 1 / 1000 or more and 1 / 500 or more, 1 / 500 or more and 1 / 300 or less, 1 / 300 or more and 1 / 200 or more and 1 / 100 or less.

[0110] Referring to Figures 6 to 9, the semiconductor device 1A includes a lower electrode layer 63. The lower electrode layer 63 is a thin metal layer and serves as the base layer for the metal electrode 16. The lower electrode layer 63 and the metal electrode 16 are stacked in this order from the chip 2 side.

[0111] In this configuration, the lower electrode layer 63 is formed to cover the surface of the interlayer film 15, the surface of the outer insulating film 62, the inner surface of the source contact opening 58, the inner surface of the outer opening 61, and the inner surface of the gate opening (not shown).

[0112] The lower electrode layer 63 is primarily a diffusion prevention layer that suppresses or prevents the diffusion of the constituent material of the metal electrode 16 (for example, a metallic material containing aluminum) into its surroundings (the surface of the outer insulating film 62, the surface of the interlayer film 15, etc.). The lower electrode layer 63 is formed using a different metallic material than the metal electrode 16.

[0113] The lower electrode layer 63 includes, for example, one or both of Ti and TiN. The lower electrode layer 63 may be a laminated film in which a Ti film and a TiN film are stacked. Of course, the lower electrode layer 63 may consist of only one of the Ti film and the TiN film.

[0114] As described above, the semiconductor device 1A includes a metal electrode 16 and an alloy layer 39. In this embodiment, the metal electrode 16 includes a source pad electrode 19, a source wiring 20, a gate pad electrode 24, and a gate wiring 25. The alloy layer 39 includes a first pad alloy layer 40, a first wiring alloy layer 41, a second pad alloy layer 42, and a second wiring alloy layer 43.

[0115] Referring to Figures 6 to 9, the source pad electrode 19 is positioned on the first main surface 3 in the active region 9. The source pad electrode 19 is made of a metallic material containing aluminum (Al). The source pad electrode 19 includes an Al-based metal film. The source pad electrode 19 may include at least one of a pure Al film (an Al film with a purity of 99% or more), an AlCu alloy film, an AlSi alloy film, and an AlSiCu alloy film. The source pad electrode 19 has an electrode surface 70 and a side wall 71 (Figure 9). A recess 72 is formed in the electrode surface 70 of the source pad electrode 19. The source pad electrode 19 has an electrode thickness T2.

[0116] A first pad alloy layer 40 is formed on the electrode surface 70 of the source pad electrode 19. The first pad alloy layer 40 covers the electrode surface 70 of the source pad electrode 19. The first pad alloy layer 40 (alloy layer 39) may include a TiAl alloy layer 80 (Figure 12). The first pad alloy layer 40 has a layer thickness T1.

[0117] As described above, the first pad alloy layer 40 has a first alloy opening 45, a second alloy opening 46, and a third alloy opening 47 formed therein.

[0118] Referring to Figures 1, 3A, 3B, and 7, the first alloy opening 45 (Figure 3B) is formed in a polygonal shape (for example, a quadrilateral shape) along the periphery of the first pad portion 21 (Figure 3A) of the source pad electrode 19 in a plan view. In a plan view, the first alloy opening 45 overlaps with the first source pad opening 34 (Figure 1) of the organic insulating film 30.

[0119] In this configuration, the inner wall of the first alloy opening 45 coincides with the inner wall of the first source pad opening 34 in a plan view. In other words, the inner wall of the first alloy opening 45 communicates with the inner wall of the first source pad opening 34. The inner wall of the first alloy opening 45 may be located inside the first source pad opening 34. The inner wall of the first alloy opening 45 may be located outside the first source pad opening 34.

[0120] Referring to Figures 1, 3A, and 3B, the second alloy opening 46 (Figure 3B) is formed in a polygonal shape (for example, a quadrilateral shape) along the periphery of the second pad portion 22 (Figure 3A) of the source pad electrode 19 in a plan view. In a plan view, the second alloy opening 46 overlaps with the second source pad opening 36 (Figure 1) of the organic insulating film 30.

[0121] In this configuration, the inner wall of the second alloy opening 46 coincides with the inner wall of the second source pad opening 36 in a plan view. In other words, the inner wall of the second alloy opening 46 communicates with the inner wall of the second source pad opening 36. The inner wall of the second alloy opening 46 may be located inside the second source pad opening 36. The inner wall of the second alloy opening 46 may be located outside the second source pad opening 36.

[0122] Referring to Figures 1, 3A, and 3B, the third alloy opening 47 (Figure 3B) is formed in a polygonal shape (for example, a quadrilateral shape) along the periphery of the third pad portion 23 (Figure 3A) of the source pad electrode 19 in a plan view. In a plan view, the third alloy opening 47 overlaps with the third source pad opening 38 (Figure 1) of the organic insulating film 30.

[0123] In this configuration, the inner wall of the third alloy opening 47 coincides with the inner wall of the third source pad opening 38 in a plan view. In other words, the inner wall of the third alloy opening 47 communicates with the inner wall of the third source pad opening 38. The inner wall of the third alloy opening 47 may be located inside the third source pad opening 38. The inner wall of the third alloy opening 47 may be located outside the third source pad opening 38.

[0124] Of the electrode surfaces 70 of the source pad electrode 19, the first pad alloy layer 40 (alloy layer 39) is not formed on the first source pad 33, the second source pad 35, and the third source pad 37. Therefore, wire bonding to the first source pad 33, the second source pad 35, and the third source pad 37 is directly connected to the electrode surface 70 of the source pad electrode 19. Since there is no alloy layer 39 interposed between the bonding wire and the source pads (first source pad 33, second source pad 35, and third source pad 37), wire bonding can be performed effectively.

[0125] In particular, in this embodiment, the first pad alloy layer 40 (alloy layer 39) includes a TiAl alloy layer 80 (Figure 12). There is a concern that if a material containing Ti is present in the source pads (first source pad 33, second source pad 35, and third source pad 37), defects may occur in wire bonding. However, in this embodiment, the first pad alloy layer 40 (alloy layer 39) is not formed on the first source pad 33, second source pad 35, and third source pad 37. Therefore, the above concern does not exist.

[0126] In other words, the electrode surface 70 of the source pad electrode 19 has a first pad alloy layer 40 (alloy layer 39) formed over the entire area except for the source pads (first source pad 33, second source pad 35, and third source pad 37).

[0127] Referring to Figure 9, the first pad alloy layer 40 covers not only the sidewall 71 of the source pad electrode 19 but also the sidewall 73 of the lower electrode layer 63 (the sidewall of the portion of the lower electrode layer 63 corresponding to the source pad electrode 19). As a result, the portion of the lower electrode layer 63 corresponding to the source pad electrode 19 is protected by the first pad alloy layer 40.

[0128] Referring to Figures 8 and 9, the source wiring 20 is positioned on the first main surface 3 in the outer peripheral region 10. The source wiring 20 is formed of a metallic material containing aluminum (Al). The source wiring 20 includes an Al-based metal film. The source wiring 20 may include at least one of a pure Al film (an Al film with a purity of 99% or more), an AlCu alloy film, an AlSi alloy film, and an AlSiCu alloy film. The source wiring 20 has an electrode surface 70 and a side wall 71. The source wiring 20 has an electrode thickness T2.

[0129] A first wiring alloy layer 41 is formed on the surface of the source wiring 20. The first wiring alloy layer 41 covers both the electrode surface 70 and the side wall 71 of the source wiring 20. The first wiring alloy layer 41 may include a TiAl alloy layer 80 (Figure 12). The first wiring alloy layer 41 has a layer thickness T1.

[0130] The first wiring alloy layer 41 covers the source wiring 20 over its entire length in the direction in which the source wiring 20 extends. In other words, the first wiring alloy layer 41 covers the source wiring 20 over its entire length in the circumferential direction of the annular source wiring 20.

[0131] The first wiring alloy layer 41 covers not only the sidewall 71 of the source wiring 20, but also the sidewall 73 of the lower electrode layer 63 (the sidewall of the portion of the lower electrode layer 63 corresponding to the source wiring 20). As a result, the portion of the lower electrode layer 63 corresponding to the source wiring 20 is protected by the first wiring alloy layer 41.

[0132] Referring to Figure 3A, the gate pad electrode 24 is positioned on the first main surface 3. In this configuration, the gate pad electrode 24 is positioned on the first main surface 3 in the active region 9. The gate pad electrode 24 may also be positioned on the first main surface 3 in the outer peripheral region 10.

[0133] The gate pad electrode 24 is formed from a metallic material containing aluminum (Al). The gate pad electrode 24 contains an Al-based metal film. The gate pad electrode 24 may contain at least one of the following: a pure Al film (an Al film with a purity of 99% or more), an AlCu alloy film, an AlSi alloy film, and an AlSiCu alloy film. The gate pad electrode 24 has an electrode surface (similar to the electrode surface 70 (Figure 6)) and a side wall (similar to the side wall 71 (Figure 9)). The gate pad electrode 24 has the same electrode thickness (electrode thickness T2 (Figure 7)) as the source pad electrode 19.

[0134] Referring to Figure 3B, a second pad alloy layer 42 is formed on the surface of the gate pad electrode 24. The second pad alloy layer 42 covers both the electrode surface and the side wall of the gate pad electrode 24. The second pad alloy layer 42 may also include a TiAl alloy layer 80 (Figure 12). The second pad alloy layer 42 has the same layer thickness (layer thickness T1 (Figure 7)) as the first pad alloy layer 40. As described above, a fourth alloy opening 48 is formed in the second pad alloy layer 42.

[0135] Referring to Figures 1, 3A, and 3B, the fourth alloy opening 48 (Figure 3B) is formed in a polygonal shape (for example, a quadrilateral shape) along the periphery of the gate pad electrode 24 (Figure 3A) in a plan view. In a plan view, the fourth alloy opening 48 overlaps with the gate pad opening 32 (Figure 1) of the organic insulating film 30.

[0136] In this configuration, the inner wall of the fourth alloy opening 48 coincides with the inner wall of the gate pad opening 32 in a plan view. In other words, the inner wall of the fourth alloy opening 48 communicates with the inner wall of the gate pad opening 32. The inner wall of the fourth alloy opening 48 may be located inside the gate pad opening 32. The inner wall of the fourth alloy opening 48 may be located outside the gate pad opening 32.

[0137] The gate pad 31 of the electrode surface 70 of the gate pad electrode 24 does not have the second pad alloy layer 42 (alloy layer 39) formed on it. Therefore, wire bonding to the gate pad 31 is directly connected to the electrode surface of the gate pad electrode 24. Since there is no alloy layer 39 interposed between the bonding wire and the gate pad 31, wire bonding can be performed well.

[0138] In particular, in this configuration, the second pad alloy layer 42 (alloy layer 39) includes a TiAl alloy layer 80 (Figure 12). There is a concern that if a material containing Ti is present on the gate pad 31, wire bonding defects may occur. However, in this configuration, since the second pad alloy layer 42 (alloy layer 39) is not formed on the gate pad 31, the above concern does not exist.

[0139] In other words, a second pad alloy layer 42 (alloy layer 39) is formed on the electrode surface of the gate pad electrode 24, covering the entire area except for the gate pad 31.

[0140] The second pad alloy layer 42 covers not only the sidewalls of the gate pad electrode 24, but also the sidewalls of the portion of the lower electrode layer 63 corresponding to the gate pad electrode 24. As a result, the portion of the lower electrode layer 63 corresponding to the gate pad electrode 24 is protected by the second pad alloy layer 42.

[0141] Referring to Figure 9, the gate wiring 25 is positioned on the first main surface 3. In this configuration, the gate wiring 25 is positioned on the first main surface 3 in the outer peripheral region 10. The gate wiring 25 may also be positioned on the first main surface 3 in the active region 9.

[0142] The gate wiring 25 is formed from a metallic material containing aluminum (Al). The gate wiring 25 includes an Al-based metal film. The gate wiring 25 may include at least one of a pure Al film (an Al film with a purity of 99% or more), an AlCu alloy film, an AlSi alloy film, and an AlSiCu alloy film. The gate wiring 25 has an electrode surface 70 and a side wall 71. The gate wiring 25 has an electrode thickness T2.

[0143] A second wiring alloy layer 43 is formed on the surface of the gate wiring 25. The second wiring alloy layer 43 covers both the electrode surface 70 and the side wall 71 of the gate wiring 25. The second wiring alloy layer 43 may also include a TiAl alloy layer 80 (Figure 12). The second wiring alloy layer 43 has a layer thickness T1.

[0144] The second wiring alloy layer 43 covers the gate wiring 25 over its entire length in the direction in which it extends. In other words, the second wiring alloy layer 43 covers the gate wiring 25 over its entire length in the circumferential direction.

[0145] The second wiring alloy layer 43 covers not only the side walls 71 of the gate wiring 25, but also the side walls 73 of the lower electrode layer 63 (the side walls of the portion of the lower electrode layer 63 corresponding to the gate wiring 25). As a result, the portion of the lower electrode layer 63 corresponding to the gate wiring 25 is protected by the second wiring alloy layer 43.

[0146] Figure 10 is a schematic diagram showing a wafer 150 used in the manufacture of semiconductor device 1A. Referring to Figure 10, the wafer 150 is the substrate for the chip 2 and contains a SiC single crystal. The wafer 150 is formed in the shape of a flat disc. Of course, the wafer 150 may also be formed in the shape of a flat rectangular parallelepiped. The wafer 150 has a first wafer main surface 151 on one side, a second wafer main surface 152 on the other side, and a wafer side surface 153 connecting the first wafer main surface 151 and the second wafer main surface 152.

[0147] The first wafer main surface 151 corresponds to the first main surface 3 of the chip 2 (Figure 2, etc.), and the second wafer main surface 152 corresponds to the second main surface 4 of the chip 2 (Figure 2, etc.). The first wafer main surface 151 and the second wafer main surface 152 are formed by the c-plane of a SiC single crystal. The first wafer main surface 151 is formed by the silicon plane of the SiC single crystal, and the second wafer main surface 152 is formed by the carbon plane of the SiC single crystal. The wafer 150 (first wafer main surface 151 and second wafer main surface 152) has the aforementioned off-direction and off-angle.

[0148] The wafer 150 has markings 154 on the wafer side surface 153 that indicate the crystal orientation of the SiC single crystal. The markings 154 may include either an orientation flat or an orientation notch, or both. An orientation flat consists of a notch that is cut out in a straight line in a plan view. An orientation notch consists of a notch that is cut out in a concave shape (for example, tapered shape) toward the center of the first wafer main surface 151 in a plan view.

[0149] The marker 154 may include either or both a first orientation flat extending in the m-axis direction and a second orientation flat extending in the a-axis direction. The marker 154 may also include either or both an orientation notch recessed in the m-axis direction and an orientation notch recessed in the a-axis direction.

[0150] The wafer 150 includes a second semiconductor region 7 (as shown in Figure 11A, described later) in the region (surface layer) on the side of the first wafer main surface 151. The second semiconductor region 7 is formed in layers extending along the first wafer main surface 151. In this configuration, the second semiconductor region 7 consists of an epitaxial layer (specifically, a SiC epitaxial layer). A drift region 8 (as shown in Figure 11A, described later) is formed in the second semiconductor region 7.

[0151] The wafer 150 includes a first semiconductor region 6 (as shown in Figure 11A, described later) in the region (surface layer) on the second wafer main surface 152 side. The first semiconductor region 6 is formed in layers extending along the second main surface 4 and is electrically connected to the first semiconductor region 6. In this embodiment, the first semiconductor region 6 consists of the wafer body (specifically, a SiC wafer). In other words, in this embodiment, the wafer 150 consists of an epitaxial wafer (a so-called epi-wafer) having a laminated structure including the wafer body and an epitaxial layer.

[0152] For example, the wafer 150 has multiple device regions 155 and multiple cutting lines 156 marked by alignment marks or the like. Each device region 155 corresponds to a semiconductor device 1A. The multiple device regions 155 are each set in a rectangular shape when viewed from above.

[0153] In this configuration, the multiple device regions 155 are arranged in a matrix along the first direction X and the second direction Y in a plan view. The multiple device regions 155 are each spaced inward from the periphery of the first wafer main surface 151 in a plan view. The multiple cutting lines 156 are arranged in a grid pattern extending along the first direction X and the second direction Y to demarcate the multiple device regions 155.

[0154] Figures 11A to 11J are cross-sectional views showing a method for manufacturing a semiconductor device 1A. Figures 11A to 11J show cross-sections of a part of the active region 9 and a part of the outer peripheral region 10. In Figures 11A to 11J, the left view corresponds to a part of the cross-section in Figure 7 (a part of the active region 9), and the right view corresponds to a part of the cross-section in Figure 8 (a part of the outer peripheral region 10).

[0155] Referring to Figure 11A, first, the aforementioned wafer 150 is prepared. Next, referring to Figure 11B, a plurality of unit cells UC are formed on the surface layer of the first wafer main surface 151 (the surface layer of the second semiconductor region 7). Specifically, a plurality of body regions 50, a plurality of source regions 51, and a plurality of body contact regions 53 are formed.

[0156] Next, referring to Figure 11C, a base insulating film 160 is formed to cover the main surface 151 of the first wafer. The base insulating film 160 is the base for the gate insulating film 56 (Figure 7) and the outer insulating film 62 (Figure 8). The base insulating film 160 may be formed by CVD or oxidation (for example, thermal oxidation). Next, a gate electrode 57 is formed on the base insulating film 160. The gate electrode 57 is conductive polysilicon. The gate electrode 57 may be formed by CVD.

[0157] Next, referring to Figure 11D, an interlayer film 15 is formed on the main surface 151 of the first wafer. This forms an interlayer film 15 having a portion that directly covers the gate electrode 57. In other words, multiple unit cells UC are covered by the interlayer film 15. The interlayer film 15 may be formed by the CVD method. After the formation of the interlayer film 15 (oxide film), a reflow process (heat treatment process) may be performed on the interlayer film 15.

[0158] Next, referring to Figure 11E, a first mask having a predetermined layout is placed on the interlayer film 15. The first mask exposes the areas where multiple source contact openings 58 and outer openings 61 are to be formed, and covers the other areas. Next, unnecessary portions of the interlayer film 15 and the base insulating film 160 are removed by etching through the first mask.

[0159] In this step, unwanted portions of the interlayer film 15 and the base insulating film 160 are removed in that order. The etching method may be a wet etching method and / or a dry etching method. The etching method is preferably an anisotropic dry etching method (for example, RIE (Reactive Ion Etching) method). By removing the unwanted portions of the interlayer film 15, a plurality of source contact openings 58 are formed in the interlayer film 15. By removing the unwanted portions of the interlayer film 15, an outer opening 61 is formed in the interlayer film 15. By removing the unwanted portions from the base insulating film 160, a gate insulating film 56 and an outer insulating film 62 are formed. The first mask is then removed.

[0160] Next, referring to Figure 11F, the lower electrode layer 63 is formed on the interlayer film 15 of the active region 9 and the peripheral region 10. The lower electrode layer 63 may be formed by sputtering or vapor deposition. The lower electrode layer 63 includes, for example, one or both of Ti and TiN.

[0161] Next, a metal electrode 16 is formed on the lower electrode layer 63. The metal electrode 16 is made of a metallic material containing aluminum (Al). Of the metal electrode 16, the source pad electrode 19 is electrically connected to a plurality of body regions 50 via a source contact opening 58. Of the metal electrode 16, the source wiring 20 is electrically connected to the outer contact region 60 via an outer opening 61.

[0162] Next, referring to Figure 11G, an alloy base film 165, which will form the base of the alloy layer 39 (Figure 3B), is formed on the interlayer film 15 of the active region 9 and the outer peripheral region 10. The alloy base film 165 is, for example, a Ti film. The alloy base film 165 may be formed by sputtering. The alloy base film 165 covers the electrode surface 70 and the side walls 71 of the metal electrode 16. The alloy base film 165 is formed to cover the entire surface of the metal electrode 16.

[0163] Next, referring to Figure 11H, the unwanted portion of the alloy base film 165 is removed by etching through the alloy forming mask 166. The alloy forming mask 166 is then removed.

[0164] Next, the material is heat-treated as shown in Figure 11I. This causes the Ti film, which is the alloy base film 165, to become alloyed. As a result, the alloy layer 39 is formed.

[0165] Next, referring to Figure 11J, an organic insulating film 30 is selectively formed on the metal electrode 16, with an alloy layer 39 in between. Then, a drain electrode 44 (Figure 2) is formed on the second wafer main surface 152. The drain electrode 44 may be formed by sputtering or vapor deposition. Then, the wafer 150 is cut along the planned cutting line 156, and a plurality of semiconductor devices 1A are cut out. A semiconductor device 1A is manufactured through the process including the above.

[0166] Conventionally, a method has been known in which the electrode surface and sidewalls of a metal electrode are coated with an organic insulating film.

[0167] When this method is used, there is a risk that moisture (water) may penetrate into the organic insulating film 30 from the outer peripheral region 10. If moisture comes into contact with (is supplied to) the metal electrode 16 that has penetrated into the organic insulating film 30, the metal electrode 16 may corrode. If the metal electrode 16 corrodes, the corroded portion may peel off.

[0168] In particular, when polyimide or polyimide is used as the organic insulating film 30, the high hygroscopicity of polyimide or polyimide increases the concern about moisture (water) penetrating into the organic insulating film 30.

[0169] Furthermore, if the metal electrode 16 is formed using a metal material containing aluminum, the risk of corrosion of the metal electrode 16 increases.

[0170] In this embodiment, the metal electrode 16 is covered by an alloy layer 39, and the metal electrode 16 is covered by an organic insulating film 30 with the alloy layer 39 in between. Since the metal electrode 16 is covered by the alloy layer 39, moisture (water) that has penetrated into the organic insulating film 30 is prevented from coming into contact with (being supplied to) the metal electrode 16 by the alloy layer 39. This prevents corrosion of the metal electrode 16.

[0171] Furthermore, according to this embodiment, the alloy layer 39 includes a first wiring alloy layer 41 that covers the source wiring 20 arranged on the outer peripheral region 10. That is, the source wiring 20, which is the outermost of the electrodes included in the metal electrode 16, is covered by the first wiring alloy layer 41.

[0172] In this layout, where the source wiring 20 is located on the outermost side, moisture (water) that penetrates into the organic insulating film 30 from the outer peripheral region 10 may reach the vicinity of the source wiring 20. However, since the first wiring alloy layer 41 prevents moisture (water) from coming into contact with the source wiring 20, corrosion of the source wiring 20 can be prevented even in this layout.

[0173] Furthermore, according to this embodiment, the first wiring alloy layer 41 covers the source wiring 20 over its entire circumferential area. Therefore, corrosion of the source wiring 20 can be prevented over its entire area.

[0174] Furthermore, due to the layout in which the source wiring 20 is positioned close to the source pad electrode 19, a higher electric field may be concentrated near the source wiring 20 than the electric field on the source pad electrode 19 side. Therefore, if moisture (water) comes into contact with the source wiring 20, corrosion of the source wiring 20 is likely to occur. However, since the first wiring alloy layer 41 prevents moisture (water) from coming into contact with the source wiring 20, corrosion of the source wiring 20 can be prevented even when a high electric field is concentrated near the source wiring 20.

[0175] Furthermore, according to this embodiment, the alloy layer 39 includes a first pad alloy layer 40 that covers the source pad electrode 19. The first pad alloy layer 40 covers at least the peripheral edge of the source pad electrode 19 over the entire area along the outer circumference of the source pad electrode 19. In other words, the entire outer circumference of the source pad electrode 19 is covered by the alloy layer 39.

[0176] Even if moisture (water) penetrates into the organic insulating film 30 covering the source pad electrode 19, the penetrated moisture (water) is prevented from coming into contact with (being supplied to) the source pad electrode 19. This prevents corrosion of the source pad electrode 19.

[0177] Furthermore, according to this embodiment, the alloy layer 39 is formed to span both the electrode surface 70 and the side wall 71 of the metal electrode 16. Therefore, the metal electrode 16 can be well protected by the alloy layer 39.

[0178] Furthermore, according to this embodiment, the metal electrode 16 is formed from a metallic material containing aluminum. The alloy layer 39 includes an aluminum alloy layer. Therefore, the alloy layer 39 has high adhesion to the metal electrode 16. As a result, it is possible to prevent the aluminum alloy layer from peeling off from the metal electrode 16.

[0179] Furthermore, according to this embodiment, the alloy layer 39 includes a TiAl alloy layer 80. The Ti-based metal material including the TiAl alloy layer 80 has high adhesion to polyimide. Therefore, it is possible to prevent moisture (water) from penetrating between the alloy layer 39 and the organic insulating film 30. This effectively prevents delamination between the alloy layer 39 and the organic insulating film 30.

[0180] Furthermore, according to this embodiment, the alloy layer 39 has a layer thickness T1 of 500 Å or less. The layer thickness T1 may be 200 Å or less. The layer thickness T1 may be 100 Å or less.

[0181] The protective effect of the alloy layer 39 on the metal electrode 16 can be achieved regardless of the thickness of the alloy layer 39. Therefore, by making the layer thickness T1 of the alloy layer 39 thin, it is possible to suppress the semiconductor device 1A from becoming thicker (increasing in size in the thickness direction). In other words, the metal electrode 16 can be well protected while suppressing the semiconductor device 1A from becoming thicker.

[0182] Next, variations of the alloy layer 39 will be described with reference to Figures 12 to 14. Figures 12 to 14 are cross-sectional views showing the first to third embodiments of the alloy layer 39, respectively.

[0183] In the configuration shown in Figure 12, the alloy layer 39 is a TiAl alloy layer 80 containing aluminum (Al) and titanium (Ti). The TiAl alloy layer 80 is formed by alloying titanium (Ti) with aluminum (Al), which is the electrode material of the metal electrode 16, by, for example, heat treatment after depositing a Ti film on the metal electrode 16. The TiAl alloy layer 80 has a layer thickness T1.

[0184] In this specification, the TiAl alloy layer 80 refers to an alloy layer containing Ti and Al. The TiAl alloy layer 80 is intended to include at least one of the following: a TiAl alloy layer, a TiAlSn alloy layer, a TiAlV alloy layer, a TiAlVSn alloy layer, a TiAlSnZrMo alloy layer, a TiVCrAl alloy layer, and a TiAlVCrMoZr alloy layer.

[0185] In the configuration shown in Figure 13, the alloy layer 39 is a CoAl alloy layer 81 containing aluminum (Al) and cobalt (Co). The CoAl alloy layer 81 is formed by alloying cobalt (Co) with aluminum (Al), which is the electrode material of the metal electrode 16, by, for example, heat treatment after depositing a Co film on the metal electrode 16. The CoAl alloy layer 81 has a layer thickness T1.

[0186] In the configuration shown in Figure 14, the alloy layer 39 is a NiAl alloy layer 82 containing aluminum (Al) and nickel (Ni). The NiAl alloy layer 82 is formed by alloying nickel (Ni) with aluminum (Al), which is the electrode material of the metal electrode 16, by, for example, heat treatment after depositing a Ni film on the metal electrode 16. The NiAl alloy layer 82 has a layer thickness T1.

[0187] In this specification, the NiAl alloy layer 82 refers to an alloy layer containing Ni and Al. The NiAl alloy layer 82 is intended to include at least one of the following: a NiAlTi alloy layer, a NiAlV alloy layer, a NiAlCr alloy layer, a NiAlMn alloy layer, a NiAlFe alloy layer, and a NiCoAl alloy layer.

[0188] Figure 15A is a plan view showing an example layout of the metal electrode 16B according to the second embodiment of the present disclosure. Figure 15B is a cross-sectional view taken along the line XVB-XVB shown in Figure 15A.

[0189] The semiconductor device 1B according to the second embodiment of this disclosure includes a metal electrode 16B instead of a metal electrode 16 (Figure 3A). The metal electrode 16B does not include a gate wiring 25 (Figure 3A). The semiconductor device 1B includes a gate embedded wiring 105 instead of a gate wiring 25. In Figures 15A and 15B, components equivalent to those in the first embodiment are denoted by the same reference numerals as in Figures 1 to 14, and their descriptions are omitted.

[0190] The gate-embedded wiring 105 is embedded wiring embedded in the interlayer membrane 15 (Figure 2). The gate-embedded wiring 105 is insulated and isolated from the source pad electrode 19 and source wiring 20 by the interlayer membrane 15. The upper surface of the gate-embedded wiring 105 is covered by the interlayer membrane 15. In other words, the upper surface of the gate-embedded wiring 105 is not exposed on the interlayer membrane 15.

[0191] The gate-embedded wiring 105 is made of conductive polysilicon. The gate-embedded wiring 105 may contain either or both of p-type conductive polysilicon and n-type conductive polysilicon.

[0192] As mentioned above, the gate embedded wiring 105 is not exposed on the interlayer film 15. Furthermore, the gate embedded wiring 105 is formed using conductive polysilicon and is not metal wiring. In other words, the gate embedded wiring 105 is not included in the metal electrode 16B.

[0193] The gate embedded wiring 105 is mechanically and electrically connected to the gate pad electrode 24. The gate embedded wiring 105 includes a plurality of finger embedded wirings 106, 107 extending in a strip-like manner from the gate pad electrode 24 in different directions. The plurality of finger embedded wirings 106, 107 are arranged in a non-parallel positional relationship with respect to each other. The plurality of finger embedded wirings 106, 107 may include a first finger embedded wiring 106 and a second finger embedded wiring 107.

[0194] The first finger embedded wiring 106 and the second finger embedded wiring 107 extend from the gate pad electrode 24 in opposite directions along the periphery of the tip 2, and in a plan view, collectively surround the source pad electrode 19. The first finger embedded wiring 106 and the second finger embedded wiring 107 may also be referred to as gate outer periphery embedded wiring.

[0195] In this configuration, the first finger embedded wiring 106 and the second finger embedded wiring 107 are each formed in a substantially U shape in plan view and have a corner C2 at a position corresponding to the corner C of the tip 2.

[0196] In this configuration, the first finger embedded wiring 106 extends from the gate pad electrode 24 along the first side 5A, the third side 5C, and the second side 5B in that order, and has a third tip portion 108 midway along the second side 5B in the first direction X. The second finger embedded wiring 107 extends from the gate pad electrode 24 along the first side 5A, the fourth side 5D, and the second side 5B in that order, and has a fourth tip portion 109 midway along the second side 5B in the first direction X. The third tip portion 108 and the fourth tip portion 109 face each other with space between them in the first direction X.

[0197] The first finger buried wiring 106 has the same layout as the first finger wiring 26 (Figure 3A) in a plan view. The second finger buried wiring 107 has the same layout as the second finger wiring 27 (Figure 3A) in a plan view. In other words, the gate buried wiring 105 has the same layout as the gate wiring 25 (Figure 3A) in a plan view.

[0198] Semiconductor device 1B provides the same effects and benefits as those described in relation to semiconductor device 1A according to the first embodiment.

[0199] Figure 16A is a plan view showing an example layout of the metal electrode 16C according to the third embodiment of the present disclosure. Figure 16B is a plan view showing an example layout of the alloy layer 39C according to the third embodiment of the present disclosure. In Figure 16B, for ease of viewing, the reference numerals of the metal electrode 16C are shown in accordance with the reference numerals of each part of the alloy layer 39C.

[0200] The semiconductor device 1C according to the third embodiment of this disclosure includes a metal electrode 16C instead of a metal electrode 16 (Figure 3A). The metal electrode 16C does not include a source wiring 20 (Figure 3A). Except for this point, the metal electrode 16C is the same as the metal electrode 16. The metal electrode 16C includes a gate wiring 25. In Figures 16A and 16B, components equivalent to those in the first embodiment are given the same reference numerals as in Figures 1 to 14, and their descriptions are omitted.

[0201] The semiconductor device 1C includes an alloy layer 39C instead of the alloy layer 39 (Figure 3B). The alloy layer 39C does not include the first wiring alloy layer 41 (Figure 3B). Except for this point, it is the same as the alloy layer 39. The alloy layer 39C includes a second wiring alloy layer 43.

[0202] In this configuration, the gate wiring 25 is the outermost electrode among the electrodes included in the metal electrode 16. The electrode surface 70 and side wall 71 of the gate wiring 25 are covered by the second wiring alloy layer 43.

[0203] Furthermore, according to this embodiment, the outermost gate wiring 25 among the electrodes included in the metal electrode 16C is covered by the second wiring alloy layer 43. Due to the layout in which the gate wiring 25 is located on the outermost side, moisture (water) that has entered the interior of the organic insulating film 30 from the outer peripheral region 10 may reach the vicinity of the gate wiring 25. However, since the second wiring alloy layer 43 prevents moisture (water) from coming into contact with the gate wiring 25, corrosion of the gate wiring 25 can be prevented even with this layout.

[0204] Furthermore, according to this embodiment, the second wiring alloy layer 43 covers the gate wiring 25 over its entire circumferential area. Therefore, corrosion of the gate wiring 25 can be prevented over its entire area.

[0205] Furthermore, semiconductor device 1C provides the same effects and benefits as those described in relation to semiconductor device 1A according to the first embodiment.

[0206] Figure 17A is a plan view showing an example layout of the metal electrode 16 according to the fourth embodiment of this disclosure. Figure 17B is a plan view showing an example layout of the alloy layer 39 according to the fourth embodiment of this disclosure. Figure 18 is a cross-sectional view showing the main part of the semiconductor device 1D according to the fourth embodiment, and shows the cross-section at the same position as in Figure 7. In Figures 17A to 18, components equivalent to those in the first embodiment are given the same reference numerals as in Figures 1 to 14, and their descriptions are omitted.

[0207] The semiconductor device 1D has a trench gate type vertical structure (trench structure) as an example of a transistor structure Tr, instead of a planar gate type vertical structure (planar structure).

[0208] The semiconductor device 1D includes a chip 2, similar to the semiconductor device 1A. The chip 2 has a stacked structure including an n-type first semiconductor region 6 and an n-type second semiconductor region 7, similar to the semiconductor device 1A, and includes a first main surface 3, a second main surface 4, and first to fourth side surfaces 5A to 5D. The second semiconductor region 7 has a drift region 8.

[0209] Referring to Figure 17A, the semiconductor device 1D includes a metal electrode 16 which comprises a source metal 17 and a gate metal 18. The source metal 17 includes a source pad electrode 19 and a source wiring 20. The gate metal 18 includes a gate pad electrode 24 and a gate wiring 25.

[0210] Referring to Figure 17B, the semiconductor device 1D includes an alloy layer 39 disposed between the metal electrode 16 and the organic insulating film 30 (Figure 18). The alloy layer 39 includes a first pad alloy layer 40, a first wiring alloy layer 41, a second pad alloy layer 42, and a second wiring alloy layer 43.

[0211] The first pad alloy layer 40 has a first alloy opening 45, a second alloy opening 46, and a third alloy opening 47 formed therein. The first alloy opening 45, the second alloy opening 46, and the third alloy opening 47 expose the first source pad 33, the second source pad 35, and the third source pad 37, respectively.

[0212] A fourth alloy opening 48 is formed in the second pad alloy layer 42. The fourth alloy opening 48 exposes the gate pad 31.

[0213] Referring to Figure 18, the semiconductor device 1D includes a plurality of trench gate structures 200. The plurality of trench gate structures 200 include a plurality of gate trenches 201 arranged in a stripe pattern extending along a first direction X, a gate insulating film 203 formed on the inner surface of the plurality of gate trenches 201, and gate electrodes 204 embedded in the plurality of gate trenches 201 via the gate insulating film 203.

[0214] Multiple gate trenches 201 are formed on the first main surface 3. The gate trenches 201 penetrate the source region 51 and the body region 50 and reach the drift region 8. Between adjacent gate trenches 201, mesa portions 202 are formed by a part of the second semiconductor region 7. The mesa portions 202 are strip-shaped and extend along the first direction X, and are arranged alternately in the second direction Y. Multiple mesa portions 202 are arranged in a stripe pattern as a whole.

[0215] Each mesa portion 202 provides a unit cell UC of a trench gate type transistor structure Tr. Each mesa portion 202 may be the smallest unit that functions as an MIS transistor, comprising at least a body region 50 and a source region 51. The body region 50 and the source region 51 are formed sequentially in the mesa portion 202 in the direction from the bottom of the gate trench 201 toward the first main surface 3.

[0216] The gate insulating film 203 covers the inner surface of the gate trench 201. The gate insulating film 203 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. In this embodiment, the gate insulating film 203 has a single-layer structure made of a silicon oxide film. The gate insulating film 203 may also include a silicon oxide film made of the oxide of the chip 2.

[0217] The gate electrode 204 may also be referred to as an "embedded conductive layer." The gate electrode 204 faces the body region 50 (channel region 52) with the gate insulating film 203 in between. The gate electrode 204 may contain p-type or n-type conductive polysilicon.

[0218] Referring to Figure 18, the metal electrode 16 is formed from a metallic material containing aluminum (Al). The metal electrode 16 has an electrode surface 70 and a side wall 71. The metal electrode 16 has an electrode thickness T2.

[0219] The alloy layer 39 is formed on the surface of the metal electrode 16. The alloy layer 39 covers both the electrode surface 70 and the side wall 71 of the metal electrode 16. The metal electrode 16 is covered by the alloy layer 39, and the metal electrode 16 is covered by the organic insulating film 30 with the alloy layer 39 in between. The alloy layer 39 may include a TiAl alloy layer 80 (Figure 12). The alloy layer 39 may include a CoAl alloy layer 81 (Figure 13). The alloy layer 39 may include a NiAl alloy layer 82 (Figure 14). The alloy layer 39 has a layer thickness T1.

[0220] The semiconductor device 1D provides the same effects and benefits as those described in relation to the semiconductor device 1A according to the first embodiment.

[0221] Furthermore, the semiconductor device 1B according to the second embodiment may be combined with the semiconductor device 1D according to the fourth embodiment. That is, in the semiconductor device 1D in which a trench gate type vertical structure is adopted as the device structure, gate embedded wiring 105 may be provided instead of gate wiring 25.

[0222] Furthermore, the semiconductor device 1C according to the third embodiment may be combined with the semiconductor device 1D according to the fourth embodiment. That is, in the semiconductor device 1D employing a trench gate type vertical structure as the device structure, the metal electrode 16C does not need to have source wiring 20 (Figure 3A).

[0223] Figure 19A is a plan view showing an example layout of the metal electrode 16 according to the fifth embodiment of this disclosure. Figure 19B is a plan view showing an example layout of the alloy layer 39 according to the fifth embodiment of this disclosure. Figure 20 is a cross-sectional view taken along the line XX-XX shown in Figure 19A.

[0224] The semiconductor device 1E according to the fifth embodiment of this disclosure has a modified configuration of the device structure related to semiconductor device 1A. More specifically, the semiconductor device 1E has a Schottky barrier diode 300 (Schottky Barrier Diode structure) on the first main surface 3 instead of an insulated gate type transistor structure Tr as a device structure. The semiconductor device 1E may also be called a semiconductor rectifier.

[0225] The semiconductor device 1E includes a chip 2, similar to the semiconductor device 1A. The chip 2 has a stacked structure including an n-type first semiconductor region 6 and an n-type second semiconductor region 7, similar to the semiconductor device 1A, and includes a first main surface 3, a second main surface 4, and first to fourth side surfaces 5A to 5D. The second semiconductor region 7 has a drift region 8.

[0226] Referring to Figure 20, the semiconductor device 1E includes a p-type guard region 301 formed on the surface of the first main surface 3. The guard region 301 is an example of a second conductivity type anode region. The guard region 301 has a p-type impurity concentration higher than the n-type impurity concentration of the second semiconductor region 7. The guard region 301 is formed in the inner part of the first main surface 3, spaced apart from the periphery (first to fourth side surfaces 5A to 5D) of the first main surface 3.

[0227] The guard region 301 extends in a band shape along the periphery of the first main surface 3. In this configuration, the guard region 301 is formed in a polygonal ring (quadrilateral ring) shape surrounding the inner part of the first main surface 3. The guard region 301 is formed on the surface of the second semiconductor region 7 with a gap between it and the first main surface 3 from the first semiconductor region 6, and faces the first semiconductor region 6 with a portion of the second semiconductor region 7 in between.

[0228] Referring to Figures 19A to 20, the semiconductor device 1E includes an insulating interlayer film 15 that selectively covers the first main surface 3. The interlayer film 15 includes contact openings 303 that selectively expose the first main surface 3 and the guard region 301. The contact openings 303 expose the inner portion of the first main surface 3 and the inner edge of the guard region 301.

[0229] The semiconductor device 1E includes a metal electrode 16E disposed on the interlayer film 15. In this embodiment, the metal electrode 16E is an anode electrode 304 to which an anode potential is applied. The anode electrode 304 is an example of a Schottky electrode. The anode electrode 304 is an example of a pad electrode. The anode electrode 304 is formed in a rectangular shape having four sides parallel to the first to fourth sides 5A to 5D in a plan view.

[0230] The anode electrode 304 comprehensively covers the region of the interlayer film 15 where the contact opening 303 is formed. The anode electrode 304 is mechanically and electrically connected to the second semiconductor region 7 and the guard region 301 on the first main surface 3. The anode electrode 304 forms a Schottky junction with the second semiconductor region 7. This forms a Schottky barrier diode 300, which is an example of a device structure.

[0231] The semiconductor device 1E includes an organic insulating film 30 that covers the interlayer film 15 on the first main surface 3 and selectively covers the metal electrode 16E. The organic insulating film 30 is formed in a rectangular shape with four sides parallel to the first to fourth side surfaces 5A to 5D in a plan view. The peripheral edge of the organic insulating film 30 is formed with a gap in the inward region from the first to fourth side surfaces 5A to 5D, exposing the first main surface 3.

[0232] An anode opening 305 is formed in the inner part of the organic insulating film 30. In a plan view, the anode opening 305 is formed in a rectangular shape along the periphery of the anode electrode 304. The anode opening 305 exposes the inner part of the electrode surface of the anode electrode 304 as an anode pad 306.

[0233] The semiconductor device 1E includes an alloy layer 39E disposed between the anode electrode 304 (metal electrode 16E) and the organic insulating film 30. The alloy layer 39E includes an anode alloy layer (pad alloy layer) 307. The anode alloy layer 307 covers the peripheral edge of the anode electrode 304.

[0234] The anode alloy layer 307 is positioned between the anode electrode 304 and the organic insulating film 30. The anode alloy layer 307 covers the electrode surface 70 and the side wall 71 of the anode electrode 304. The anode electrode 304 is covered by the anode alloy layer 307, and the anode electrode 304 is covered by the organic insulating film 30 with the anode alloy layer 307 in between. The anode alloy layer 307 may include a TiAl alloy layer 80 (Figure 12). The anode alloy layer 307 may include a CoAl alloy layer 81 (Figure 13). The anode alloy layer 307 may include a NiAl alloy layer 82 (Figure 14). The anode alloy layer 307 has a layer thickness T1.

[0235] A fifth alloy opening 308 is formed in the anode alloy layer 307. In a plan view, the fifth alloy opening 308 is formed in a square shape along the periphery of the anode electrode 304. The fifth alloy opening 308 exposes the inner part of the electrode surface of the anode electrode 304 as an anode pad 306. In a plan view, the fifth alloy opening 308 overlaps with the anode opening 305 of the organic insulating film 30.

[0236] In this configuration, the inner wall of the fifth alloy opening 308 is aligned with the inner wall of the anode opening 305 in a plan view. In other words, the inner wall of the fifth alloy opening 308 communicates with the inner wall of the anode opening 305. The inner wall of the fifth alloy opening 308 may be located outside the anode opening 305. The inner wall of the fifth alloy opening 308 may be located inside the anode opening 305.

[0237] A cathode electrode 309 to which a cathode potential is applied is positioned on the second main surface 4.

[0238] The semiconductor device 1E provides the same effects and benefits as those described in relation to the semiconductor device 1A according to the first embodiment.

[0239] The following are examples of features extracted from this specification and drawings. The alphanumeric characters in parentheses below represent the corresponding components in the embodiments described above, but this is not intended to limit the scope of each Clause to the embodiments. The term "semiconductor device" in the following items may be replaced with "SiC semiconductor device," "wide bandgap semiconductor device," "semiconductor switching device," "semiconductor rectifier," "MISFET device," "IGBT device," "diode device," etc., as needed.

[0240] One of the objectives of this disclosure is to provide a semiconductor device in which corrosion of metal electrodes is prevented while the metal electrodes are coated with an organic insulating film.

[0241] [Note 1-1] A semiconductor device (1A, 1B, 1C, 1D, 1E) comprising: a chip (2) having a main surface (3); a device structure (Tr) formed on the main surface (3); metal electrodes (16, 16B, 16C, 16E) covering the main surface (3); alloy layers (39, 39C, 39E) covering the metal electrodes (16, 16B, 16C, 16E); and an organic insulating film (30) covering the metal electrodes (16, 16B, 16C, 16E) with the alloy layers (39, 39C, 39E) in between.

[0242] [Appendix 1-2] The semiconductor device (1A, 1B, 1C, 1D) according to Appendix 1-1, further comprising: an active region (9) provided in the inner part of the main surface (3) on which the device structure (Tr) is formed; and an outer peripheral region (10) provided on the periphery of the main surface (3) and surrounding the active region (9); wherein the metal electrodes (16, 16B, 16C) include pad electrodes (19, 24) and wiring (20, 25) electrically connected to the pad electrodes (19, 24) and formed on the outer peripheral region (10); and the alloy layers (39, 39C) include wiring alloy layers (41, 43) covering the wiring (20, 25).

[0243] [Note 1-3] The wiring (20, 25) is formed in a band shape so as to surround the periphery of the active region (9) in a plan view, and the wiring alloy layer (41, 43) covers the wiring (20, 25) over the entire area in the direction in which the wiring (20, 25) extends, as described in Note 1-2 (1A, 1B, 1C, 1D).

[0244] [Appendix 1-4] The semiconductor device (1A, 1B, 1C, 1D) described in Appendix 1-2 or Appendix 1-3, wherein the alloy layer (39, 39C, 39E) includes a pad alloy layer (40, 42) that covers the pad electrodes (19, 24).

[0245] [Appendix 1-5] The pad electrodes (19, 24, 304) are formed in a polygonal shape in plan view, and the pad alloy layer (40, 42, 307) covers at least the peripheral edges of the pad electrodes (19, 24, 304), as described in Appendix 1-4 (1A, 1B, 1C, 1D).

[0246] [Appendix 1-6] The organic insulating film (30) has pad openings (32, 34, 36, 38) that expose the pad electrodes (19, 24) as pads (31, 33, 35, 37), and the pad alloy layer (40, 42, 307) has alloy pad openings (45, 46, 47, 48) in regions corresponding to the pad openings (32, 34, 36, 38) that expose the pad electrodes (19, 24, 304) as pads (31, 33, 35, 37), and the semiconductor device (1A, 1B, 1C, 1D) as described in Appendix 1-4 or Appendix 1-5.

[0247] [Appendix 1-7] The semiconductor device (1A, 1B, 1D) according to any one of the appendices 1-2 to 1-6, wherein the pad electrode (24) includes a source pad electrode (24), and the wiring (25) includes a source wiring (25).

[0248] [Appendix 1-8] The semiconductor device (1A, 1B, 1C, 1D, 1E) according to any one of the appendices 1-1 to 1-7, wherein the metal electrodes (16, 16B, 16C, 16E) have an electrode surface (70) and a side wall (71), and the alloy layer (39, 39C, 39E) is formed to span both the electrode surface (70) and the side wall (71).

[0249] [Appendix 1-9] The metal electrodes (16, 16B, 16C, 16E) are formed from a metallic material containing aluminum, and the alloy layers (39, 39C, 39E) include an aluminum alloy layer (39, 39C, 39E), as described in any one of Appendix 1-1 to 1-8, semiconductor device (1A, 1B, 1C, 1D, 1E).

[0250] [Appendix 1-10] The semiconductor device (1A, 1B, 1C, 1D, 1E) according to Appendix 1-9, wherein the metal electrodes (16, 16B, 16C, 16E) have a single-layer structure of the metal material including aluminum.

[0251] [Appendix 1-11] The alloy layers (39, 39C, 39E) include a TiAl alloy layer (80), as described in Appendix 1-9 or Appendix 1-10, for the semiconductor device (1A, 1B, 1C, 1D, 1E).

[0252] [Appendix 1-12] The semiconductor device (1A, 1B, 1C, 1D, 1E) according to Appendix 1-9 or Appendix 1-10, wherein the alloy layers (39, 39C, 39E) include at least one of a CoAl alloy layer (81) and a NiAl layer (82).

[0253] [Appendix 1-13] The alloy layer (39, 39C, 39E) has a layer thickness (T1) of 500 Å or less, as described in any one of Appendix 1-1 to 1-12, semiconductor device (1A, 1B, 1C, 1D, 1E).

[0254] [Note 1-14] The semiconductor device described in Note 1-13 (1A, 1B, 1C, 1D, 1E), wherein the layer thickness (T1) is 200 Å or less.

[0255] [Note 1-15] The semiconductor device described in Note 1-14 (1A, 1B, 1C, 1D, 1E), wherein the layer thickness (T1) is 100 Å or less.

[0256] [Appendix 1-16] The metal electrodes (16, 16B, 16C, 16E) have an electrode thickness (T2) of 4 μm or more, as described in any one of Appendix 1-1 to 1-15, semiconductor device (1A, 1B, 1C, 1D, 1E).

[0257] [Appendix 1-17] The semiconductor device (1A, 1B, 1C, 1D, 1E) described in any one of Appendix 1-1 to 1-16, wherein the thickness ratio (T1 / T2) of the layer thickness (T1) of the alloy layer (39, 39C, 39E) to the electrode thickness (T2) of the metal electrode (16, 16B, 16C, 16E) is 1 / 100 or less.

[0258] [Appendix 1-18] The organic insulating film (30) comprises polyimide or polyamide, as described in any one of Appendix 1-1 to 1-17, for the semiconductor device (1A, 1B, 1C, 1D, 1E).

[0259] [Appendix 1-19] The metal electrode film (16, 16B, 16C, 16E) is formed of a metallic material containing aluminum, the alloy layer (39, 39C, 39E) includes a TiAl alloy layer (80), and the organic insulating film (30) contains polyimide, as described in any one of Appendix 1-1 to 1-18 (1A, 1B, 1C, 1D, 1E).

[0260] [Appendix 1-20] The chip (2) is a semiconductor device (1A, 1B, 1C, 1D, 1E) as described in any one of Appendix 1-1 to 1-19, including a SiC chip.

[0261] [Appendix 1-21] A semiconductor device (1A, 1B, 1C) according to any one of Appendix 1-1 to 1-20, further comprising a semiconductor region (7) of a first conductivity type formed on the surface layer of the main surface (3), wherein the device structure (Tr) comprises a plurality of planar gate structures (11) having a plurality of gate electrodes (57) arranged in a stripe shape on the main surface (3), and a gate insulating film (56) between the plurality of gate electrodes (57) and the main surface (3), a plurality of body regions (50) of a second conductivity type formed on the surface layer of the semiconductor region (7) and facing the gate electrodes (57), and a source region (51) of a first conductivity type formed on the surface layer of each of the body regions (50).

[0262] [Appendix 1-22] The semiconductor device (1D) according to any one of Appendix 1-1 to 1-20, further comprising a semiconductor region (6) of a first conductivity type formed on the surface of the main surface (3), wherein the device structure (Tr) includes a body region (50) of a second conductivity type formed on the surface of the semiconductor region (6), a source region (51) of a first conductivity type formed on the surface of the body region (50), and a plurality of trench gate structures (200) having a plurality of gate trenches (201) arranged in a stripe pattern that penetrate the source region (51) and the body region (50) and reach the semiconductor region (6), a gate insulating film (203) formed on the inner surface of the plurality of gate trenches (201), and gate electrodes (204) embedded in the plurality of gate trenches (201) via the gate insulating film (203).

[0263] [Appendix 1-23] A semiconductor device (1E) according to any one of Appendix 1-1 to 1-20, further comprising a semiconductor region (6) of a first conductivity type formed on the surface of the main surface (3), wherein the device structure (Tr) includes a Schottky barrier diode (300) comprising a second conductivity type anode region (301) formed on the surface of the semiconductor region (6), and a Schottky electrode (304) Schottky bonded to the anode region (301).

[0264] 1A...Semiconductor device, 1B...Semiconductor device, 1C...Semiconductor device, 1D...Semiconductor device, 1E...Semiconductor device, 2...Chip, 3...First main surface, 4...Second main surface, 5A...First side surface, 5B...Second side surface, 5C...Third side surface, 5D...Fourth side surface, 6...First semiconductor region, 7...Second semiconductor region, 8...Drift region, 9...Active region, 10...Peripheral region, 11...Gate structure, 12...Outer well region, 13...First outer well region, 14...Second outer well region, 15...Interlayer film, 16...Metal electrode, 16B...Metal electrode, 16C...Metal electrode, 16E...Metal electrode, 17...Source metal ,18...Gate metal, 19...Source pad electrode (pad electrode), 20...Source wiring (wiring), 21...First pad section, 22...Second pad section, 23...Third pad section, 24...Gate pad electrode (pad electrode), 25...Gate wiring (wiring), 26...First finger wiring, 27...Second finger wiring, 28...First tip section, 29...Second tip section, 30...Organic insulating film, 31...Gate pad (pad), 32...Gate pad opening (pad opening), 33...First source pad (pad), 34...First source pad opening (pad opening), 35...Second source pad (pad), 3 6...Second source pad opening (pad opening), 37...Third source pad (pad), 38...Third source pad opening (pad opening), 39...Alloy layer, 39C...Alloy layer, 39E...Alloy layer, 40...First pad alloy layer (pad alloy layer), 41...First wiring alloy layer (wiring alloy layer), 42...Second pad alloy layer (pad alloy layer), 43...Second wiring alloy layer (wiring alloy layer), 44...Drain electrode, 45...First alloy opening, 46...Second alloy opening, 47...Third alloy opening, 48...Fourth alloy opening, 50...Body region, 51...Source region, 52...Channel region, 53...Body contact region 55...Gate structure, 56...Gate insulating film, 57...Gate electrode, 58...Source contact opening, 60...Outer contact region, 61...Outer opening, 62...Outer insulating film, 63...Lower electrode layer, 70...Electrode surface, 71...Side wall, 72...Recess, 73...Side wall, 150...Wafer, 151...First wafer main surface, 152...Second wafer main surface, 153...Wafer side, 154...Marker, 155...Device region, 156...Cutting line, 160...Base insulating film, 165...Alloy base film, 166...Mask for alloy formation, 200...Gate structure, 201...Gate trench, 202...Mesa region,203...Gate insulating film, 204...Gate electrode, 300...Schottky barrier diode, 301...Guard region (anode region), 303...Contact aperture, 304...Anode electrode (Schottky electrode, pad electrode), 305...Anode aperture, 306...Anode pad, 307...Anode alloy layer, 308...Fifth alloy aperture, 309...Cathode electrode, C...Corner, C1...Corner, T1...Layer thickness, T2...Electrode thickness, Tr...Transistor structure (device structure), UC...Unit cell, X...First direction, Y...Second direction, Z...Vertical direction

Claims

1. A semiconductor device comprising: a chip having a main surface; a device structure formed on the main surface; a metal electrode covering the main surface; an alloy layer covering the metal electrode; and an organic insulating film covering the metal electrode with the alloy layer in between.

2. The semiconductor device according to claim 1, further comprising: an active region provided in the inner part of the main surface on which the device structure is formed; and an outer peripheral region provided in the peripheral part of the main surface and surrounding the active region, wherein the metal electrode includes a pad electrode and wiring electrically connected to the pad electrode and formed on the outer peripheral region, and the alloy layer includes a wiring alloy layer covering the wiring.

3. The semiconductor device according to claim 2, wherein the wiring is formed in a strip shape so as to surround the periphery of the active region in a plan view, and the wiring alloy layer covers the wiring over the entire area in the direction in which the wiring extends.

4. The semiconductor device according to claim 2 or 3, wherein the alloy layer includes a pad alloy layer that covers the pad electrode.

5. The semiconductor device according to claim 4, wherein the pad electrode is formed in a polygonal shape in a plan view, and the pad alloy layer covers at least the peripheral edge of the pad electrode.

6. The semiconductor device according to claim 4 or 5, wherein the organic insulating film has a pad opening that exposes the pad electrode as a pad, and the pad alloy layer has an alloy pad opening in a region corresponding to the pad opening that exposes the pad electrode as a pad.

7. The semiconductor device according to any one of claims 2 to 6, wherein the pad electrode includes a source pad electrode, and the wiring includes a source wiring.

8. The semiconductor device according to any one of claims 1 to 7, wherein the metal electrode has an electrode surface and a side wall, and the alloy layer is formed to span both the electrode surface and the side wall.

9. The semiconductor device according to any one of claims 1 to 8, wherein the metal electrode is formed of a metallic material including aluminum, and the alloy layer includes an aluminum alloy layer.

10. The semiconductor device according to claim 9, wherein the metal electrode has a single-layer structure of the metal material including aluminum.

11. The semiconductor device according to claim 9 or 10, wherein the alloy layer includes a TiAl alloy layer.

12. The semiconductor device according to claim 9 or 10, wherein the alloy layer comprises at least one of a CoAl alloy layer and a NiAl layer.

13. The semiconductor device according to any one of claims 1 to 12, wherein the alloy layer has a layer thickness of 500 Å or less.

14. The semiconductor device according to claim 13, wherein the layer thickness is 200 Å or less.

15. The semiconductor device according to claim 14, wherein the layer thickness is 100 Å or less.

16. The semiconductor device according to any one of claims 1 to 15, wherein the metal electrode has an electrode thickness of 4 μm or more.

17. The semiconductor device according to any one of claims 1 to 16, wherein the thickness ratio of the layer thickness of the alloy layer to the electrode thickness of the metal electrode is 1 / 100 or less.

18. The semiconductor device according to any one of claims 1 to 17, wherein the organic insulating film comprises polyimide or polyamide.

19. The semiconductor device according to any one of claims 1 to 18, wherein the metal electrode is formed of a metallic material containing aluminum, the alloy layer includes a TiAl alloy layer, and the organic insulating film contains polyimide.

20. The semiconductor device according to any one of claims 1 to 19, wherein the chip includes a SiC chip.

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