Instruction execution method and apparatus

Abstract

Provided in the embodiments of the present disclosure are an instruction execution method and an apparatus. The method comprises: on the basis of the executed current instruction, determining a first instruction address of the next instruction and acquiring a second instruction address of the next instruction; on the basis of the first instruction address, the second instruction address and an instruction key state table, determining the instruction state of the next instruction, the instruction key state table comprising a group of instruction addresses and key instruction flags corresponding to the group of instruction addresses, and the key instruction flags being used for indicating whether instructions stored in respective instruction addresses in the group of instruction addresses are key instructions; and, when the instruction state of the next instruction indicates that the next instruction is a key instruction, recording the next instruction in a first instruction queue different from a second instruction queue, the execution priority of instructions in the first instruction queue being higher than the execution priority of instructions in the second instruction queue, and the first instruction queue and the second instruction queue being used for recording instructions to be executed.

Description

Instruction execution method and apparatus

[0001] Cross-reference to Related Applications

[0002] The present disclosure is based on Chinese Patent Application No. CN202411304130.4 entitled “Instruction execution method and apparatus” filed on September 18, 2024, and claiming priority to the same, the disclosure of which is incorporated herein by reference in its entirety. TECHNICAL FIELD

[0003] Embodiments of the present disclosure relate to the field of computer technology, in particular to an instruction execution method and apparatus. BACKGROUND

[0004] In the network packet processing scenario, the instruction queue of the common processing engine is in and out in the form of instruction packets. This method cannot flexibly change the execution order of instructions. At the same time, due to the lack of consideration of the dependency relationship between instructions and the factors such as memory access waiting, the processing engine also lacks the ability to analyze and select the transmission of the critical path of the fixed program flow, which easily causes the execution stage module in the processing engine to enter stagnation, and reduces the performance of the processing engine. In addition, the branch predictor of the existing processing engine is mostly through table lookup hash logic and multi-level table items to make different behavior patterns of branches not mixed with each other in the limited branch prediction table items, and make each branch disperse to each branch prediction table item to the maximum extent, and fully utilize all the space of the branch prediction table item. However, such a branch predictor needs a long time of training and does not make use of the scene information, and is difficult to deploy on the processing engine and has poor effect. SUMMARY

[0005] Embodiments of the present disclosure provide an instruction execution method and apparatus to at least solve the problem that the processing engine in the related art cannot flexibly change the execution order of instructions, which reduces the performance of the processing engine.

[0006] According to an embodiment of the present disclosure, an instruction execution method is provided, comprising: determining a first instruction address of a next instruction according to a current instruction being executed, and obtaining a second instruction address of the next instruction; determining an instruction state of the next instruction according to the first instruction address, the second instruction address, and an instruction critical state table, wherein the instruction critical state table is used to determine a critical instruction through a critical instruction flag associated with an instruction; determining that the next instruction is a critical instruction based on the instruction state of the next instruction, and recording the next instruction into an instruction queue for priority execution.

[0007] According to another embodiment of the present disclosure, there is provided an instruction execution apparatus, comprising: an obtaining module configured to determine a first instruction address of a next instruction according to a current instruction being executed, and obtain a second instruction address of the next instruction; a determining module configured to determine an instruction state of the next instruction according to the first instruction address, the second instruction address, and an instruction key state table, wherein the instruction key state table is used to determine a key instruction by a key instruction flag stored in association with an instruction; and a recording module configured to record the next instruction into an instruction queue for priority execution based on the instruction state of the next instruction.

[0008] According to yet another embodiment of the present disclosure, there is also provided a computer readable storage medium having a computer program stored therein, wherein the computer program is configured to perform the steps of any of the method embodiments described above when executed.

[0009] According to yet another embodiment of the present disclosure, there is also provided an electronic device comprising a memory having a computer program stored therein and a processor configured to execute the computer program to perform the steps of any of the method embodiments described above.

[0010] According to yet another embodiment of the present disclosure, there is also provided a computer program product comprising a computer program configured to perform the steps of any of the method embodiments described above when executed by a processor. BRIEF DESCRIPTION OF DRAWINGS

[0011] Fig. 1 is a hardware structure block diagram of a computer terminal running the method embodiments of the present disclosure;

[0012] Fig. 2 is a schematic diagram of a processing engine network architecture according to an embodiment of the present disclosure;

[0013] Fig. 3 is a flow chart of an instruction execution method according to an embodiment of the present disclosure;

[0014] Fig. 4 is a schematic diagram of branch target table predicting an instruction address according to an embodiment of the present disclosure;

[0015] Fig. 5 is a schematic diagram of an instruction key state table determining an instruction state according to an embodiment of the present disclosure;

[0016] Fig. 6 is a flow chart of a scene recognition based instruction address predicting method according to an embodiment of the present disclosure;

[0017] Fig. 7 is a structure block diagram of an instruction execution apparatus according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0018] Embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings and in conjunction with embodiments.

[0019] It should be noted that the terms "first", "second", and the like in the description and claims of the present disclosure and the above drawings are used to distinguish similar objects, and do not necessarily indicate a specific order or sequence.

[0020] The method embodiments provided in the embodiments of the present disclosure can be executed in a mobile terminal, a computer terminal or similar computing device. Taking the case of running on a computer terminal, Fig. 1 is a hardware structure block diagram of a computer terminal running the method embodiments of the present disclosure. As shown in Fig. 1, the computer terminal can include one or more (only one is shown in Fig. 1) processors 102 (the processor 102 can include but not limited to a processing device such as a microprocessor MCU or a programmable logic device FPGA) and a memory 104 for storing data, wherein the above computer terminal can further include a transmission device 106 for communication function and an input and output device 108. Those skilled in the art can understand that the structure shown in Fig. 1 is only schematic, which does not limit the structure of the above computer terminal. For example, the computer terminal can further include more or less components than those shown in Fig. 1, or have a different configuration from that shown in Fig. 1.

[0021] The memory 104 can be used to store computer programs, for example, software programs of application software and modules, such as the computer program corresponding to the instruction execution method in the embodiments of the present disclosure, and the processor 102 executes various functional applications and data processing by running the computer program stored in the memory 104, that is, implements the above method. The memory 104 can include a high-speed random access memory, and can also include a non-volatile memory, such as one or more magnetic storage devices, flash memories, or other non-volatile solid-state memories. In some examples, the memory 104 can further include a memory remotely arranged with respect to the processor 102, which can be connected to the computer terminal through a network. Examples of the above network include but are not limited to the Internet, an intranet, a local area network, a mobile communication network, and a combination thereof.

[0022] The transmission device 106 is used to receive or send data via a network. The specific examples of the above network can include a wireless network provided by a communication provider of the computer terminal. In one example, the transmission device 106 includes a network adapter (Network Interface Controller, NIC for short), which can be connected to other network devices through a base station so as to communicate with the Internet. In one example, the transmission device 106 can be a radio frequency (Radio Frequency, RF for short) module, which is used to communicate with the Internet in a wireless manner.

[0023] The embodiments of the present disclosure relate to a novel processing engine design in the network packet processing scenario, wherein the network packet refers to the basic unit of data transmission in the computer network, usually containing source address, target address, data content and other information; the processing engine is a component in the network device responsible for processing network packets, including functions such as analysis, analysis and forwarding of network packets.

[0024] The processing engine in the embodiments of the present disclosure mainly relates to branch predictor design and instruction queue design. Among them, the design of the branch predictor includes: dividing the branch predictor into blocks, and combining the user-configurable lookup table technology of the scene identifier, so that the branch prediction results in different scenarios do not interfere with each other, wherein the branch predictor is divided into blocks, that is, the branch predictor is divided into a branch history table and a branch target table, so that the prediction of instruction addresses is divided into address prediction and jump prediction, thereby improving the branch prediction accuracy in each scenario and improving the performance of the processing engine. The instruction queue design includes memory critical path selection technology and instruction bypass technology, which makes the critical instructions of the memory path be dispatched and executed in priority through the memory critical path selection technology and the instruction bypass technology, reduces the pipeline blocking caused by memory, improves the utilization rate of the execution stage module in the processing engine, and thus improves the performance of the processing engine. Among them, the execution stage at least includes: branch jump module, logic operation module, memory module.

[0025] The processing engine of the embodiments of the present disclosure is a dual-emission processor, which includes three main parts: a processing engine basic part, a configurable scene identification branch predictor, and a key program flow execution module. Among them, the processing engine basic part is a component possessed by a general processing engine, and the configurable scene identification branch predictor and the key program flow execution module involve newly added components of the embodiments of the present disclosure. Specifically, the modules / units specifically contained in the three main parts are shown in Table 1.

[0026] Table 1

[0027] FIG. 2 is a schematic diagram of the network architecture of the processing engine according to the embodiments of the present disclosure. As can be known from Table 1, the processing engine basic part includes an instruction fetch module (IF), a decoding module (ID), a renaming module (IR), a regular instruction queue (A-IQ), a branch jump module (BJU), a logic operation module (ALU), a machine state register management module (CSR), a memory module (LSU), an instruction submission module (IC), a branch history table (BHT).

[0028] The instruction fetch module is mainly responsible for fetching instructions from memory and providing correct operation codes for the subsequent instruction execution stage. The instruction address of the current instruction to be predicted is determined according to the results of the branch jump module, the branch prediction results, and the instruction address increment value of the previous instruction. The instruction address of the current instruction to be predicted is selected from the branch jump module results and the branch prediction results in priority. If the instruction address of the current instruction to be predicted cannot be selected, the instruction address increment value of the previous instruction is selected as the instruction address of the current instruction to be predicted.

[0029] In one embodiment, the instructions used by the processing engine are 4 byte wide and the normal instruction fetch width per cycle is 2, so the instruction address increment value of each instruction is 8.

[0030] In one embodiment, the determined instruction address of the previous instruction to be predicted needs to be sent to the branch target table, the branch history table, the instruction key state table, and the instruction cache.

[0031] The decode module is responsible for decoding the operation code of the instruction into control information required for executing the corresponding operation. The instruction returned by the instruction cache is obtained, and according to the encoding format and operation code field of the instruction, the decoding logic can determine what type of instruction the instruction is, such as arithmetic instruction, logic instruction, branch instruction, etc. According to the type and operand of the instruction, the corresponding operation control signal is generated. These signals guide the operation of the subsequent stage, for example, the selection of the arithmetic logic unit in the execution stage, the memory operation type in the memory stage, etc.

[0032] The renaming module is responsible for adding a renaming tag to the source register of the instruction to distinguish the writing of the same logical register by adjacent instructions. The source operand of the instruction is identified and the renaming table is queried, and then the tag in the table is spliced with the source operand to form a renaming identification code and sent to the regular instruction queue or the bypass queue. Whether the data corresponding to the source operand in the renaming table is available is read out, and if available, a read source operand request is sent to the register file, which provides the register value to the regular instruction queue and the bypass queue in the next instruction execution cycle. The key state bit of each instruction is identified to determine which queue to put in, for example: instructions with an empty state will be randomly placed in the regular instruction queue or the bypass queue; instructions with a non-key state will be placed in the regular instruction queue; instructions with a key state will be placed in the bypass queue.

[0033] The conventional instruction queue is a module for determining whether an instruction can be executed and dispatching the instruction into a corresponding execution stage module (hereinafter referred to as "firing" the instruction into the corresponding execution stage). The conventional instruction queue (hereinafter referred to as "the queue") stores source register values of each instruction and sends the register values to an execution unit of the corresponding execution stage module when the instruction is fired. The queue is designed in the same way as a FIFO, and only the first instruction (hereinafter referred to as "the head instruction") can be fired. The head instruction can be fired only when both source register data are available. When the head instruction has source register data that is not available, the subsequent instructions in the queue cannot be fired. The module matches the renaming identification code returned by the instruction submission module and the renaming identification code of all instructions in each instruction execution cycle, and if they are the same, the corresponding data is stored in the queue and the source register data is marked as available.

[0034] The branch jump module is a logic for determining whether the source register of an instruction satisfies a branch condition and calculating a jump address. The module is one of the execution units, which determines whether the source register satisfies the corresponding branch condition according to the operation code, and calculates the jump address according to the instruction register or the immediate number information. If the condition is satisfied, the module sends a jump signal and the jump address to the instruction fetch stage, the branch target table, and the branch history table.

[0035] The logic operation module is a logic for determining whether the source register of an instruction satisfies a branch condition and calculating a jump address. The module is one of the execution units, which determines the logic operation to be performed according to the operation code, and performs the operation on the source register data or the immediate number, and then transmits the result to the next pipeline until the instruction submission module.

[0036] The machine state register management module is a logic unit for managing reading and writing of machine state registers, controlling WFI determination, and processing interrupt signals. When the module receives an instruction to access a machine state register, it reads and writes the corresponding machine state register according to the operation code. When the module receives a WFI instruction, it turns off the power of the logic except the register file, the branch predictor, and the csr logic. After receiving the WFI instruction, the module turns off the power of all pipeline registers and all stages of the pipeline to save power consumption. The logic retains the power of the register file to avoid losing execution information; retains the power of the branch predictor to quickly restore the branch prediction function and improve performance when the wake-up signal arrives; and retains the csr logic to process the wake-up signal. When an interrupt signal arrives in the WFI state, the module reads the mcause value transmitted from the outside according to the agreed protocol and stores it in the mcause register. Then, the module turns on the power of the processor, transmits the value of mtvec to the instruction fetch stage, and becomes a new instruction fetch PC, so that the instruction fetch stage can start fetching instructions from the address pointed by mtvec, thereby entering the interrupt processing function and starting the processor to execute a new task.

[0037] The memory access module includes two key aspects of memory access logic arbitration and memory control designed for the processing engine. The arbitration process ensures that the access request of the processing engine is correctly routed to the target unit (DATA RAM, Ingress Unit or Egress Unit), avoiding conflicts through address resolution and priority decision. Among the memory-related functions, the Load-Store Unit (LSU) is responsible for managing and controlling access to the DATA RAM, including address calculation, data transfer, error handling and performance optimization. The interaction with the Ingress Unit adopts a single read handshake protocol, and the efficient processing engine wake-up and data transfer are realized through the EN signal and data transmission. The interaction with the Egress Unit adopts a DMA burst transmission protocol, and the data transmission rate is adjusted through the en signal and credit counter, while handling abnormal situations. The global time counter is used to record the system running time, and the addresses of various peripherals can be configured according to the requirements. Overall, these designs ensure the effective memory access operation of the processing engine to different units, and improve the system performance and data transmission efficiency.

[0038] The instruction commit module is the logic that processes the execution unit results and writes them back to the register file. It writes the results of the execution unit execution into the logical registers specified by the corresponding instructions and broadcasts the renaming identification code and the results to the instruction queue.

[0039] The branch history table is a logic that stores the branch jump conditions and makes branch jump condition predictions for the fetch address. It is a 128-entry table; it uses the instruction address XOR global branch history index, which stores a 2-bit saturation counter, and takes the high bit as the jump decision. If it is 1, it is predicted to jump, and if it is 0, it is predicted not to jump. The branch history table will judge whether the predicted jump result (whether to jump) and the jump result returned by the execution stage are the same, and whether the saturation counter has been saturated. If it is saturated and the same, it does not need to be updated, otherwise the saturation counter of the corresponding table entry is updated.

[0040] As shown in Table 1, the configurable scenario identification branch predictor includes a branch target table (BTB), a user configuration unit (BTB Ctrl), and an exception cause register (Mcause).

[0041] Branch target buffer is a logic that stores branch target and makes branch target prediction for instruction fetch address. Branch target buffer is n tables, n is a value that can be configured by designer. It uses the comparison result from user configuration unit to select the corresponding table. The Kth bit of the comparison result is high, then the Kth table is selected. If multiple bits are high, multiple tables are selected. The table uses the low eight bits of instruction fetch address as index, and stores the high bits of instruction fetch address as tag and branch offset. When tag matches, the offset and current instruction fetch address are added to get the instruction fetch address of next cycle. If tag does not match, it is considered that branch target buffer is missing. Branch target buffer will judge whether the predicted jump target address and the result of the corresponding instruction returned by execution stage are the same. If they are different, the table entry is updated. When updating, only the table corresponding to the high Boolean vector is updated, and the table entry corresponding to the instruction address index returned by the branch module is matched with the tag. If they match, the corresponding table entry is updated. If there is no matching table entry, the corresponding table entry in any table is updated randomly.

[0042] User configuration unit is a logic that processes and stores user configuration information, and selects the corresponding branch target buffer combined with configuration information and exception cause register. It has a configuration table with n table entries, and each table entry stores a user configuration value. User can configure this configuration unit through a self-defined ucbr instruction. The ucbr instruction has two source operands, the first source operand corresponds to a branch target buffer entry, and the second source operand corresponds to a configuration value. This instruction is considered as a write machine state register instruction and is executed in the machine state register management module. When it is executed, it will write the value of the second source operand to the table entry specified by the first source operand. Every cycle, it reads the value of the exception cause register and compares it with the data in all configuration tables. The comparison result is sent to the branch target buffer in the form of a Boolean vector, where the Kth bit is high, which means that the value of table entry K is the same as the value of the exception cause register.

[0043] Exception cause register is a register in machine state register. Since its function is closely related to this patent, it is listed separately. This register is configured by interrupt source. When an interrupt signal arrives, it is written into this register through the interrupt port. The machine state register management module can also read and write this register. The value of this register is read by the subsequent program processing function, and the corresponding program processing function is jumped to according to the value, so the value of this register can be regarded as a scene identifier. The value of this register is sent to the user configuration unit every cycle.

[0044] As shown in Table 1, the critical program flow execution module includes instruction critical state table (CIT), register dependency table (RDT), and bypass queue (B-IQ).

[0045] The instruction critical state table is a table for storing critical path instruction information. The same index strategy as the instruction cache is used, and the high bits of the instruction address are stored as a tag. However, if the instruction cache uses a group connection strategy, the tag and index required for cache access are combined into a tag for table entry query. The content is a critical vector composed of whether all instructions in this cache line are critical. If the Kth bit of the critical vector is high, it means that the Kth instruction in this cache line is a critical instruction. When the instruction fetch module queries the instruction cache, the address will also be sent to the instruction critical state table for tag matching. If the corresponding table entry is matched, the critical vector is extracted. If the table lookup fails, the instruction is in an "empty state", that is, it cannot be determined whether it is critical or not; if the table lookup is successful, the critical / non-critical state is determined according to the value of the critical vector. The instruction critical state table transmits the above information to the renaming module to help it dispatch the corresponding instructions to the corresponding queue. The instruction critical state table collects the critical information of new instructions from the register dependency table every cycle, and uses the high bits of the instruction address to query the corresponding table entry and update the corresponding bits using the low bits of the address.

[0046] The register dependency table is a logic for collecting register dependency relationships and critical instruction information. It has a table entry number equal to the number of logical registers, and the table entry records the address of the instruction last written into the corresponding logical register. Each instruction will write its instruction address into the table entry corresponding to its destination register when it is renamed. If a critical instruction is encountered during renaming, the instruction address in the source register table entry is transmitted back to the instruction critical state table.

[0047] The bypass queue has the same structure as the regular instruction queue. However, when the transmission of instructions in the bypass queue and the transmission of instructions in the regular instruction queue compete for resources, the transmission port will preferentially select the instructions in the bypass queue for transmission.

[0048] In the embodiment, an instruction execution method running on the above computer terminal or processing engine is provided. In the method, the determination method of the instruction address includes: generating an instruction address by a branch jump module in the processing engine according to a current instruction; generating an instruction address by a branch target table prediction in the processing engine; and generating an instruction address by a value fetch module according to an instruction address increment value.

[0049] FIG. 3 is a flowchart of an instruction execution method according to an embodiment of the present disclosure. As shown in FIG. 3, the flow includes the following steps:

[0050] In step S302, a first instruction address of a next instruction is determined according to a current instruction executed, and a second instruction address of the next instruction is obtained.

[0051] In the embodiment, the first instruction address is determined by the branch jump module according to the current instruction, and the second instruction address is predicted by the branch target table in advance. The branch target table includes labels and address offsets in a corresponding relationship.

[0052] In an example embodiment, the branch jump module calculates the instruction address of the next instruction, i.e., the first instruction address, according to the instruction register or the immediate number information of the current instruction.

[0053] In step S302 of the embodiment, before obtaining the second instruction address of the next instruction, the method further includes: determining a branch target table and a branch history table corresponding to a scene represented by the pre-obtained scene identifier, wherein the branch target table includes first labels and address offsets in a corresponding relationship; and the branch history table includes second labels and jump identifiers in a corresponding relationship, the jump identifier being used to indicate whether to jump to the instruction address of the next instruction of the instruction corresponding to the second label.

[0054] In an embodiment, in the case that the current instruction is the first instruction of a task and the next instruction is the second instruction of the task, obtaining the second instruction address of the next instruction, the method further includes: the processing engine receives an interrupt signal sent externally for indicating the start of the task and a scene identifier, and writes the scene identifier into the Mcause buffer according to the interrupt signal; selects a corresponding branch target table through the scene identifier, predicts the instruction address of the first instruction of the task through the corresponding branch target table according to the configured initial instruction address, and predicts the instruction address of the second instruction of the task (i.e., the second instruction address of the next instruction) according to the predicted instruction address of the first instruction.

[0055] The scene identifier can be used to determine the instruction address corresponding to the scene identifier. Therefore, when the branch predictor performs instruction address prediction, the identification code of different scenes can be recognized and compared with the allocation registers in different storage units. If they are the same, the corresponding branch predictor storage unit (including the branch target table and the branch history table) is called to use the branch prediction result trained in the current scene for prediction, thereby reducing the aliasing phenomenon of branch prediction in different scenes and improving the branch prediction accuracy.

[0056] In an embodiment, in the case that the current instruction is the Nth instruction of a task and the next instruction is the (N+1)th instruction of the task, obtaining the second instruction address of the next instruction, the method further includes: the processing engine selects a corresponding branch target table through the scene identifier, and predicts the instruction address of the (N+1)th instruction (i.e., the second instruction address of the next instruction) through the corresponding branch target table according to the instruction address of the Nth instruction. N is a positive integer greater than 1.

[0057] In the embodiment, before predicting the second instruction address of the next instruction, the first instruction address and the second instruction address are matched in executing the current instruction, and only when the matching is successful, the instruction address of the next instruction is determined according to the instruction address of the current instruction. The matching success conditions include that the first instruction address is the same as the second instruction address, and the jump identifier corresponding to the second instruction address indicates a jump.

[0058] In one embodiment, the second instruction address of the next instruction is obtained, including: predicting the instruction address of the next instruction according to the instruction address of the current instruction and the branch target table, and determining the predicted instruction address as the second instruction address; determining the jump identifier corresponding to the second instruction address according to the instruction address of the current instruction and the branch history table.

[0059] FIG. 4 is a schematic diagram of predicting an instruction address by a branch target table according to an embodiment of the present disclosure. As shown in FIG. 4, the processing engine receives the scene identifier "2" as written in Mcause, the user configuration unit selects the corresponding branch target table from the plurality of branch targets in the processing engine according to the stored user configuration information and in combination with the scene identifier "2", then indexes the corresponding table item from the corresponding branch target table according to the address low bit of the instruction address of the current instruction, and then matches the address high bit of the instruction address of the current instruction with the tag recorded in the corresponding table item. When the matching is successful, the instruction address of the next instruction, i.e. the second instruction address, is predicted according to the instruction address of the current instruction and the address offset.

[0060] In the embodiment, for the focus scene which is more important to the user, more branch target tables and branch history tables can be allocated to the focus scene to improve the branch storage capacity of the focus scene, so that more branch information can be stored and recognized, and the branch prediction accuracy is improved.

[0061] In step S304, the instruction state of the next instruction is determined according to the first instruction address, the second instruction address and the instruction key state table, wherein the instruction key state table is used to determine a key instruction by a key instruction flag associated with the instruction.

[0062] In step S304 of the embodiment, the instruction state of the next instruction is determined according to the first instruction address, the second instruction address, and the instruction key state table; in the case that the first instruction address is the same as the second instruction address and the jump identifier corresponding to the second instruction address indicates a jump, the instruction state of the next instruction is determined in the instruction key state table according to the second instruction address; or in the case that the first instruction address is the same as the second instruction address and the jump identifier corresponding to the second instruction address indicates a non-jump, the instruction state of the next instruction is determined in the instruction key state table according to the first instruction address; or in the case that the first instruction address is not the same as the second instruction address, the instruction state of the next instruction is determined in the instruction key state table according to the first instruction address.

[0063] In one embodiment, when the current instruction is located in the branch jump module, the branch jump module matches the first instruction address determined according to the current instruction and the second instruction address predicted in advance, and combines the jump identifier of the corresponding second instruction address, in the case that the first instruction address is the same as the second instruction address and the jump identifier corresponding to the second instruction address indicates a jump, the second instruction address is determined as the instruction address of the next instruction, the second instruction address is sent to the instruction key state table to determine the instruction state of the next instruction, and the second instruction address is sent to the branch target table and the branch history table for prediction of subsequent instructions; or in the case that the first instruction address is the same as the second instruction address but the jump identifier corresponding to the second instruction address indicates a non-jump, the first instruction address is determined as the instruction address of the next instruction, the first instruction address is sent to the instruction key state table to determine the instruction state of the next instruction, and the first instruction address is sent to the branch target table and the branch history table for prediction of subsequent instructions; or in the case that the first instruction address is not the same as the second instruction address, the first instruction address is determined as the instruction address of the next instruction, the first instruction address is sent to the instruction key state table to determine the instruction state of the next instruction, and the first instruction address is sent to the branch target table and the branch history table for prediction of subsequent instructions.

[0064] In one embodiment, determining the instruction state of the next instruction according to the first instruction address, the second instruction address, and the instruction key state table comprises: acquiring a key vector corresponding to the next instruction from the instruction key state table according to the first m bits (i.e. high bits of the instruction address) of the first instruction address or the second instruction address; and determining the instruction state of the next instruction from the key vector according to the last m bits (i.e. low bits of the instruction address) of the first instruction address or the second instruction address, wherein m is a positive integer and the number of bits of the instruction address of the next instruction is 2m.

[0065] Figure 5 is a schematic diagram of determining instruction state of an instruction key state table according to an embodiment of the present disclosure. As shown in Figure 5, the high bits of the instruction address of the current instruction are stored as tagl, tagl is matched with tag2 stored in the key state table, and a key vector (i.e. the horizontally framed part in Figure 5) with tagl = tag2 is selected from the key state table, wherein the key vector is a set of binary numbers, and each binary number of the key vector represents a key instruction identifier of an instruction; the corresponding key instruction identifier is indexed from the key vector according to the low bits of the instruction address of the current instruction; for example, if the low bits of the instruction address of the current instruction are converted into a decimal number as 3, the third binary number of the key vector is indexed, and if the third binary number is 1, it means that the current instruction is a key instruction.

[0066] In one embodiment, in the case that the current instruction is determined as a key instruction, the current instruction is recorded into the bypass queue B-IQ (i.e. the first instruction queue), and the execution stage module preferentially selects the instructions in the bypass queue B-IQ for execution; in the case that the current instruction is determined as a non-key instruction, the current instruction is recorded into the regular instruction queue A-IQ (i.e. the second instruction queue); in the case that the current instruction is determined as an empty state, the current instruction is recorded into the bypass queue B-IQ or the regular instruction queue A-IQ.

[0067] In one embodiment, after the instruction state of the current instruction is determined, the instruction state of the current instruction is sent to the renaming module as instruction information, and the decoding module sends the source register 1 and the source register 2 determined according to the current instruction to the renaming module as instruction information; if the current instruction is a key instruction, the renaming module queries the register dependency table according to the received instruction state of the current instruction and the source register 1 and the source register 2 corresponding to the current instruction, determines the instruction 1 and the instruction 2 dependent on the source register 1 and the source register 2, and updates the instruction 1 and the instruction 2 in the key state table as key instructions; similarly, if the instruction state of the current instruction is a non-key instruction, the instruction 1 and the instruction 2 in the key state table are updated as non-key instructions.

[0068] In one embodiment, the memory module encountering a long-latency memory instruction also transmits the corresponding instruction address to the instruction key state table, updates the corresponding instruction in the instruction key state table as a key instruction, so as to preferentially execute through the bypass queue in the next execution of the long-latency memory instruction, thereby avoiding long delay.

[0069] In step S306, it is determined that the next instruction is a key instruction based on the instruction state of the next instruction, and the next instruction is recorded into the instruction queue for preferential execution.

[0070] In one embodiment, the next instruction is recorded into the first instruction queue if the instruction status of the next instruction indicates that the next instruction is a critical instruction; the next instruction is recorded into the second instruction queue if the instruction status of the next instruction indicates that the next instruction is a non-critical instruction; wherein the execution priority of the first instruction queue is higher than the execution priority of the second instruction queue, and the first instruction queue and the second instruction queue are used to record instructions to be executed.

[0071] In one embodiment, the branch target table and the branch history table predict an instruction address of a target instruction while an execution stage module executes a current instruction, wherein the target instruction is an instruction after the current instruction, and a plurality of instructions are included between the target instruction and the current instruction; therefore, the method further comprises: when the first instruction address is the same as the second instruction address, and a jump identifier corresponding to the second instruction address indicates a jump according to the branch history table, predicting the instruction address of the target instruction according to a first manner based on an instruction address of a previous instruction of the target instruction, wherein the first manner is a manner of obtaining the predicted instruction address of the target instruction.

[0072] In one exemplary embodiment, the branch target table and the branch history table predict an instruction address of an (N+x)th instruction while an execution stage module executes an Nth instruction, wherein x is an integer greater than 1.

[0073] In one exemplary embodiment, when the execution stage module determines that a first instruction address of an (N+1)th instruction does not match a second instruction address of the (N+1)th instruction, the predicted instruction addresses of the (N+1)th instruction to an (N+x)th instruction are reset and the instruction addresses of the (N+1)th instruction to the (N+x)th instruction are re-predicted, wherein the first instruction address of the (N+1)th instruction is determined by the branch prediction module based on the Nth instruction, and the second instruction address of the (N+1)th instruction is predicted by the branch target table based on the Nth instruction.

[0074] In one example embodiment, when the execution stage module determines that the first instruction address of the N+1 instruction is not the same as the second instruction address of the N+1 instruction, the instruction addresses of the N+1 instruction to the N+x instruction are re-predicted, including: sending the first instruction address of the N+1 instruction to the instruction fetch module, so that the first instruction address of the N+1 instruction is taken as the actual instruction address of the N+1 instruction, and the corresponding instruction is obtained from the instruction cache, so that the instruction is sent to the decode module, and then the execution stage module executes the instruction; at the same time, the first instruction address of the N+1 instruction is sent to the branch target table and the branch history table, the instruction address of the N+2 instruction is predicted through the branch target table and the branch history table according to the first instruction address of the N+1 instruction, and the instruction addresses of the N+2 to N+x instructions are re-predicted in the same way as the instruction address of the N+2 instruction is generated.

[0075] In one example embodiment, when the execution stage module determines that the first instruction address of the N+1 instruction is the same as the second instruction address of the N+1 instruction, and the jump corresponding to the N+1 instruction is a jump, the instruction addresses of the N+1 instruction to the N+x instruction are re-predicted, including: sending the second instruction address of the N+1 instruction to the instruction fetch module, so that the second instruction address of the N+1 instruction is taken as the actual instruction address of the N+1 instruction, and the corresponding instruction is obtained from the instruction cache, so that the instruction is sent to the decode module, and then the execution stage module executes the instruction; at the same time, the second instruction address of the N+1 instruction is sent to the branch target table and the branch history table, the instruction address of the N+2 instruction is predicted through the branch target table and the branch history table according to the second instruction address of the N+1 instruction, and the instruction addresses of the N+2 to N+x instructions are re-predicted in the same way as the instruction address of the N+2 instruction is generated.

[0076] In one example embodiment, when the execution stage module determines that the first instruction address of the N+1 instruction is the same as the second instruction address of the N+1 instruction, and the jump corresponding to the N+1 instruction is a non-jump, the instruction addresses of the N+1 instruction to the N+x instruction are re-predicted, including: the actual instruction address of the N+1 instruction is generated according to the instruction address of the N instruction through a second way, and is sent to the instruction fetch module, so that the actual instruction address of the N+1 instruction is obtained from the instruction cache according to the actual instruction address of the N+1 instruction, so that the instruction is sent to the decode module, and then the execution stage module executes the instruction; at the same time, the actual instruction address of the N+1 instruction is sent to the branch target table and the branch history table, the instruction address of the N+2 instruction is predicted through the branch target table and the branch history table according to the actual instruction address of the N+1 instruction, and the instruction addresses of the N+2 to N+x instructions are re-predicted in the same way as the instruction address of the N+2 instruction is generated.

[0077] In one embodiment, the second mode is to determine the instruction address of the next instruction according to the instruction address of the current instruction that has been executed and a preset address increment value.

[0078] In one embodiment, the instruction address of the target instruction is predicted according to the instruction address of the previous instruction of the target instruction and in the first mode, including: in a case where the first tag determined according to the instruction address of the previous instruction of the target instruction is the same as a second tag included in the branch target table and the jump identifier corresponding to the instruction address of the target instruction indicates a jump, determining the instruction address of the target instruction according to the address offset in the branch target table having a corresponding relationship with the second tag and the instruction address of the previous instruction.

[0079] In one embodiment, in a case where the first tag is the same as the second tag included in the branch target table and the jump identifier corresponding to the instruction address of the target instruction indicates no jump, the instruction address of the target instruction is predicted according to the instruction address of the previous instruction of the target instruction and a preset address increment value; or, in a case where the first tag and the tags in the branch target table are all different, the instruction address of the target instruction is determined according to the instruction address of the previous instruction of the target instruction and a preset address increment value.

[0080] FIG. 6 is a flowchart of a method for predicting an instruction address based on scene recognition according to an embodiment of the present disclosure, as shown in FIG. 6, the flow includes the following steps:

[0081] In step S601, a user configures a user configuration unit using a ucbr instruction according to a requirement, and configures more branch history tables and branch target tables for a focus scene than for a normal scene when initializing.

[0082] In step S602, the user configuration unit converts a scene identifier into a Boolean vector according to a corresponding value in the configuration and sends the Boolean vector to a branch target table.

[0083] In step S603, a fetch module sends an instruction address of an Nth instruction to a branch history table and a branch target table.

[0084] In step S604, a corresponding branch target table is selected according to the Boolean vector, and a corresponding table entry of the branch target table corresponding to the address low index of the instruction address of the Nth instruction is selected.

[0085] In step S605, the address high of the instruction address of the Nth instruction is matched with a tag in the corresponding table entry, only the target table entry matching the tag is fetched, and the instruction address of an N+1th instruction is predicted according to an address offset recorded in the target table entry and the instruction address of the Nth instruction.

[0086] Step S606, according to the instruction address of the Nth instruction, the corresponding target table item is taken out from the branch history table, and the high bit of the two-bit saturating counter is used as the predicted jump identifier corresponding to the (N+1)th instruction.

[0087] In one embodiment, in the case that the first instruction address is not the same as the second instruction address, for the instructions after the next instruction, the instruction addresses of the partial instructions after the current instruction are predicted again according to the first instruction address and in a second manner different from the first manner.

[0088] In one embodiment, the second manner is to determine the instruction address of the (M+1)th instruction according to the instruction address of the Mth instruction and a preset address increment value. M is a positive integer greater than or equal to 1.

[0089] In one embodiment, the method further comprises: in the case that the instruction state is the empty state, recording the next instruction into the first instruction queue; or in the case that the instruction state is the empty state, recording the next instruction into the second instruction queue.

[0090] Before step S306 of the embodiment, the method further comprises: the instruction fetching module fetching the corresponding instruction from the instruction cache according to the actual instruction address of the next instruction, and sending the corresponding instruction to the decoding module; the decoding module decoding the operation code of the corresponding instruction into the logic of the control information required for performing the corresponding operation, and sending the decoded instruction to the instruction key state table to determine the instruction state of the next instruction through the instruction key state table, so as to record the next instruction into the corresponding instruction queue according to the instruction state of the next instruction.

[0091] In one embodiment, the decoding module sends the decoded instruction to the instruction key state table and also sends the decoded instruction to the renaming module, and the instruction key state table also sends the instruction state of the next instruction to the renaming module, so that the renaming module renames the source register and the destination register of the next instruction, and writes the renamed source register into the register dependence table according to the source operand information of the next instruction.

[0092] In one embodiment, when the first instruction queue receives the next instruction, it is determined whether the head instruction of the queue can be emitted, and if so, the head instruction is sent to the branch jump module.

[0093] In an example embodiment, after the first instruction queue receives the N+3th instruction, the N+2th instruction at the head is determined to be able to be sent to the branch jump module when the N+2th instruction at the head can be executed, the N+2th instruction is executed through the branch jump module, and the execution result of the N+2th instruction is returned to the branch target table and the branch history table, so that the branch target table and the branch history table are updated according to the execution result of the N+2th instruction.

[0094] In an example embodiment, in a case where the instruction address of the executed N+2th instruction does not correspond to the instruction address of the predicted N+2th instruction, the Boolean vector is determined according to the N+1th instruction, the corresponding branch target table is updated to high according to the Boolean vector, and the table entry matching the tag in the corresponding branch target table according to the instruction address index returned by the branch jump module. If there is a match, the corresponding table entry is updated, and if there is no matching table entry, the corresponding table entry in any table is updated randomly.

[0095] In an example embodiment, in a case where the corresponding jump identifier of the predicted N+2th instruction indicates no jump, the Boolean vector is determined according to the N+1th instruction, the corresponding branch history table is updated to high according to the Boolean vector, and the table entry matching the tag in the corresponding branch history table according to the instruction address index returned by the branch jump module. Then, the value of the saturation counter is reduced by one; otherwise, in a case of jump, the value is increased by one.

[0096] Through the above steps, based on the instruction key state table, the instruction state of the next instruction is determined before the next instruction is executed, so that the next instruction is recorded in the instruction queue for priority execution in a case where the instruction state of the next instruction is a key instruction. In this way, the execution order of the instructions can be flexibly changed, and the execution stage module can be prevented from entering a stall state due to a fixed instruction execution order. Therefore, the problem that the processing engine cannot flexibly change the execution order of the instructions in the related art can be solved, and the performance of the network packet processing engine is improved.

[0097] In the embodiments of the present disclosure, after a certain task ends, that is, after the instructions corresponding to the same scene representation are all executed, the processing engine executes a wait for interrupt (WFI) instruction and enters a low-power consumption state to wait for an interrupt signal.

[0098] Through the above embodiments of the present disclosure, a 64-bit processing engine based on the RISC-V instruction set is implemented, which supports a wide range of functions, including but not limited to the wait for interrupt (WFI) function and the atomswap instruction. This makes the processing engine of the embodiments of the present disclosure meet the conditions of multi-core parallel processing of network packet-related loads, and has certain flexibility and versatility.

[0099] Meanwhile, the processing engine disclosed by the embodiments of the present disclosure is a comprehensive test suite covering functions such as scheduling, waking up, distribution, and testing; it can not only provide comprehensive evaluation means for the robustness of a multi-core system, but also provide a solid foundation for further optimization and upgrading of a network packet processing system.

[0100] Those skilled in the art can clearly understand that the method according to the above embodiments can be realized by means of software and necessary general hardware platforms, of course, it can also be realized by hardware, but in many cases, the former is a better implementation. Based on such understanding, the technical solutions of the present disclosure can be embodied in the form of a software product, which is stored in a storage medium (such as a ROM / RAM, a magnetic disk, or an optical disc) and includes a plurality of instructions for causing a terminal device (which can be a mobile phone, a computer, a server, or a network device) to execute the methods described in the various embodiments of the present disclosure.

[0101] In the embodiments, an instruction execution apparatus is also provided, which is used to implement the above embodiments and preferred embodiments, and will not be described again. As used below, the term "module" can be a combination of software and / or hardware that implements a predetermined function. Although the apparatus described in the following embodiments is preferably implemented in software, hardware, or a combination of software and hardware is also possible and is contemplated.

[0102] FIG. 7 is a structural block diagram of an instruction execution apparatus according to an embodiment of the present disclosure, as shown in FIG. 7, the apparatus includes an obtaining module 710, a determining module 720, and a recording module 730.

[0103] The obtaining module 710 is configured to determine a first instruction address of a next instruction according to a current instruction executed, and obtain a second instruction address of the next instruction;

[0104] The determining module 720 is configured to determine an instruction state of the next instruction according to the first instruction address, the second instruction address, and an instruction key state table, wherein the instruction key state table is used to determine a key instruction by a key instruction flag stored in association with the instruction;

[0105] The recording module 730 is configured to determine that the next instruction is a key instruction based on the instruction state of the next instruction, and record the next instruction into a priority execution instruction queue.

[0106] In one embodiment, the recording module 730 is further configured to record the next instruction into the first instruction queue if the instruction state of the next instruction indicates that the next instruction is a critical instruction, and record the next instruction into the second instruction queue if the instruction state of the next instruction indicates that the next instruction is a non-critical instruction; wherein the execution priority of the first instruction queue is higher than the execution priority of the second instruction queue, and the first instruction queue and the second instruction queue are used to record instructions to be executed.

[0107] It should be noted that the above various modules can be implemented by software or hardware, and for the latter, the following implementation manners can be used, but are not limited thereto: all the above modules are located in the same processor; or the above various modules are located in different processors in any combination.

[0108] Embodiments of the present disclosure further provide a computer readable storage medium, which stores a computer program, and the computer program is configured to execute the steps in any of the above method embodiments when running.

[0109] In one exemplary embodiment, the above computer readable storage medium can include, but is not limited to, a U disk, a read-only memory (ROM), a random access memory (RAM), a mobile hard disk, a magnetic disk or an optical disk, and various media that can store computer programs.

[0110] Embodiments of the present disclosure further provide an electronic device, which comprises a memory storing a computer program and a processor configured to execute the computer program to perform the steps in any of the above method embodiments.

[0111] In one exemplary embodiment, the above electronic device can further comprise a transmission device connected to the processor and an input / output device connected to the processor.

[0112] The specific examples in the present embodiment can refer to the examples described in the above embodiments and exemplary implementation manners, and the present embodiment will not be described here again.

[0113] It is apparent that those skilled in the art should understand that the modules or steps of the present disclosure described above can be realized by general computing devices, which can be centralized on a single computing device or distributed on a network composed of multiple computing devices, and can be realized by program codes executable by the computing devices, so that they can be stored in storage devices and executed by the computing devices, and in some cases, the steps shown or described can be executed in different orders, or they can be respectively manufactured into individual integrated circuit modules, or multiple modules or steps thereof can be manufactured into a single integrated circuit module. Thus, the present disclosure is not limited to any particular combination of hardware and software.

[0114] The preferred embodiments of the present disclosure are described above, but the present disclosure is not limited to the above. Those skilled in the art can make various modifications and changes to the present disclosure. Any modification, equivalent replacement, improvement, etc. made within the principles of the present disclosure shall be included in the protection scope of the present disclosure.

Claims

1. A method for instruction execution, comprising: determining a first instruction address of a next instruction according to a current instruction executed, and obtaining a second instruction address of the next instruction; determining an instruction state of the next instruction according to the first instruction address, the second instruction address and an instruction key state table, wherein the instruction key state table is used to determine a key instruction by a key instruction flag stored in association with an instruction; determining that the next instruction is a key instruction based on the instruction state of the next instruction, and recording the next instruction into a first instruction queue for priority execution.

2. The method of claim 1, wherein, Before the obtaining of the second instruction address of the next instruction, the method further comprises: determining a branch target table and a branch history table corresponding to a scene represented by a previously obtained scene identifier, wherein the branch target table comprises a first label and an address offset having a corresponding relationship; and the branch history table comprises a second label and a jump identifier having a corresponding relationship, the jump identifier being used to indicate whether to jump to an instruction address of a next instruction of an instruction corresponding to the second label.

3. The method of claim 2, wherein, The obtaining of the second instruction address of the next instruction comprises: predicting the instruction address of the next instruction according to an instruction address of the current instruction and the branch target table, and determining the predicted instruction address as the second instruction address; determining a jump identifier corresponding to the second instruction address according to the instruction address of the current instruction and the branch history table.

4. The method of claim 3, wherein, The determining of the instruction state of the next instruction according to the first instruction address, the second instruction address and the instruction key state table comprises: in a case where the first instruction address is the same as the second instruction address, and a jump identifier corresponding to the second instruction address indicates a jump, determining the instruction state of the next instruction in the instruction key state table according to the second instruction address; or in a case where the first instruction address is not the same as the second instruction address, determining the instruction state of the next instruction in the instruction key state table according to the first instruction address.

5. The method of claim 4, wherein, The determining of the instruction state of the next instruction according to the first instruction address, the second instruction address and the instruction key state table comprises: obtaining a key vector corresponding to the next instruction from the instruction key state table according to a first m bits of the first instruction address or the second instruction address; determining the instruction state of the next instruction from the key vector according to a second m bits of the first instruction address or the second instruction address, wherein m is a positive integer, and a bit number of the instruction address of the next instruction is 2m.

6. The method of claim 1, further comprising: in a case where the instruction state of the next instruction indicates that the next instruction is a key instruction, recording the next instruction into the first instruction queue. In a case where the instruction state of the next instruction indicates that the next instruction is a non-critical instruction, the next instruction is recorded into the second instruction queue; wherein the execution priority of the first instruction queue is higher than the execution priority of the second instruction queue, and the first instruction queue and the second instruction queue are used to record instructions to be executed.

7. The method of claim 2, further comprising: In a case where the first instruction address is the same as the second instruction address, and the jump identifier corresponding to the second instruction address indicates a jump according to the branch history table, the instruction address of the target instruction is predicted in a first manner according to the instruction address of the previous instruction of the predicted target instruction, wherein the target instruction is an instruction after the current instruction, and the target instruction and the current instruction include a plurality of instructions; and the first manner is a manner of predicting the instruction address of the target instruction.

8. The method of claim 7, wherein, According to the instruction address of the previous instruction of the predicted target instruction, and predicting the instruction address of the target instruction in the first manner, comprises: In a case where the first tag is the same as a second tag included in the branch target table, and the jump identifier corresponding to the instruction address of the target instruction indicates a jump, the instruction address of the target instruction is determined according to the branch target table and the instruction address of the previous instruction of the target instruction, wherein the first tag is a tag determined according to the instruction address of the previous instruction of the target instruction.

9. The method of claim 8, further comprising: In a case where the first tag is the same as a second tag included in the branch target table, and the jump identifier corresponding to the instruction address of the target instruction indicates a jump, the instruction address of the target instruction is determined according to the branch target table and the instruction address of the previous instruction of the target instruction, wherein the first tag is a tag determined according to the instruction address of the previous instruction of the target instruction. Or, In a case where the first tag is not the same as any tag in the branch target table, the instruction address of the target instruction is determined according to the instruction address of the previous instruction of the target instruction and a preset address increment value.

10. An instruction execution apparatus, comprising: an obtaining module configured to determine a first instruction address of a next instruction according to a current instruction being executed, and to obtain a second instruction address of the next instruction; a determining module configured to determine an instruction state of the next instruction according to the first instruction address, the second instruction address, and an instruction critical state table, wherein the instruction critical state table is used to determine a critical instruction through a critical instruction flag associated with an instruction; a recording module configured to record the next instruction into a priority execution instruction queue based on the instruction state of the next instruction indicating that the next instruction is a critical instruction.

11. A computer readable storage medium having stored therein a computer program, wherein, The computer program is executed by a processor to implement the steps of the method described in any one of claims 1 to 9. The computer program is executed by a processor to implement the steps of the method described in any one of claims 1 to 9.

12. An electronic device comprising a memory, a processor, and a computer program stored on the memory and executable on the processor, the processor implementing the steps of the method according to any one of claims 1 to 9 when executing the computer program.

13. A computer program product comprising a computer program which, when executed by a processor, implements the steps of the method according to any one of claims 1 to 9.

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