Key warp scheduling method and apparatus

Abstract

A key warp scheduling method and apparatus, relating to the technical field of GPGPUs. Warps which are executed sequentially and warps which branch are scheduled at different frequencies. In this way, different scheduling solutions are specified for the two types of warps, thereby ensuring to the greatest extent that the parallel performance of the sequential warps is not affected, accelerating the running of the branch warps, avoiding the problem of extended running time of the warps caused by too many thread branches, and improving the parallel performance of general-purpose graphics processing units to a certain extent.

Description

A key thread bundle scheduling method and device

[0001] The present application claims priority to the Chinese patent application No. 202411325860.2, filed on September 23, 2024, and entitled "A key thread bundle scheduling method and device", the whole content of which is incorporated herein by reference. TECHNICAL FIELD

[0002] The present application relates to the technical field of GPGPU, in particular to a key thread bundle scheduling method and device. BACKGROUND

[0003] Thread bundle scheduling is a common concept in general-purpose graphics processing unit (GPGPU). A thread bundle is a collection of a certain number of threads, which is the smallest execution granularity of a general-purpose graphics processing unit. The thread bundle scheduler allocates the required storage resources and computing resources for the ready thread bundle to ensure the correct execution of the thread bundle task. The purpose of scheduling is to make all resources busy, so that multiple thread bundles can effectively share resources and improve the parallel performance of GPGPU.

[0004] With the development of computer languages and software technologies (especially artificial intelligence technologies), the processor needs to handle more and more branch judgments in real-time running. Unlike the CPU, which trades off complex branch management with hardware resources, GPGPU concentrates main resources on computing cores to achieve branch management by serially executing each branch thread. In complex branch judgment application scenarios, the serial execution of branch threads not only reduces the utilization of hardware (at the same time, the threads of one branch in the thread bundle will occupy all resources), but also greatly prolongs the overall running time of the thread bundle as the number of branches increases, ultimately affecting the execution efficiency of the entire task. SUMMARY

[0005] In order to overcome the above technical deficiencies, the present application provides a key thread bundle scheduling method and device for meeting the efficient parallel computing needs of GPGPU in complex branch judgment scenarios.

[0006] The technical solution adopted by the present application to overcome the technical problems is:

[0007] A key thread bundle scheduling method, comprising a branch management unit and a thread bundle scheduling unit.

[0008] The scheduling method when the sequentially executed thread bundle is scheduled is:

[0009] S1-1. The sequentially executed thread bundle instruction is passed into the key thread bundle discriminator of the branch management unit, which marks the sequentially executed thread as a normal thread bundle;

[0010] S1-2. The thread branch stack in the branch management unit stores the initial address of the thread marked as a normal thread bundle as the instruction address of the next code to be executed in the stack entry, and stores the end address of the thread as the instruction address of the branch reunion point in the entry;

[0011] S1-3. The branch management unit sends the thread bundle state and control information to the thread bundle scheduling unit through the control interface;

[0012] S1-4. After receiving the control information, the thread bundle scheduling unit identifies the thread bundle as a normal thread bundle, judges whether the thread bundle is ready according to the available computing and storage resources in the current GPGPU, and stores the ready thread bundle in the scheduling queue of the thread bundle scheduling unit;

[0013] The scheduling method when the branch executed thread bundle is scheduled is:

[0014] S2-1. The thread bundle instruction extracts the operand type through decoding, and the key thread bundle discriminator marks the thread bundle as a normal thread bundle or a key thread bundle;

[0015] S2-2. The thread branch stack in the branch management unit stores the first instruction address of each branch marked as a normal thread bundle or a key thread bundle as the instruction address of the next code to be executed in the stack entry, and stores the current branch end address of the thread as the instruction address of the branch reunion point in the entry;

[0016] S2-3. The branch management unit sends the thread bundle state and control information to the thread bundle scheduling unit through the control interface;

[0017] S2-4. After receiving the control information, the thread bundle scheduling unit identifies whether the thread bundle is a key thread bundle, and the polling scheduler of the thread bundle scheduling unit judges whether the thread bundle is ready according to the available computing and storage resources in the current GPGPU, and stores the ready thread bundle in the scheduling queue of the thread bundle scheduling unit.

[0018] Further, in step S1-1, the key thread bundle discriminator decodes the sequentially executed thread bundle instruction and extracts the operand type of the instruction. For the sequentially executed thread instruction, the operand is set as a non-branch jump type, and the key thread bundle discriminator marks the sequentially executed thread as a normal thread bundle.

[0019] Further, the end address of the thread end is stored as the instruction address of the branch reassembly point in the entry in step S1-2, and all bits of the thread mask in the entry are set to 1, and the key thread bundle flag in the entry is set to 0.

[0020] Further, the key thread bundle counter in the thread bundle scheduling unit is initialized to one half of the length of the scheduling queue after the thread bundle scheduling unit receives the control information and identifies the thread bundle as a normal thread bundle in step S1-4, and if the thread bundle is identified as a key thread bundle, the initial value of the key thread bundle counter is reduced to one half of the original value, and if the thread bundle is identified as a normal thread bundle, the initial value of the key thread bundle counter is doubled.

[0021] Further, the key thread bundle is marked as a normal thread bundle by the key thread bundle discriminator before the first branch judgment occurs after the operand type is extracted by decoding in step S2-1, and the key thread bundle is marked as a key thread bundle when the first branch judgment occurs, and the operand of the instruction is of a branch jump type.

[0022] Further, the key thread bundle is marked as a key thread bundle before all branches end in step S2-1, and the initial state is restored after all branches end.

[0023] Further, the thread mask is set according to whether the thread needs to execute the branch in step S2-2, a thread mask bit of 1 indicates that the corresponding thread executes the branch, and a thread mask bit of 0 indicates that the corresponding thread does not execute the branch, and the key thread bundle flag in the entry is defined according to the key thread bundle discrimination result, the key thread bundle is 1, and the normal thread bundle is 0.

[0024] Further, the key thread bundle counter in the thread bundle scheduling unit is initialized to one half of the length of the scheduling queue after the thread bundle scheduling unit receives the control information and identifies the thread bundle as a normal thread bundle in step S1-4, and if the thread bundle is identified as a key thread bundle, the initial value of the key thread bundle counter is reduced to one half of the original value, and if the thread bundle is identified as a normal thread bundle, the initial value of the key thread bundle counter is doubled.

[0025] Further, the key thread bundle counter is reduced by 1 after the thread bundle completes a scheduling in step S2-4, and if the key thread bundle counter is zero, the corresponding thread bundle is inserted into the front end of the scheduling queue again.

[0026] On the other hand, the present application also relates to a key thread bundle scheduling device, comprising a branch management unit and a thread bundle scheduling unit.

[0027] The branch management unit comprises:

[0028] The key thread bundle discriminator is used for decoding the thread bundle instruction, discriminating the operation number and marking the type of the thread bundle.

[0029] The thread branch stack is used for stacking the state information of the thread bundle temporarily.

[0030] The thread bundle scheduling unit comprises:

[0031] The polling scheduler is used for clearing the initial value of the key thread bundle counter and storing the thread information into the scheduling queue according to the polling scheduling strategy, and waiting for scheduling.

[0032] The key thread bundle counter is used for marking the type of the thread bundle.

[0033] The scheduling queue is used for storing the thread bundle scheduling unit which clears the initial value of the key thread bundle counter and stores the thread information according to the polling scheduling strategy.

[0034] The key thread bundle scheduling strategy adopts the method of marking the key thread bundle, marks the branch thread bundle and the sequential execution thread bundle as the key thread bundle and the ordinary thread bundle respectively, and executes different scheduling schemes. BRIEF DESCRIPTION OF DRAWINGS

[0035] Fig. 1 is an architecture diagram of the thread bundle scheduling method of the present application;

[0036] Fig. 2 is a scheduling method flow chart of the key thread bundle of the present application;

[0037] Fig. 3 is a complex thread division diagram of the present application;

[0038] Fig. 4 is an actual application diagram of the scheduler of the present application. DETAILED DESCRIPTION

[0039] The preferred embodiments of the present application will be described in detail below with reference to Figs. 1-4, so that the advantages and features of the present application can be more clearly understood by those skilled in the art, and the scope of protection of the present application can be more clearly defined.

[0040] In the description of the present application, it should be noted that the embodiments described in the present application are part of the embodiments of the present application, but not all the embodiments; based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor are within the scope of protection of the present application.

[0041] The terms "first", "second", etc. in the specification and claims and the above-described drawings are used to distinguish similar objects, and do not necessarily describe a specific order or sequence. It should be understood that the data thus used can be interchanged under appropriate circumstances, so that the embodiments of the present application described herein can be implemented in an order other than that illustrated or described herein. In addition, the terms "include" and "have" and any variations thereof are intended to cover non-exclusive inclusion, for example, a process, method, device, product or equipment including a series of steps or units does not have to be limited to those steps or units clearly listed, but can include other steps or units not clearly listed or inherent to these processes, methods, products or equipment.

[0042] Embodiment 1:

[0043] The critical thread bundle scheduling strategy adopts the method of "marking critical thread bundles", and marks the branch thread bundles and the sequential execution thread bundles as critical thread bundles and ordinary thread bundles respectively, and executes different scheduling schemes. The specific scheduling strategy is that the ordinary thread bundles are scheduled in a polling manner, the critical thread bundles have a higher scheduling frequency, and are inserted into the scheduling queue with a higher priority to accelerate the execution of the critical thread bundles. For ordinary thread bundles, the scheduler will assign different thread bundle IDs to them according to the order in which these thread bundles enter the scheduling unit, and assign ordinary priority, and then select the thread bundles in the ready state in turn and store them into the scheduling queue. For critical thread bundles, the scheduler adjusts the scheduling frequency of the thread bundle in real time according to the number of thread branches generated, and assigns a higher priority, and then inserts the ready critical thread bundle into the front end of the scheduling queue. Finally, the two types of thread bundles are executed in different frequencies and in order. The core of this design is to schedule the sequential execution thread bundles and the thread bundles with branches at different frequencies, which specifies different scheduling schemes for the two types of thread bundles, maximizes the parallel performance of the sequential thread bundles, speeds up the running of the branch thread bundles, avoids the problem of prolonged execution time of the thread bundles due to too many thread branches, and improves the parallel performance of the general-purpose graphics processor to a certain extent.

[0044] The key thread bundle scheduling method of the present application, as shown in Fig. 1, comprises a branch management unit and a thread bundle scheduling unit. As can be seen from Fig. 1, the key thread bundle scheduling method designed by the present application is composed of the branch management unit and the thread bundle scheduling unit, wherein the branch management unit is realized by a key thread bundle discriminator and a thread branch stack; the thread bundle scheduling unit is realized by a polling scheduler, a key thread bundle counter and a scheduling queue; the branch management unit and the thread bundle scheduling unit are connected by a control interface.

[0045] As shown in Fig. 2, the branch management unit is mainly composed of a key thread bundle discriminator and a thread branch stack. The key thread bundle scheduler decodes the thread bundle instruction, extracts the operand type for judgment, and marks whether the thread bundle is a key thread bundle. The thread branch stack is essentially a stack structure, the entry and exit of the stack are in the form of stack pushing and stack popping, and the top pointer always points to the last entry into the stack. Each entry contains the following four fields: the instruction address of the branch reconvergence point (RPC), the value of which is determined by the first executed reconvergence point instruction address (for example, in the thread branch flow diagram of Fig. 3, after the code block B is executed, the three threads pass through two branch paths C and D and then converge at E, and the code block E is called the first executed reconvergence point, i.e. the branch reconvergence point); the instruction address of the next code to be executed (NPC), which saves the instruction address to be executed by the branch corresponding to the entry; the thread mask, which represents whether each thread in the branch needs to be executed; and the key thread bundle mark, which is used to distinguish whether it is a key thread bundle. The thread bundle scheduling unit mainly includes a polling scheduler, a key thread bundle counter and a scheduling queue. The polling scheduler is used to uniformly manage the scheduling of all thread bundles, the key thread bundle counter is used to control the scheduling frequency of the two types of thread bundles (the key thread bundle counter sets the initial value according to the thread bundle type, and dynamically adjusts it when a new branch is generated or the branch ends), and the scheduling queue is used to store the thread bundles to be scheduled, and realizes the ordered execution of each thread bundle. The branch management unit and the thread bundle scheduling unit are connected by a control interface, and the control interface contains information such as thread bundle state and key thread bundle discrimination result.

[0046] The scheduling method when the sequentially executed thread bundle is scheduled is as follows:

[0047] S1-1. The sequentially executed thread bundle instruction is transmitted into the key thread bundle discriminator of the branch management unit, and the key thread bundle discriminator marks the sequentially executed thread as a normal thread bundle.

[0048] S1-2. The thread branch stack in the branch management unit stores the initial address of the thread marked as a normal thread bundle as the instruction address of the next code to be executed into the entry in the stack, and stores the end address of the thread as the instruction address of the branch reconvergence point into the entry.

[0049] S1-3. The branch management unit sends the thread bundle state and control information to the thread bundle scheduling unit through the control interface.

[0050] S1-4. After receiving the control information, the thread bundle scheduling unit identifies the thread bundle as a normal thread bundle, judges whether the thread bundle is ready according to the available computing and storage resources in the current GPGPU, and stores the ready thread bundle into the scheduling queue of the thread bundle scheduling unit.

[0051] The scheduling method when the thread bundle of branch execution is scheduled is as follows:

[0052] S2-1. The thread bundle instruction extracts the operand type through decoding, and the key thread bundle discriminator marks the thread bundle as a normal thread bundle or a key thread bundle.

[0053] S2-2. The thread branch stack in the branch management unit stores the first instruction address of each branch marked as a normal thread bundle or a key thread bundle as the instruction address of the next code to be executed into the stack entry, and stores the current branch end address of the end of the thread as the instruction address of the branch reunion point into the entry.

[0054] S2-3. The branch management unit sends the thread bundle state and control information to the thread bundle scheduling unit through the control interface.

[0055] S2-4. After receiving the control information, the thread bundle scheduling unit identifies whether the thread bundle is a key thread bundle, and the polling scheduler of the thread bundle scheduling unit judges whether the thread bundle is ready according to the available computing and storage resources in the current GPGPU, and stores the ready thread bundle into the scheduling queue of the thread bundle scheduling unit.

[0056] In this embodiment, the key thread bundle discriminator decodes the thread bundle instruction of sequential execution and extracts the operand type of the instruction in step S1-1, and for the thread instruction of sequential execution, sets the operand as a non-branch jump type, and marks the thread of sequential execution as a normal thread bundle.

[0057] In this embodiment, after storing the end address of the end of the thread as the instruction address of the branch reunion point into the entry in step S1-2, all bits of the thread mask in the entry are set to 1 (sequential execution does not occur branch, all threads execute the same instruction), and the key thread bundle mark in the entry is set to 0.

[0058] In this embodiment, the thread bundle scheduling unit receives the control information in step S1-4, and initializes the corresponding critical thread bundle counter in the thread bundle scheduling unit to 0 after identifying the thread bundle as a normal thread bundle (representing that the thread bundle does not need to increase the call frequency by technical methods), and the polling scheduler in the thread bundle scheduling unit generates a scheduling ID according to the order in which the thread bundle enters the thread bundle scheduling unit and assigns the thread bundle a normal priority.

[0059] In this embodiment, the thread bundle instruction extracts the operand type through decoding in step S2-1, and the instruction operand is of a non-branch jump type before the first branch judgment occurs, the critical thread bundle discriminator marks the thread bundle as a normal thread bundle, and when the instruction operand is of a branch jump type at the first branch judgment, the critical thread bundle discriminator marks the thread bundle as a critical thread bundle.

[0060] In this embodiment, the thread bundle is marked as a critical thread bundle before all branches end in step S2-1, and the initial state is restored after all branches end.

[0061] In this embodiment, the thread mask is set according to whether the thread needs to execute the branch in step S2-2, the thread mask bit is 1, indicating that the corresponding thread executes this branch, and the thread mask bit is 0, indicating that the corresponding thread does not execute this branch, and the critical thread bundle mark in the entry is defined according to the critical thread bundle discrimination result, the critical thread bundle is 1, and the normal thread bundle is 0.

[0062] In this embodiment, the thread bundle scheduling unit receives the control information in step S2-4, and initializes the corresponding critical thread bundle counter in the thread bundle scheduling unit to half of the length of the scheduling queue after identifying whether the thread bundle is a critical thread bundle, if the thread bundle is identified as a critical thread bundle, the initial value of the critical thread bundle counter is reduced by half based on the original value, if the thread bundle is identified as a normal thread bundle, the initial value of the critical thread bundle counter is doubled based on the original value. The call frequency of the thread bundle is changed by dynamically adjusting the initial value of the counter.

[0063] In this embodiment, the critical thread bundle counter is decremented by 1 after the thread bundle completes a scheduling in step S2-4, and if the critical thread bundle counter is zero (the initial value is assigned again and the counting is restarted), the corresponding thread bundle is inserted into the front end of the scheduling queue again, realizing the priority repeated scheduling.

[0064] As shown in FIG. 4, the application replaces the basic polling scheduler with a thread bundle scheduler constructed according to the critical thread bundle scheduling strategy, controls the calling frequency of different types of thread bundles through the scheduler, and realizes efficient and orderly execution of each thread bundle. For a thread bundle to be executed in sequence, the critical thread bundle scheduler reads a thread bundle instruction from the instruction cache, identifies the thread bundle as a normal thread bundle, and sends the prepared thread bundle to the execution unit according to the basic polling rule. The execution unit completes the execution of all threads in the thread bundle in a single scheduling period, and then schedules other thread bundles in sequence. For a thread bundle to be executed in branches, the critical thread bundle scheduler identifies it as a critical thread bundle and sends it to the execution unit with a higher priority. The execution unit completes the execution of threads in a branch in a single scheduling period, and then schedules the thread bundle at a higher frequency until all branches in the thread bundle are completed.

[0065] Embodiment 2:

[0066] A critical thread bundle scheduling device includes a branch management unit and a thread bundle scheduling unit.

[0067] The branch management unit includes:

[0068] A critical thread bundle discriminator decodes thread bundle instructions, discriminates operands, and marks the type of thread bundle.

[0069] A thread branch stack temporarily stacks state information of the thread bundle.

[0070] The thread bundle scheduling unit includes:

[0071] A polling scheduler clears the initial value of the critical thread bundle counter, stores thread information into a scheduling queue according to the polling scheduling strategy, and waits for scheduling.

[0072] A critical thread bundle counter marks the type of thread bundle.

[0073] A scheduling queue stores thread information cleared by the thread bundle scheduling unit from the initial value of the critical thread bundle counter and according to the polling scheduling strategy.

[0074] When the scheduling system executes the sequential thread bundle, the critical thread bundle discriminator decodes the thread bundle instruction, discriminates the operand, marks the type of the thread bundle; the branch management unit pushes the state information of the thread bundle into the thread branch stack, and transmits the control information of the thread bundle through the control interface; the thread bundle scheduling unit clears the initial value of the critical thread bundle counter, and stores the thread information into the scheduling queue according to the round-robin scheduling strategy, and waits for scheduling. When the scheduling system executes the branch thread bundle, the critical thread bundle discriminator marks the type of the thread bundle; the branch management unit firstly pushes the state information of the thread bundle into the thread branch stack, and then manages the unit to push or pop the branch thread into or out of the stack when the thread bundle generates a new branch or ends the branch, and transmits the control information of the thread bundle through the control interface; the thread bundle scheduling unit sets the initial value of the critical thread bundle counter, and according to the value of the counter, inserts the thread bundle into the front end of the scheduling queue at a faster frequency, and repeats the scheduling.

[0075] It should also be understood that, in the embodiments herein, the term "and / or" is merely an association relationship of the associated objects, and means that there can be three relationships. For example, A and / or B can mean that there are three cases of A alone, A and B together, and B alone. In addition, the character " / " herein generally means that the front and rear associated objects are in an "or" relationship.

[0076] Those skilled in the art can realize that the units and algorithm steps of the examples described in combination with the embodiments disclosed herein can be realized in electronic hardware, computer software or a combination of both. In order to clearly illustrate the interchangeability of hardware and software, the components and steps of the examples have been described in the above description in general terms. Whether the functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. A person skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of the present disclosure.

[0077] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working processes of the above-described system, device and unit can refer to the corresponding processes in the foregoing method embodiments, which will not be described here.

[0078] In several embodiments provided herein, it should be understood that the disclosed system, apparatus and method can be implemented in other manners. For example, the apparatus embodiments described above are merely schematic, and the division of units is merely logical function division, and there can be other division manners in actual implementation. For example, a plurality of units or components can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the displayed or discussed mutual couplings or direct couplings or communication connections can be indirect couplings or communication connections through some interfaces, devices or units, and can be electric, mechanical or in other forms.

[0079] The units described as separate components can or can not be physically separate, and the components shown as units can or can not be physical units, i.e., can be located in one place, or can be distributed on a plurality of network units. Part or all of the units can be selected according to actual needs to achieve the purpose of the embodiments provided herein.

[0080] In addition, each functional unit in each embodiment herein can be integrated into a processing unit, or each unit can be physically present separately, or two or more units can be integrated into one unit. The integrated unit can be realized in the form of hardware or in the form of a software functional unit.

[0081] The integrated unit, if realized in the form of a software functional unit and sold or used as an independent product, can be stored in a computer readable storage medium. Based on this understanding, the technical solutions herein, essentially or the part that contributes to the prior art, or the whole or part of the technical solutions can be embodied in the form of a software product. The computer software product is stored in a storage medium, and includes a number of instructions for causing a computer device (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the methods described in each embodiment herein. The aforementioned storage medium includes: a U disk, a mobile hard disk, a read-only memory (ROM, Read-Only Memory), a random access memory (RAM, Random Access Memory), a magnetic disk or an optical disk, and various media that can store program codes.

[0082] Finally, it should be noted that the above only describes the preferred embodiments of the present application and is not intended to limit the present application. Although the present application has been described in detail with reference to the foregoing embodiments, those skilled in the art will appreciate that the technical solutions described in the foregoing embodiments can be modified or some technical features thereof can be replaced by equivalent features. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A method of critical thread bundle scheduling, the method comprising: The branch management unit, the thread bundle scheduling unit; The scheduling method when the sequentially executed thread bundle is scheduled is as follows: S1-1: The sequentially executed thread bundle instruction is input into the key thread bundle discriminator of the branch management unit, and the key thread bundle discriminator marks the sequentially executed thread as a normal thread bundle; S1-2: The thread branch stack in the branch management unit stores the initial address of the thread marked as the normal thread bundle as the instruction address of the next code to be executed in the stack entry, and stores the end address of the thread as the instruction address of the branch reunion point in the entry; S1-3: The branch management unit sends the thread bundle state and control information to the thread bundle scheduling unit through the control interface; S1-4: After receiving the control information, the thread bundle scheduling unit identifies the thread bundle as a normal thread bundle, judges whether the thread bundle is ready according to the available computing and storage resources in the current GPGPU, and stores the ready thread bundle in the scheduling queue of the thread bundle scheduling unit. The scheduling method when the branch executed thread bundle is scheduled is as follows: S2-1: The thread bundle instruction extracts the operand type through decoding, and the key thread bundle discriminator marks the thread bundle as a normal thread bundle or a key thread bundle; S2-2: The thread branch stack in the branch management unit stores the first instruction address of each branch marked as the normal thread bundle or the key thread bundle as the instruction address of the next code to be executed in the stack entry, and stores the current branch end address of the thread as the instruction address of the branch reunion point in the entry; S2-3: The branch management unit sends the thread bundle state and control information to the thread bundle scheduling unit through the control interface; S2-4: After receiving the control information, the thread bundle scheduling unit identifies whether the thread bundle is a key thread bundle, and the polling scheduler of the thread bundle scheduling unit judges whether the thread bundle is ready according to the available computing and storage resources in the current GPGPU, and stores the ready thread bundle in the scheduling queue of the thread bundle scheduling unit.

2. The critical thread bundle scheduling method of claim 1, wherein: In step S1-1, the key thread bundle discriminator decodes the sequentially executed thread bundle instruction and extracts the operand type of the instruction. For the sequentially executed thread instruction, the operand is set as a non-branch jump type, and the key thread bundle discriminator marks the sequentially executed thread as a normal thread bundle.

3. The critical thread bundle scheduling method of claim 1, wherein: In step S1-2, after storing the end address of the thread as the instruction address of the branch reunion point in the entry, all bits of the thread mask in the entry are set to 1, and the key thread bundle mark in the entry is set to 0.

4. The critical thread bundle scheduling method of claim 1, wherein: In step S1-4, after the thread bundle scheduling unit identifies the thread bundle as a normal thread bundle, the key thread bundle counter corresponding to the thread bundle in the thread bundle scheduling unit is initialized to 0, and the polling scheduler in the thread bundle scheduling unit generates a scheduling ID according to the order in which the thread bundle enters the thread bundle scheduling unit and assigns the normal priority to the thread bundle.

5. The critical thread bundle scheduling method of claim 1, wherein: In step S2-1, the instruction of the thread bundle is of non-branch jump type before the first branch judgment, and the key thread bundle discriminator marks the thread bundle as a normal thread bundle. When the instruction is of branch jump type, the key thread bundle discriminator marks the thread bundle as a key thread bundle.

6. The critical thread bundle scheduling method of claim 5, wherein: In step S2-1, the thread bundle is marked as a key thread bundle before all branches end, and the initial state is restored after all branches end.

7. The critical thread bundle scheduling method of claim 1, wherein: In step S2-2, the thread mask is set according to whether the thread needs to execute the branch. The thread mask bit of 1 indicates that the corresponding thread executes the branch, and the thread mask bit of 0 indicates that the corresponding thread does not execute the branch. The key thread bundle flag in the entry is defined according to the key thread bundle discrimination result. The key thread bundle is 1, and the normal thread bundle is 0.

8. The critical thread bundle scheduling method of claim 1, wherein: In step S2-4, the thread bundle scheduling unit receives the control information to identify whether the thread bundle is a key thread bundle, and initializes the corresponding key thread bundle counter in the thread bundle scheduling unit to one half of the length of the scheduling queue. If the thread bundle is identified as a key thread bundle, the initial value of the key thread bundle counter is reduced by one half based on the original value. If the thread bundle is identified as a normal thread bundle, the initial value of the key thread bundle counter is doubled based on the original value.

9. The critical thread bundle scheduling method of claim 1, wherein: In step S2-4, when the thread bundle completes a scheduling, the key thread bundle counter is reduced by 1. If the key thread bundle counter is zero, the corresponding thread bundle is inserted into the front end of the scheduling queue again.

10. A critical thread bundle scheduling apparatus, characterized by comprising: The branch management unit and the thread bundle scheduling unit are included. The branch management unit includes: The key thread bundle discriminator is used for decoding and discriminating the operation of the thread bundle instruction, and marking the type of the thread bundle. The thread branch stack is used for stacking the state information of the thread bundle temporarily. The thread bundle scheduling unit includes: The polling scheduler is used for clearing the initial value of the key thread bundle counter, and storing the thread information into the scheduling queue according to the polling scheduling strategy, and waiting for scheduling. The key thread bundle counter is used for marking the type of the thread bundle. The scheduling queue is used for storing the thread information cleared by the thread bundle scheduling unit according to the polling scheduling strategy.

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