Method for writing mask data

Abstract

The present invention provides an interface system, comprising a main controller, an interface module, and a functional module. The main controller is connected to the interface module. The interface module is connected to the functional module. On the basis of the interface system, the present invention provides a method for writing mask data. The main controller sends a command packet to the interface module. The command packet comprises one or more commands, at least one of which is a write mask command. The write mask command comprises an address field, a data field, and a mask field. Upon receiving the command packet, the interface module sends the command packet to the functional module. Upon receiving the command packet, the functional module executes a command comprised in the command packet. Execution of the write mask command comprises: writing, into a storage space indicated by the address field of the write mask command, bits of the data field in the write mask command which correspond to bits having the values of 1 of the mask field in the write mask command.

Description

A method of writing mask data TECHNICAL FIELD

[0001] The present application relates to the field of communication technology, in particular to a method of writing mask data. BACKGROUND

[0002] I2C (Inter-Integrated Circuit) bus is a simple, bidirectional serial bus developed by Philips Company. An I2C master device connects one or more I2C slave devices through an I2C bus, the I2C bus includes an I2C clock line (generally named SCL) and an I2C data line (generally named SDA), the I2C master device drives the I2C clock line, initiates an I2C write operation or read operation to the I2C slave device, and judges whether the data transmission is successful through the response bit returned by the I2C slave device.

[0003] SPI (Serial Peripheral Interface) is a high-speed, full-duplex, synchronous communication bus. SPI usually has four signal lines, including SPI_CSN signal line, SPI_CK signal line, SPI_MOSI signal line and SPI_MISO signal line. The SPI master device connects the SPI slave device through the four signal lines, the SPI master device drives the SPI_CSN signal line, the SPI_CK signal line and the SPI_MOSI signal line, the SPI slave device receives the SPI_CSN signal line, the SPI_CK signal line and the SPI_MOSI signal line, the SPI slave device drives the SPI_MISO signal line, and the SPI master device receives the SPI_MISO signal line. The SPI_CSN signal line is a selection signal, in the SPI protocol, the SPI slave device can only transmit data when the SPI_CSN signal line is low. One SPI master device can connect one or more SPI slave devices: when one SPI master device connects multiple SPI slave devices, at any time, only the SPI_CSN signal line connected to one SPI slave device is low; when one SPI master device only connects one SPI slave device, the SPI master device and the SPI slave device can have no SPI_CSN signal line, at this time, the SPI master device and the SPI slave device can only be connected through the SPI_CK signal line, the SPI_MOSI signal line and the SPI_MISO signal line.

[0004] In the present application, the I2C master controller is an I2C master device, the I2C interface module is an I2C slave device, the SPI master controller is an SPI master device, and the SPI interface module is an SPI slave device.

[0005] In the application, the main controller can be an I2C main controller or an SPI main controller, or a main controller conforming to other interface protocols such as serial UART protocol, CAN protocol, LIN protocol, etc.; the interface module can be an I2C interface module or an SPI interface module, or an interface module conforming to other interface protocols such as serial UART protocol, CAN protocol, LIN protocol, etc.

[0006] The main controller sends commands or data to the functional module through the interface module. In the application, the module that finally receives the commands or data is referred to as the functional module. The interface module and the functional module can be in the same chip, or the same circuit board, or the same device, or can be in different devices. The interface module and the functional module can communicate through existing or self-defined communication protocols.

[0007] In some applications, the main controller needs to write data to part of bits in the storage space pointed to by the target address in the functional module. For example, the main controller configures part of bits in a register in the functional module. When configuring, part of bits in the register need to be overwritten by new values, while the remaining bits of the register should remain unchanged. When the main controller can directly configure the functional module, the main controller usually uses the write mask method to configure part of bits in the storage space in the functional module.

[0008] If the main controller cannot directly configure the functional module and needs to configure the functional module through an I2C or SPI interface module, in the prior art, the following configuration method is generally used: the main controller first initiates a write operation to the interface module, sends a read command to the interface module, the interface module forwards the read command to the functional module, the functional module executes the read command, reads out the data in the storage space pointed to by the target address (this read-out data is referred to as read data in the application) and sends it to the interface module, and the interface module receives the read data; then the main controller initiates a read operation to the interface module, the main controller reads the read data from the interface module, replaces the bits in the read data corresponding to the bits with value 1 in the mask with configuration data, and keeps the remaining bits of the read data unchanged, and takes the replaced read data as the data to be written; then the main controller initiates a write operation to the interface module again, sends a write command containing the data to be written to the interface module, the interface module forwards the write command to the functional module, the functional module executes the write command, and writes the data to be written into the storage space pointed to by the target address. This method is complicated and time-consuming.

[0009] The application discloses a method for a master controller to quickly configure part of bits in a storage space pointed by a target address in a functional module through an interface module such as an I2C or SPI interface, that is, a method for the master controller to quickly write mask data into a target device through an I2C or SPI interface. SUMMARY

[0010] The application discloses a method for a master controller to quickly configure part of bits in a storage space pointed by a target address in a functional module through an interface module such as an I2C or SPI interface, that is, a method for the master controller to quickly write mask data into a target device through an I2C or SPI interface.

[0011] To solve the above technical problems, the application adopts the following technical scheme:

[0012] As a method for writing mask data, the application is based on an interface system, which comprises a master controller, an interface module and a functional module, the master controller is connected to the interface module, the interface module is connected to the functional module, the master controller sends a command package to the interface module, the command package comprises one or more commands, at least one command is a write mask command, the write mask command comprises an address field, a data field and a mask field, the interface module sends the command package to the functional module after receiving the command package, the functional module executes the commands contained in the command package, and the execution of the write mask command comprises: writing the bits in the data field of the write mask command corresponding to the bits in the mask field of the write mask command into a storage space pointed by the address field of the write mask command.

[0013] Preferably, after the functional module executes the commands contained in the command package, the functional module returns a state package to the interface module, which comprises: when the results of the execution of each command contained in the command package by the functional module are all successful, the functional module returns a state package with successful state information; when the result of the execution of at least one command contained in the command package by the functional module is unsuccessful, the functional module returns a state package with unsuccessful state information; and when the interface module receives the state package from the functional module, the interface module returns the state information of the state package to the master controller.

[0014] Preferably, the command package comprises one or more commands, at least one command is a write command, the write command comprises an address field and a data field, the functional module executes the commands contained in the command package after receiving the command package, and the execution of the write command comprises: writing the data field in the write command into a storage space pointed by the address field of the write command.

[0015] Further, the master controller is an I2C master controller, the interface module is an I2C interface module, and the I2C master controller is connected to the I2C interface module through an I2C clock line and an I2C data line.

[0016] Further, the I2C master controller initiates an I2C write operation to send a command packet to the I2C interface module, and the I2C interface module pulls down the I2C clock line after receiving the command packet and sends the command packet to the function module.

[0017] Further, when the I2C interface module receives a status packet from the function module and the status information of the status packet is success, the I2C interface module stops pulling down the I2C clock line and returns an I2C ACK to the I2C master controller, and when the I2C interface module receives a status packet from the function module and the status information of the status packet is failure, the I2C interface module stops pulling down the I2C clock line and returns an I2C NAK to the I2C master controller.

[0018] Further, when the I2C interface module receives a status packet from the function module, the I2C interface module stops pulling down the I2C clock line and returns an I2C ACK or an I2C NAK to the I2C master controller, and if the subsequent I2C operation initiated by the I2C master controller is an I2C read operation, the I2C interface module returns the status information of the status packet to the I2C master controller.

[0019] Further, after the I2C interface module receives a command packet, if the subsequent I2C operation initiated by the I2C master controller is an I2C read operation, the I2C interface module returns the status information of the status packet to the I2C master controller after receiving the status packet from the function module.

[0020] Further, after the I2C interface module receives a command packet, if the subsequent I2C operation initiated by the I2C master controller is an I2C write operation, and the I2C interface module receives a status packet from the function module and the status information of the status packet is success, the I2C interface module receives the subsequent I2C write operation initiated by the I2C master controller, and after the I2C interface module receives a command packet, if the subsequent I2C operation initiated by the I2C master controller is an I2C write operation, and the I2C interface module receives a status packet from the function module and the status information of the status packet is failure, the I2C interface module returns an I2C NAK to the I2C master controller.

[0021] Further, the I2C master controller initiates an I2C write operation to send a command package to the I2C interface module, and then initiates a subsequent I2C read operation to read state information, after the I2C interface module receives the address byte of the subsequent I2C read operation, the I2C interface module pulls down the I2C clock line, and sends the received command package to the function module, the function module executes the command in the command package, and returns a state package to the interface module, when the I2C interface module receives the state package from the function module, the I2C interface module stops pulling down the I2C clock line, and returns the state information of the state package to the I2C master controller.

[0022] Further, the master controller is an SPI master controller, and the interface module is an SPI interface module, and the SPI master controller is connected to the SPI interface module through an SPI_CK signal line, an SPI_MOSI signal line, and an SPI_MISO signal line.

[0023] Further, the SPI master controller generates a clock edge on the SPI_CK signal line, sends a command package to the SPI interface module through the SPI_MOSI signal line, the SPI interface module reads the command package through the SPI_MOSI signal line, the command package starts with a first identification field, and after the SPI interface module receives a state package from the function module, when the SPI master controller generates a clock edge on the SPI_CK, the SPI interface module sends a feedback package to the SPI master controller through the SPI_MISO signal line, the SPI master controller reads the feedback package through the SPI_MISO signal line, the feedback package starts with a second identification field, and the feedback package contains the state information contained in the state package.

[0024] Further, when the SPI master controller generates a clock edge on the SPI_CK, if the SPI interface module does not receive a state package from the function module, the SPI interface module sends data that cannot be identified as the feedback package to the SPI master controller through the SPI_MISO signal line.

[0025] Further, after the SPI interface module sends the feedback package through the SPI_MISO signal line, the SPI interface module can continue to receive a subsequent command package sent by the SPI master controller through the SPI_MOSI signal line.

[0026] Further, the feedback packet is divided into a success feedback packet and a failure feedback packet, when the SPI interface module receives the state packet from the function module and the state information contained in the state packet is success, the SPI interface module sends the success feedback packet through the SPI_MISO signal line, when the SPI interface module receives the state packet from the function module and the state information contained in the state packet is failure, the SPI interface module sends the failure feedback packet through the SPI_MISO signal line, the second identification field of the success feedback packet is different from the second identification field of the failure feedback packet.

[0027] As a write mask command, the write mask command contains an address field, a data field and a mask field, the write mask command is contained in a command packet, the command packet contains one or more commands, at least one command is the write mask command, the command packet is transmitted and executed based on an interface system, the interface system includes a host controller, an interface module and a function module, the host controller is connected to the interface module, the interface module is connected to the function module, the host controller sends the command packet to the interface module, the interface module sends the command packet to the function module after receiving the command packet, the function module executes the command contained in the command packet after receiving the command packet, and executing the write mask command includes: writing the bit of the write mask command data field corresponding to the bit of the write mask command in which the mask field is 1 into the storage space pointed by the write mask command address field.

[0028] Preferably, the function module returns a state packet to the interface module after executing the command contained in the command packet, including: when the result of the function module executing each command contained in the command packet is success, the function module returns a state packet with success state information, when the result of the function module executing at least one command contained in the command packet is failure, the function module returns a state packet with failure state information, and when the interface module receives the state packet from the function module, the interface module returns the state information of the state packet to the host controller.

[0029] Further, the host controller is an I2C host controller, the interface module is an I2C interface module, and the I2C host controller is connected to the I2C interface module through an I2C clock line and an I2C data line.

[0030] Further, the I2C host controller initiates an I2C write operation to send the command packet to the I2C interface module, and the I2C interface module pulls down the I2C clock line after receiving the command packet and sends the command packet to the function module.

[0031] Further, when the I2C interface module receives the status package from the function module and the status information of the status package is success, the I2C interface module stops pulling down the I2C clock line level and returns I2C ACK to the I2C master controller, and when the I2C interface module receives the status package from the function module and the status information of the status package is failure, the I2C interface module stops pulling down the I2C clock line level and returns I2C NAK to the I2C master controller.

[0032] Further, when the I2C interface module receives the status package from the function module, the I2C interface module stops pulling down the I2C clock line level and returns I2C ACK or I2C NAK to the I2C master controller, and if the subsequent I2C operation initiated by the I2C master controller is I2C read operation, the I2C interface module returns the status information of the status package to the I2C master controller.

[0033] Further, after the I2C interface module receives the command package, if the subsequent I2C operation initiated by the I2C master controller is I2C read operation, the I2C interface module returns the status information of the status package to the I2C master controller after receiving the status package from the function module.

[0034] Further, after the I2C interface module receives the command package, if the subsequent I2C operation initiated by the I2C master controller is I2C write operation, and the I2C interface module receives the status package from the function module and the status information of the status package is success, the I2C interface module receives the subsequent I2C write operation initiated by the I2C master controller, and after the I2C interface module receives the command package, if the subsequent I2C operation initiated by the I2C master controller is I2C write operation, and the I2C interface module receives the status package from the function module and the status information of the status package is failure, the I2C interface module returns I2C NAK to the I2C master controller.

[0035] Further, the I2C master controller initiates I2C write operation to send the command package to the I2C interface module, and then the I2C master controller initiates subsequent I2C read operation to read the status information, the I2C interface module pulls down the I2C clock line level after receiving the address byte of the subsequent I2C read operation, and sends the received command package to the function module, the function module returns the status package to the interface module after executing the command contained in the command package, and when the I2C interface module receives the status package from the function module, the I2C interface module stops pulling down the I2C clock line level and returns the status information of the status package to the I2C master controller.

[0036] Further, the main controller is an SPI master controller, and the interface module is an SPI interface module, and the SPI master controller is connected to the SPI interface module through an SPI_CK signal line, an SPI_MOSI signal line and an SPI_MISO signal line.

[0037] Further, the SPI master controller generates a clock edge on the SPI_CK signal line, sends a command packet to the SPI interface module through the SPI_MOSI signal line, the SPI interface module reads the command packet through the SPI_MOSI signal line, the command packet starts with a first identification field, after the SPI interface module receives a state packet from the functional module, when the SPI master controller generates a clock edge on the SPI_CK, the SPI interface module sends a feedback packet to the SPI master controller through the SPI_MISO signal line, the SPI master controller reads the feedback packet through the SPI_MISO signal line, the feedback packet starts with a second identification field, and the feedback packet contains state information contained in the state packet.

[0038] Further, when the SPI master controller generates a clock edge on the SPI_CK, if the SPI interface module does not receive a state packet from the functional module, the SPI interface module sends data that cannot be identified as the feedback packet to the SPI master controller through the SPI_MISO signal line.

[0039] Further, after the SPI interface module sends the feedback packet through the SPI_MISO signal line, the SPI interface module can continue to receive a subsequent command packet sent by the SPI master controller through the SPI_MOSI signal line.

[0040] Further, the feedback packet is divided into a success feedback packet and a failure feedback packet, when the SPI interface module receives a state packet from the functional module and the state information contained in the state packet is success, the SPI interface module sends the success feedback packet through the SPI_MISO signal line, when the SPI interface module receives a state packet from the functional module and the state information contained in the state packet is failure, the SPI interface module sends the failure feedback packet through the SPI_MISO signal line, and the second identification field of the success feedback packet is different from the second identification field of the failure feedback packet.

[0041] The application provides a method for writing mask data, and a main controller can quickly configure part of bits in a storage space pointed by a target address in a functional module through an interface module such as an I2C or an SPI, that is, the main controller can quickly write mask data to a target device through an I2C interface or an SPI interface. BRIEF DESCRIPTION OF DRAWINGS

[0042] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the accompanying drawings needed to be used in the description of the embodiments or the prior art will be briefly introduced. Obviously, the accompanying drawings in the following description are some embodiments of the present application, and other drawings can be obtained by those skilled in the art without any creative effort based on these drawings.

[0043] Fig. 1 shows a structural block diagram of an interface system according to the present application;

[0044] Fig. 2 shows a transmission diagram of a command packet, a status packet and status information in an interface system according to the present application;

[0045] Fig. 3 shows a data structure diagram of a command packet according to the present application;

[0046] Fig. 4 shows a structural diagram of a command packet containing a write mask command according to the present application;

[0047] Fig. 5 shows a data structure diagram of a write mask command according to the present application;

[0048] Fig. 6 shows a structural diagram of a command packet containing a write mask command and a write command according to the present application;

[0049] Fig. 7 shows a data structure diagram of a write command according to the present application;

[0050] Fig. 8 shows a structural diagram of a command packet containing a write mask command and a read command according to the present application;

[0051] Fig. 9 shows a data structure diagram of a read command according to the present application;

[0052] Fig. 10 shows a structural diagram of a command packet containing a write mask command, a write command and a read command according to the present application;

[0053] Fig. 11 shows a structural block diagram of an interface system according to the present application, in which the main controller is an I2C main controller and the interface module is an I2C interface module;

[0054] Fig. 12 shows a timing diagram of an I2C write operation according to the present application;

[0055] Fig. 13 shows a timing diagram of an I2C read operation according to the present application;

[0056] Fig. 14 shows a timing diagram of an I2C continuous read-write operation according to the present application;

[0057] Fig. 15 shows a timing diagram of sending a command packet to initiate an I2C write operation according to the present application;

[0058] Figure 16 shows a timing diagram of initiating an I2C write operation to send a command packet and the status information of the status packet is success, and a timing diagram of initiating an I2C write operation to send a command packet and the status information of the status packet is failure, according to an embodiment of the present application;

[0059] Figure 17 shows a timing diagram of initiating an I2C write operation to send a command packet and the subsequent I2C operation is an I2C read operation, according to an embodiment of the present application;

[0060] Figure 18 shows a timing diagram of initiating an I2C write operation to send a command packet and the subsequent I2C operation is an I2C read operation, according to another embodiment of the present application;

[0061] Figure 19 shows a timing diagram of initiating an I2C write operation to send a command packet and the status information of the status packet is success, according to another embodiment of the present application;

[0062] Figure 20 shows a timing diagram of initiating an I2C write operation to send a command packet and the status information of the status packet is failure, according to another embodiment of the present application;

[0063] Figure 21 shows a structural diagram of an interface system according to an embodiment of the present application, in which the main controller is an SPI main controller and the interface module is an SPI interface module;

[0064] Figure 22 shows a data structure of a command packet according to an embodiment of the present application, in which the main controller is an SPI main controller and the interface module is an SPI interface module;

[0065] Figure 23 shows a timing diagram of an SPI data write according to a first embodiment of the present application;

[0066] Figure 24 shows a timing diagram of an SPI data write according to a second embodiment of the present application;

[0067] Figure 25 shows a timing diagram of an SPI data write according to a third embodiment of the present application.

[0068] The meanings of the textual labels in the above figures are as follows:

[0069] 100: main controller; 100a: I2C main controller; 100b: SPI main controller;

[0070] 200: interface module; 200a: I2C interface module; 200b: SPI interface module;

[0071] 300: functional module;

[0072] SDA: I2C data line; SCL: I2C clock line;

[0073] S: indicates an I2C START signal, and the corresponding I2C bus state is that when the SCL is high, the SDA appears a jump from high level to low level;

[0074] P: indicates I2C STOP signal, the corresponding I2C bus state is that SDA appears a jump from low level to high level when SCL is high level;

[0075] Sr: the corresponding I2C bus state is the same as S;

[0076] Sr / P: the corresponding I2C bus state is Sr or P;

[0077] ADR: I2C address;

[0078] R / W: indicates read-write operation indication bit, when the bit is R, it indicates that the current is I2C read operation, when the bit is W, it indicates that the current is I2C write operation;

[0079] R: indicates read operation indication bit, the corresponding I2C bus state is that SDA is high level during SCL is high level;

[0080] W: indicates write operation indication bit, the corresponding I2C bus state is that SDA is low level during SCL is high level;

[0081] BYTE: write operation data or read operation data, usually a multi-byte sequence, the content in the bracket after it indicates the serial number of the byte in the sequence, the command package is sent through the write operation data, the read data or status information is read through the read operation data, the one with smaller serial number value is sent first;

[0082] A: indicates I2C ACK, the corresponding I2C bus state is that SDA is always low level during SCL is high level;

[0083] N: indicates I2C NAK, the corresponding I2C bus state is that SDA is always high level during SCL is high level;

[0084] STATUS: byte containing status information and sequence of I2C ACK / I2C NAK between bytes;

[0085] A / N: the corresponding I2C bus state is that SDA is always high level or always low level during SCL is high level:

[0086] HOLD: SCL is continuously low level;

[0087] IDLE: the corresponding I2C bus state includes the following two possibilities:

[0088] (1) SCL and SDA are both high level;

[0089] (2) SCL and SDA can appear other level states, but the combination of these level states does not appear legal I2C operation, at the end of IDLE, SCL and SDA are both high level;

[0090] SPI_CK: SPI_CK signal line; SPI_MOSI: SPI_MOSI signal line; SPI_MISO: SPI_MISO signal line; SPI_CSN: SPI_CSN signal line. DETAILED DESCRIPTION

[0091] In order to make the above and other features and advantages of the present application more comprehensible, further descriptions will be given below with reference to the accompanying drawings. It should be understood that the specific embodiments given herein are only for the purpose of illustration and are not restrictive.

[0092] As shown in FIG. 1, according to an embodiment of the present application, an interface system is provided, which comprises a main controller 100, an interface module 200, and a function module 300. The main controller 100 is connected to the interface module 200, and the interface module 200 is connected to the function module 300. The interface module 200 and the function module 300 can be in the same chip, or the same circuit board, or the same device, or can be in different devices. The present application does not limit the distance between the interface module 200 and the function module 300. The interface module 200 and the function module 300 can communicate through existing or self-defined communication protocols.

[0093] As shown in FIG. 2, according to an embodiment of the present application, a method for writing mask data is provided. The main controller 100 sends a command package to the interface module 200, which contains one or more commands. After receiving the command package, the interface module 200 sends the command package to the function module 300. When the interface module 200 sends the command package to the function module 300, it can modify, add or delete the contents in the command package. The present application does not limit or regulate this. After receiving the command package, the function module 300 executes the commands contained in the command package and returns a status package to the interface module 200, including: when the result of executing each command contained in the command package by the function module 300 is successful, the function module 300 returns a status package with successful status information; when the result of executing at least one command contained in the command package by the function module 300 is unsuccessful, the function module 300 returns a status package with unsuccessful status information. After receiving the status package from the function module 300, the interface module 200 returns the status information of the status package to the main controller 100.

[0094] As shown in FIG. 3, the command package contains one or more commands. An exemplary command package contains command 1, command 2, …, command K.

[0095] In one embodiment, the functional module 300 receives the command package and executes one or more commands contained in the command package, when the execution result of one command is failure, the functional module 300 stops executing the subsequent commands, and the functional module 300 returns the status information to the interface module 200 as a status package of failure. In another embodiment, when the execution result of one command is failure, the functional module 300 can choose to continue executing the subsequent commands, and the functional module 300 returns the status information to the interface module 200 as a status package of failure.

[0096] As shown in FIG. 4, in one application embodiment of the present application, the command package contains one or more commands, and at least one command is a write mask command, the write mask command contains an address field, a data field, and a mask field.

[0097] In this embodiment, the specific structure of the write mask command is shown in FIG. 5. The lower 6 bits of byte 0 in FIG. 5 is a command category identification field, and "001000" indicates that the command is a write mask command. The write mask command further contains an 8-bit register base address field SEG[7:0], a 10-bit register offset address field ADDR[9:0], a 16-bit data field Data[15:0], and a 16-bit mask field MASK[15:0]. The 8-bit register base address field SEG[7:0] and the 10-bit register offset address field ADDR[9:0] are collectively referred to as an address field Address. In other embodiments, the positions and bit widths of the command category identification field, the address field, the data field, and the mask field in the write mask command can be different from those in this embodiment, or there can be no command category identification field. The present application does not limit the positions and bit widths of the address field, the data field, and the mask field in the write mask command.

[0098] After the functional module 300 receives the command package, the commands contained in the command package are executed, wherein executing the write mask command includes: writing the bits of the data field of the write mask command corresponding to the bits of the mask field of the write mask command which are 1 into the storage space pointed to by the address field of the write mask command. For example, if the mask field MASK is a 16-bit binary sequence "0001000100010001", then the 0th, 4th, 8th, and 12th bits from the low bit to the high bit of the data field Data should be written into the 0th, 4th, 8th, and 12th bits of the storage space, and the remaining bits of the storage space remain unchanged.

[0099] In some application embodiments, the storage space itself supports the write mask function (e.g. SRAM supporting the write mask function), and the functional module 300 can directly send the address field Address, the data field Data, and the mask field MASK to the storage space, and the storage space can complete the write mask function. In other application embodiments, the storage space itself does not support the write mask function, and the functional module 300 can read out the data in the storage space pointed by the address field Address as read data rdata, perform a bitwise logical AND operation between the mask field MASK and the data field Data, perform a bitwise logical AND operation between the inverse of the mask field MASK and the read data rdata, and perform a bitwise logical OR operation between the results of the two logical AND operations as the data to be written wdata, and then write the data to be written wdata into the storage space pointed by the address field Address.

[0100] As shown in FIG. 6, in another application embodiment of the present application, the command packet contains one or more commands, at least one of which is a write mask command, and at least one of which is a write command, the write mask command contains an address field, a data field, and a mask field, and the write command contains an address field and a data field.

[0101] In this embodiment, the specific structure of the write mask command is shown in FIG. 5, and the specific structure of the write command is shown in FIG. 7. The lower 6 bits of byte 0 in FIG. 7 are the command type identification field, and "000000" indicates that the command is a write command. The write command further contains an 8-bit register base address field SEG[7:0], a 10-bit register offset address field ADDR[9:0], and a 16-bit data field Data[15:0]. The 8-bit register base address field SEG[7:0] and the 10-bit register offset address field ADDR[9:0] are collectively referred to as the address field Address. In other embodiments, the positions and bit widths of the command type identification field, the address field, and the data field in the write command can be different from those in this embodiment, or the command type identification field can be omitted, and the present application does not limit the positions and bit widths of the address field and the data field in the write command.

[0102] After the functional module 300 receives the command packet, the functional module 300 executes the commands contained in the command packet, and executing the write command includes writing the data field in the write command into the storage space pointed by the address field in the write command.

[0103] As shown in FIG. 8, in another application embodiment of the present application, the command packet contains one or more commands, at least one of which is a write mask command, and at least one of which is a read command, the write mask command contains an address field, a data field, and a mask field, and the read command contains an address field.

[0104] In the embodiment, the specific structure of the write mask command is shown in Fig. 5, and the specific structure of the read command is shown in Fig. 9. In Fig. 9, the lower 6 bits of byte 0 are the command class identifier field, and "010000" indicates that the command is a read command. The read command further includes an 8-bit register base address field SEG[7:0], a 10-bit register offset address field ADDR[9:0], and an 8-bit register base address field SEG[7:0] and a 10-bit register offset address field ADDR[9:0] are collectively referred to as the address field Address. In other embodiments, the positions and bit widths of the command class identifier field and the address field in the read command can be different from those in the embodiment, or the command class identifier field can be omitted, and the present application does not limit the positions and bit widths of the address field in the read command.

[0105] After the functional module 300 receives the command packet, the functional module 300 executes the command included in the command packet. The execution of the read command includes reading out the data in the storage space pointed to by the address field in the read command.

[0106] After the functional module 300 executes the read command included in the command packet, the functional module 300 not only returns the status packet to the interface module 200, but also returns the read data to the interface module 200. After the interface module 200 receives the read data and the status packet from the functional module 300, the interface module 200 returns the status information of the read data and the status packet to the host controller 100.

[0107] As shown in Fig. 10, in another application embodiment of the present application, the command packet includes one or more commands, at least one of which is a write mask command, at least one of which is a write command, and at least one of which is a read command. The write mask command includes an address field, a data field, and a mask field. The write command includes an address field and a data field. The read command includes an address field.

[0108] In the embodiment, the specific structure of the write mask command is shown in Fig. 5, the specific structure of the write command is shown in Fig. 7, and the specific structure of the read command is shown in Fig. 9.

[0109] As shown in Fig. 11, in one embodiment, the host controller 100 is an I2C host controller 100a, and the interface module 200 is an I2C interface module 200a.

[0110] The I2C host controller 100a connects the I2C interface module 200a through an I2C clock line (SCL) and an I2C data line (SDA). The I2C host controller 100a initiates an I2C write operation to send a command packet to the I2C interface module 200a. After the I2C interface module 200a receives the command packet, the I2C interface module 200a pulls down the I2C clock line (SCL) and sends the command packet to the functional module 300.

[0111] The function module 300 receives the command packet, executes one or more commands contained in the command packet, and returns a status packet to the I2C interface module 200a. The I2C interface module 200a receives the status packet from the function module 300 and returns status information of the status packet to the I2C master controller 100a, including:

[0112] When the I2C interface module 200a receives the status packet from the function module 300 and the status information of the status packet is success, the I2C interface module 200a stops pulling down the I2C clock line (SCL) level and returns I2C ACK to the I2C master controller 100a.

[0113] When the I2C interface module 200a receives the status packet from the function module 300 and the status information of the status packet is failure, the I2C interface module 200a stops pulling down the I2C clock line (SCL) level and returns I2C NAK to the I2C master controller 100a.

[0114] As shown in FIG. 12, the I2C write operation contains a write address byte and one or more write operation data bytes (BYTE(1), …, BYTE(N) with shading). The write address byte is the first transmitted byte, and the write address byte includes an I2C address (ADR) and a write operation indication bit (W). According to the standard I2C specification, the write operation indication bit (W) is low.

[0115] In this embodiment, the write address byte and the write operation data byte are both 8 bits, and the write address byte contains 7 bits of the I2C address (ADR) and 1 bit of the write operation indication bit (W). The present application does not limit the number of bits of the write address byte and the write operation data byte. In other embodiments, the write address byte and the write operation data byte can have other numbers of bits.

[0116] When the I2C master controller 100a initiates the I2C write operation, the I2C master controller 100a first drives the I2C clock line (SCL) and the I2C data line (SDA) according to the standard I2C specification to generate an I2C START signal (S), and then transmits the write address byte. After receiving the write address byte, the I2C interface module 200a drives the I2C data line (SDA) to generate a response bit. According to the standard I2C specification, the response bit can be I2C ACK (I2C data line level low) or I2C NAK (I2C data line level high).

[0117] When the response bit of the write address byte is I2C ACK, the I2C master controller 100a can send one or more write operation data bytes, and the I2C interface module 200a drives the I2C data line (SDA) to generate a response bit after receiving each write operation data byte, the response bit of the write operation data byte can be I2C ACK (the I2C data line is low) or I2C NAK (the I2C data line is high).

[0118] According to the standard I2C specification, when sending the write address byte and one or more write operation data bytes, the I2C master controller 100a sends the number of bits contained in the write address byte and the write operation data byte by driving the I2C data line (SDA), and for each bit contained in the write address byte and the write operation data byte, the I2C master controller 100a drives the I2C clock line (SCL) to generate a clock pulse.

[0119] According to the standard I2C specification, the I2C master controller 100a also drives the I2C clock line (SCL) to generate a clock pulse corresponding to the response bit of the write address byte and the response bit of the write operation data byte. The I2C master controller 100a ends the current write operation by sending the I2C STOP signal (P) or the I2C START signal (S) defined in the standard I2C specification.

[0120] As shown in FIG. 13, the I2C read operation includes a read address byte and one or more read operation data bytes (BYTE(1), …, BYTE(N), no shading), the read address byte is the first byte, sent by the I2C master controller 100a, and the one or more read operation data bytes are sent by the I2C interface module 200a, the read address byte contains an I2C address (ADR) and a read operation indication bit (R), according to the standard I2C specification, the read operation indication bit (R) is high.

[0121] In this embodiment, the read address byte and the read operation data byte are both 8 bits, and the read address byte contains 7 bits of the I2C address (ADR) and 1 bit of the read operation indication bit (R). The present application does not limit the number of bits of the read address byte and the read operation data byte, and in other embodiments, the read address byte and the read operation data byte can have other numbers of bits.

[0122] When I2C master controller 100a initiates an I2C read operation, I2C master controller 100a first drives I2C clock line and I2C data line according to standard I2C specification to generate I2C START signal (S), and then sends a read address byte. After receiving the read address byte, I2C interface module 200a drives I2C data line to generate a response bit. According to standard I2C specification, the response bit can be I2C ACK (I2C data line is low) or I2C NAK (I2C data line is high).

[0123] When the response bit of the read address byte is I2C ACK, I2C interface module 200a can return one or more read operation data bytes by driving I2C data line. After receiving each read operation data byte, I2C master controller 100a drives I2C data line to generate a response bit. The response bit of the read operation data byte can be I2C ACK (I2C data line is low) or I2C NAK (I2C data line is high).

[0124] According to standard I2C specification, when I2C master controller 100a sends a read address byte and I2C interface module 200a returns one or more read operation data bytes, I2C master controller 100a sends the number of bits contained in the read address byte by driving I2C data line, and I2C interface module 200a returns the number of bits contained in the read operation data byte by driving I2C data line. For each bit contained in the read address byte and the read operation data byte, I2C master controller 100a drives I2C clock line to generate a clock pulse.

[0125] According to standard I2C specification, for the response bit of the read address byte and the response bit of the read operation data byte, I2C master controller 100a also drives I2C clock line to generate a clock pulse. I2C master controller 100a ends the current read operation by sending I2C STOP signal (P) or I2C START signal (S) defined in standard I2C specification.

[0126] An I2C write operation or an I2C read operation is started by I2C START signal (S), but there are two ways to end it. The first way is to end with I2C STOP signal (P), and the timing is shown in FIG. 12 and FIG. 13.

[0127] The second way is to generate a new I2C START signal (S) to enter the next I2C write operation or I2C read operation, and the timing is shown in FIG. 14. In FIG. 14, the dashed line (such lines in other figures) between the response bit (A / N) and the I2C START signal (Sr) is because the timing diagram is too long to be described in the same row, so it is split into multiple rows, indicating that there is a connection relationship between the two timing diagrams.

[0128] The end of the I2C operation (I2C write operation or I2C read operation) is described in the embodiment by using the I2C STOP signal (P) for convenience of description.

[0129] The command packet in the application is sent by writing operation data bytes (BYTE (1), …, BYTE (N), shaded), as shown in FIG. 3, two command packet embodiments are given:

[0130] The command packet can only contain command 1, command 2, …, command K.

[0131] The command packet can also contain the command packet length field and command 1, command 2, …, command K.

[0132] Wherein "BYTE (1), …, BYTE (N)" indicates one or more write operation data bytes, and "command 1, command 2, …, command K" indicates one or more commands.

[0133] The command in FIG. 3 can be a write mask command, or a write command, or a read command. A command packet can contain one or more of the three types of commands: write mask command, write command, and read command. Each type of command can have one or more commands, as shown in FIGS. 4, 6, 8, and 10.

[0134] It should be noted that the application does not limit the format of the command packet, that is, the format of the command packet in the application is not limited to the two command packet embodiments shown in FIG. 3. The I2C master controller 100a and the I2C interface module 200a can agree on other command packet formats. The application also does not limit the type of command contained in the command packet and the number of commands of each type.

[0135] For example, when the I2C master controller 100a initiates a command packet, the I2C master controller 100a initiates an I2C write operation to send the write address byte and one or more write operation data bytes (BYTE (1), …, BYTE (N), shaded) containing the command packet to the I2C interface module 200a.

[0136] The I2C interface module 200a has a logic circuit of an I2C interface, and the I2C interface module 200a receives and responds to data from the I2C master controller 100a. The I2C interface module 200a and the I2C master controller 100a are interconnected through an I2C bus (I2C clock line and I2C data line), one I2C master controller 100a is connected with one or more I2C interface modules 200a, and each I2C interface module 200a has a unique I2C address (ADR) on the I2C bus (I2C clock line and I2C data line) where it is located. According to the standard I2C specification, each I2C write operation or I2C read operation except I2C write broadcast is only for one I2C address (ADR), and the I2C interface module 200a using other I2C addresses does not participate in the I2C write operation or I2C read operation.

[0137] As shown in FIG. 15, in a specific embodiment, the I2C interface module 200a has an I2C address 0x50 (corresponding to a write address byte 0xA0 or a binary value 1010000) with a length of 7 bits, and the I2C master controller 100a initiates an I2C write operation to sequentially write 0x06, 0x11, 0x21, 0x31, 0x41, 0x51, and 0x61, a total of 7 bytes of write operation data to the I2C interface module 200a, and the 7 bytes of write operation data contains a command packet. The 0xA0 byte corresponds to a write address byte, the high 7 bits of which correspond to the I2C address (ADR) of the I2C interface module 200a, and the low 1 bit is a write operation indication bit (W), and the value of the write operation indication bit (W) is 0, indicating that the current is a write operation, and the value of this byte is a binary number 10100000, i.e., a hexadecimal number 0xA0.

[0138] In this example, the command packet format can be two command packet embodiments as shown in FIG. 3, or other command packet formats agreed between the I2C master controller 100a and the I2C interface module 200a.

[0139] In the present application, the I2C interface module 200a receives the write operation data containing a complete command packet as indicated by the command packet. As shown in the embodiment of FIG. 15, the 7 bytes of write operation data containing a complete command packet, i.e., 0x06, 0x11, 0x21, 0x31, 0x41, 0x51, and 0x61, so the I2C interface module 200a receives the last bit of the 0x61 byte, i.e., the I2C interface module 200a receives the command packet.

[0140] As shown in FIG. 3, the command packet can contain a command packet length field, and the I2C interface module 200a can determine whether the received write operation data contains a complete command packet based on the command packet length field (or part of the command packet length field) according to an agreement between the I2C interface module 200a and the I2C master controller 100a. As shown in FIG. 3, the command packet can also not contain a command packet length field, in which case the I2C interface module 200a can determine whether the received write operation data contains a complete command packet according to an agreement between the I2C interface module 200a and the I2C master controller 100a (which is not based on the command packet length field).

[0141] In the embodiment shown in FIG. 15, the I2C interface module 200a receives the last bit of the 0x61 byte, receives the command packet, and then pulls the I2C clock line low, and the I2C bus is in a HOLD state (a persistent low level state). The I2C interface module 200a sends the command packet to the function module 300. The function module 300 receives the command packet and executes one or more commands contained in the command packet, i.e., command 1, command 2, …, command K, and then returns a status packet to the I2C interface module 200a, including:

[0142] When the execution result of each command contained in the command packet is successful, the function module 300 returns a status packet with successful status information to the I2C interface module 200a;

[0143] When the execution result of at least one of the commands contained in the command packet is a failure, the function module 300 returns a status packet with failure status information to the I2C interface module 200a.

[0144] In the present application, the I2C interface module 200a can modify, add, or delete the contents in the command packet when sending the command packet to the function module 300, and the present application does not limit or regulate this.

[0145] According to the embodiment of the present application, when the I2C interface module 200a receives the status packet from the function module 300 and the status information of the status packet is successful, the I2C interface module 200a stops pulling the I2C clock line low and returns an I2C ACK to the I2C master controller 100a.

[0146] When the I2C interface module 200a receives the status packet from the function module 300 and the status information of the status packet is a failure, the I2C interface module 200a stops pulling the I2C clock line low and returns an I2C NAK to the I2C master controller 100a.

[0147] The subsequent I2C operation referred to in the present application is relative to the I2C operation before it, and the I2C operation can be an I2C write operation or an I2C read operation.

[0148] As shown in Fig. 16, the case when the I2C interface module 200a receives the status package from the function module 300 and the status information of the status package is success, and the case when the I2C interface module 200a receives the status package from the function module 300 and the status information of the status package is failure, are respectively exemplarily described.

[0149] The I2C master controller 100a initiates an I2C operation (I2C write operation) with a serial number m (m is a natural number), and the I2C operation with a serial number m+1 initiated by the I2C master controller 100a is a subsequent I2C operation (relative to the I2C operation with the serial number m).

[0150] In one embodiment shown in Fig. 16, the I2C master controller 100a sends the command package through the I2C write operation with the serial number m, and the I2C interface module 200a pulls down the I2C clock line after receiving the command package (after receiving BYTE(N)).

[0151] At the first time, the I2C interface module 200a receives the status package from the function module 300 and the status information of the status package is success, and the I2C interface module 200a stops pulling down the I2C clock line and terminates the HOLD state (terminates the persistent low level state).

[0152] At the second time, the I2C interface module 200a returns the I2C ACK to the I2C master controller 100a, and the I2C master controller 100a terminates the I2C operation (I2C write operation) with the serial number m, and initiates the I2C operation (subsequent I2C operation) with the serial number m+1, which is the I2C write operation or the I2C read operation.

[0153] After the I2C interface module 200a returns the I2C ACK in the I2C operation with the serial number m, it continues to receive the subsequent I2C operation initiated by the I2C master controller 100a (i.e. returns the I2C ACK after receiving the read address byte or the write address byte in the I2C operation with the serial number m+1 and continues the I2C operation with the serial number m+1). If the subsequent I2C operation is an I2C write operation, the I2C interface module 200a returns the I2C ACK after receiving the write address byte and continues to receive the write operation byte. If the subsequent I2C operation is an I2C read operation, the I2C interface module 200a returns the I2C ACK after receiving the read address byte and continues to return the status information (STATUS) of the status packet (the part of the subsequent I2C operation after the read address byte or the write address byte is not shown in Fig. 16). If the command packet sent by the I2C write operation with the serial number m contains a read command, the subsequent I2C operation should be an I2C read operation, the I2C interface module 200a returns the I2C ACK after receiving the read address byte and continues to return the status information (STATUS) and the read data of the status packet.

[0154] In another embodiment shown in Fig. 16, the I2C master controller 100a sends a command packet through the I2C write operation with the serial number m, and the I2C interface module 200a pulls down the I2C clock line after receiving the command packet (after receiving the BYTE(N)).

[0155] At the first time, the I2C interface module 200a receives the status packet from the function module 300 and the status information of the status packet is failure, the I2C interface module 200a stops pulling down the I2C clock line and terminates the HOLD state (terminates the continuous low level state).

[0156] At the second time, the I2C interface module 200a returns the I2C NAK to the I2C master controller 100a, and the I2C master controller 100a terminates the I2C operation (I2C write operation) with the serial number m.

[0157] If the I2C master controller 100a initiates a subsequent I2C operation after the I2C interface module 200a returns the I2C NAK in the I2C operation with the serial number m, and the subsequent I2C operation is an I2C write operation, the I2C interface module 200a returns the I2C NAK to the I2C master controller 100a after receiving the write address byte, so that the subsequent I2C operation (I2C write operation) is terminated. If the I2C master controller 100a initiates a subsequent I2C operation after the I2C interface module 200a returns the I2C NAK in the I2C operation with the serial number m, and the subsequent I2C operation is an I2C read operation, the I2C interface module 200a returns the I2C ACK to the I2C master controller 100a after receiving the read address byte, and continues to return the status information (STATUS) of the status packet. After completing the subsequent I2C operation (I2C read operation), the I2C interface module 200a can continue to receive a further subsequent I2C operation initiated by the I2C master controller 100a (part of the subsequent I2C operation is not shown in FIG. 16).

[0158] In the present application, the status information (STATUS) can be success or failure information contained in the status packet, or can contain other information contained in the status packet. In an embodiment, the status information (STATUS) can contain execution result information of each command in the command packet executed by the function module 300. After receiving the status information, the I2C master controller 100a can know the execution of each command in the command packet by the function module 300 according to the status information, and then can perform subsequent processing according to the execution. As shown in the embodiment of FIG. 16, when the I2C interface module 200a receives the status packet from the function module 300, the I2C interface module 200a stops pulling down the I2C clock line, and returns the I2C ACK (when the status information of the status packet is success) or the I2C NAK (when the status information of the status packet is failure) to the I2C master controller 100a. If the I2C master controller 100a initiates a subsequent I2C operation after the I2C interface module 200a returns the I2C NAK in the I2C operation with the serial number m, and the subsequent I2C operation is an I2C read operation, the I2C interface module 200a returns the I2C ACK to the I2C master controller 100a after receiving the read address byte, and continues to return the status information (STATUS) of the status packet.

[0159] As shown in the embodiment of Fig. 17, the I2C master controller 100a sends a command package through an I2C write operation with serial number m, at the first time, the I2C interface module 200a pulls down the I2C clock line after receiving the command package (after receiving the BYTE(N)), at the second time, the I2C interface module 200a stops pulling down the I2C clock line after receiving the status package from the functional module 300, and returns the I2C ACK or I2C NAK to the I2C master controller 100a, in this case, the I2C ACK or I2C NAK can be self-agreed between the I2C master controller 100a and the I2C interface module 200a. After the I2C interface module 200a stops pulling down the I2C clock line and returns the I2C ACK or I2C NAK to the I2C master controller 100a, if the I2C master controller 100a initiates a subsequent I2C operation and the subsequent I2C operation is an I2C write operation, after the I2C interface module 200a receives the write address byte, the I2C interface module 200a returns the I2C NAK to the I2C master controller 100a, so that the subsequent I2C operation (I2C write operation) is terminated, if the I2C master controller 100a initiates a subsequent I2C operation and the subsequent I2C operation is an I2C read operation, after the I2C interface module 200a receives the read address byte, the I2C interface module 200a returns the I2C ACK to the I2C master controller 100a and continues to return the status information (STATUS) of the status package, if the command package sent by the I2C write operation with serial number m contains a read command, the I2C interface module 200a should also return the read data to the I2C master controller 100a, after completing the subsequent I2C operation (I2C read operation), the I2C interface module 200a can continue to receive the subsequent I2C operation initiated by the I2C master controller 100a (in this case, the part of the subsequent I2C operation which is an I2C write operation is not shown in Fig. 17).

[0160] According to the embodiment of the present application, the I2C master controller 100a connects the I2C interface module 200a through the I2C clock line and the I2C data line, the I2C master controller 100a initiates an I2C write operation to send a command package to the I2C interface module 200a, and the I2C interface module 200a sends the command package to the functional module 300 after receiving the command package.

[0161] After the functional module 300 receives the command package, one or more commands contained in the command package are executed, i.e. command 1, command 2, …, command K, and then a status package with successful status information is returned to the I2C interface module 200a.

[0162] When the execution result of each command contained in the command package is successful, the functional module 300 returns a status package with successful status information to the I2C interface module 200a.

[0163] When the execution result of at least one of the commands contained in the command package is failure, the function module 300 returns a state package with the state information of failure to the I2C interface module 200a.

[0164] In the present application, when the I2C interface module 200a sends the command package to the function module 300, the content in the command package can be modified, added or deleted, which is not limited or regulated in the present application.

[0165] The function module 300 returns the state package to the I2C interface module 200a, and the I2C interface module 200a returns the state information of the state package to the I2C master controller 100a, including:

[0166] After the I2C interface module 200a receives the command package, if the subsequent I2C operation initiated by the I2C master controller 100a is I2C read operation, and the I2C interface module 200a receives the state package from the function module 300, the I2C interface module 200a returns the state information of the state package to the I2C master controller 100a.

[0167] If the subsequent I2C operation initiated by the I2C master controller 100a is I2C write operation, and the I2C interface module 200a receives the state package from the function module 300 and the state information of the state package is success, the I2C interface module 200a receives the subsequent I2C write operation initiated by the I2C master controller 100a;

[0168] If the subsequent I2C operation initiated by the I2C master controller 100a is I2C write operation, and the I2C interface module 200a receives the state package from the function module 300 and the state information of the state package is failure, the I2C interface module 200a returns I2C NAK to the I2C master controller 100a.

[0169] As shown in FIG. 18, the I2C operation with the serial number m initiated by the I2C master controller 100a is I2C write operation, and the command package is sent to the I2C interface module 200a. For the first N-1 write operation data bytes (BYTE(1), …, BYTE(N-1)), after each write operation data byte is sent, the I2C interface module 200a returns I2C ACK to the I2C master controller 100a.

[0170] After the I2C interface module 200a receives the Nth write operation data byte (BYTE(N)), that is, after the I2C interface module 200a receives the complete command packet, the I2C interface module 200a can return an I2C ACK or an I2C NAK to the I2C master controller 100a, which is selected by an agreement between the I2C master controller 100a and the I2C interface module 200a. The I2C master controller 100a and the I2C interface module 200a can agree that, after the Nth write operation data byte (BYTE(N)), whether the I2C ACK or the I2C NAK indicates the successful reception of the Nth write operation data byte (that is, the complete command packet). In the following description of the present application, after the Nth write operation data byte (BYTE(N)), whether the I2C interface module 200a returns the I2C ACK or the I2C NAK to the I2C master controller 100a indicates the successful reception of the Nth write operation data byte (that is, the complete command packet).

[0171] After the I2C master controller 100a completes the sending of the Nth write operation data byte (BYTE(N)), whether the I2C interface module 200a returns the I2C ACK or the I2C NAK to the I2C master controller 100a, the I2C master controller 100a terminates the I2C operation (I2C write operation) with the serial number m and can select to initiate the I2C operation (subsequent I2C operation) with the serial number m+1.

[0172] When the I2C operation (subsequent I2C operation) with the serial number m+1 is an I2C read operation, if the I2C interface module 200a receives the status packet (corresponding to the I2C operation with the serial number m) from the functional module 300, after the I2C master controller 100a sends the read address byte, the I2C interface module 200a returns the I2C ACK to the I2C master controller 100a and returns the status information (STATUS) of the status packet. If the command packet sent by the I2C write operation with the serial number m contains a read command, the I2C interface module 200a should also return the read data to the I2C master controller 100a.

[0173] As shown in FIGS. 19 and 20, the I2C operation (subsequent I2C operation) with the serial number m initiated by the I2C master controller 100a is an I2C write operation, and the command packet is sent to the I2C interface module 200a. For the first N-1 write operation data bytes (BYTE(1), …, BYTE(N-1)), after each write operation data byte is sent, the I2C interface module 200a returns the I2C ACK to the I2C master controller 100a.

[0174] I2C interface module 200a receives the Nth write operation data byte (BYTE(N)), (i.e. I2C interface module 200a receives the complete command packet), I2C interface module 200a can return I2C ACK or I2C NAK to I2C master controller 100a.

[0175] After I2C master controller 100a completes the transmission of the Nth write operation data byte (BYTE(N)), regardless of whether I2C interface module 200a returns I2C ACK or I2C NAK to I2C master controller 100a, I2C master controller 100a terminates the I2C operation (I2C write operation) with sequence number m and can choose to initiate the I2C operation (subsequent I2C operation) with sequence number m+1.

[0176] When the I2C operation (subsequent I2C operation) with sequence number m+1 is an I2C write operation, if I2C interface module 200a receives the status packet (corresponding status packet during the I2C operation with sequence number m) from functional module 300 and the status information of the status packet is success, after I2C master controller 100a transmits the write address byte, I2C interface module 200a returns I2C ACK to I2C master controller 100a, and I2C interface module 200a receives the write operation data byte transmitted by I2C master controller 100a initiating the I2C operation (subsequent I2C operation / I2C write operation) with sequence number m+1, as shown in FIG. 19.

[0177] When the I2C operation (subsequent I2C operation) with sequence number m+1 is an I2C write operation, if I2C interface module 200a receives the status packet (corresponding status packet during the I2C operation with sequence number m) from functional module 300 and the status information of the status packet is failure, after I2C master controller 100a transmits the write address byte, I2C interface module 200a returns I2C NAK to I2C master controller 100a, and I2C master controller 100a terminates the I2C operation (subsequent I2C operation / I2C write operation) with sequence number m+1, as shown in FIG. 20.

[0178] As shown in FIG. 11, in another embodiment, master controller 100 is I2C master controller 100a, and interface module 200 is I2C interface module 200a. I2C master controller 100a initiates an I2C write operation to transmit a command packet to I2C interface module 200a, and then I2C master controller 100a initiates a subsequent I2C read operation to read status information,

[0179] In this example, after I2C master controller 100a initiates an I2C write operation to transmit a command packet to I2C interface module 200a, I2C master controller 100a initiates a subsequent I2C read operation to read status information,

[0180] The I2C interface module 200a pulls down the I2C clock line after receiving the address byte of the subsequent I2C read operation, and sends the received command package to the function module 300,

[0181] After the function module 300 receives the command package, it executes one or more commands contained in the command package, and returns a status package to the I2C interface module 200a, including:

[0182] When the execution result of each command contained in the command package is successful, the function module 300 returns a status package with successful status information to the I2C interface module 200a,

[0183] When the execution result of at least one command contained in the command package is failed, the function module 300 returns a status package with failed status information to the I2C interface module 200a,

[0184] After the I2C interface module 200a receives the status package from the function module 300, the I2C interface module 200a stops pulling down the I2C clock line, and returns the status information of the status package to the I2C master controller 100a.

[0185] As shown in FIG. 21, in one embodiment, the master controller 100 is an SPI master controller 100b, and the interface module 200 is an SPI interface module 200b. The SPI master controller 100b is connected to the SPI interface module 200b through an SPI_CK signal line, an SPI_MOSI signal line and an SPI_MISO signal line.

[0186] The SPI master controller 100b generates a clock edge on the SPI_CK signal line, and sends a command package to the SPI interface module 200b through the SPI_MOSI signal line. The command package starts with a first identification field. After the SPI interface module 200b receives the command package from the SPI_MOSI, it sends the command package to the function module 300.

[0187] After the function module 300 receives the command package, it executes one or more commands contained in the command package, i.e., command 1, command 2, …, command K, and then returns a status package to the SPI interface module 200b, including:

[0188] When the execution result of each command contained in the command package is successful, the function module 300 returns a status package with successful status information to the SPI interface module 200b;

[0189] When the execution result of at least one command contained in the command package is failed, the function module 300 returns a status package with failed status information to the SPI interface module 200b.

[0190] In the application, the SPI interface module 200b can modify, add or delete the content in the command packet when sending the command packet to the function module 300, and the application does not limit or regulate this.

[0191] The function module 300 returns the state packet to the SPI interface module 200b, the SPI interface module 200b receives the state packet from the function module 300, and returns the state information of the state packet to the SPI master controller 100b, including:

[0192] After the SPI interface module 200b receives the state packet from the function module 300, when the SPI master controller 100b generates a clock edge on SPI_CK, the SPI interface module 200b sends a feedback packet to the SPI master controller 100b through the SPI_MISO signal line, the feedback packet starts with a second identification field, and the feedback packet contains the state information contained in the state packet.

[0193] As shown in the embodiment of FIG. 22, when the master controller 100 is the SPI master controller 100b and the interface module 200 is the SPI interface module 200b, the data structure of the command packet. Two command packet embodiments are exemplarily given in the embodiment:

[0194] The command packet can contain a first identification field and commands 1, 2, …, K, and start with the first identification field.

[0195] The command packet can also contain a first identification field, a command packet length field, and commands 1, 2, …, K, and start with the first identification field.

[0196] The first identification field, the command packet length field (if present), commands 1, 2, …, K contained in the command packet are composed of binary bit sequences, and the application does not limit the length of the binary bit sequences of the first identification field, the command packet length field (if present), commands 1, 2, …, K.

[0197] The command in FIG. 22 can be a write mask command, or a write command, or a read command. One command packet can contain one or more of the three types of commands: write mask command, write command, and read command, and each type of command can have one or more commands, as shown in FIGS. 4, 6, 8, and 10.

[0198] It should be noted that the application does not limit the format of the command packet, i.e., the command packet format in the application is not limited to the two command packet embodiments shown in FIG. 22. The SPI master controller 100b and the SPI interface module 200b can agree on other command packet formats, and the application does not limit the type of command contained in the command packet and the number of each type of command.

[0199] In the present application, the SPI interface module 200b receives the command packet, the data received by the SPI interface module 200b from the SPI_MOSI signal line contains a complete command packet, as shown in FIG. 22, the command packet can contain a command packet length field, the SPI interface module 200b can determine whether the received data contains a complete command packet based on the command packet length field (or part of the command packet length field) according to the agreement between the SPI master controller 100b and the SPI interface module 200b, as shown in FIG. 22, the command packet can also not contain a command packet length field, in this case, the SPI interface module 200b determines whether the received data contains a complete command packet according to the agreement between the SPI master controller 100b and the SPI interface module 200b (this agreement is not based on the command packet length field).

[0200] The SPI master controller 100b drives the SPI_CK signal line, the SPI master controller 100b generates a clock edge on the SPI_CK signal line, the SPI master controller 100b samples the data on the SPI_MISO signal line through the clock rising edge or the clock falling edge on the SPI_CK signal line, and the SPI interface module 200b samples the data on the SPI_MOSI signal line through the clock rising edge or the clock falling edge on the SPI_CK signal line, to realize the bidirectional transmission of data between the SPI master controller 100b and the SPI interface module 200b.

[0201] The present application does not limit the sampling of the data on the SPI_MISO signal line and the SPI_MOSI signal line through the clock rising edge or the clock falling edge on the SPI_CK signal line, in the embodiments described below in the present application, the data on the SPI_MISO signal line and the SPI_MOSI signal line is sampled through the clock rising edge on the SPI_CK signal line, that is, the clock rising edge on the SPI_CK signal line is the sampling clock edge in the embodiments described below in the present application. In other embodiments of the present application, the data on the SPI_MISO signal line and the SPI_MOSI signal line can also be sampled through the clock falling edge on the SPI_CK signal line, that is, the clock falling edge on the SPI_CK signal line is the sampling clock edge in these embodiments.

[0202] As shown in FIG. 23, the SPI master controller 100b generates a clock edge on the SPI_CK signal line, and drives the SPI_MOSI signal line at the same time, to send a command packet to the SPI interface module 200b through the SPI_MOSI signal line, the command packet contains N bytes, each byte is 8-bit binary data, the first byte is a first identification field, the 8-bit binary data of the first byte is represented as C10, C11…C17, the Nth byte of the command packet is the last byte of the command packet, and the 8-bit binary data of the Nth byte of the command packet is represented as CN0, CN1…CN7.

[0203] The SPI interface module 200b samples the data on the SPI_MOSI signal line on the clock rising edge of the SPI_CK signal line, receives the command package from the SPI_MOSI signal line, and when the SPI interface module 200b samples the CN7 bit, the data received from the SPI_MOSI signal line contains a complete command package, and the SPI interface module 200b receives the command package.

[0204] After the SPI interface module 200b receives the command package from the SPI_MOSI signal line, the command package is sent to the functional module 300. In the present application, when the SPI interface module 200b sends the command package to the functional module 300, the content in the command package can be modified, added or deleted, and the present application does not limit or regulate this.

[0205] After the functional module 300 receives the command package, one or more commands contained in the command package, i.e., command 1, command 2, …, command K, are executed, and then a status package is returned to the SPI interface module 200b, including:

[0206] When the execution result of each command contained in the command package is successful, the functional module 300 returns a status package with successful status information to the SPI interface module 200b;

[0207] When the execution result of at least one command in the command package is failed, the functional module 300 returns a status package with failed status information to the SPI interface module 200b.

[0208] At the first time, the SPI interface module 200b receives the status package, the SPI master controller 100b generates a clock edge on the SPI_CK signal line, the SPI interface module 200b drives the SPI_MISO signal line, and sends a feedback package through the SPI_MISO signal line. The SPI master controller 100b samples the data on the SPI_MISO signal line on the clock rising edge of the SPI_CK signal line, reads the feedback package, and the feedback package starts with a second identification field. The feedback package contains the status information contained in the status package, which can be success and failure, or other status information. In an embodiment, the status information can contain the execution result information of each command in the command package executed by the functional module 300. After receiving the feedback package, the SPI master controller 100b can know the execution situation of each command in the command package by the functional module 300 according to the feedback package, and then can perform subsequent processing according to the execution situation.

[0209] The feedback packet includes M bytes, each byte is 8-bit binary data, the first byte is the second identification field, the 8-bit binary data of the first byte is represented as A10, A11...A17, the Mth byte of the feedback packet is the last byte of the feedback packet, and the 8-bit binary data of the Mth byte of the feedback packet is represented as AM0, AM1...AM7.

[0210] For easy understanding, in the embodiment shown in FIG. 23 and the description hereinafter of the present application, each byte is described as 8-bit binary data, but the present application does not limit the number of bits of each byte, and each byte can also be other number of bits.

[0211] In the embodiment shown in FIG. 23, the lengths of the first identification field and the second identification field are one byte, and the lengths of the command packet and the feedback packet are integral multiples of bytes. For easy understanding, in the description hereinafter of the present application, the lengths of the first identification field and the second identification field are one byte, and the lengths of the command packet, the feedback packet (including the success feedback packet and the failure feedback packet) are integral multiples of bytes, but the present application does not limit the lengths of the first identification field and the second identification field to be one byte, nor limit the lengths of the first identification field and the second identification field to be integral multiples of bytes, nor limit the lengths of the command packet, the feedback packet (including the success feedback packet and the failure feedback packet) to be integral multiples of bytes.

[0212] In the interval identified as "no clock edge", the SPI master controller 100b does not generate a sampling clock edge on the SPI_CK signal line. In the description of the embodiment hereinafter of the present application, the levels on the SPI_MOSI and SPI_MISO signal lines do not change in the "no clock edge" interval, but the present application does not limit the levels on the SPI_MOSI and SPI_MISO signal lines in the "no clock edge" interval, and the levels on the SPI_MOSI and SPI_MISO signal lines can also change in the "no clock edge" interval, but because the sampling of the data on the SPI_MOSI and SPI_MISO signal lines is only performed at the sampling clock edge (the rising clock edge in the embodiment shown in FIG. 23) on the SPI_CK signal line, the change of the levels on the SPI_MOSI and SPI_MISO signal lines in the "no clock edge" interval will not be received by sampling.

[0213] In the embodiment shown in FIG. 23, the SPI master controller 100b generates a clock edge on the SPI_CK signal line while driving the SPI_MOSI signal line, and the SPI interface module 200b has no feedback packet to send through the SPI_MOSI signal line at this time, so the SPI interface module 200b drives the SPI_MISO signal line to high level during this period. During this period, the SPI interface module 200b can also drive the SPI_MISO signal line to low level or a varying level, but the SPI interface module 200b should ensure that the level value or varying level value driven by it on the SPI_MISO signal line, if sampled by the SPI master controller 100b at the sampling clock edge on the SPI_CK signal line (the clock rising edge in the embodiment shown in FIG. 23), is not identified as the second identification field (i.e., not identified as the valid value of the second identification field, thereby avoiding being identified as a feedback packet). Taking the embodiment shown in FIG. 23 as an example, because the SPI interface module 200b drives the SPI_MISO signal line to high level (sampling is continuous binary bit 1) during this period, in order not to be identified as the second identification field, the value of the second identification field should not be 0xFF.

[0214] In the embodiment shown in FIG. 23, the SPI master controller 100b generates a clock edge on the SPI_CK signal line while driving the SPI_MOSI signal line, and the SPI interface module 200b has no feedback packet to send through the SPI_MOSI signal line at this time, so the SPI interface module 200b drives the SPI_MISO signal line to high level during this period. During this period, the SPI interface module 200b can also drive the SPI_MISO signal line to low level or a varying level, but the SPI interface module 200b should ensure that the level value or varying level value driven by it on the SPI_MISO signal line, if sampled by the SPI master controller 100b at the sampling clock edge on the SPI_CK signal line (the clock rising edge in the embodiment shown in FIG. 23), is not identified as the second identification field (i.e., not identified as the valid value of the second identification field, thereby avoiding being identified as a feedback packet). Taking the embodiment shown in FIG. 23 as an example, because the SPI interface module 200b drives the SPI_MISO signal line to high level (sampling is continuous binary bit 1) during this period, in order not to be identified as the second identification field, the value of the second identification field should not be 0xFF.

[0215] The SPI interface module 200b can be connected to the SPI master controller 100b through the SPI_CSN signal line in addition to the SPI_CK signal line, the SPI_MOSI signal line and the SPI_MISO signal line. The SPI master controller 100b drives the SPI_CSN signal line, the SPI_CK signal line and the SPI_MOSI signal line, and the SPI interface module 200b receives the SPI_CSN signal line, the SPI_CK signal line and the SPI_MOSI signal line. The SPI interface module 200b drives the SPI_MISO signal line, and the SPI master controller 100b receives the SPI_MISO signal line. The SPI_CSN signal line is a selection signal. In the SPI protocol, data transmission is performed only when the SPI_CSN signal line is low. One SPI master controller 100b can be connected to multiple SPI interface modules 200b. The SPI_CK signal line, the SPI_MOSI signal line and the SPI_MISO signal line are shared by the SPI master controller 100b and the multiple SPI interface modules 200b. However, each SPI interface module 200b has an independent SPI_CSN signal line input. When the SPI_CSN signal line of one SPI interface module 200b is high, the SPI interface module 200b does not drive the SPI_MISO signal line (the driver output of the SPI_MISO signal line of the SPI interface module 200b is in the Hi-Z state). One SPI interface module 200b drives the SPI_MISO signal line only when its SPI_CSN signal line is low. When one SPI master controller 100b is connected to multiple SPI interface modules 200b, at any time, only the SPI_CSN signal line of one SPI interface module 200b is low, so that the conflict caused by the simultaneous driving of the SPI_MISO signal line by multiple SPI interface modules 200b can be avoided.

[0216] When one SPI master controller 100b is connected to one SPI interface module 200b, the SPI interface module 200b can drive the SPI_MISO signal line at any time without causing conflict. In this case, the SPI master controller 100b and the SPI interface module 200b can have no SPI_CSN signal line, i.e., the SPI master controller 100b and the SPI interface module 200b can be connected only through the SPI_CK signal line, the SPI_MOSI signal line and the SPI_MISO signal line. The above description of the embodiment shown in FIG. 23 is for this case.

[0217] In the description of the present application, only the case that there is no SPI_CSN signal line between the SPI master controller 100b and the SPI interface module 200b is described, but according to the description of the present application, it is easy to extend to the case that there is an SPI_CSN signal line between the SPI master controller 100b and the SPI interface module 200b, and the case that there is an SPI_CSN signal line between the SPI master controller 100b and the SPI interface module 200b is not described again in the description of the present application. Whether there is an SPI_CSN signal line between the SPI master controller 100b and the SPI interface module 200b or not, it is within the protection scope of the present application.

[0218] According to the embodiment of the present application, the SPI master controller 100b generates a clock edge on the SPI_CK signal line, reads the feedback packet through the SPI_MISO signal line,

[0219] When the SPI interface module 200b does not receive the state packet, the SPI interface module 200b sends data that cannot be recognized as a feedback packet to the SPI master controller 100b through the SPI_MISO signal line.

[0220] For example, as shown in FIG. 24, the SPI master controller 100b generates a clock edge on the SPI_CK signal line, sends a command packet to the SPI interface module 200b through the SPI_MOSI signal line, the SPI interface module 200b receives the command packet from the SPI_MOSI signal line, sends the command packet to the functional module 300, the functional module 300 executes one or more commands contained in the command packet, and then returns a status packet to the SPI interface module 200b. At the third moment, the SPI interface module 200b receives the status packet from the functional module 300. Before the third moment when the SPI interface module 200b receives the status packet from the functional module 300, between the first moment and the second moment, the SPI master controller 100b generates a clock edge on the SPI_CK signal line. In the embodiment shown in FIG. 24, the SPI interface module 200b drives the SPI_MISO signal line to high level during this period. During this period, the SPI interface module 200b can also drive the SPI_MISO signal line to low level or a changing level, but the SPI interface module 200b should ensure that the level value or the changing level value driven by it on the SPI_MISO signal line, if sampled by the sampling clock edge on the SPI_CK signal line (the clock rising edge in the embodiment shown in FIG. 24), is not recognized as the second identification field (i.e. not recognized as the valid value of the second identification field, so as to avoid being recognized as a feedback packet). That is, when the SPI master controller 100b generates a clock edge on the SPI_CK signal line, if the SPI interface module 200b does not receive the status packet from the functional module 300, the SPI interface module 200b sends data through the SPI_MISO signal line to the SPI master controller 100b, which cannot be recognized as a feedback packet. After the SPI interface module 200b receives the status packet from the functional module 300 at the third moment, the SPI master controller 100b generates a clock edge on the SPI_CK signal line, and reads the feedback packet from the SPI interface module 200b through the SPI_MISO signal line.

[0221] In the embodiment shown in FIG. 25, the SPI master controller 100b generates a clock edge on the SPI_CK signal line, sends a command packet to the SPI interface module 200b through the SPI_MOSI signal line, the SPI interface module 200b receives the command packet from the SPI_MOSI signal line, sends the command packet to the functional module 300, the functional module 300 executes one or more commands contained in the command packet, and then returns a status packet to the SPI interface module 200b. At the first time point, the SPI interface module 200b receives the status packet from the functional module 300, the SPI master controller 100b generates a clock edge on the SPI_CK signal line, and reads the feedback packet from the SPI interface module 200b through the SPI_MISO signal line. At the second time point, the SPI master controller 100b completes reading the feedback packet, the SPI interface module 200b completes sending the feedback packet, and the SPI master controller 100b continues to generate a clock edge on the SPI_CK signal line. At this time, the SPI interface module 200b drives the SPI_MISO signal line to be high. During this period, the SPI interface module 200b can also drive the SPI_MISO signal line to be low or to change the level, but the SPI interface module 200b should ensure that the level value or the changing level value driven by it on the SPI_MISO signal line is not recognized as the second identification field (i.e., not recognized as the valid value of the second identification field, so as to avoid being recognized as the feedback packet) if it is sampled by the sampling clock edge (the rising clock edge in the embodiment shown in FIG. 25) on the SPI_CK signal line of the SPI master controller 100b.

[0222] According to the embodiment of the application, the SPI master controller 100b generates a clock edge on the SPI_CK signal line, and sends a command packet to the SPI interface module 200b through the SPI_MOSI signal line.

[0223] Then the SPI master controller 100b generates a clock edge on the SPI_CK signal line, reads the feedback packet through the SPI_MISO signal line, and the SPI interface module 200b can continue to receive a subsequent command packet after sending the feedback packet through the SPI_MISO signal line.

[0224] In the application, the SPI master controller 100b generates a clock edge on the SPI_CK signal line, sends a command package to the SPI interface module 200b through the SPI_MOSI signal line, the SPI interface module 200b sends the command package to the functional module 300 after receiving the command package from the SPI_MOSI signal line, the functional module 300 receiving the command package executes one or more commands contained in the command package, and then returns a state package to the SPI interface module 200b, then the SPI master controller 100b generates a clock edge on the SPI_CK signal line, reads a feedback package through the SPI_MISO signal line, if the SPI master controller 100b drives the SPI_MOSI signal line to send a command package before the SPI master controller 100b reads the feedback package, the SPI interface module 200b can choose not to receive the command package sent by the SPI master controller 100b before the SPI master controller 100b reads the feedback package, and after the SPI master controller 100b reads the feedback package, that is, after the SPI interface module 200b sends the feedback package through the SPI_MISO signal line, the SPI interface module 200b can continue to receive a subsequent command package.

[0225] According to the embodiment of the application, the feedback package can be divided into a success feedback package and a failure feedback package.

[0226] The SPI master controller 100b generates a clock edge on the SPI_CK signal line, reads a feedback package through the SPI_MISO signal line,

[0227] When the SPI interface module 200b receives a state package from the functional module 300 and the state information contained in the state package is success, the SPI interface module 200b sends a success feedback package through the SPI_MISO signal line.

[0228] When the SPI interface module 200b receives a state package from the functional module 300 and the state information contained in the state package is failure, the SPI interface module 200b sends a failure feedback package through the SPI_MISO signal line.

[0229] In the application, the second identification field of the success feedback package is different from the second identification field of the failure feedback package, including that the binary sequence contained in the second identification field of the success feedback package is different from the binary sequence contained in the second identification field of the failure feedback package. The second identification field of the success feedback package and the second identification field of the failure feedback package can adopt the same or different bit width length, and the application does not limit whether the second identification field is fixed length.

[0230] As shown in FIG. 23, the SPI master controller 100b generates a clock edge on the SPI_CK signal line, sends a command package to the SPI interface module 200b through the SPI_MOSI signal line, the SPI interface module 200b receives the command package from the SPI_MOSI signal line, sends the command package to the function module 300, the function module 300 receives the command package, executes one or more commands contained in the command package, and then returns a status package to the SPI interface module 200b, at the first time, the SPI interface module 200b receives the status package from the function module 300. If the status information contained in the status package received by the SPI interface module 200b is success, when the SPI master controller 100b generates a clock edge on the SPI_CK signal line and reads the feedback package from the SPI interface module 200b through the SPI_MISO signal line, the SPI interface module 200b drives the SPI_MISO signal line to send a success feedback package to the SPI master controller 100b through the SPI_MISO signal line; if the status information contained in the status package received by the SPI interface module 200b is failure, when the SPI master controller 100b generates a clock edge on the SPI_CK signal line and reads the feedback package from the SPI interface module 200b through the SPI_MISO signal line, the SPI interface module 200b drives the SPI_MISO signal line to send a failure feedback package to the SPI master controller 100b through the SPI_MISO signal line.

[0231] The second identification field of the success feedback package in the application is different from the second identification field of the failure feedback package, when the SPI master controller 100b reads the feedback package, it can judge whether the read feedback package is a success feedback package or a failure feedback package through the second identification field of the feedback package, therefore, the feedback package can only contain the second identification field, which can make the SPI master controller 100b distinguish whether the read feedback package is a success feedback package or a failure feedback package.

[0232] The master controller 100 in the application can be an I2C master controller 100a and an SPI master controller 100b, and can also be a master controller conforming to other interface protocols (for example, a master controller conforming to a serial port UART protocol, a CAN protocol, a LIN protocol and the like), the interface module 200 in the application can be an I2C interface module 200a and an SPI interface module 200b, and can also be an interface module conforming to other interface protocols (for example, an interface module conforming to a serial port UART protocol, a CAN protocol, a LIN protocol and the like), using a master controller conforming to other interface protocols and an interface module conforming to other interface protocols are also within the protection scope of the application.

[0233] According to the embodiment of the present application, the master controller 100 (I2C master controller 100a or SPI master controller 100b or master controller conforming to other interface protocol) sends a command package to the interface module 200 (I2C interface module 200a or SPI interface module 200b or interface module conforming to other interface protocol), and after the interface module 200 receives the command package, the interface module 200 sends the command package to the function module 300. The command package contains one or more commands, as shown in FIG. 3 and FIG. 22. Each command can be a write mask command, or a write command, or a read command. One command package can contain one or more of the three types of commands, and each type of command can have one or more commands, as shown in FIG. 4, FIG. 6, FIG. 8, and FIG. 10.

[0234] The above merely provides the preferred embodiments of the present application, but the protection scope of the present application is not limited thereto, and any person skilled in the art should cover the changes, modifications, replacements and variations of the above embodiments within the technical range disclosed by the present application in the protection scope of the present application.

Claims

1. A method for writing mask data based on an interface system, the interface system comprising a host controller, an interface module, and a function module, the host controller being connected to the interface module, and the interface module being connected to the function module, characterized in that the host controller sends a command package to the interface module, the command package comprising one or more commands, at least one of the commands being a write mask command, the write mask command comprising an address field, a data field, and a mask field, the interface module, after receiving the command package, sends the command package to the function module, and the function module, after receiving the command package, executes the commands contained in the command package, and the execution of the write mask command comprises writing the bits of the data field of the write mask command corresponding to the bits of the mask field of the write mask command which are 1 into the storage space pointed to by the address field of the write mask command. 2.The method of claim 1, characterized in that the function module, after executing the commands contained in the command package, returns a status package to the interface module, including: when the results of the execution of each command contained in the command package by the function module are all successful, the function module returns a status package with a status information of success, and when the result of the execution of at least one command contained in the command package by the function module is a failure, the function module returns a status package with a status information of failure, and the interface module, after receiving the status package from the function module, returns the status information of the status package to the host controller. 3.The method of claim 1, characterized in that the command package comprises one or more commands, at least one of the commands being a write command, the write command comprising an address field and a data field, the function module, after receiving the command package, executes the commands contained in the command package, and the execution of the write command comprises writing the data field of the write command into the storage space pointed to by the address field of the write command. 4.The method of claim 2, characterized in that the host controller is an I2C host controller, the interface module is an I2C interface module, and the I2C host controller is connected to the I2C interface module through an I2C clock line and an I2C data line. 5.The method of claim 4, characterized in that the I2C host controller initiates an I2C write operation to send the command package to the I2C interface module, and the I2C interface module, after receiving the command package, pulls down the level of the I2C clock line and sends the command package to the function module. 6.The method of claim 5, characterized in that when the I2C interface module receives the status package from the function module and the status information of the status package is success, the I2C interface module stops pulling down the level of the I2C clock line and returns an I2C ACK to the I2C host controller, and when the I2C interface module receives the status package from the function module and the status information of the status package is failure, the I2C interface module stops pulling down the level of the I2C clock line and returns an I2C NAK to the I2C host controller. 7.The method of claim 5, characterized in that ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ When the I2C interface module receives the status package from the function module, the I2C interface module stops pulling down the I2C clock line level, and returns the I2C ACK or I2C NAK to the I2C master controller, If the subsequent I2C operation initiated by the I2C master controller is an I2C read operation, the I2C interface module returns the status information of the status package to the I2C master controller.

8. The method of claim 4, wherein, After the I2C interface module receives the command package, if the subsequent I2C operation initiated by the I2C master controller is an I2C read operation, the I2C interface module returns the status information of the status package to the I2C master controller after receiving the status package from the function module.

9. The method of claim 4, wherein, After the I2C interface module receives the command package, if the subsequent I2C operation initiated by the I2C master controller is an I2C write operation, and the I2C interface module receives the status package from the function module, and the status information of the status package is success, the I2C interface module receives the subsequent I2C write operation initiated by the I2C master controller, After the I2C interface module receives the command package, if the subsequent I2C operation initiated by the I2C master controller is an I2C write operation, and the I2C interface module receives the status package from the function module, and the status information of the status package is failure, the I2C interface module returns the I2C NAK to the I2C master controller.

10. The method of claim 4, wherein, The I2C master controller initiates an I2C write operation to send the command package to the I2C interface module, and then the I2C master controller initiates a subsequent I2C read operation to read the status information, the I2C interface module pulls down the I2C clock line level after receiving the address byte of the subsequent I2C read operation, and sends the received command package to the function module, The function module returns a status package to the interface module after executing the command included in the command package, When the I2C interface module receives the status package from the function module, the I2C interface module stops pulling down the I2C clock line level, and returns the status information of the status package to the I2C master controller.

11. The method of claim 2, wherein, The master controller is an SPI master controller, and the interface module is an SPI interface module, and the SPI master controller is connected to the SPI interface module through an SPI_CK signal line, an SPI_MOSI signal line, and an SPI_MIS0 signal line.

12. The method of claim 11, wherein, The SPI master controller generates a clock edge on the SPI_CK signal line, sends a command package to the SPI interface module through the SPI_MOSI signal line, and the SPI interface module reads the command package through the SPI_MOSI signal line, and the command package starts with a first identification field, When the SPI interface module receives the status package from the functional module, the SPI interface module sends a feedback package to the SPI master controller through the SPI_MISO signal line when the SPI master controller generates a clock edge on the SPI_CK, and the SPI master controller reads the feedback package through the SPI_MISO signal line, wherein the feedback package starts with a second identification field, and the feedback package contains the state information contained in the status package.

13. The method of claim 12, wherein, When the SPI master controller generates a clock edge on the SPI_CK, if the SPI interface module does not receive a status package from the functional module, the SPI interface module sends data that cannot be identified as the feedback package to the SPI master controller through the SPI_MISO signal line.

14. The method of claim 12, wherein, After the SPI interface module sends the feedback package through the SPI_MISO signal line, the SPI interface module can continue to receive subsequent command packages sent by the SPI master controller through the SPI_MOSI signal line.

15. The method of claim 12, wherein, The feedback package is divided into a success feedback package and a failure feedback package, When the SPI interface module receives a status package from the functional module and the state information contained in the status package is success, the SPI interface module sends a success feedback package through the SPI_MISO signal line, When the SPI interface module receives a status package from the functional module and the state information contained in the status package is failure, the SPI interface module sends a failure feedback package through the SPI_MISO signal line, The second identification field of the success feedback package is different from the second identification field of the failure feedback package.

16. A write mask command, comprising: The write mask command contains an address field, a data field, and a mask field, The write mask command is contained in a command package, the command package contains one or more commands, at least one command is a write mask command, the command package is transmitted and executed based on an interface system, the interface system includes a master controller, an interface module, and a functional module, the master controller is connected to the interface module, and the interface module is connected to the functional module, The master controller sends the command package to the interface module, the interface module receives the command package, and sends the command package to the functional module, the functional module receives the command package, and executes the command contained in the command package, and executing the write mask command includes: writing the bit of the write mask command data field corresponding to the bit of the write mask command data field corresponding to the bit of the write mask command data field corresponding to the bit of the write mask command data field corresponding to the bit of the write mask command data field corresponding to the bit of the write mask command data field corresponding to the bit of the write mask command data field corresponding to the bit of the write mask command data field corresponding to the bit of the write mask command data field corresponding to the bit of the write mask command data field corresponding to the bit of the write mask command data field corresponding to the bit of the write mask command data field corresponding to the bit of the write mask command data field corresponding to the bit of the write mask command data field corresponding to the bit of the write mask command data field corresponding to the bit of the write mask command data field corresponding to the bit of the write mask command data field corresponding to the bit of the write mask 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corresponding to the bit of the write mask command data field corresponding to the bit of the write mask command data field corresponding to the bit of the write mask command data field corresponding to the bit of the write mask command data field corresponding to the bit of the write mask command data field corresponding to the bit of the write mask command data field corresponding to the bit of the write mask command data field corresponding to the bit of the write mask command data field corresponding to the bit of the write mask command data field corresponding to the bit of the write mask command data field corresponding to the bit of the write mask command data field corresponding to the bit of the write mask command data field corresponding to the bit of the write mask command data field corresponding to the bit of the write mask command data field corresponding to the bit of the write mask command data field corresponding to the bit of the write mask command data field corresponding to the bit of the write mask command data field corresponding to the bit of the write mask command data field corresponding to the bit of the write mask command data field corresponding to the bit of the write mask command data field corresponding to the bit of the write mask command data field corresponding to the bit of the write mask command data field corresponding to the bit of the write mask command data field corresponding to the bit of the write mask command data field corresponding to the bit of the write mask command data field corresponding to the bit of the write mask command ​ The function module returns a state package to the interface module after executing the commands in the command package, including: when the result of executing each command in the command package is success, the function module returns a state package with success state information; when the result of executing at least one command in the command package is failure, the function module returns a state package with failure state information, When the interface module receives the state package from the function module, the interface module returns the state information of the state package to the host controller.

18. The write mask command of claim 17, wherein The host controller is an I2C host controller, and the interface module is an I2C interface module, and the I2C host controller is connected to the I2C interface module through an I2C clock line and an I2C data line.

19. The write mask command of claim 18, wherein The I2C host controller initiates an I2C write operation to send the command package to the I2C interface module, and the I2C interface module pulls down the I2C clock line after receiving the command package, and sends the command package to the function module.

20. The write mask command of claim 19, wherein When the I2C interface module receives the state package from the function module and the state information of the state package is success, the I2C interface module stops pulling down the I2C clock line, and returns I2C ACK to the I2C host controller, When the I2C interface module receives the state package from the function module and the state information of the state package is failure, the I2C interface module stops pulling down the I2C clock line, and returns I2C NAK to the I2C host controller.

21. The write mask command of claim 19, wherein When the I2C interface module receives the state package from the function module, the I2C interface module stops pulling down the I2C clock line, and returns I2C ACK or I2C NAK to the I2C host controller, If the subsequent I2C operation initiated by the I2C host controller is an I2C read operation, the I2C interface module returns the state information of the state package to the I2C host controller.

22. The write mask command of claim 18, wherein If the subsequent I2C operation initiated by the I2C host controller is an I2C read operation after the I2C interface module receives the command package, the I2C interface module returns the state information of the state package to the I2C host controller after receiving the state package from the function module.

23. The write mask command of claim 18, wherein If the subsequent I2C operation initiated by the I2C host controller is an I2C write operation after the I2C interface module receives the command package, and the I2C interface module receives the state package from the function module and the state information of the state package is success, the I2C interface module receives the subsequent I2C write operation initiated by the I2C host controller, If the I2C interface module receives the command packet, and the subsequent I2C operation initiated by the I2C master controller is an I2C write operation, and the I2C interface module receives a status packet from the functional module, and the status information of the status packet is a failure, the I2C interface module returns an I2C NAK to the I2C master controller.

24. The write mask command of claim 18, wherein: The I2C master controller initiates an I2C write operation to send a command packet to the I2C interface module, and then initiates a subsequent I2C read operation to read the status information, and after the I2C interface module receives the address byte of the subsequent I2C read operation, the I2C interface module pulls down the I2C clock line, and sends the received command packet to the functional module, The functional module executes the command contained in the command packet, and returns a status packet to the interface module, When the I2C interface module receives the status packet from the functional module, the I2C interface module stops pulling down the I2C clock line, and returns the status information of the status packet to the I2C master controller.

25. The write mask command of claim 17, wherein: The master controller is an SPI master controller, and the interface module is an SPI interface module, and the SPI master controller is connected to the SPI interface module through an SPI_CK signal line, an SPI_MOSI signal line, and an SPI_MIS0 signal line.

26. The write mask command of claim 25, wherein: The SPI master controller generates a clock edge on the SPI_CK signal line, and sends a command packet to the SPI interface module through the SPI_MOSI signal line, and the SPI interface module reads the command packet through the SPI_MOSI signal line, and the command packet starts with a first identification field, After the SPI interface module receives a status packet from the functional module, when the SPI master controller generates a clock edge on the SPI_CK, the SPI interface module sends a feedback packet to the SPI master controller through the SPI_MISO signal line, and the SPI master controller reads the feedback packet through the SPI_MISO signal line, and the feedback packet starts with a second identification field, and the feedback packet contains the status information contained in the status packet.

27. The write mask command of claim 26, wherein: When the SPI master controller generates a clock edge on the SPI_CK, if the SPI interface module does not receive a status packet from the functional module, the SPI interface module sends data that cannot be identified as the feedback packet to the SPI master controller through the SPI_MISO signal line.

28. The write mask command of claim 26, wherein: After the SPI interface module sends the feedback packet through the SPI_MISO signal line, the SPI interface module can continue to receive a subsequent command packet sent by the SPI master controller through the SPI_MOSI signal line.

29. The write mask command of claim 26, wherein: The feedback packet is divided into a success feedback packet and a failure feedback packet, When the SPI interface module receives the state package from the function module and the state information contained in the state package is success, the SPI interface module sends a success feedback package through the SPI_MISO signal line, When the SPI interface module receives the state package from the function module and the state information contained in the state package is failure, the SPI interface module sends a failure feedback package through the SPI_MISO signal line, The second identification field of the success feedback package is different from the second identification field of the failure feedback package.

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