Preparation method for sub-nanometer node transistor based on non-EUV technology

Abstract

Disclosed in the present invention is a preparation method for a sub-nanometer node transistor based on non-EUV technology. A source electrode, a drain electrode and an electrode isolation layer of a transistor are prepared in three steps, such that the spacing between the source electrode and the drain electrode is determined on the basis of the thickness of the isolation layer, thereby realizing a transistor having an ultra-short channel length of 1-10 nanometers. To address the problems of EUV lithography solutions, such as low single-process precision, high device cost, etc., the present invention utilizes the difference in surface hydrophilicity between a semiconductor and an electrode to realize the lateral ALD growth of a dielectric on the side wall of the electrode, so as to form an electrode isolation layer, and controls the channel length of a transistor by means of the growth thickness of the dielectric; and due to the advantage of an ALD method in dielectric thickness control, the single-process precision reaches 1 nanometer, which is far superior to the single-process precision of existing EUV lithography devices, thereby greatly simplifying the microelectronic manufacturing process flow and improving the device yield.

Description

Method for manufacturing sub-nanometer node transistor of non-EUV technology TECHNICAL FIELD

[0001] The present application belongs to the field of microelectronic sub-nanometer advanced technology node manufacturing technology, and specifically relates to a method for manufacturing sub-nanometer node transistor of non-EUV technology. BACKGROUND

[0002] The integrated circuit industry has followed Moore's law for many years, using a method of successive miniaturization to continuously improve the integration and performance of silicon-based chips. So far, the silicon-based Moore's law has reached its limit, and the actual channel length of the silicon-based transistor has stopped at 12 nanometers, i.e. 1 nanometer technology node. Two-dimensional van der Waals semiconductors can continue to miniaturize the channel length to below 10 nanometers, and thus are important candidate materials for subsequent sub-nanometer technology nodes.

[0003] The minimum line width of a transistor in a microelectronic process is mainly determined by the wavelength of the lithography machine. At present, the single exposure accuracy of extreme ultraviolet (EUV) lithography is 13 nanometers, so the preparation of a sub-10 nanometer (especially 3 to 7 nanometers) channel length transistor using the EUV scheme requires multiple exposures, which greatly affects the process complexity and device yield. Other methods for mass production of ultra-short channel transistors have also been reported, but they generally have problems such as low process resolution, poor controllability, and CMOS compatibility.

[0004] As disclosed in the paper "Sub-15-nm patterning of asymmetric metal electrodes and devices by adhesion lithography" by D. J. Beesley et al., Nat. Commun, 5, 3933 (2014), a scheme for preparing sub-15 nanometer ultra-short metal electrode pairs and short channel transistors using the ordered and close self-assembly of organic molecules on the sidewalls of gold electrodes. Since this scheme relies on factors such as the affinity of the end chemical bond of the organic molecule and the metal electrode, and the coverage of the sidewall self-assembly, it has problems such as poor material universality and low process yield.

[0005] As disclosed in the paper "Bilayer Tungsten Diselenide Transistors with On-state Currents Exceeding 1.5 Milliamperes per Micrometre" by R. Wu et al., Nat. Electron., 5, 497 (2022), a scheme for obtaining ultra-short electrode pairs using nanoscale cracks in two-dimensional materials, with a minimum electrode spacing of 2 nanometers. Since the natural crack position and distance of the material are random, this scheme cannot be compatible with large-scale manufacturing processes.

[0006] CN117594449A (Publication Date: 2024-02-23) discloses a vertical self-aligned double-gate transistor and a preparation method thereof, and relates to the technical field of semiconductor devices. The method comprises the following steps: sequentially forming a stack of a first metal layer, a first dielectric layer, a second metal layer, a second dielectric layer, and a third metal layer, wherein the first metal layer and the third metal layer are respectively a source and a drain, and the second metal layer is a gate; etching the stack to form a groove, and exposing the first metal layer; oxidizing the sidewall of the second metal layer in the stack after etching at the groove to form a first gate dielectric and a second gate dielectric; filling the groove with a semiconductor material to form a channel layer; and forming a channel passivation layer on the channel layer by deposition technology.

[0007] CN118486711A (Publication Date: 2024-08-13) discloses a silicon carbide trench gate insulated gate bipolar transistor and a manufacturing method thereof, and relates to the technical field of semiconductor devices. The silicon carbide trench gate insulated gate bipolar transistor includes a layer-stacked contact arrangement of an emitter region, a base region, a drift layer, and a substrate, which form a PNPN structure or an NPNP structure; the device structure forms a heteroepitaxial single crystal silicon doping at the bottom and sidewall of the trench through selective epitaxial growth technology, which significantly improves the channel carrier mobility of the device.

[0008] After searching, it is found that although there are a few patents on the preparation method of transistors, there is still a gap in the preparation method of sub-nanometer transistors.

[0009] In summary, there is still a lack of low-cost, high-precision, CMOS process compatible manufacturing method of sub-nanometer node ultra-short channel transistor and array. SUMMARY

[0010] To solve the above technical problems, the present application provides a preparation method of a sub-nanometer node transistor by non-EUV technology.

[0011] A preparation method of a sub-nanometer node transistor by non-EUV technology, comprising the following steps,

[0012] Step S1, preparing a semiconductor and gate control composite structure: the semiconductor and gate control composite structure is a multi-layer structure or a silicon-on-insulator prepared by ion implantation;

[0013] Step S2, making a source metal electrode: making a source electrode on one side of the transistor on the semiconductor and gate control composite structure;

[0014] Step S3, making electrode isolation layer: according to the difference between the hydrophilic and hydrophobic of the semiconductor and the source electrode, the electrode isolation layer is selectively deposited on the sidewall of the source electrode by atomic layer deposition (ALD) technology;

[0015] Step S4, making drain metal electrode: the drain electrode on the other side of the transistor is made close to the source electrode coated with the electrode isolation layer, so as to form a single ultra-short channel transistor between the source electrode, the electrode isolation layer and the drain electrode.

[0016] Further, the thickness of the electrode isolation layer in step S3 is precisely controlled between 1 to 10 nanometers, preferably between 3 to 7 nanometers.

[0017] Further, if the top gate control is needed, the preparation method further comprises step S5: surface planarization; the surface planarization process is used to remove the excess material on the surface to obtain a flat upper surface, which is convenient for subsequent processes.

[0018] Further, when the semiconductor and gate control composite structure in step S1 is a multi-layer structure, the preparation method comprises the following steps,

[0019] Step S101, making bottom gate: making metal bottom gate on insulating substrate;

[0020] Step S102, making bottom gate dielectric: making bottom gate dielectric on metal bottom gate;

[0021] Step S103, making semiconductor channel material: making semiconductor channel material on bottom gate dielectric.

[0022] Further, the insulating substrate in step S101 comprises one or more of sapphire, low resistance silicon, silicon on insulator, silicon containing surface insulating layer, chip containing surface insulating layer;

[0023] The metal bottom gate is a global gate or a local gate.

[0024] Further, the bottom gate dielectric in step S102 is high-k dielectric, and the preparation method thereof comprises one or more of atomic layer deposition, chemical vapor deposition, physical vapor deposition, pulsed laser deposition, electron beam evaporation;

[0025] The high-k dielectric comprises one or more of HfO2, Al2O3, Ta2O5, TiO2, La2O3, HfZrO4.

[0026] Further, the preparation method of making semiconductor channel material on bottom gate dielectric in step S103 comprises one or more of deposition, transfer and ion implantation.

[0027] Further, the semiconductor channel material in step S103 is a semiconductor with a forbidden band, including one or more of two-dimensional metal chalcogenides, Si, Ge, carbon nanotubes, GaAs, GaN, SiC, diamond, ZnO;

[0028] The preparation method of the semiconductor channel material includes one or more of mechanical transfer, bonding, chemical vapor deposition, physical vapor deposition, pulsed laser deposition, electron beam evaporation, ion implantation.

[0029] Further, when the semiconductor channel material in step S103 is a hydrophobic semiconductor, no hydrophobic treatment is required; when the semiconductor channel material 203 is a hydrophilic semiconductor, hydrophobic treatment is performed.

[0030] Further, the source electrode in step S2 includes one or more of two-dimensional layered metals, Ni, Cr, Au, Ag, Cu, Co, Ru, Pt, Pd, Sb, Bi, and Al.

[0031] Further, the electrode isolation layer in step S3 includes one or more of HfO2, SiO2, Al2O3, Ta2O5, TiO2, La2O3, HfZrO4, and organic media.

[0032] Further, the drain electrode in step S4 includes one or more of two-dimensional layered metals, Ni, Cr, Au, Ag, Cu, Co, Ru, Pt, Pd, Sb, Bi, and Al.

[0033] The width and patterning of the source electrode and the drain electrode are made by deep ultraviolet or electron beam lithography; the number of lithography times is single or multiple.

[0034] Compared with the prior art, the advantages and effects of the present application are as follows:

[0035] 1. The present application provides a sub-nanometer node transistor manufacturing method without EUV technology, which uses a low-cost ALD device to replace expensive EUV lithography to define the minimum line width of the transistor, greatly saving process cost.

[0036] 2. The present application provides a sub-nanometer node transistor manufacturing method without EUV technology, which separates the source electrode, the electrode isolation layer, and the drain electrode to define the channel length of the transistor by the thickness of the electrode isolation layer.

[0037] 3. The present application provides a sub-nanometer node transistor manufacturing method without EUV technology, which uses ALD medium thickness precision control, with a single process precision of 1 nanometer, far superior to the single process precision (13 nanometers) of existing EUV lithography equipment, which can simplify the process flow and improve device yield.

[0038] 4. The application provides a non-EUV technology sub-nanometer node transistor manufacturing method, which is compatible with the existing microelectronic CMOS process and is suitable for large-scale industrial application.

[0039] The above description is only a summary of the technical solutions of the present application. In order to more clearly understand the technical means of the present application, the contents of the specification can be implemented, and in order to make the above and other purposes, characteristics and advantages of the present application more obvious and easy to understand, the following will be described in detail with the preferred embodiments of the present application and with the help of the accompanying drawings.

[0040] According to the detailed description of the specific embodiments of the present application in the following combined with the drawings, those skilled in the art will more clearly understand the above and other purposes, advantages and characteristics of the present application. BRIEF DESCRIPTION OF DRAWINGS

[0041] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the drawings needed in the embodiment or the prior art description will be briefly introduced below. Obviously, the drawings in the following description are some embodiments of the present application, and those skilled in the art can also obtain other drawings without creating laborious work. In all the drawings, similar elements or parts are generally identified by similar reference numerals. In the drawings, each element or part is not necessarily drawn according to the actual proportion.

[0042] Wherein:

[0043] Figure 1 is a flow chart of a non-EUV technology sub-nanometer node transistor manufacturing method of the present application;

[0044] Figure 2 is a schematic diagram of the structure of the sub-nanometer node transistor prepared by the present application;

[0045] Figure 3 is a cross-sectional TEM image of a 3-nanometer ultra-short channel length transistor prepared by the present application;

[0046] Figure 4 is a schematic diagram of a multi-layer structure prepared by the present application;

[0047] Figure 5 is a second flow chart of a non-EUV technology sub-nanometer node transistor manufacturing method of the present application;

[0048] Figure 6 is a schematic diagram of the transistor structure after the surface planarization process in the present application.

[0049] Reference numerals: 100 - semiconductor and gate control composite structure; 200 - insulating substrate; 201 - metal bottom gate; 202 - bottom gate dielectric; 203 - semiconductor channel; 204 - source electrode; 205 - electrode isolation layer; 206 - drain electrode. DETAILED DESCRIPTION

[0050] In order to make the objects, technical solutions and advantages of the embodiments of the present application clearer, the following will be combined with the accompanying drawings for the embodiments of the present application to make a clear and complete description of the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments of the present application. In the following description, specific details such as specific configurations and components are provided only for the purpose of helping to fully understand the embodiments of the present application. Therefore, those skilled in the art should clearly understand that various changes and modifications can be made to the embodiments described herein without departing from the scope and spirit of the present application. In addition, in order to be clear and concise, the description of known functions and structures is omitted in the embodiments.

[0051] It should be understood that the "one embodiment" or "the embodiment" mentioned throughout the specification means that the specific features, structures or characteristics related to the embodiment are included in at least one embodiment of the present application. Therefore, "one embodiment" or "the embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. In addition, these specific features, structures or characteristics can be combined in one or more embodiments in any suitable manner.

[0052] In addition, reference numerals and / or letters can be repeated in different examples in the present application. Such repetition is for the purpose of simplification and clarity, and does not itself indicate a relationship between the various embodiments and / or arrangements discussed.

[0053] The term "and / or" herein is only a description of the association relationship of the associated objects, which means that there can be three relationships, for example, A and / or B can mean that A exists alone, B exists alone, and A and B exist together. The term "and" herein is a description of another association relationship of the associated objects, which means that there can be two relationships, for example, A and B can mean that A exists alone and A and B exist together. In addition, the character " / " herein generally represents an "or" relationship between the associated objects before and after it.

[0054] The term "at least one" herein is only a description of the association relationship of the associated objects, which means that there can be three relationships, for example, at least one of A and B can mean that A exists alone, A and B exist together, and B exists alone.

[0055] It should also be noted that the relationship terms such as first and second in the present document are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between the entities or operations. Moreover, the terms "include", "contain" or any other variants thereof are intended to cover non-exclusive inclusion. Embodiment 1

[0056] The embodiment is a sub-nanometer node transistor preparation method of non-EUV technology.

[0057] Please refer to Fig. 1, which is a preparation flow chart of a sub-nanometer node transistor of non-EUV technology according to the present application.

[0058] A preparation method of a sub-nanometer node transistor of non-EUV technology comprises the following steps,

[0059] Step S1, preparing a semiconductor and gate control composite structure 100: the semiconductor and gate control composite structure 100 is a multi-layer structure or a silicon-on-insulator prepared by ion implantation.

[0060] Step S2, making a source metal electrode 204: making a source electrode 204 on one side of the transistor on the semiconductor and gate control composite structure 100.

[0061] Step S3, making an electrode isolation layer 205: using atomic layer deposition (ALD) technology, the electrode isolation layer 205 is selectively deposited on the sidewall of the source electrode 204 according to the different hydrophilic and hydrophobic properties of the composite structure 100 and the source electrode 204.

[0062] Step S4, making a drain metal electrode 206: making a drain electrode 206 on the other side of the transistor close to the source electrode 204 coated with the electrode isolation layer 205, thereby forming a single super short channel transistor between the source electrode 204, the electrode isolation layer 205, and the drain electrode 206.

[0063] Further, the thickness of the electrode isolation layer in step S3 is precisely controlled between 1 to 10 nanometers, preferably between 3 to 7 nanometers.

[0064] Please refer to Fig. 2, which is a schematic diagram of a sub-nanometer node transistor structure prepared according to the present application. Above the semiconductor and gate control composite structure 100 are the source electrode 204, the electrode isolation layer 205, and the drain electrode 206. The electrode isolation layer 205 is between the source electrode 204 and the drain electrode 206, and the distance between the source electrode 204 and the drain electrode 206 is determined by the thickness of the electrode isolation layer 205, thereby defining the channel length of the transistor. In the schematic diagram, there are drain electrodes 206 on both sides of the source electrode 204, defining two transistors.

[0065] Please refer to Fig. 3, which is a cross-sectional TEM image of a single 3-nanometer super short channel length transistor prepared according to the above method. The thickness of the electrode isolation layer 205 is precisely controlled at 3 nanometers.

[0066] Technical effects of the embodiment: provide a sub-nanometer node transistor manufacturing method of non-EUV technology, unlike the electrode self-alignment technology of the transistor, the source electrode, the electrode isolation layer and the drain electrode are independently prepared in three steps in the transistor preparation method of the application. The electrode isolation layer adopts ALD medium thickness precise control, the single process precision is 1 nanometer, which is much better than the single process precision (13 nanometers) of the existing EUV photoetching equipment, can simplify the process flow, improve the device yield. In addition, the low-cost ALD equipment is used instead of expensive EUV photoetching to manufacture the minimum line width of the transistor, which greatly saves the process cost. Embodiment 2

[0067] Based on embodiment 1, the preparation method of the multilayer semiconductor and gate control composite structure is provided.

[0068] Please refer to figure 4, figure 4 is a schematic diagram of the multilayer structure prepared by the application; the preparation method of the multilayer structure comprises the following steps:

[0069] Step S101, preparing the bottom gate: preparing the metal bottom gate 201 on the insulating substrate 200.

[0070] Step S102, preparing the bottom gate dielectric: preparing the bottom gate dielectric 202 on the metal bottom gate 201.

[0071] Step S103, preparing the semiconductor channel material: preparing the semiconductor channel material 203 on the bottom gate dielectric 202.

[0072] Further, the insulating substrate 200 in step S101 includes one or more of sapphire, low resistance silicon, silicon on insulator, silicon containing surface insulating layer, chip containing surface insulating layer;

[0073] The metal bottom gate 201 is a global gate or a local gate.

[0074] Further, the bottom gate dielectric 202 in step S102 is a high-k dielectric, and the preparation method thereof includes one or more of atomic layer deposition, chemical vapor deposition, physical vapor deposition, pulsed laser deposition, electron beam evaporation;

[0075] The high-k dielectric includes one or more of HfO2, Al2O3, Ta2O5, TiO2, La2O3 and HfZrO4.

[0076] Further, the preparation method of the semiconductor channel material 203 on the bottom gate dielectric 202 in step S103 includes one or more of deposition, transfer and ion implantation.

[0077] Further, the semiconductor channel material 203 in step S103 is a semiconductor with a forbidden band, including one or more of two-dimensional metal chalcogenide, Si, Ge, carbon nanotube, GaAs, GaN, SiC, diamond, ZnO;

[0078] The preparation method of the semiconductor channel material 203 includes one or more of mechanical transfer, bonding, chemical vapor deposition, physical vapor deposition, pulsed laser deposition, electron beam evaporation, ion implantation.

[0079] Further, the contact angle between the sidewall metal of the source electrode 204 and water is between 0-90°, showing hydrophilicity, and the contact angle between the semiconductor channel material 203 and water is between 90-180°, showing hydrophobicity.

[0080] Further, when the semiconductor channel material 203 in step S103 is a hydrophobic semiconductor, no hydrophobic treatment is needed; when the semiconductor channel material 203 is a hydrophilic semiconductor, hydrophobic treatment is performed.

[0081] Technical effects of the embodiment: according to design and process requirements, the gate is defined as a global gate or a local gate; the channel material is pre-treated with hydrophobicity according to the situation, and the difference in hydrophilicity between the electrode sidewall and the semiconductor channel is used to controllably deposit an electrode isolation layer on the electrode sidewall. Embodiment 3

[0082] Based on embodiment 1, this embodiment is a further process consideration of the sub-nanometer node transistor preparation method of non-EUV technology, such as adding top gate control. Please refer to FIG. 5, which is a second preparation flowchart of a sub-nanometer node transistor of the present application of non-EUV technology. Please refer to FIG. 6, which is a device schematic diagram after surface planarization.

[0083] Further, after obtaining the sub-nanometer node transistor shown in FIG. 2, in order to further prepare a top gate composite structure to enhance the gate control ability to the channel, surface planarization can be performed using step S5 to remove excess materials on the surface.

[0084] Technical effects of the embodiment: the present application provides a sub-nanometer node transistor manufacturing method of non-EUV technology, which further improves device performance by surface planarization and subsequent preparation of a top gate composite structure on a flat surface. The method is compatible with existing microelectronic CMOS processes and is suitable for large-scale industrial applications.

[0085] The above detailed description of the specific embodiments of the present application has been given to understand the purpose, technical solutions and beneficial effects of the present application. It should be understood that the above description is only a specific embodiment of the present application and is not intended to limit the present application. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A method of fabricating a sub-nanometer node transistor using non-EUV technology, comprising: The method comprises the following steps: Step S1, preparing a semiconductor and gate control composite structure (100): the semiconductor and gate control composite structure (100) is a multilayer structure or a silicon-on-insulator prepared by ion implantation; Step S2, preparing a source metal electrode (204): a source electrode (204) on one side of the transistor is prepared on the semiconductor and gate control composite structure (100); Step S3, preparing an electrode isolation layer (205): an electrode isolation layer (205) is deposited on the sidewall of the source electrode (204) by using an atomic layer deposition (ALD) technique; Step S4, preparing a drain metal electrode (206): a drain electrode (206) on the other side of the transistor is prepared close to the source electrode (204) coated with the electrode isolation layer (205), so as to form an ultra-short channel transistor between the source electrode (204), the electrode isolation layer (205) and the drain electrode (206).

2. The method of claim 1, wherein the non-EUV sub-nanometer node transistor is formed by: The thickness of the electrode isolation layer (205) in step S3 is precisely controlled to be 1-10 nanometers, and preferably 3-7 nanometers.

3. The method of claim 1, wherein the non-EUV sub-nanometer node transistor is formed by: If it is necessary to further increase top gate control, the preparation method further comprises step S5: surface planarization; the surface planarization process is used to remove the excess material on the surface, so as to obtain a flat upper surface, and facilitate subsequent processes.

4. The method of claim 1, wherein the non-EUV sub-nanometer node transistor is formed by: When the semiconductor and gate control composite structure in step S1 is a multilayer structure, the preparation method comprises the following steps: Step S101, preparing a bottom gate: a metal bottom gate (201) is prepared on an insulating substrate (200); Step S102, preparing a bottom gate dielectric: a bottom gate dielectric (202) is prepared on the metal bottom gate (201); Step S103, preparing a semiconductor channel material: a semiconductor channel material (203) is prepared on the bottom gate dielectric (202).

5. The method of claim 4, wherein the non-EUV sub-nanometer node transistor is formed by: The insulating substrate (200) in step S101 comprises one or more of sapphire, low-resistance silicon, silicon-on-insulator, silicon containing a surface insulating layer and a chip containing a surface insulating layer; The metal bottom gate (201) is a global gate or a local gate.

6. The method of claim 4, wherein the non-EUV sub-nanometer node transistor is formed by: The preparation method of the semiconductor channel material (203) on the bottom gate dielectric (202) in step S103 comprises one or more of deposition, transfer and ion implantation.

7. The method of claim 4, wherein the non-EUV sub-nanometer node transistor is formed by: When the semiconductor channel material (203) in step S103 is a hydrophobic semiconductor, no hydrophobic treatment is needed; when the semiconductor channel material (203) is a hydrophilic semiconductor, hydrophobic treatment is needed.

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