Carrier for at least one chiplet and method for providing same

Abstract

The invention relates to a carrier for at least one chiplet, having a plurality of connection regions for connecting connections of the at least one chiplet, wherein contact elements for contacting the connections of the at least one chiplet are provided in each of the plurality of connection regions, and the carrier has connection lines for connecting the contact elements of at least two different connection regions to one another.

Description

[0001] R.409094

[0002] - 1 -

[0003] Description

[0004] title

[0005] Carrier for at least one chiplet and method for providing therefor

[0006] State of the art

[0007] The revelation concerns a carrier for at least one chiplet

[0008] The disclosure also relates to a method for providing a carrier for at least one chiplet.

[0009] Disclosure of the invention

[0010] Some examples refer to a support, for example a substrate, for at least one chiplet, having several connection areas for connecting terminals of the at least one chiplet, wherein each of the several connection areas contains contact elements for contacting the terminals of the at least one chiplet, and wherein the support has connecting lines for connecting the contact elements to at least two different connection areas. In some examples, this allows for a flexible arrangement of chiplets on the support, for example in different relative orientations of the chiplets to each other and / or to the support.

[0011] In some chiplets, the connections of at least one chiplet are, for example, so-called die-to-die ("d2d") connections, which are, for example, geometrically attached to defined points on the respective chiplet and which represent, for example, point-to-point connections (e.g., single-ended), i.e., are not buses (data buses).

[0012] In some conventional systems, therefore, predefined chiplets "A", "B" are usually arranged in a configuration determined by the arrangement of the (d2d) connections. R.409094

[0013] - 2 - to arrange the chiplets in a relative orientation to each other or on a conventional carrier, resulting in a specific first multi-chip configuration. If the specified chiplets "A", "B" are to be used for another, e.g., a second, multi-chip configuration, which, for example, has at least one further chiplet, e.g., of type "C", itself with specified (d2d) connections, it may occur that the existing (d2d) connections of at least some of the chiplets "A", "B" no longer geometrically match each other, i.e., the existing (d2d) connections of some other chiplets "C". This means that in some conventional systems, the other chiplet "C" to be connected does not geometrically align with the connections of chiplets "A" and / or "B".

[0014] These problems of conventional chiplet systems can be reduced or completely avoided in some examples by the principle according to the disclosure, since the principle according to the disclosure allows, in some examples, a separation between the geometric connection of the chiplets and the establishment of data connections, e.g., between chiplets, such as data routing, for example, by appropriately configuring the carrier's connecting lines. In this way, chiplet systems with different chiplet types, e.g., "A", "B", "C", ..., can be efficiently provided in some examples, each of which may also have different relative arrangements to each other and / or to the carrier. This eliminates the need in some examples to produce different variants of a chiplet "A", which, for example, differ in their configuration.solely by the geometric arrangement of one or more (d2d) connections on the chiplet "A", as is required for some conventional approaches.

[0015] In some examples, one or more of the connecting lines are at least partially or partially integrated into the support, for example, not arranged on an outer surface of the support.

[0016] In some examples, the support has a multi-layered structure, with one or more of the connecting lines arranged in different layers of the multi-layered structure. This allows for a comparatively large number of connecting lines to be provided in the support in some examples, R.409094

[0017] - 3 - which also allow for the implementation of comparatively complex parallel bus systems, e.g. for high bitrate data connections between chiplets.

[0018] In some examples, at least one of the multiple connection areas contains several contact elements, each with a different orientation. This allows, for example, further degrees of freedom regarding the arrangement of chiplets relative to or on the substrate.

[0019] In some examples, one or more of the connecting lines are configurable, whereby, for example, at least one connecting line can be manufactured or separated, for instance, during and / or after the manufacturing of the carrier. This allows the topology of the at least one connecting line to be flexibly adapted to different chiplets and / or arrangements of chiplets on the carrier, possibly even after the carrier has been manufactured.

[0020] In some examples, one or more of the connecting lines a) have one or more short-circuit bridges, and / or b) are designed as short-circuit bridges. This allows for a particularly simple configuration of connections in some examples.

[0021] In some examples, one or more of the connecting lines have at least one initial connecting line section that extends, for example, substantially perpendicular to a surface of the support. This allows, for example, at least a portion of the support's volume to be used for the connecting lines.

[0022] In some examples, one or more of the connecting lines have at least a second connecting line section that extends, for example, substantially parallel to a surface of the support, wherein, for example, the at least one second connecting line section is associated with, for example, arranged in, at least one layer of a multilayer structure. This allows, for example, at least a portion of the support's volume to be used for the connecting lines, for example, also in a multilayer configuration. R.409094

[0023] - 4 -

[0024] In some examples, the multiple connection areas are designed to connect at least one of the following elements: a) data lines of the at least one chiplet, or b) power supply lines of the at least one chiplet, or c) optical connection lines.

[0025] In some examples, the carrier has at least one connection device, such as a multiplexer, configured to selectively connect contact elements from different connection areas of the multiple connection areas. This connection device can be configured, for example, by means of short-circuit bridges. This allows, for example, the selection of which contact elements should be used and connected, thus enabling the definition of data routing for chiplets that can be connected to or are connected to the respective contact elements, e.g., within the carrier.

[0026] Some examples refer to a system comprising at least one carrier according to the disclosure and at least one chiplet.

[0027] Some examples relate to a method for providing a carrier, for example, a substrate, for at least one chiplet, comprising several connection areas for connecting terminals of the at least one chiplet, wherein each of the several connection areas provides contact elements for contacting the terminals of the at least one chiplet, wherein the carrier has connecting lines for connecting the contact elements to at least two different connection areas, wherein the method comprises: providing the carrier, determining information for the arrangement of the connection areas and contact elements, creating the contact elements in the connection areas, creating the connecting lines, and, optionally, configuring the connecting lines (for example, configuring an optionally available connection device, for example, a multiplexer device), and, optionally,Arranging at least one chiplet on the carrier.

[0028] Some examples refer to a use of the carrier according to the revelation and / or the system according to the revelation and / or R.409094

[0029] - 5 -

[0030] Method according to the disclosure for at least one of the following elements: a) connecting, for example flexibly connecting, chiplets to the carrier and / or to each other, for example by means of the carrier, or b) arranging, for example flexibly arranging chiplets on the carrier, or c) increasing a number of identical parts with respect to the chiplets, or d) avoiding a change of chiplets, or e) integrating a configuration for a connection, for example data connection, between chiplets on the carrier.

[0031] Further features, applications, and advantages of the invention will become apparent from the following description of examples illustrated in the figures of the drawing. All features described or illustrated, individually or in any combination, constitute the subject matter of the disclosure, irrespective of their compilation in the claims or their cross-reference, and irrespective of their formulation or representation in the description or in the drawing.

[0032] The drawing shows:

[0033] Fig. 1 schematically shows a block diagram according to some examples,

[0034] Fig. 2 schematically shows a side view according to some examples,

[0035] Fig. 3 schematically shows a side view according to some examples,

[0036] Fig. 4A schematically shows a top view according to some examples,

[0037] Fig. 4B schematically shows a side view of Fig. 4A,

[0038] Fig. 5A schematically shows a top view according to some examples,

[0039] Fig. 5B schematically shows a side view of Fig. 5A,

[0040] Fig. 6 schematically shows a flowchart according to some examples,

[0041] Fig. 7 schematically shows aspects of uses according to further examples, R.409094

[0042] - 6 -

[0043] Fig. 8A schematically shows a side view according to some examples,

[0044] Fig. 8B schematically shows a side view according to some examples.

[0045] Some examples, Fig. 1, relate to a carrier 100, for example a substrate, for at least one chiplet 200-1, 200-2, ..., having several connection areas 110-1, 110-2, ... for connecting terminals 200-1a, 200-2a, ... of the at least one chiplet 200-1, 200-2, ..., wherein contact elements 112-1, 112-2, 112-2a, 112-2b, ... are provided in each of the several connection areas 110-1, 110-2, ... for contacting the terminals 200-1a, 200-2a, ... of the at least one chiplet 200-1, 200-2, ..., and wherein the carrier 100 provides connecting lines VL, VL', ... for connecting the contact elements 112-1, 112-2, 112-2a, 112-2b, ... each has at least two different connection areas 110-1, 110-2, ... connected to each other. This allows, in some examples, a flexible arrangement of chiplets 200-1, 200-2, ... on the carrier 100, for example in different relative orientations of the chiplets to each other and / or with respect to the carrier.For example, the contact elements 112-1 , 112-2, 112-2a, 112-2b, ... are arranged on a surface 102 of the carrier 100.

[0046] In some examples, Fig. 1, at least one connection device, for example a multiplexer device, 120, is provided, which is designed to selectively connect contact elements 112-1, 112-2, 112-2a, 112-2b, ... from different connection areas 110-1, 110-2, ... of the several connection areas to each other, see the connecting lines 122a, 122b, wherein, for example, the connection device 120 is configurable, for example by means of short-circuit bridges (not shown in Fig. 1, see Fig. 8A, 8B).

[0047] In some examples, Fig. 1, one or more of the connecting lines VL, VL', 122a, 122b, ... are at least partially or partially integrated into the support 100.

[0048] In some examples, Fig. 2, the support 100a has a multilayer structure 100-ML, wherein one or more of the connecting lines VL, VL' (Fig. 1) are arranged in different layers of the multilayer structure 100-ML. R.409094

[0049] - 7 -

[0050] In some examples, Fig. 1, at least one connection area 110-2 of the several connection areas has several contact elements 112-2a, 112-2b in different orientations.

[0051] In some examples, Fig. 1, 2, one or more of the connecting lines VL, VL' are configured, wherein, for example, at least one connecting line VL, VL' can be manufactured or cut, for example, during and / or after the fabrication of the carrier 100, 100a. This allows the topology of the at least one connecting line to be flexibly adapted to different chiplets and / or arrangements of chiplets on the carrier, possibly even after the carrier has been fabricated.

[0052] In some examples, Fig. 1, 2, one or more of the connecting lines VL, VL', 122a, 122b a) have one or more short-circuit bridges, and / or b) are designed as short-circuit bridges. This allows for a particularly simple configuration of connections in some examples.

[0053] In some examples, Fig. 2, one or more of the connecting lines VL have at least one first connecting line section VLA-1, VLA-3, which extends, for example, substantially perpendicular to one or the surface 102 of the support 100a. This allows, for example, at least part of the volume of the support 100a to be used for the connecting lines VL.

[0054] In some examples, Fig. 2, one or more of the connecting lines VL have at least a second connecting line section VLA-2, which extends, for example, substantially parallel to a surface 102 of the support 100a, wherein, for example, the at least one second connecting line section VLA-2 is associated with, for example, arranged in, at least one layer L-1 of a multilayer structure 100-ML. This allows, for example, at least a portion of the volume of the support 100a to be used for the connecting lines VL, VL', 122a, 122b, for example, also in a multilayer configuration, see Fig. 2, in which, as an example, some further layers of connecting lines are shown, which, however, are not individually labeled for the sake of clarity. R.409094

[0055] - 8 -

[0056] In some examples, Fig. 1, 2, the multiple connection areas 110-a, 110-2 are configured to connect at least one of the following elements: a) data lines (e.g. electrical and / or optical data lines) of the at least one chiplet, or b) power supply lines of the at least one chiplet.

[0057] Fig. 3 shows a carrier 100b according to further examples, on whose surface 102, for example, two chiplets 200-1, 200-2 are arranged and connected to each other via several unlabeled connecting lines VL. Since several different groups 112-2a, 112-2a' of contact elements are provided in the connection area 110-2, corresponding degrees of freedom result for the design of the connecting lines VL, so that the configuration according to Fig. 3 can be adapted, for example, to different chiplets 200-2, and / or to different arrangements of the chiplet 200-2 on the carrier 100b. For example, the contact elements 112-2a located further to the left on the carrier 100b in Fig. 3 and / or those shown in Fig.3 contact elements 112-2a' located further to the right on the carrier 100b are used for connection with the chiplet 200-2, which provides, for example, different degrees of freedom for establishing a data connection between the chiplet 200-2 and the chiplet 200-1.

[0058] Fig. 4A shows a carrier 100c according to further examples, on which four chiplets 200-1, 200-2, 200-3, 200-4 are arranged. This forms a multi-chip module of the first type.

[0059] In some examples, Fig. 4A, the carrier 100c has at least one, in this example two, connection device(s) 120a, 120b, for example multiplexer device(s), which are configured to selectively connect contact elements from different connection areas of the multiple connection areas to each other, wherein, for example, the connection devices 120a, 120b are configurable, for example by means of short-circuit bridges. In the example according to Fig. 4A, the chiplets 200-1, 200-2, 200-3, 200-4 each have connections configured, for example, as so-called die-to-die interfaces D2D for connection to each other and / or to the carrier 100c. In some examples, the die-to-die R.409094

[0060] - 9 -

[0061] Interfaces D2D can be connected, for example, with at least one of the connection device(s) 120a, 120b, for example via connecting lines VL, VL', 122a, 122b as described above as an example with reference to Fig. 1 to Fig. 3.

[0062] Fig. 4B schematically shows a side view of the support 100c according to Fig. 4A.

[0063] In some examples, Fig. 4A, 4B, the die-to-die interfaces D2D are not directly connected to the logic on the respective chiplet, but are first routed, for example, via a die-to-die multiplexer, e.g., implemented using the interconnect devices 120a, 120b. In some examples, the die-to-die multiplexer 120a, 120b is configured by shorting bridges KB on or in the carrier 100c. In some examples, a connection, e.g., an actual connection between the chiplets, is implemented using connecting lines VL" on or in the carrier 100c.

[0064] In some examples, Figs. 5A, 5B, a reconnection, for example rewiring, of existing chiplets, e.g., to realize a different multi-chip module than the multi-chip module of the first type shown as an example in Figs. 4A, 4B, is comparatively easy to implement, for example, by different routing of short-circuit bridges KB and connecting lines VL'" on the carrier 100c, see Figs. 5A, 5B. Compared to Figs. 4A, 4B, according to Figs. 5A, 5B, a different arrangement with the same chiplets 200-2, 200-4 is possible without modifying the chiplets 200-2, 200-4, i.e., in particular without having to change the geometric location of the die-to-die interfaces D2D of the chiplets 200-2, 200-4.

[0065] In some examples, Fig. 4A, 4B, 5A, 5B, the short-circuit bridges KB can be implemented, for example, in the area of ​​the connecting device 120a, 120b, for example, by means of the connecting device 120a, 120b.

[0066] Some examples, Fig. 1, refer to a system 1000 comprising at least one support 100, 100a, 100b, 100c according to the disclosure and at least one chiplet 200-1 , ...., which is arranged, for example, on the support.

[0067] Some examples, Fig. 6, relate to a method for providing a carrier 100, 100a, 100b, 100c, for example substrate, for at least R.409094

[0068] - 10 - a chiplet having several connection areas for connecting terminals of the at least one chiplet, wherein contact elements for contacting the terminals of the at least one chiplet are provided in each of the several connection areas, wherein the carrier has connecting lines for connecting the contact elements to at least two different connection areas together, wherein the method comprises: providing 300 of the carrier 100, 100a, 100b, 100c, determining 302 information 1-1 for the arrangement of the connection areas 110-1, 110-2, ... and contact elements 112-1, 112-2, 112-2a, 112-2a', ..., creating 304 the contact elements 112-1, 112-2, 112-2a, 112-2a', ...in the connection areas, create 306 the connection lines VL, VL', VL", VL'", 122a, 122b, and, optionally, configure 307 the connection lines VL; VL', VL", VL'", 122a, 122b (for example, configuring an optionally existing connection device, for example, multiplexer device, 120), and, optionally, arrange 308 the at least one chiplet on the carrier.

[0069] For example, the arrangement 308 can also include a connection, such as an electrical connection, between at least one chiplet and the carrier, for example to establish data connections and / or electrical power supply connections between the carrier and the at least one chiplet. Establishing optical connections between the carrier and chiplet components in the arrangement is also conceivable in some examples.

[0070] Some examples, Fig. 7, relate to a use 400 of the carrier 100, 100a, 100b, 100c according to the disclosure and / or the system 1000 according to the disclosure and / or the method according to the disclosure for at least one of the following elements: a) connecting 401, for example flexibly connecting 402, of chiplets to the carrier and / or to each other, or b) arranging 403, for example flexibly arranging 404 of chiplets on the carrier, or c) increasing 405 a number of identical parts with respect to the chiplets, or d) avoiding 406 a change of chiplets, e.g. for a manufacture of different multi-chip systems, or e) integrating 407 a configuration for a connection, for example data connection, between chiplets on the carrier. R.409094

[0071] - 11 -

[0072] Fig. 8A schematically shows a side view of a carrier 10Od according to the disclosure in a first configuration according to some examples. Two chiplets 200-1, 200-2 are flexibly connectable to each other via connecting lines VL, wherein one or more of the connecting lines are configurable, wherein, for example, at least one connecting line can be manufactured or cut, for example, during and / or after the production of the carrier 100d. This allows the topology of the at least one connecting line to be flexibly adapted to different chiplets and / or arrangements of chiplets 200-1, 200-2 on the carrier 10Od, optionally also after the production of the carrier 100d. In the present case, the configurability is realized, for example, by short-circuit bridges A1, which, in the configuration shown in Fig. 8A, connect the connecting lines VL (and thus, for example,The connection of the first chiplet 200-1 to the second chiplet 200-2 is also implemented in area B1 of the second chiplet 200-2. In some examples, the short-circuit bridges A1 can have different lengths and / or thicknesses. In contrast, the arrows A2 in Fig. 8A symbolize an area B2 in which the connecting lines VL are not connected to the second chiplet 200-2.

[0073] Fig. 8B schematically shows a side view of a carrier 10Od according to the disclosure in a second configuration according to some examples. In contrast to the configuration according to Fig. 8A, in the configuration according to Fig. 8B the connecting lines VL in region B1 are implemented by means of short-circuit bridges AT, which connect two connecting line sections VL-1, VL-2, e.g., in the carrier 100d, to each other, but do not establish a connection to the second chiplet 200-2. In region B2, the connecting lines VL, e.g., the connecting line sections VL-2, are, however, connected to the chiplet 200-2, see the arrows A2'.

[0074] In some examples, one or more of the connecting lines VL a) have one or more short-circuit bridges, and / or b) are designed as short-circuit bridges. This allows for a particularly simple configuration of connections in some examples.

[0075] In some examples, the carrier 100, 100a, ... , e.g. by inserting short-circuit bridges A1 , AT, e.g. of different lengths and / or thicknesses, can be connected to different chiplets 200-1 , 200-2, ..., e.g. to a respective R.409094

[0076] - 12 -

[0077] The connection map of the different chiplets, e.g. silicon chips, can be adapted, for example during manufacturing, e.g. without having to implement different substrate layouts for the carrier.

[0078] The principle according to the disclosure allows, in some examples, a separation between a geometric connection of the chiplets (for example, defined by the positions of (d2d) connections on the chiplets) and data routing. In some examples, data routing on the chiplets is at least partially integrated, for example, by means of the connections 200-1 a, 200-2a, ... of the chiplets, but configurable by short-circuit bridges KB of the carrier or, more generally, by the connecting lines VL, VL', VL", VL'", 122a, 122b and / or the connecting device 120, 120a, 120b, for example, a multiplexer device, of the carrier.

[0079] In some examples, the carrier is specific to a particular multi-chip module, and the connecting lines VL, VL', VL", VL'", 122a, 122b, possibly with short-circuit bridges KB, are present in the carrier, for example, in a substrate material of the carrier, for example, by means of which data routing for at least one chiplet arranged on the carrier can be configured. This means that in some examples, a particular chiplet can remain universal, i.e., without variants, because project-specific adaptations, such as a specific arrangement of the chiplet on the carrier, e.g., relative to at least one other chiplet, can be enabled by the carrier, whose connecting lines VL, VL', ... or short-circuit bridges KB or connection device, e.g., multiplexer device, 120, are specifically adaptable to a particular project, e.g., configurable.This eliminates the need for software-based configuration on the chiplet in some examples, which is not possible or only implementable with considerable effort in some cases due to comparatively high signal frequencies on the data lines. Furthermore, it eliminates the need for hardware-based configuration on the chiplet in some examples, for example using gates, which is not possible or only implementable with considerable effort in some cases due to the comparatively low impedances required on at least some lines in certain applications.

Claims

R.409094 - 13 - Claims 1. Carrier (100; 100a; 100b; 100c; 100d), for example substrate, for at least one chiplet (200-1 , 200-2, ...), having several connection areas (110-1 , 110-2, ...) for connecting terminals (200-1 a, 200-2a, ...) of the at least one chiplet (200-1 , 200-2, ...), wherein contact elements (112-1 , 112-2, ...) are provided in each of the several connection areas (110-1 , 110-2, ...) for contacting the terminals (200-1 a, 200-2a, ...) of the at least one chiplet (200-1 , 200-2, ...), and wherein the carrier (100; 100a; 100b; 100c; 100d) Connecting lines (VL; VL') for connecting the contact elements (112-1 , 112-2, ...) have at least two different connection areas (110-1 , 110-2, ...) together.

2. Carrier (100; 100a; 100b; 100c; 100d) according to claim 1, wherein one or more of the connecting lines (VL; VL') are at least partially or partially integrated into the carrier (100; 100a; 100b; 100c; 100d).

3. Carrier (100; 100a; 100b; 100c; 10Od) according to at least one of the preceding claims, wherein the carrier (100; 100a; 100b; 100c; 100d) has a multilayer structure (100-ML), wherein one or more of the connecting lines (VL; VL') are arranged in different layers of the multilayer structure (100-ML).

4. Carrier (100; 100a; 100b; 100c; 10Od) according to at least one of the preceding claims, wherein in at least one connection area (110-2) of the several connection areas (110-1 , 110-2, ...) several contact elements (112-2a, 112-2b, ...) are provided in each of different orientations.

5. Carrier (100; 100a; 100b; 100c; 10Od) according to at least one of the preceding claims, wherein one or more of the connecting lines (VL; VL') are configurable, wherein, for example, at least one connecting line can be manufactured or separated, for example, during and / or after the manufacture of the carrier (100; 100a; 100b; 100c; 10Od). R.409094 - 14 - 6. Carrier (100; 100a; 100b; 100c; 10Od) according to at least one of the preceding claims, wherein one or more of the connecting lines (VL; VL') a) have one or more short-circuit bridges, and / or b) are designed as short-circuit bridges.

7. Support (100; 100a; 100b; 100c; 100d) according to at least one of the preceding claims, wherein one or more of the connecting lines (VL; VL') have at least one first connecting line section (VLA-1 , VLA-3) which extends, for example, substantially perpendicular to a surface (102) of the support (100; 100a; 100b; 100c ).

8. Carrier (100; 100a; 100b; 100c; 10Od) according to at least one of the preceding claims, wherein one or more of the connecting lines (VL; VL') have at least one second connecting line section (VLA-2) which extends, for example, substantially parallel to a surface (102) of the carrier (100; 100a; 100b; 100c; 100d), wherein, for example, the at least one second connecting line section (VLA-2) is associated with, for example, arranged in, at least one layer (L-1) of a multilayer structure (100-ML).

9. Carrier (100; 100a; 100b; 100c; 10Od) according to at least one of the preceding claims, wherein the multiple connection areas (110-1 , 110-2, ...) are configured for connecting at least one of the following elements: a) data lines (DL) of the at least one chiplet (200-1 , 200-2, ...), or b) power supply lines (EVL) of the at least one chiplet (200-1 , 200-2, ...).

10. Carrier (100; 100a; 100b; 100c; 100d) according to at least one of the preceding claims, comprising at least one connecting device, for example a multiplexer device, (120) which is configured to selectively connect contact elements (112-1 , 112-2, ...) from different connection areas (110-1 , 110-2, ...) of the several connection areas (110-1 , 110-2, ...) to each other, wherein, for example, the connecting device (120) is configurable, for example by means of short-circuit bridges (122a, 122b). R.409094 - 15 - 11. System (1000) comprising at least one carrier (100; 100a; 100b; 100c; 100d) according to at least one of the preceding claims and at least one chiplet (200-1 , 200-2, ...).

12. Method for providing a carrier (100; 100a; 100b; 100c; 100d), for example substrates, for at least one chiplet (200-1 , 200-2, ...), comprising several connection areas (110-1 , 110-2, ...) for connecting terminals (200-1 a, 200-2a, ...) of the at least one chiplet (200-1 , 200-2, ...), wherein contact elements (112-1 , 112-2, ...) are provided in each of the several connection areas (110-1 , 110-2, ...) for contacting the terminals (200-1 a, 200-2a, ...) of the at least one chiplet (200-1 , 200-2, ...), and wherein the carrier (100; 100a; 100b; 100c; 100d) connecting lines (VL; VL') for connecting the contact elements (112-1 , 112-2, ...) have at least two different connection areas (110-1 , 110-2, ...) to each other, wherein the method comprises: providing (300) the carrier (100; 100a; 100b; 100c; 100d), determining (302) information (1-1) for the arrangement of the connection areas (110-1 , 110-2, ...) and contact elements (112-1 , 112-2, ...), creating (304) the contact elements (112-1 , 112-2, ...) in the connection areas (110-1 , 110- 2, ...), creating (306) the connecting lines (VL; VL'), and, optionally, configuring (307) the connecting lines (VL; VL'), and, optionally, arranging (308) the at least one chiplet (200-1 , 200-2, ...) on the carrier (100; 100a; 100b; 100c; 100d).

13. Use (400) of the carrier (100; 100a; 100b; 100c; 100d) according to at least one of claims 1 to 10 and / or of the system (1000) according to claim 11 and / or of the method according to claim 12 for at least one of the following elements: a) connecting (401), for example flexibly connecting (402), of chiplets to the carrier, or b) arranging (403), for example flexibly arranging (404) of chiplets on the carrier, or c) increasing (405) a number of identical parts with respect to the chiplets, or d) preventing (406) a change of chiplets, or e) integrating (407) a configuration for a connection, for example a data connection, between chiplets on the carrier.

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