Display substrate and preparation method therefor, and display device

Abstract

A display substrate and a preparation method therefor, and a display device. The display substrate comprises a plurality of circuit units, first connection lines (81), first power source traces (91), second connection lines (82), second power source traces (92) and data signal lines (70). The display substrate is divided into a first region (110) and a second region (120), wherein the first region (110) is a region where the first connection lines (81) or the second connection lines (82) are disposed, and the second region (120) is a region where no first connection lines (81) and second connection lines (82) are disposed; in the second region (120), the first power source traces (91) are connected to the second power source traces (92); and in the first region (110), a second power source trace (92) is disposed between two adjacent second connection lines (82), and / or, a first power source trace (91) is disposed between two adjacent first connection lines (81).

Description

Display substrate, preparation method thereof and display device TECHNICAL FIELD

[0001] The present document relates to, but is not limited to, the technical field of display, in particular to a display substrate, a preparation method thereof and a display device. BACKGROUND

[0002] Organic light emitting diode (OLED) and quantum dot light emitting diode (QLED) are active light emitting display devices, which have the advantages of self-luminous, wide viewing angle, high contrast, low power consumption, extremely high response speed, lightness, flexibility, low cost, etc. With the continuous development of display technology, flexible display devices with OLED or QLED as light emitting devices and controlled by thin film transistors (TFT) have become the mainstream products in the current display field.

[0003] SUMMARY

[0004] The following is a summary of the subject matter of the detailed description herein. This summary is not intended to limit the scope of the claims.

[0005] In one aspect, the present disclosure provides a display substrate, comprising a plurality of circuit units forming a plurality of unit rows and a plurality of unit columns, at least one first connection line extending along a first direction, at least one first power supply trace extending along the first direction, at least one second connection line extending along a second direction, at least one second power supply trace extending along the second direction, and a plurality of data signal lines extending along the second direction, the first direction and the second direction intersecting; at least one circuit unit comprises a pixel driving circuit, the pixel driving circuit is connected with the data signal line, the second connection line is connected with the data signal line through the first connection line; the display substrate is divided into a first area and a second area, the first area is an area where the first connection line is arranged or the second connection line is arranged, and the second area is an area where the first connection line and the second connection line are not arranged; in the second area, the first power supply trace and the second power supply trace are connected; in the first area, at least one second power supply trace is arranged between two second connection lines adjacent in the first direction, and / or at least one first power supply trace is arranged between two first connection lines adjacent in the second direction.

[0006] In an exemplary embodiment, the first power supply line arranged between two of the second connection lines in the first region extends to the second region and is connected with the second power supply line in the second region.

[0007] In an exemplary embodiment, the second power supply line arranged between two of the second connection lines in the first region extends to the second region and is connected with the first power supply line in the second region.

[0008] In an exemplary embodiment, in the first region, at least one second power supply line is arranged between two of the second connection lines adjacent in the first direction, at least one first connection line and at least one first power supply line are arranged in at least one cell row, a first break is arranged between the first connection line and the first power supply line, and the second power supply line arranged between two of the second connection lines is connected with the first power supply line on one side of the first break.

[0009] In an exemplary embodiment, in the first region, at least one first power supply line is arranged between two of the first connection lines adjacent in the second direction, at least one second connection line and at least one second power supply line are arranged in at least one cell column, a second break is arranged between the second connection line and the second power supply line, and the first power supply line arranged between two of the first connection lines is connected with the second power supply line on one side of the second break.

[0010] In an exemplary embodiment, in the first region, at least one second power supply line is arranged between two of the second connection lines adjacent in the first direction, at least one first power supply line is arranged between two of the first connection lines adjacent in the second direction, and the second power supply line arranged between two of the second connection lines is connected with the first power supply line arranged between two of the first connection lines.

[0011] In an exemplary embodiment, at least one first connection line and at least one first power supply line are arranged in at least one cell row, a first break is arranged between the first connection line and the first power supply line, and the second power supply line arranged between two of the second connection lines is connected with the first power supply line on one side of the first break; at least one second connection line and at least one second power supply line are arranged in at least one cell column, a second break is arranged between the second connection line and the second power supply line, and the first power supply line arranged between two of the first connection lines is connected with the second power supply line on one side of the second break.

[0012] In an exemplary embodiment, in the first region, two second power supply lines are arranged between two second connection lines adjacent in the first direction, and one first power supply line is arranged between two first connection lines adjacent in the second direction.

[0013] In an exemplary embodiment, in the first region, one second power supply line is arranged between two second connection lines adjacent in the first direction, and two first power supply lines are arranged between two first connection lines adjacent in the second direction.

[0014] In an exemplary embodiment, in a direction perpendicular to the display substrate, the display substrate comprises a plurality of conductive layers, the first connection lines and the first power supply lines are arranged in the same conductive layer, the second connection lines, the second power supply lines and the data signal lines are arranged in the same conductive layer, and the first connection lines and the second connection lines are arranged in different conductive layers.

[0015] In an exemplary embodiment, the display substrate further comprises at least one first power supply line extending along the second direction, and the pixel driving circuit comprises at least a storage capacitor, the storage capacitor comprises a first plate and a second plate, and a projection of the second plate on a display substrate plane at least partially overlaps a projection of the first plate on the display substrate plane; in at least one circuit unit, the first power supply line is connected to the second plate through a power supply connection strip; in at least one unit row, a part of the circuit units are provided with the power supply connection strip, and another part of the circuit units are not provided with the power supply connection strip.

[0016] In an exemplary embodiment, in at least one unit row, the power supply connection strip is arranged in the circuit units of odd-numbered unit columns, or the power supply connection strip is arranged in the circuit units of even-numbered unit columns.

[0017] In an exemplary embodiment, at least one circuit unit further comprises a first power supply electrode and a second power supply electrode, the second plate is connected to the power supply connection strip through the first power supply electrode, and the first power supply line is connected to the power supply connection strip through the second power supply electrode; in at least one unit row, the second plates in some adjacent circuit units are an integral structure connected to each other, the second power supply electrodes in some adjacent circuit units are an integral structure connected to each other, the second plates and the second power supply electrodes form a transverse power supply connection line extending along the first direction, and the transverse power supply connection line and the first power supply line form a meshed communication structure for transmitting a first power supply signal in a meshed manner.

[0018] In an exemplary embodiment, in at least one unit row, all circuit units are provided with the power connection strips, and in at least another unit row, part of the circuit units are provided with the power connection strips.

[0019] In an exemplary embodiment, the unit row in which all the circuit units are provided with the power connection strips and the unit row in which part of the circuit units are provided with the power connection strips are arranged alternately.

[0020] In an exemplary embodiment, in at least one unit row, the second plates in adjacent circuit units are connected to each other through plate connection strips to form a horizontal power connection line extending along the first direction, and the horizontal power connection line and the first power lines form a meshed communication structure for transmitting the first power signal in a meshed manner.

[0021] In an exemplary embodiment, all the unit rows are the unit rows in which part of the circuit units are provided with the power connection strips.

[0022] In another aspect, the present disclosure also provides a display device comprising the aforementioned display substrate.

[0023] In yet another aspect, the present disclosure also provides a preparation method of a display substrate, comprising forming a plurality of circuit units in a plurality of unit rows and a plurality of unit columns, at least one first connection line extending along a first direction, at least one first power line extending along the first direction, at least one second connection line extending along a second direction, at least one second power line extending along the second direction, and a plurality of data signal lines extending along the second direction, the first direction and the second direction intersecting; the preparation method comprises:

[0024] forming a pixel driving circuit in at least one circuit unit, the pixel driving circuit being connected to the data signal line, the second connection line being connected to the data signal line through the first connection line; the display substrate is divided into a first region and a second region, the first region being a region in which the first connection line or the second connection line is arranged, and the second region being a region in which the first connection line and the second connection line are not arranged; in the second region, the first power line and the second power line are connected; in the first region, at least one second power line is arranged between two second connection lines adjacent in the first direction, and / or at least one first power line is arranged between two first connection lines adjacent in the second direction.

[0025] Other aspects can become apparent after reading and understanding the accompanying drawings and detailed description. BRIEF DESCRIPTION OF DRAWINGS

[0026] The accompanying drawings are used to provide an understanding of the technical solutions of the present disclosure, and constitute a part of the specification, and are used to explain the technical solutions of the present disclosure together with the embodiments of the present disclosure, and do not constitute a limitation on the technical solutions of the present disclosure.

[0027] FIG. 1 is a structural schematic diagram of a display device;

[0028] FIG. 2 is a structural schematic diagram of a display substrate;

[0029] FIG. 3 is a plan structural schematic diagram of a display area in a display substrate;

[0030] FIG. 4 is a cross-sectional structural schematic diagram of a display area in a display substrate;

[0031] FIG. 5 is an equivalent circuit schematic diagram of a pixel driving circuit;

[0032] FIG. 6 is a structural schematic diagram of a data connection line according to an example embodiment of the present disclosure;

[0033] FIG. 7 is a structural schematic diagram of a data connection line and a power supply line according to an example embodiment of the present disclosure;

[0034] FIG. 8A is a plan structural schematic diagram of a display substrate according to an example embodiment of the present disclosure;

[0035] FIG. 8B is a structural schematic diagram of a data connection line and a power supply line in FIG. 8A;

[0036] FIG. 9 is a schematic diagram of forming a shielding layer pattern of a display substrate according to the present disclosure;

[0037] FIGS. 10A and 10B are schematic diagrams of a display substrate after forming a first semiconductor layer pattern according to the present disclosure;

[0038] FIGS. 11A and 11B are schematic diagrams of a display substrate after forming a first conductive layer pattern according to the present disclosure;

[0039] FIGS. 12A and 12B are schematic diagrams of a display substrate after forming a second conductive layer pattern according to the present disclosure;

[0040] FIGS. 13A and 13B are schematic diagrams of a display substrate after forming a second semiconductor layer pattern according to the present disclosure;

[0041] FIGS. 14A and 14B are schematic diagrams of a display substrate after forming a third conductive layer pattern according to the present disclosure;

[0042] FIG. 15 is a schematic diagram of a display substrate after forming a sixth insulating layer pattern according to the present disclosure;

[0043] FIGS. 16A and 16B are schematic diagrams of a display substrate after forming a fourth conductive layer pattern according to the present disclosure;

[0044] FIG. 17 is a schematic view of a display substrate according to an embodiment of the present disclosure after forming a first planarization layer pattern;

[0045] FIGS. 18A and 18B are schematic views of a display substrate according to an embodiment of the present disclosure after forming a fifth conductive layer pattern;

[0046] FIG. 19 is a schematic view of a display substrate according to an embodiment of the present disclosure after forming a second planarization layer pattern;

[0047] FIGS. 20A and 20B are schematic views of a display substrate according to an embodiment of the present disclosure after forming a sixth conductive layer pattern;

[0048] FIG. 21 is a schematic view of another display substrate according to an embodiment of the present disclosure;

[0049] FIG. 22 is a schematic view of a display substrate according to another embodiment of the present disclosure after forming a second conductive layer pattern;

[0050] FIG. 23 is a schematic view of another data connection line and power supply line according to an embodiment of the present disclosure;

[0051] FIG. 24 is a schematic view of another data connection line and power supply line according to an embodiment of the present disclosure;

[0052] FIG. 25 is a schematic view of another data connection line and power supply line according to an embodiment of the present disclosure;

[0053] FIG. 26 is a schematic view of another data connection line and power supply line according to an embodiment of the present disclosure.

[0054] The reference signs are explained as follows: 11-first active layer; 12-second active layer; 13-third active layer; 14-fourth active layer; 15-fifth active layer; 16-sixth active layer; 17-seventh active layer; 18-eighth active layer; 21-first scan signal line; 22-second scan signal line; 23-third scan signal line; 24-fourth scan signal line; 25-emitting signal line; 31-first plate; 32-second plate; 33-opening; 34-plate connecting strip; 35-shielding line; 41-first initial signal line; 42-second initial signal line; 43-third initial signal line; 44-fourth initial connecting block; 45-fifth initial connecting block; 46-sixth initial connecting block; 47-first initial connecting line; 48-second initial connecting line; 49-third initial connecting line; 51-first connecting electrode; 52-second connecting electrode; 53-third connecting electrode; 54-fourth connecting electrode; 55-fifth connecting electrode; 56-sixth connecting electrode; 57-seventh connecting electrode; 58-eighth connecting electrode; 59-ninth connecting electrode; 60-power supply connecting strip; 61-eleventh connecting electrode; 62-twelfth connecting electrode; 63-thirteenth connecting electrode; 70-data signal line; 71-first power supply line; 72-anode connecting electrode; 80-data lead-out line; 81-first connecting line; 82-second connecting line; 83-data connecting block; 84-first data transfer strip; 85-first dummy electrode; 86-second data transfer strip; 91-first power supply trace; 92-second power supply trace; 93-trace connecting block; 94-trace transfer strip; 95-second dummy electrode; 100-display area; 101-substrate.102 - driving structure layer; 103 - light emitting structure layer; 104 - encapsulation structure layer; 110 - first area; 120 - second area; 130 - shielding electrode; 131 - first shielding connection strip; 132 - second shielding connection strip; 133 - third shielding connection strip; 134 - fourth shielding connection strip; 200 - binding area; 300 - frame area. DETAILED DESCRIPTION

[0055] For the purposes of the present disclosure, the technical solutions and advantages will be more clearly apparent in the following detailed description of embodiments of the present disclosure. Note that the embodiments can be implemented in many different forms. It can be easily understood by those skilled in the art that the manner and content can be changed into various forms without departing from the spirit and scope of the present disclosure. Therefore, the present disclosure should not be interpreted as being limited to the content described in the following embodiments. The embodiments in the present disclosure and the features in the embodiments can be arbitrarily combined with each other as long as they do not conflict.

[0056] The scale of the drawings in the present disclosure can be used as a reference in the actual process, but is not limited thereto. For example, the width-length ratio of the channel, the thickness and spacing of each film layer, and the width and spacing of each signal line can be adjusted as needed. The number of pixels in the display substrate and the number of sub-pixels in each pixel are also not limited to the number shown in the drawings. The drawings described in the present disclosure are only schematic diagrams, and one embodiment of the present disclosure is not limited to the shapes or values shown in the drawings.

[0057] The ordinal numbers "first", "second", "third", and the like in the present specification are set in order to avoid confusion of the components, and are not intended to be limiting in terms of number.

[0058] In the present specification, the words indicating the orientation or positional relationship such as "middle", "upper", "lower", "front", "rear", "vertical", "horizontal", "top", "bottom", "inner", "outer", and the like are used to explain the positional relationship of the components with reference to the drawings, and are only for the convenience of describing the present specification and simplifying the description, and do not indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation on the present disclosure. The positional relationship of the components is appropriately changed according to the direction of describing each component. Therefore, it is not limited to the words described in the specification, and can be appropriately changed according to the situation.

[0059] In this specification, unless otherwise explicitly specified and limited, the terms "mount", "connected", and "linked" are to be interpreted broadly. For example, can be fixedly connected, or detachably connected, or integrally connected; can be mechanically connected, or electrically connected; can be directly connected, or indirectly connected via an intervening member, or internal communication of two elements. The specific meaning of the above terms in the present disclosure can be understood in light of the specific circumstances for those skilled in the art.

[0060] In this specification, a transistor refers to an element including at least a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between a drain electrode (a drain electrode terminal, a drain region, or a drain electrode) and a source electrode (a source electrode terminal, a source region, or a source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, the channel region refers to a region where current flows mainly.

[0061] In this specification, the first electrode can be a drain electrode and the second electrode can be a source electrode, or the first electrode can be a source electrode and the second electrode can be a drain electrode. The functions of the "source electrode" and the "drain electrode" are sometimes interchanged with each other in the case of using a transistor whose polarity is reversed or in the case where the direction of current flowing in a circuit is changed, and the like. Therefore, in this specification, the "source electrode" and the "drain electrode" can be interchanged with each other, and the "source terminal" and the "drain terminal" can be interchanged with each other.

[0062] In this specification, "electrically connected" includes the case where components are connected through a component having some function of electricity. The component having some function of electricity is not particularly limited as long as electric signals can be transmitted and received between components to be connected. Examples of the component having some function of electricity include an electrode and a wiring as well as a switching element such as a transistor, a resistor, an inductor, a capacitor, and another component having some function.

[0063] In this specification, "parallel" refers to a state where an angle formed between two straight lines is greater than or equal to -10° and less than or equal to 10°, and thus includes a state where the angle is greater than or equal to -5° and less than or equal to 5°. In addition, "perpendicular" refers to a state where an angle formed between two straight lines is greater than or equal to 80° and less than or equal to 100°, and thus includes a state where the angle is greater than or equal to 85° and less than or equal to 95°.

[0064] In this specification, "film" and "layer" can be interchanged with each other. For example, "a conductive layer" can be replaced with "a conductive film". Similarly, "an insulating film" can be replaced with "an insulating layer".

[0065] In the present specification, a triangle, a rectangle, a trapezoid, a pentagon, or a hexagon, etc. are not strictly so, and can be an approximate triangle, rectangle, trapezoid, pentagon, or hexagon, etc. There can be some small deformation due to a tolerance, there can be a lead angle, an arc edge, and deformation, etc.

[0066] In the present disclosure, "about" means not strictly limited boundaries, allowing values within the range of process and measurement errors.

[0067] FIG. 1 is a structural schematic diagram of a display device. As shown in FIG. 1, the display device can include a timing controller, a data driver, a scan driver, a light emitting driver, and a pixel array, the timing controller is connected with the data driver, the scan driver, and the light emitting driver respectively, the data driver is connected with a plurality of data signal lines (D1 to Dn) respectively, the scan driver is connected with a plurality of scan signal lines (S1 to Sm) respectively, and the light emitting driver is connected with a plurality of light emitting signal lines (E1 to Eo) respectively. The pixel array can include a plurality of sub-pixels Pxij, i and j can be natural numbers, at least one sub-pixel Pxij can include a circuit unit and a light emitting unit, the circuit unit can include at least a pixel driving circuit, the pixel driving circuit is connected with the scan signal line, the light emitting signal line, and the data signal line respectively, and the light emitting unit can include a light emitting device connected with the pixel driving circuit of the circuit unit. In an exemplary embodiment, the timing controller can provide a gray value and a control signal suitable for the specification of the data driver to the data driver, can provide a clock signal, a scan start signal, and the like suitable for the specification of the scan driver to the scan driver, and can provide a clock signal, an emission stop signal, and the like suitable for the specification of the light emitting driver to the light emitting driver. The data driver can generate data voltages to be provided to the data signal lines D1, D2, D3, …, and Dn using the gray value and the control signal received from the timing controller. For example, the data driver can sample the gray value using the clock signal, and apply data voltages corresponding to the gray value to the data signal lines D1 to Dn in units of a pixel row. n can be a natural number. The scan driver can generate scan signals to be provided to the scan signal lines S1, S2, S3, …, and Sm by receiving the clock signal, the scan start signal, and the like from the timing controller. For example, the scan driver can sequentially provide the scan signal having an on-level pulse to the scan signal lines S1 to Sm. For example, the scan driver can be configured in the form of a shift register, and can generate the scan signal in a manner that sequentially transfers the scan start signal provided in the form of an on-level pulse to a next stage circuit under the control of the clock signal. m can be a natural number. The light emitting driver can generate emission signals to be provided to the light emitting signal lines E1, E2, E3, …, and Eo by receiving the clock signal, the emission stop signal, and the like from the timing controller. For example, the light emitting driver can sequentially provide the emission signal having an off-level pulse to the light emitting signal lines E1 to Eo. For example, the light emitting driver can be configured in the form of a shift register, and can generate the emission signal in a manner that sequentially transfers the emission stop signal provided in the form of an off-level pulse to a next stage circuit under the control of the clock signal. o can be a natural number. In an exemplary embodiment, the pixel array can be disposed on a display substrate.

[0068] FIG. 2 is a structural diagram of a display substrate. As shown in FIG. 2, the display substrate can include a display area 100, a binding area 200 located on one side of the display area 100, and a frame area 300 located on the other side of the display area 100. In an exemplary embodiment, the display area 100 can be a flat area including a plurality of sub-pixels constituting a pixel array, the plurality of sub-pixels being configured to display dynamic pictures or static images, and the display area 100 can be referred to as an active area (AA). In an exemplary embodiment, the display substrate can adopt a flexible substrate, and thus the display substrate can be deformable, for example, curled, bent, folded, or rolled up.

[0069] In an exemplary embodiment, the binding area 200 can include, in sequence along a direction away from the display area, a lead-out line area, a bending area, a driving chip area, and a binding pin area, the lead-out line area being connected to the display area 100 and including at least data lead-out lines. The bending area can be connected to the lead-out line area and can include at least a composite insulating layer provided with a recess configured to bend the binding area to the back of the display area. The driving chip area can include an integrated circuit (IC) configured to be connected to the plurality of data lead-out lines. The binding pin area can include a bonding pad configured to be connected to an external flexible printed circuit (FPC).

[0070] In an exemplary embodiment, the frame area 300 can include, in sequence along a direction away from the display area 100, a circuit area, a power line area, a crack dam area, and a cutting area. The circuit area can be connected to the display area 100 and can include at least a gate driving circuit connected to a scanning signal line and a light-emitting signal line in the display area 100. The power line area can be connected to the circuit area and can include at least a frame power lead extending along a direction parallel to an edge of the display area and connected to a cathode in the display area 100. The crack dam area can be connected to the power line area and can include at least a plurality of cracks provided on a composite insulating layer. The cutting area can be connected to the crack dam area and can include at least a cutting groove provided on the composite insulating layer, the cutting groove being configured to be cut by a cutting device along the cutting groove after all film layers of the display substrate are prepared.

[0071] In an exemplary embodiment, the lead-out line area in the binding area 200 and the power line area in the frame area 300 can be provided with an isolation dam, the isolation dam extending along a direction parallel to an edge of the display area and forming a ring structure surrounding the display area 100, the edge of the display area being an edge of the display area on one side of the binding area or the frame area.

[0072] FIG. 3 is a schematic diagram of a planar structure of a display region in a display substrate. As shown in FIG. 3, the display region can include a plurality of pixel units P arranged in a matrix manner, and at least one pixel unit P can include a first sub-pixel P1, a second sub-pixel P2, a third sub-pixel P3, and a fourth sub-pixel P4. Each sub-pixel can include a circuit unit and a light-emitting unit, and the circuit unit can include at least a pixel driving circuit. The pixel driving circuit is connected to a scan signal line, a light-emitting signal line, and a data signal line, respectively, and is configured to receive a data voltage transmitted by the data signal line under the control of the scan signal line and the light-emitting signal line, and output a corresponding current to the light-emitting unit. The light-emitting unit can include a light-emitting device connected to the pixel driving circuit of the sub-pixel where the light-emitting device is located, and the light-emitting device is configured to emit light with a corresponding brightness in response to the current output by the pixel driving circuit of the sub-pixel where the light-emitting device is located.

[0073] In an example embodiment, the first sub-pixel P1 can be a red sub-pixel (R) that emits red light, the second sub-pixel P2 can be a blue sub-pixel (B) that emits blue light, and the third sub-pixel P3 and the fourth sub-pixel P4 can be green sub-pixels (G) that emit green light. In an example embodiment, the shape of the sub-pixel can be rectangular, diamond, pentagonal, or hexagonal, and the four sub-pixels can be arranged in an RGBG manner.

[0074] In other example embodiments, the pixel unit can include three sub-pixels arranged in a horizontal parallel manner or a vertical parallel manner, and the present disclosure does not limit the same.

[0075] FIG. 4 is a schematic diagram of a cross-sectional structure of a display region in a display substrate, illustrating the structure of four sub-pixels in the display region. As shown in FIG. 4, in a plane perpendicular to the display substrate, the display substrate can include a driving structure layer 102 disposed on a substrate 101, a light-emitting structure layer 103 disposed on a side of the driving structure layer 102 away from the substrate 101, and an encapsulation structure layer 104 disposed on a side of the light-emitting structure layer 103 away from the substrate 101. In some possible implementations, the display substrate can include other film layers, such as a touch structure layer, and the present disclosure does not limit the same.

[0076] In an example embodiment, the substrate 101 can be a flexible substrate or can be a rigid substrate. The driving structure layer 102 can include a plurality of circuit units, which can at least include a pixel driving circuit composed of a plurality of transistors and a storage capacitor. The light-emitting structure layer 103 can include a plurality of light-emitting units, each of which can include a light-emitting device, which can at least include an anode, an organic light-emitting layer, and a cathode, the anode being connected with the pixel driving circuit, the organic light-emitting layer being connected with the anode, and the cathode being connected with the organic light-emitting layer, the organic light-emitting layer emitting light of a corresponding color under the driving of the anode and the cathode. The encapsulating structure layer 104 can include a first encapsulating layer, a second encapsulating layer, and a third encapsulating layer stacked together, the first encapsulating layer and the third encapsulating layer can be made of inorganic materials, the second encapsulating layer can be made of an organic material, the second encapsulating layer being arranged between the first encapsulating layer and the third encapsulating layer to form an inorganic material / organic material / inorganic material stacked structure, which can ensure that external water vapor cannot enter the light-emitting structure layer 103.

[0077] FIG. 5 is an equivalent circuit schematic diagram of a pixel driving circuit. In an example embodiment, the pixel driving circuit can be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, 7T1C, or 8T1C structure. As shown in FIG. 5, the pixel driving circuit can include 8 transistors (first transistor T1 to eighth transistor T8) and 1 storage capacitor C, and is connected with 10 signal lines (first scan signal line S1, second scan signal line S2, third scan signal line S3, fourth scan signal line S4, light-emitting signal line EM, first initial signal line INIT1, second initial signal line INIT2, third initial signal line INIT3, data signal line DATA, and first power supply line VDD).

[0078] In an example embodiment, the pixel driving circuit can include a first node N1, a second node N2, a third node N3, and a fourth node N4. The first node N1 is connected with the first electrode of the second transistor T2, the gate electrode of the third transistor T3, and the first end of the storage capacitor C, respectively. The second node N2 is connected with the first electrode of the third transistor T3, the second electrode of the fourth transistor T4, the second electrode of the fifth transistor T5, and the second electrode of the eighth transistor T8, respectively. The third node N3 is connected with the second electrode of the first transistor T1, the second electrode of the second transistor T2, the second electrode of the third transistor T3, and the first electrode of the sixth transistor T6, respectively. The fourth node N4 is connected with the second electrode of the sixth transistor T6 and the second electrode of the seventh transistor T7, respectively.

[0079] In an example embodiment, the first end of the storage capacitor C is connected with the first node N1, and the second end of the storage capacitor C is connected with the first power supply line VDD.

[0080] In an exemplary embodiment, the first transistor T1 can be referred to as a first initialization transistor, a gate electrode of the first transistor T1 is connected to the third scan signal line S3, a first electrode of the first transistor T1 is connected to the first initial signal line INIT1, and a second electrode of the first transistor T1 is connected to the third node N3.

[0081] In an exemplary embodiment, the second transistor T2 can be referred to as a compensation transistor, a gate electrode of the second transistor T2 is connected to the fourth scan signal line S4, a first electrode of the second transistor T2 is connected to the first node N1, and a second electrode of the second transistor T2 is connected to the third node N3.

[0082] In an exemplary embodiment, the third transistor T3 can be referred to as a driving transistor, a gate electrode of the third transistor T3 is connected to the first node N1, a first electrode of the third transistor T3 is connected to the second node N2, and a second electrode of the third transistor T3 is connected to the third node N3.

[0083] In an exemplary embodiment, the fourth transistor T4 can be referred to as a data write transistor, a gate electrode of the fourth transistor T4 is connected to the first scan signal line S1, a first electrode of the fourth transistor T4 is connected to the data signal line DATA, and a second electrode of the fourth transistor T4 is connected to the second node N2.

[0084] In an exemplary embodiment, the fifth transistor T5 can be referred to as a first emission control transistor, a gate electrode of the fifth transistor T5 is connected to the emission signal line EM, a first electrode of the fifth transistor T5 is connected to the first power supply line VDD, and a second electrode of the fifth transistor T5 is connected to the second node N2.

[0085] In an exemplary embodiment, the sixth transistor T6 can be referred to as a second emission control transistor, a gate electrode of the sixth transistor T6 is connected to the emission signal line EM, a first electrode of the sixth transistor T6 is connected to the third node N3, and a second electrode of the sixth transistor T6 is connected to the fourth node N4.

[0086] In an exemplary embodiment, the seventh transistor T7 can be referred to as a second initialization transistor, a gate electrode of the seventh transistor T7 is connected to the second scan signal line S2, a first electrode of the seventh transistor T7 is connected to the second initial signal line INIT2, and a second electrode of the seventh transistor T7 is connected to the fourth node N4.

[0087] In an exemplary embodiment, the eighth transistor T8 can be referred to as a third initialization transistor, a gate electrode of the eighth transistor T8 is connected to the second scan signal line S2, a first electrode of the eighth transistor T8 is connected to the third initial signal line INIT3, and a second electrode of the eighth transistor T8 is connected to the second node N2.

[0088] In an example embodiment, the first electrode of the light emitting device EL is connected to the fourth node N4, and the second electrode of the light emitting device EL is connected to the second power supply line VSS. The light emitting device EL can be an OLED including a first electrode (anode), an organic light emitting layer, and a second electrode (cathode) stacked, or can be a QLED including a first electrode (anode), a quantum dot light emitting layer, and a second electrode (cathode) stacked.

[0089] In an example embodiment, the first power supply line VDD is configured to provide a constant first voltage signal to the pixel driving circuit, the second power supply line VSS is configured to provide a constant second voltage signal to the light emitting device, and the voltage of the first voltage signal can be greater than the voltage of the second voltage signal, the first voltage signal can be referred to as a high level signal, and the second voltage signal can be referred to as a low level signal. The first initial voltage signal, the second initial voltage signal, and the third initial voltage signal can be constant voltage signals, which are not limited in the present disclosure.

[0090] In an example embodiment, the first transistor T1 to the eighth transistor T8 can be P-type transistors, or can be N-type transistors. Using the same type of transistors in the pixel driving circuit can simplify the process flow, reduce the process difficulty of the display panel, and improve the yield of the product. In some possible implementations, the first transistor T1 to the eighth transistor T8 can include P-type transistors and N-type transistors.

[0091] In an example embodiment, the first transistor T1 to the eighth transistor T8 can use low temperature poly-silicon transistors, or can use oxide transistors, or can use low temperature poly-silicon transistors and metal oxide transistors. The active layer of the low temperature poly-silicon transistor uses low temperature poly-silicon (LTPS), and the active layer of the metal oxide transistor uses oxide. The low temperature poly-silicon transistor has the advantages of high mobility and fast charging, and the oxide transistor has the advantage of low leakage current. Integrating the low temperature poly-silicon transistor and the metal oxide transistor on one display substrate forms an LTPO (Low Temperature Polycrystalline + Oxide) display substrate, which can take advantage of both and can achieve low frequency driving, reduce power consumption, and improve display quality.

[0092] With the development of display technology, consumers have higher and higher requirements on display effect and display quality of display products. Full screen and narrow frame products have gradually become the development trend of display products due to their large screen ratio and ultra-narrow frame. Therefore, the narrow frame design or even the frameless design in OLED display product design is paid more and more attention. In a display substrate, the data signal of an integrated circuit in a binding area needs to be introduced into a wider display area in a fanout manner through a data lead-out line, so that the lead-out line area occupies a larger space, resulting in a larger width of the lower frame. In addition, the gate drive circuit and the power lead line need to be arranged in the frame area, and the gate drive circuit and the power lead line occupy a larger space, resulting in a larger width of the left and right frames.

[0093] To reduce the width of the lower frame, the display substrate provided by the exemplary embodiments of the present disclosure adopts a Fanout in Pixel (FIP) structure, a plurality of data connection lines are arranged in the display area, one end of the plurality of data connection lines is connected with a plurality of data signal lines in the display area, the other end of the plurality of data connection lines extends to the binding area, and the plurality of data connection lines are connected with the integrated circuit through a plurality of data lead-out lines in the lead-out line area. Since the lead-out line area does not need to be arranged with fan-shaped diagonal lines, the width of the lead-out line area is reduced, and thus the width of the lower frame is reduced.

[0094] The exemplary embodiments of the present disclosure provide a display substrate. In an exemplary embodiment, the display substrate includes a plurality of circuit units forming a plurality of unit rows and a plurality of unit columns, at least one first connection line extending along a first direction, at least one first power trace extending along the first direction, at least one second connection line extending along a second direction, at least one second power trace extending along the second direction, and a plurality of data signal lines extending along the second direction, the first direction and the second direction intersecting; at least one circuit unit includes a pixel drive circuit connected with the data signal line, the second connection line is connected with the data signal line through the first connection line; the display substrate is divided into a first area and a second area, the first area is an area where the first connection line or the second connection line is arranged, and the second area is an area where the first connection line and the second connection line are not arranged; in the second area, the first power trace and the second power trace are connected; in the first area, at least one second power trace is arranged between two second connection lines adjacent in the first direction, and / or at least one first power trace is arranged between two first connection lines adjacent in the second direction.

[0095] In an exemplary embodiment, the first power supply line arranged between two of the first connection lines in the first region extends to the second region and is connected with the second power supply line in the second region.

[0096] In an exemplary embodiment, the second power supply line arranged between two of the second connection lines in the first region extends to the second region and is connected with the first power supply line in the second region.

[0097] In an exemplary embodiment, in the first region, at least one second power supply line is arranged between two of the second connection lines adjacent in the first direction, at least one first connection line and at least one first power supply line are arranged in at least one unit row, a first break is arranged between the first connection line and the first power supply line, and the second power supply line arranged between two of the second connection lines is connected with the first power supply line on one side of the first break.

[0098] In an exemplary embodiment, in the first region, at least one first power supply line is arranged between two of the first connection lines adjacent in the second direction, at least one second connection line and at least one second power supply line are arranged in at least one unit column, a second break is arranged between the second connection line and the second power supply line, and the first power supply line arranged between two of the first connection lines is connected with the second power supply line on one side of the second break.

[0099] In an exemplary embodiment, in the first region, at least one second power supply line is arranged between two of the second connection lines adjacent in the first direction, at least one first power supply line is arranged between two of the first connection lines adjacent in the second direction, and the second power supply line arranged between two of the second connection lines is connected with the first power supply line arranged between two of the first connection lines.

[0100] FIG. 6 is a structural schematic diagram of a data connection line in an exemplary embodiment of the present disclosure, in which the data connection line adopts a FIP structure. As shown in FIG. 6, in a plane parallel to the display substrate, the display substrate can include a display region 100, a binding region 200 located on one side of the display region 100, and a frame region 300 located on the other side of the display region 100. In a plane perpendicular to the display substrate, the display substrate can include a driving structure layer arranged on a substrate, a light-emitting structure layer arranged on a side of the driving structure layer away from the substrate, and an encapsulation structure layer arranged on a side of the light-emitting structure layer away from the substrate.

[0101] In an example embodiment, the driving structure layer of the display region 100 can include a plurality of circuit units constituting a plurality of unit rows and a plurality of unit columns, at least one circuit unit can include a pixel driving circuit configured to output a corresponding current to the connected light emitting device. The light emitting structure layer of the display region 100 can include a plurality of light emitting units, at least one light emitting unit can include a light emitting device connected with the pixel driving circuit of the corresponding circuit unit, the light emitting device is configured to emit light of a corresponding brightness in response to the current output by the connected pixel driving circuit.

[0102] In an example embodiment, the circuit unit referred to in the present disclosure refers to an area divided according to the pixel driving circuit, and the light emitting unit referred to in the present disclosure refers to an area divided according to the light emitting device. In an example embodiment, the position of the orthographic projection of the light emitting unit on the substrate can correspond to the position of the orthographic projection of the circuit unit on the substrate, or the position of the orthographic projection of the light emitting unit on the substrate can not correspond to the position of the orthographic projection of the circuit unit on the substrate.

[0103] In an example embodiment, a plurality of circuit units arranged in sequence along the first direction X can be referred to as a unit row, a plurality of circuit units arranged in sequence along the second direction Y can be referred to as a unit column, the plurality of unit rows and the plurality of unit columns constitute an array of circuit units arranged in an array, and the first direction X and the second direction Y intersect.

[0104] In an example embodiment, the driving structure layer of the display region 100 can further include a plurality of data signal lines 70, a plurality of first connection lines 81 and a plurality of second connection lines 82. The shape of the plurality of first connection lines 81 can be a straight line or a polyline extending along the first direction X, and the shape of the plurality of data signal lines 70 and the plurality of second connection lines 82 can be a straight line or a polyline extending along the second direction Y.

[0105] In the example embodiment, a plurality of data signal lines 70 are arranged in the first direction X at a set interval, at least one data signal line 70 is connected to a plurality of pixel driving circuits in a unit column, and the data signal line 70 is configured to provide a data signal to the connected pixel driving circuit. A plurality of first connection lines 81 are arranged in the second direction Y at a set interval, and a plurality of second connection lines 82 are arranged in the first direction X at a set interval. A first end of at least one first connection line 81 is connected to a data signal line 70, a second end is connected to a first end of a second connection line 82, and a second end of the second connection line 82 is connected to a data lead-out line 80 after extending to the binding area, so that the data signal line 70 in the display area is connected to the data lead-out line 80 in the binding area 200 through the first connection line 81 and the second connection line 82, forming an FIP structure (also referred to as an FIAA structure). In the example embodiment, the first connection line 81 and the second connection line 82 are collectively referred to as a data connection line.

[0106] In the example embodiment, the binding area 200 can include at least a lead-out line area connected to the display area 100, and the lead-out line area can be provided with a plurality of data lead-out lines 80 extending in a direction away from the display area. A first end of a portion of the data lead-out lines 80 is connected to the second connection line 82 in the display area 100, and a first end of another portion of the data lead-out lines 80 is connected to the data signal line 70 in the display area 100. The second ends of all the data lead-out lines 80 extend along the second direction Y and are connected to an integrated circuit, so that the data signal output by the integrated circuit is transmitted to the data signal line through the data lead-out line and the data connection line. Since the first connection line 81 and the second connection line 82 are arranged in the display area, the length of the binding area in the second direction Y can be effectively reduced, the lower frame width is greatly reduced, the screen-to-body ratio is improved, and the full-screen display is facilitated.

[0107] In the example embodiment, the number of data connection lines in the display area can be the same as the number of data signal lines, and each data signal line is connected to a data lead-out line through a data connection line. Alternatively, the number of data connection lines in the display area can be less than the number of data signal lines, and a portion of the data signal lines in the display area are connected to the data lead-out line through the data connection line, and another portion of the data signal lines are directly connected to the data lead-out line, which is not limited in the present disclosure.

[0108] In the example embodiment, the data lead-out line 80 can be directly connected to the data signal line 70 and the second connection line 82, or can be connected through a via, which is not limited in the present disclosure.

[0109] In an exemplary embodiment, the display area can have a center line O, the plurality of data signal lines 70, the plurality of first connection lines 81, and the plurality of second connection lines 82 on the display substrate can be symmetrically arranged relative to the center line O, and the center line O can be a straight line that bisects the plurality of unit columns of the display area and extends along the second direction Y.

[0110] In an exemplary embodiment, the drive structure layer of the display area 100 can further include a plurality of first power supply lines and a plurality of second power supply lines, which together can be referred to as power supply lines.

[0111] FIG. 7 is a schematic diagram of a structure of a data connection line and a power supply line according to an exemplary embodiment of the present disclosure. As shown in FIG. 7, the drive structure layer of the display area can include a plurality of data signal lines 70, a plurality of first connection lines 81, a plurality of second connection lines 82, a plurality of first power supply lines 91, and a plurality of second power supply lines 92. The first connection lines 81 and the first power supply lines 91 can have a shape of a straight line or a broken line extending along the first direction X, and the data signal lines 70, the second connection lines 82, and the second power supply lines 92 can have a shape of a straight line or a broken line extending along the second direction Y.

[0112] In an exemplary embodiment, the plurality of data signal lines 70 can be respectively arranged in each unit column and sequentially arranged along the first direction X, and the data signal lines 70 are connected to the pixel driving circuit of all circuit units in the unit column. The plurality of first connection lines 81 can be respectively arranged in the corresponding unit rows, and the plurality of second connection lines 82 can be respectively arranged between the corresponding unit columns, and the second connection lines 82 are connected to the data signal lines 70 through the first connection lines 81.

[0113] In an exemplary embodiment, the plurality of first power supply lines 91 can be respectively arranged in the corresponding unit rows and sequentially arranged along the second direction Y, and the plurality of second power supply lines 92 can be respectively arranged between the corresponding unit columns and sequentially arranged along the first direction X.

[0114] In an example embodiment, in a direction perpendicular to the display substrate, the driving structure layer of the display substrate can include a plurality of conductive layers. The first connection line 81 and the second connection line 82 can be disposed in different conductive layers, the first connection line 81 and the data signal line 70 can be disposed in different conductive layers, the first end of the first connection line 81 can be connected with the data signal line 70 through a via, the second end of the first connection line 81 is extended along the first direction X or the opposite direction of the first direction X and then connected with the first end of the second connection line 82 through a via, and the second end of the second connection line 82 is extended along the second direction Y towards the direction of the bonding area and then connected with the data lead-out line. The first power supply line 91 and the second power supply line 92 can be disposed in different conductive layers, and at least one second power supply line 92 can be connected with at least one first power supply line 91 through a via to form a mesh communication structure for transmitting a power supply signal in the display area.

[0115] In an example embodiment, the first connection line 81 and the first power supply line 91 can be disposed in the same layer and formed synchronously through the same patterning process, and the data signal line 70, the second connection line 82 and the second power supply line 92 can be disposed in the same layer and formed synchronously through the same patterning process.

[0116] In an example embodiment, in at least one unit row, at least one first connection line 81 and at least one first power supply line 91 can be disposed, and a first break K1 can be disposed between the first connection line 81 and the first power supply line 91, the first break K1 being configured to realize mutual insulation between the first connection line 81 and the first power supply line 91.

[0117] In an example embodiment, in at least one unit row, only one first power supply line 91 can be disposed, and no first connection line 81 is disposed in the unit row.

[0118] In an example embodiment, between at least one unit column, at least one second connection line 82 and at least one second power supply line 92 can be disposed, and a second break K2 can be disposed between the second connection line 82 and the second power supply line 92, the second break K2 being configured to realize mutual insulation between the second connection line 82 and the second power supply line 92.

[0119] In an example embodiment, between at least one unit column, only one second power supply line 92 can be disposed, and no second connection line 82 is disposed between the unit column.

[0120] In the exemplary embodiments, the first connection lines 81 and the second connection lines 82 can be arranged in the display area close to the binding area. Since the data connection lines are arranged in a part of the display area and the power supply lines are arranged in another part of the display area, the display area can be divided into the first area 110 and the second area 120 according to the positions of the data connection lines. The first area 110 can be an area in which the first connection lines 81 or the second connection lines 82 are arranged, such as the dark area in FIG. 7. The second area 120 can be an area in which the first connection lines 81 and the second connection lines 82 are not arranged, such as the area outside the dark area in FIG. 7. In the present disclosure, the first area 110 can be referred to as an FIP area, and the second area 120 can be referred to as a non-FIP area.

[0121] In the exemplary embodiments, in the first area 110, a first power supply line 91 can be arranged between two adjacent first connection lines 81, which can be referred to as an inserted first power supply line 91, and a second power supply line 92 can be arranged between two adjacent second connection lines 82, which can be referred to as an inserted second power supply line 92. The inserted first power supply line 91 and the inserted second power supply line 92 can be connected to each other to form a meshed communication structure for transmitting power supply signals in the first area 110.

[0122] In the exemplary embodiments, in the first area 110, the first power supply line 91 arranged in the same unit row as the first connection line 81 and disconnected from the first connection line 81 can be connected to the inserted second power supply line 92, and the second power supply line 92 arranged in the same unit column as the second connection line 82 and disconnected from the second connection line 82 can be connected to the inserted first power supply line 91, as a component of the meshed communication structure in the first area 110.

[0123] In the exemplary embodiments, the inserted first power supply line 91 in the first area 110 can extend to the second area 120 and be connected to the second power supply line 92 in the second area 120, and the inserted second power supply line 92 in the first area 110 can extend to the second area 120 and be connected to the first power supply line 91 in the second area 120, to realize the interconnection between the meshed communication structure in the first area and the meshed communication structure in the second area.

[0124] In the exemplary embodiment, in the first region 110, two data signal lines 70 can be arranged between the second connection line 82 and the first power supply line 91 adjacent in the first direction X, or two data signal lines 70 can be arranged between the first power supply line 91 and the second connection line 82 adjacent in the first direction X. One first power supply line 91 and four data signal lines 70 can be arranged between two second connection lines 82 adjacent in the first direction X, or one second connection line 82 and four data signal lines 70 can be arranged between two first power supply lines 91 adjacent in the first direction X.

[0125] In the exemplary embodiment, in the second region 120, at least one first power supply line 91 and at least one second power supply line 92 can be connected to each other, forming a meshed communication structure for transmitting power supply signals in the second region 120.

[0126] In the exemplary embodiment, the first region 110 and the second region 120 can be symmetrically arranged relative to the center line.

[0127] The embodiment of the present disclosure effectively improves the uniformity of the second power supply signal in the FIP region, and effectively improves the uniformity of the second power supply signal in the entire display region, thereby improving the display quality and display performance.

[0128] FIG. 8A is a schematic diagram of a planar structure of a display substrate according to an exemplary embodiment of the present disclosure, which is an enlarged view of the region A in FIG. 7 (located in the first region). As shown in FIG. 8A, the driving structure layer of the display region can include a plurality of circuit units constituting a plurality of unit rows and a plurality of unit columns. At least one circuit unit can include a pixel driving circuit, and the pixel driving circuit can be connected to the first scan signal line 21, the second scan signal line 22, the third scan signal line 23, the fourth scan signal line 24, the light-emitting signal line 25, the first initial signal line 41, the second initial signal line 42, the third initial signal line 43, the data signal line 70, and the first power supply line 71, respectively.

[0129] In the example embodiment, the first scan signal line 21, the second scan signal line 22, the third scan signal line 23, the fourth scan signal line 24, and the light-emitting signal line 25 are configured to provide a first scan signal, a second scan signal, a third scan signal, a fourth scan signal, and a light-emitting control signal to the pixel driving circuit, respectively; the first initial signal line 41, the second initial signal line 42, and the third initial signal line 43 are configured to provide a first initial signal, a second initial signal, and a third initial signal to the pixel driving circuit, respectively; the data signal line 70 is configured to provide a data signal to the pixel driving circuit; and the first power supply line 71 is configured to provide a first power supply signal to the pixel driving circuit. The plurality of signal lines connected to the pixel driving circuit can be located within the corresponding circuit unit.

[0130] In the example embodiment, the first scan signal line 21, the second scan signal line 22, the third scan signal line 23, the fourth scan signal line 24, the light-emitting signal line 25, the first initial signal line 41, the second initial signal line 42, and the third initial signal line 43 can have a shape of a straight line or a broken line with a main part extending along the first direction X; and the data signal line 70 and the first power supply line 71 can have a shape of a straight line or a broken line with a main part extending along the second direction Y.

[0131] In the present disclosure, A extending along B direction means that A can include a main part and a secondary part connected to the main part, the main part is a line, a line segment, or a bar-shaped body, the main part extends along the B direction, and the length of the main part extending along the B direction is greater than the length of the secondary part extending along other directions. In the following description, A extending along B direction means A main part extending along B direction.

[0132] In the example embodiment, the pixel driving circuit can include at least a storage capacitor and a plurality of transistors. The storage capacitor can include a first electrode plate and a second electrode plate stacked, and the plurality of transistors can include a first transistor T1 as a first reset transistor, a second transistor T2 as a compensation transistor, a third transistor T3 as a driving transistor, a fourth transistor T4 as a data writing transistor, a fifth transistor T5 as a first light-emitting control transistor, a sixth transistor T6 as a second light-emitting control transistor, a seventh transistor T7 as a second reset transistor, and an eighth transistor T8 as a third reset transistor. The second transistor T2 can be a metal oxide transistor (N-type transistor), and the first transistor T1, the third transistor T3 to the eighth transistor T8 can be low-temperature polysilicon transistors (P-type transistors).

[0133] In the exemplary embodiment, the gate electrode of the first transistor T1 is connected to the third scan signal line 23, the first electrode of the first transistor T1 is connected to the first initial signal line 41, and the second electrode of the first transistor T1 is connected to the second electrode of the second transistor T2, the second electrode of the third transistor T3, and the first electrode of the sixth transistor T6, respectively. The gate electrode of the second transistor T2 is connected to the fourth scan signal line 24, and the first electrode of the second transistor T2 and the first electrode plate of the storage capacitor (which is also the gate electrode of the third transistor T3) are connected. The first electrode of the third transistor T3 is connected to the second electrode of the fourth transistor T4, the second electrode of the fifth transistor T5, and the second electrode of the eighth transistor T8, respectively. The gate electrode of the fourth transistor T4 is connected to the first scan signal line 21, and the first electrode of the fourth transistor T4 is connected to the data signal line 70. The gate electrode of the fifth transistor T5 is connected to the light emission signal line 25, and the first electrode of the fifth transistor T5 is connected to the first power supply line 71. The gate electrode of the sixth transistor T6 is connected to the light emission signal line 25, and the second electrode of the sixth transistor T6 is connected to the second electrode of the seventh transistor T7. The gate electrode of the seventh transistor T7 is connected to the second scan signal line 22, and the first electrode of the seventh transistor T7 is connected to the second initial signal line 42. The gate electrode of the eighth transistor T8 is connected to the second scan signal line 22, and the first electrode of the eighth transistor T8 is connected to the third initial signal line 43.

[0134] In the exemplary embodiment, in at least one circuit unit, the fourth scan signal line 24 can be disposed on the side opposite to the second direction Y of the storage capacitor (third transistor T3), and the first scan signal line 21 can be disposed on the side away from the storage capacitor of the fourth scan signal line 24. The light emission signal line 25 can be disposed on the side of the second direction Y of the storage capacitor, the second scan signal line 22 can be disposed on the side away from the storage capacitor of the light emission signal line 25, and the third scan signal line 23 can be disposed on the side away from the storage capacitor of the second scan signal line 22.

[0135] In the exemplary embodiment, the orthogonal projection of the first initial signal line 41 on the substrate at least partially overlaps the orthogonal projection of the second scan signal line 22 on the substrate, the orthogonal projection of the second initial signal line 42 on the substrate at least partially overlaps the orthogonal projection of the third scan signal line 23 on the substrate, and the orthogonal projection of the third initial signal line 43 on the substrate at least partially overlaps the orthogonal projection of the light emission signal line 25 on the substrate.

[0136] In an example embodiment, the pixel driving circuits of adjacent unit columns can be mirror symmetrical with respect to a column boundary line, which can be a fold line located in the middle of the adjacent unit columns and extending along the second direction Y. For example, the pixel driving circuits of the Nth unit column and the (N+1)th unit column can be mirror symmetrical with respect to the column boundary line, and the pixel driving circuits of the (N+1)th unit column and the (N+2)th unit column can be mirror symmetrical with respect to the column boundary line. In an example embodiment, the positions and shapes of the pixel driving circuits in the plurality of unit rows can be substantially the same.

[0137] In an example embodiment, the driving structure layer of the display region can further include at least one first connection line 81, at least one second connection line 82, at least one first power supply line 91, and at least one second power supply line 92.

[0138] FIG. 8B is a structural schematic diagram of the data connection lines and the power supply lines in FIG. 8A. As shown in FIG. 8B, the display region can further include at least one first connection line 81, at least one second connection line 82, at least one first power supply line 91, and at least one second power supply line 92. The shapes of the first connection line 81 and the first power supply line 91 can be straight lines or fold lines extending along the first direction X in the main part, and the shapes of the data signal line 70, the second connection line 82, and the second power supply line 92 can be straight lines or fold lines extending along the second direction Y in the main part. In the direction perpendicular to the display substrate, the display substrate can include a plurality of conductive layers, the first connection line 81 and the first power supply line 91 can be disposed in the same conductive layer and formed synchronously by the same patterning process, and the data signal line 70, the second connection line 82, and the second power supply line 92 can be disposed in the same conductive layer and formed synchronously by the same patterning process.

[0139] In an example embodiment, the first region can be provided with the first connection line 81, the second connection line 82, the first power supply line 91, and the second power supply line 92, and only the first power supply line 91 and the second power supply line 92 can be provided in the second region.

[0140] In an example embodiment, at least one first connection line 81 and at least one first power supply line 91 can be provided in at least one unit row of the first region, and a first break K1 can be provided between the first connection line 81 and the first power supply line 91, which is configured to realize mutual insulation between the first connection line 81 and the first power supply line 91.

[0141] In an example embodiment, only one first power supply line 91 can be provided in at least one unit row of the first region, and no first connection line 81 is provided in the unit row.

[0142] In an example embodiment, at least one second connection line 82 and at least one second power supply line 92 can be arranged between at least one unit column of the first region, and a second break K2 can be arranged between the second connection line 82 and the second power supply line 92, and the second break K2 is configured to realize mutual insulation between the second connection line 82 and the second power supply line 92.

[0143] In an example embodiment, only one second power supply line 92 can be arranged between at least one unit column of the first region, and no second connection line 82 is arranged between the unit column.

[0144] In an example embodiment, in the first region, one first power supply line 91 can be arranged between two adjacent first connection lines 81, one second power supply line 92 can be arranged between two adjacent second connection lines 82, and the first power supply line 91 arranged between the two first connection lines 81 and the second power supply line 92 arranged between the two second connection lines 82 can be connected to each other, thereby forming a meshed communication structure for transmitting power supply signals in a meshed manner in the first region.

[0145] In an example embodiment, in the second region, at least one first power supply line 91 and at least one second power supply line 92 can be connected to each other, thereby forming a meshed communication structure for transmitting power supply signals in a meshed manner in the second region.

[0146] In an example embodiment, in the first region, one first connection line 81 can be connected to one data signal line 70 through the eleventh connection electrode 61 and the second data transfer strip 86, and one second connection line 82 can be connected to the first connection line 81 through the data connection block 83 and the first data transfer strip 84. For example, the second connection line 82 arranged between the (N+6)th unit column and the (N+7)th unit column can be connected to the first connection line 81 arranged in the Mth unit row, and the first connection line 81 arranged in the Mth unit row can be connected to the data signal line 70 arranged in the Nth unit column. For another example, the second connection line 82 arranged between the (N+2)th unit column and the (N+3)th unit column can be connected to the first connection line 81 arranged in the (M+2)th unit row, and the first connection line 81 arranged in the (M+2)th unit row can be connected to the data signal line 70 arranged in the (N+1)th unit column.

[0147] In an example embodiment, the shape of the eleventh connection electrode 61 can be block-shaped (e.g., rectangular), the shape of the second data transfer strip 86 can be strip-shaped, the two ends of the second data transfer strip 86 are respectively connected to the first connection line 81 and the eleventh connection electrode 61, and the data signal line 70 is connected to the eleventh connection electrode 61 through a via, thereby realizing the connection between the data signal line 70 and the first connection line 81.

[0148] In an example embodiment, the data connection block 83 can have a block shape (e.g., a rectangular shape), the first data transfer bar 84 can have a bar shape, two ends of the first data transfer bar 84 can be connected to the first connection line 81 and the data connection block 83 respectively, and the second connection line 82 can be connected to the data connection block 83 through a via, thereby realizing the connection between the first connection line 81 and the second connection line 82.

[0149] In an example embodiment, in the first region, at least one second power supply line 92 can be connected to at least one first power supply line 91 through a line connection block 93 and a line transfer bar 94. For example, the second power supply line 92 arranged between the (N+4)th unit column and the (N+5)th unit column can be connected to the first power supply line 91 arranged in the (M+1)th unit row.

[0150] In an example embodiment, the line connection block 93 can have a block shape (e.g., a rectangular shape), the line transfer bar 94 can have a bar shape, two ends of the line transfer bar 94 can be connected to the first power supply line 91 and the line connection block 93 respectively, and the second power supply line 92 can be connected to the line connection block 93 through a via, thereby realizing the connection between the first power supply line 91 and the second power supply line 92.

[0151] In an example embodiment, the first region can further include at least one first dummy electrode 85 and at least one second dummy electrode 95, at least one second connection line 82 can be connected to the first dummy electrode 85 or the second dummy electrode 95 through a via, and at least one second power supply line 92 can be connected to the first dummy electrode 85 or the second dummy electrode 95 through a via, so as to improve the uniformity of the etching process and realize shadow elimination. The position, shape and connection structure of the first dummy electrode 85 can be substantially the same as those of the data connection block 83, except that the first dummy electrode 85 is arranged in isolation. The position, shape and connection structure of the second dummy electrode 95 can be substantially the same as those of the line connection block 93, except that the second dummy electrode 95 is arranged in isolation.

[0152] In an example embodiment, the first connection line 81, the data connection block 83, the first data transfer bar 84, the first dummy electrode 85, the second data transfer bar 86, the first power supply line 91, the line connection block 93, the line transfer bar 94 and the second dummy electrode 95 can be arranged in the same conductive layer and formed synchronously through the same patterning process.

[0153] The preparation process of the display substrate is exemplarily described below. The "patterning process" in the present disclosure includes deposition, coating photoresist, mask exposure, development, etching, stripping photoresist, etc. for metal material, inorganic material or transparent conductive material, and includes coating organic material, mask exposure and development, etc. for organic material. The deposition can use any one or more of sputtering, evaporation, chemical vapor deposition, the coating can use any one or more of spraying, spin coating and inkjet printing, and the etching can use any one or more of dry etching and wet etching, which are not limited in the present disclosure. The "thin film" refers to a thin film of a certain material on a substrate made by deposition, coating or other processes. If the "thin film" does not need a patterning process during the entire manufacturing process, the "thin film" can also be referred to as a "layer". If the "thin film" needs a patterning process during the entire manufacturing process, it is referred to as a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern". The "A and B are arranged in the same layer" in the present disclosure means that A and B are formed at the same time by the same patterning process. The "thickness" of the film layer is the size of the film layer in the direction perpendicular to the display substrate. In the exemplary embodiments of the present disclosure, "the orthographic projection of B is within the orthographic projection of A" or "the orthographic projection of A contains the orthographic projection of B" means that the boundary of the orthographic projection of B falls within the boundary of the orthographic projection of A, or the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.

[0154] In the exemplary embodiments, taking 24 circuit units (3 unit rows and 8 unit columns) as an example, the preparation process of the display substrate can include the following operations.

[0155] (1) Forming a shielding layer pattern. In the exemplary embodiments, forming a shielding layer pattern can include: depositing a shielding thin film on a substrate, patterning the shielding thin film by a patterning process, and forming a shielding layer pattern on the substrate, as shown in FIG. 9. In the exemplary embodiments, the shielding layer can be referred to as a bottom metal (LS) layer.

[0156] In the exemplary embodiments, the shielding layer pattern of each circuit unit in the display area can include at least a shielding electrode 130, a first shielding connection bar 131, a second shielding connection bar 132, a third shielding connection bar 133 and a fourth shielding connection bar 134.

[0157] In the exemplary embodiments, the shielding electrode 130 can be rectangular in shape, and the corners of the rectangular shape can be provided with chamfers or grooves. The shielding electrode 130 can be arranged in the middle region of the first direction X and the second direction Y of the circuit unit. In the exemplary embodiments, the shielding electrode 130 is configured to shield the channel region of the third transistor T3.

[0158] In an exemplary embodiment, the first shielding connection strip 131 can be in a straight line shape or a broken line shape with a main body extending along the first direction X. The first shielding connection strip 131 can be arranged on one side of the shielding electrode 130 along the first direction X or on the side opposite to the first direction X. The first end of the first shielding connection strip 131 is connected to the shielding electrode 130 of the current circuit unit, and the second end of the first shielding connection strip 131 is connected to the shielding electrode 130 of the circuit unit adjacent to the current circuit unit along the first direction X.

[0159] In an exemplary embodiment, the shielding electrode 130 and the first shielding connection strip 131 in at least one circuit unit can be in an integrated structure.

[0160] In an exemplary embodiment, the plurality of shielding electrodes 130 and the plurality of first shielding connection strips 131 in at least one unit row can be in an integrated structure.

[0161] In an exemplary embodiment, the second shielding connection strip 132 and the third shielding connection strip 133 can be in a straight line shape or a broken line shape with a main body extending along the second direction Y. The second shielding connection strip 132 can be arranged on one side of the shielding electrode 130 along the second direction Y, and the third shielding connection strip 133 can be arranged on the side opposite to the second direction Y. The first end of the second shielding connection strip 132 is connected to the shielding electrode 130 of the current circuit unit, and the second end of the second shielding connection strip 132 is connected to the third shielding connection strip 133 of the circuit unit in the next unit row after extending along the second direction Y. The first end of the third shielding connection strip 133 is connected to the shielding electrode 130 of the current circuit unit, and the second end of the third shielding connection strip 133 is connected to the second shielding electrode 92 of the circuit unit in the previous unit row after extending along the direction opposite to the second direction Y.

[0162] In an exemplary embodiment, the shielding electrode 130, the second shielding connection strip 132, and the third shielding connection strip 133 in at least one circuit unit can be in an integrated structure.

[0163] In an exemplary embodiment, the plurality of shielding electrodes 130, the plurality of second shielding connection strips 132, and the plurality of third shielding connection strips 133 in at least one unit column can be in an integrated structure.

[0164] In an exemplary embodiment, the shielding layer can extend to the frame area or the binding area and be connected to the first power supply lead wire for transmitting the first power supply signal. The shielding layers in the plurality of unit rows and the plurality of unit columns are in an integrated structure, which can ensure that the shielding layers in the display substrate have the same potential, thereby improving the uniformity of the panel, avoiding display defects of the display substrate, and ensuring the display effect of the display substrate.

[0165] In an exemplary embodiment, the barrier layer of adjacent cell columns can be mirror symmetrical with respect to the column boundary line. For example, the barrier layer of the Nth cell column and the barrier layer of the N+lth cell column can be mirror symmetrical with respect to the column boundary line, and the barrier layer of the N+lth cell column and the barrier layer of the N+2th cell column can be mirror symmetrical with respect to the column boundary line. In an exemplary embodiment, the position and shape of the barrier layer in the plurality of cell rows can be substantially the same.

[0166] (2) Forming a first semiconductor layer pattern. In an exemplary embodiment, forming the first semiconductor layer pattern can include: sequentially depositing a first insulating thin film and a first semiconductor thin film on a substrate on which the aforementioned pattern is formed, patterning the first semiconductor thin film by a patterning process, forming a first insulating layer covering the barrier layer, and a first semiconductor layer pattern disposed on the first insulating layer, as shown in FIGS. 10A and 10B, which is a plan view of the first semiconductor layer in FIG. 10A.

[0167] In an exemplary embodiment, the first semiconductor layer pattern of each circuit unit in the display area can include at least the first active layer 11 of the first transistor T1, the third active layer 13 of the third transistor T3 to the eighth active layer 18 of the eighth transistor T8, and the third active layer 13 to the seventh active layer 17 are an integrated structure connected to each other, and the first active layer 11 and the eighth active layer 18 are separately provided.

[0168] In an exemplary embodiment, in the first direction X, the first active layer 11 and the sixth active layer 16 can be located on one side of the third active layer 13 in the present circuit unit, and the fourth active layer 14 and the fifth active layer 15 can be located on the other side of the third active layer 13 in the present circuit unit. In the second direction Y, the fourth active layer 14 can be located on one side of the third active layer 13 in the present circuit unit in the opposite direction of the second direction Y, and the first active layer 11, the fifth active layer 15, the sixth active layer 16, the seventh active layer 17, and the eighth active layer 18 can be located on one side of the third active layer 13 in the present circuit unit in the second direction Y.

[0169] In an exemplary embodiment, the third active layer 13 can have an inverted "Ω" shape, the first active layer 11, the fourth active layer 14, the fifth active layer 15, and the sixth active layer 16 can have an "I" shape, the seventh active layer 17 can have an inverted "L" shape, and the eighth active layer 18 can have an "L" shape.

[0170] In the example embodiment, the first active layer 11, the third active layer 13 to the eighth active layer 18 can each include a first region, a second region, and a channel region between the first region and the second region. In the example embodiment, the first region 13-1 of the third active layer, the second region 14-2 of the fourth active layer, and the second region 15-2 of the fifth active layer can be connected to each other, and the first region 13-1 of the third active layer can serve as the second region 14-2 of the fourth active layer and the second region 15-2 of the fifth active layer at the same time. The second region 13-2 of the third active layer and the first region 16-1 of the sixth active layer can be connected to each other, and the second region 13-2 of the third active layer can serve as the first region 16-1 of the sixth active layer. The second region 16-2 of the sixth active layer and the second region 17-2 of the seventh active layer can be connected to each other, and the second region 16-2 of the sixth active layer can serve as the second region 17-2 of the seventh active layer. The first region 11-1 of the first active layer, the second region 11-2 of the first active layer, the first region 14-1 of the fourth active layer, the first region 15-1 of the fifth active layer, the first region 17-1 of the seventh active layer, the first region 18-1 of the eighth active layer, and the second region 18-2 of the eighth active layer can be separately provided.

[0171] In the example embodiment, in at least one unit row, the first region 15-1 of the fifth active layer in part of two adjacent circuit units can be connected to each other, and the fifth active layer in the two circuit units can be an integrated structure connected to each other. For example, the fifth active layer in the Nth unit column and the fifth active layer in the N+1th unit column can be an integrated structure connected to each other, the fifth active layer in the N+2th unit column and the fifth active layer in the N+3th unit column can be an integrated structure connected to each other, the fifth active layer in the N+4th unit column and the fifth active layer in the N+5th unit column can be an integrated structure connected to each other, and the fifth active layer in the N+6th unit column and the fifth active layer in the N+7th unit column can be an integrated structure connected to each other. Since the first region of the fifth active layer is configured to be connected to the first power line formed subsequently, by forming the fifth active layer in adjacent circuit units into an integrated structure connected to each other, it can be ensured that the first electrode of the fifth transistor T5 in the adjacent circuit units has the same potential, which is conducive to improving the uniformity of the panel, avoiding display defects of the display substrate, and ensuring the display effect of the display substrate.

[0172] In the example embodiment, in at least one unit row, the first region 18-1 of the eighth active layer in the two adjacent circuit units can be connected to each other, and the eighth active layer in the two circuit units can be an integrated structure connected to each other. For example, the eighth active layer of the Nth unit column and the eighth active layer of the N+1th unit column can be an integrated structure connected to each other, the eighth active layer of the N+2th unit column and the eighth active layer of the N+3th unit column can be an integrated structure connected to each other, the eighth active layer of the N+4th unit column and the eighth active layer of the N+5th unit column can be an integrated structure connected to each other, and the eighth active layer of the N+6th unit column and the eighth active layer of the N+7th unit column can be an integrated structure connected to each other. Since the first region 18-1 of the eighth active layer is configured to be connected to the third initial signal line formed subsequently, by forming the first region 18-1 of the eighth active layer of the adjacent circuit units into an integrated structure connected to each other, the first electrode of the eighth transistor of the adjacent circuit units can have the same potential, which is conducive to improving the uniformity of the panel, avoiding display defects of the display substrate, and ensuring the display effect of the display substrate.

[0173] In the example embodiment, the first semiconductor layer of the adjacent unit columns can be mirror symmetrical with respect to the column boundary line. For example, the first semiconductor layer of the Nth unit column and the first semiconductor layer of the N+1th unit column can be mirror symmetrical with respect to the column boundary line, and the first semiconductor layer of the N+1th unit column and the first semiconductor layer of the N+2th unit column can be mirror symmetrical with respect to the column boundary line. In the example embodiment, the position and shape of the first semiconductor layer in the plurality of unit rows can be substantially the same.

[0174] In the example embodiment, the first semiconductor layer can be polycrystalline silicon (p-Si), i.e., the first transistor T1, the third transistor T3 to the eighth transistor T8 are LTPS transistors. In the example embodiment, the patterning process for patterning the first semiconductor thin film can include: first forming an amorphous silicon (a-si) thin film on the first insulating thin film, performing dehydrogenation treatment on the amorphous silicon thin film, and performing crystallization treatment on the dehydrogenation-treated amorphous silicon thin film to form a polycrystalline silicon thin film. Subsequently, the polycrystalline silicon thin film is patterned to form a first semiconductor layer pattern.

[0175] (3) Forming a first conductive layer pattern. In the example embodiment, forming the first conductive layer pattern can include: sequentially depositing a second insulating thin film and a first conductive thin film on the substrate on which the aforementioned patterns are formed, patterning the first conductive thin film by a patterning process to form a second insulating layer covering the first semiconductor layer pattern, and a first conductive layer pattern disposed on the second insulating layer, as shown in FIGS. 11A and 11B, FIG. 11B is a plan view of the first conductive layer in FIG. 11A. In the example embodiment, the first conductive layer can be referred to as a first gate metal (GATE1) layer.

[0176] In an example embodiment, the first conductive layer pattern of each circuit unit in the display area includes at least: a first scan signal line 21, a second scan signal line 22, a third scan signal line 23, a light emitting signal line 25, and a first plate 31 of a storage capacitor.

[0177] In an example embodiment, the first plate 31 can be rectangular in shape, and the corners of the rectangular shape can be chamfered. The orthographic projection of the first plate 31 on the substrate at least partially overlaps the orthographic projection of the third active layer of the third transistor T3 on the substrate. In an example embodiment, the first plate 31 can simultaneously serve as the lower plate of the storage capacitor and the gate electrode of the third transistor T3.

[0178] In an example embodiment, the first scan signal line 21 can be linear or zigzag in shape with a main body portion extending along the first direction X, and the first scan signal line 21 can be located on the side opposite to the second direction Y of the first plate 31. The region where the first scan signal line 21 overlaps the fourth active layer can serve as the gate electrode of the fourth transistor T4.

[0179] In an example embodiment, the second scan signal line 22 can be linear or zigzag in shape with a main body portion extending along the first direction X, and the second scan signal line 22 can be located on the side of the second direction Y of the first plate 31. The region where the second scan signal line 22 overlaps the seventh active layer can serve as the gate electrode of the seventh transistor T7, and the region where the second scan signal line 22 overlaps the eighth active layer can serve as the gate electrode of the eighth transistor T8.

[0180] In an example embodiment, the third scan signal line 23 can be linear or zigzag in shape with a main body portion extending along the first direction X, and the third scan signal line 23 can be located on the side of the second scan signal line 22 away from the first plate 31. The region where the third scan signal line 23 overlaps the first active layer can serve as the gate electrode of the first transistor T1.

[0181] In an example embodiment, the light emitting signal line 25 can be linear or zigzag in shape with a main body portion extending along the first direction X, and the light emitting signal line 25 can be located between the second scan signal line 22 and the first plate 31. The region where the light emitting signal line 25 overlaps the fifth active layer can serve as the gate electrode of the fifth transistor T5, and the region where the light emitting signal line 25 overlaps the sixth active layer can serve as the gate electrode of the sixth transistor T6.

[0182] In the exemplary embodiments, the first scan signal line 21, the second scan signal line 22, the third scan signal line 23 and the light emitting signal line 25 can be designed in a zigzag shape, which not only facilitates the layout of the pixel structure, but also reduces the parasitic capacitance between the signal lines.

[0183] In the exemplary embodiments, the first scan signal line 21, the second scan signal line 22, the third scan signal line 23 and the light emitting signal line 25 can be designed in a non-equal width, the width being the size of the second direction Y, and the signal lines can include a region overlapping the first semiconductor layer and a region not overlapping the first semiconductor layer, and the width of the signal line in the region overlapping the first semiconductor layer can be greater than the width of the signal line in the region not overlapping the first semiconductor layer.

[0184] In the exemplary embodiments, the first conductive layer of adjacent unit columns can be mirror-symmetrical with respect to the column boundary line. For example, the first conductive layer of the Nth unit column and the first conductive layer of the N+1th unit column can be mirror-symmetrical with respect to the column boundary line, and the first conductive layer of the N+1th unit column and the first conductive layer of the N+2th unit column can be mirror-symmetrical with respect to the column boundary line. In the exemplary embodiments, the position and shape of the first conductive layer in the plurality of unit rows can be substantially the same.

[0185] In the exemplary embodiments, after forming the first conductive layer pattern, the first semiconductor layer can be conductorized using the first conductive layer as a shield, the first semiconductor layer in the region shielded by the first conductive layer forms the channel region of the first transistor T1, the third transistor T3 to the eighth transistor T8, and the first semiconductor layer in the region not shielded by the first conductive layer is conductorized, i.e., the first region and the second region of the first transistor T1, the third transistor T3 to the eighth transistor T8 are conductorized.

[0186] (4) Forming a second conductive layer pattern. In the exemplary embodiments, forming the second conductive layer pattern can include: sequentially depositing a third insulating film and a second conductive film on the substrate on which the aforementioned pattern is formed, patterning the second conductive film using a patterning process, forming a third insulating layer covering the first conductive layer, and a second conductive layer pattern disposed on the third insulating layer, as shown in FIGS. 12A and 12B, FIG. 12B is a plan view of the second conductive layer in FIG. 12A. In the exemplary embodiments, the second conductive layer can be referred to as a second gate metal (GATE2) layer.

[0187] In the exemplary embodiments, the second conductive layer pattern of each circuit unit in the display area at least includes: a second plate 32 of a storage capacitor and a shield line 35.

[0188] In an example embodiment, the second plate 32 can have a rectangular shape, and the corners of the rectangular shape can be chamfered. The second plate 32 can be used as an upper plate of a storage capacitor, and the first plate 31 and the second plate 32 can form a storage capacitor of a pixel driving circuit.

[0189] In an example embodiment, the second plate 32 can be provided with an opening 33, and the opening 33 can have a rectangular shape and be located in the middle of the second plate 32 to form a ring-shaped structure of the second plate 32. The opening 33 exposes the third insulating layer covering the first plate 31, and the first plate 31 can have a projection on the substrate that contains a projection of the opening 33 on the substrate. In an example embodiment, the opening 33 is configured to accommodate a thirteenth via to be formed later, and the thirteenth via is located in the opening 33 and exposes the first plate 31, so that a first connecting electrode to be formed later is connected to the first plate 31.

[0190] In an example embodiment, in one unit row, the second plates 32 in some adjacent circuit units can be connected to each other by plate connection strips 34 to form an integrated structure. For example, the second plates 32 in the Nth unit column and the (N+1)th unit column can be connected to each other by the plate connection strips 34. For another example, the second plates 32 in the (N+2)th unit column and the (N+3)th unit column can be connected to each other by the plate connection strips 34. For another example, the second plates 32 in the (N+4)th unit column and the (N+5)th unit column can be connected to each other by the plate connection strips 34. For another example, the second plates 32 in the (N+6)th unit column and the (N+7)th unit column can be connected to each other by the plate connection strips 34. Since the second plate 32 is connected to a first power supply line to be formed later, by forming the second plates 32 in some adjacent circuit units into an integrated structure, the second plates in the integrated structure can be reused as a power supply signal line, and the second plates in adjacent circuit units can have the same potential, which is beneficial to improve the uniformity of the panel, avoid display defects of the display substrate, and ensure the display effect of the display substrate.

[0191] In an example embodiment, the shielding line 35 can have a shape of a straight line or a broken line extending along the first direction X, and can be located between the first scan signal line 21 and the second plate 32. The shielding line 35 is configured as a shielding layer of the second transistor T2, shields the channel region of the second transistor T2, ensures the electrical performance of the oxide second transistor T2, and is also configured as a bottom gate electrode of the second transistor T2.

[0192] In an exemplary embodiment, the shield lines 35 can be designed with non-equal width, which can not only facilitate the layout of the pixel structure, but also reduce the parasitic capacitance between the signal lines.

[0193] In an exemplary embodiment, the second conductive layers of adjacent unit columns can be mirror-symmetrical with respect to the column boundary line. For example, the second conductive layer of the Nth unit column and the second conductive layer of the (N+1)th unit column can be mirror-symmetrical with respect to the column boundary line, and the second conductive layer of the (N+1)th unit column and the second conductive layer of the (N+2)th unit column can be mirror-symmetrical with respect to the column boundary line. In an exemplary embodiment, the position and shape of the second conductive layer in the plurality of unit rows can be substantially the same.

[0194] (5) Forming a second semiconductor layer pattern. In an exemplary embodiment, forming the second semiconductor layer pattern can include: sequentially depositing a fourth insulating thin film and a second semiconductor thin film on the substrate on which the aforementioned pattern is formed, patterning the second semiconductor thin film by a patterning process, forming a fourth insulating layer covering the substrate, and a second semiconductor layer pattern disposed on the fourth insulating layer, as shown in FIGS. 13A and 13B, FIG. 13B being a plan view of the second semiconductor layer in FIG. 13A.

[0195] In an exemplary embodiment, the second semiconductor layer pattern of each circuit unit in the display area at least includes: a second active layer 12 of a second transistor T2.

[0196] In an exemplary embodiment, the shape of the second active layer 12 can be in the shape of an inverted "L", and the orthographic projection of the second active layer 12 on the substrate at least partially overlaps with the orthographic projection of the shield line 35 on the substrate.

[0197] In an exemplary embodiment, the first region 12-1 of the second active layer can be located on the side of the shield line 35 away from the second plate 32, and the second region 12-2 of the second active layer can be located on the side of the shield line 35 close to the second plate 32.

[0198] In an exemplary embodiment, the second semiconductor layers of adjacent unit columns can be mirror-symmetrical with respect to the column boundary line. For example, the second semiconductor layer of the Nth unit column and the second semiconductor layer of the (N+1)th unit column can be mirror-symmetrical with respect to the column boundary line, and the second semiconductor layer of the (N+1)th unit column and the second semiconductor layer of the (N+2)th unit column can be mirror-symmetrical with respect to the column boundary line. In an exemplary embodiment, the position and shape of the second semiconductor layer in the plurality of unit rows can be substantially the same.

[0199] In an exemplary embodiment, the second semiconductor layer can employ an oxide, i.e., the second transistor T2 is an oxide transistor. In an exemplary embodiment, the second semiconductor thin film can employ indium gallium zinc oxide (IGZO), which has a higher electron mobility than amorphous silicon.

[0200] (6) Forming a third conductive layer pattern. In an exemplary embodiment, forming the third conductive layer pattern can include: on the substrate on which the aforementioned patterns are formed, sequentially depositing a fifth insulating thin film and a third conductive thin film, patterning the third conductive thin film by a patterning process, forming a fifth insulating layer covering the second semiconductor layer, and a third conductive layer pattern disposed on the fifth insulating layer, as shown in FIGS. 14A and 14B, which is a plan view of the third conductive layer in FIG. 14A. In an exemplary embodiment, the third conductive layer can be referred to as a third gate metal (GATE3) layer.

[0201] In an exemplary embodiment, the third conductive layer pattern of each circuit unit in the display area at least includes: a fourth scan signal line 24, a first initial signal line 41, a second initial signal line 42, and a third initial signal line 43.

[0202] In an exemplary embodiment, the fourth scan signal line 24 can have a shape of a straight line or a broken line with a main body portion extending along the first direction X, the fourth scan signal line 24 can be located between the first scan signal line 21 and the second plate 32, and an area where the fourth scan signal line 24 overlaps with the second active layer can serve as a gate electrode of the second transistor T2.

[0203] In an exemplary embodiment, the fourth scan signal line 24 and the shielding line 35 can be connected to the same signal source, such that the shielding line 35 can serve as a bottom gate electrode of the second transistor T2, and the fourth scan signal line 24 can serve as a top gate electrode of the second transistor T2, forming a top gate bottom gate structure of the second transistor T2.

[0204] In an exemplary embodiment, the first initial signal line 41 can have a shape of a straight line or a broken line with a main body portion extending along the first direction X, and the first initial signal line 41 can be located between the third scan signal line 23 and the light-emitting signal line 25. The first initial signal line 41 of each circuit unit can be provided with a first initial connection block 41-1, which can have a shape of a block (e.g., a rectangle) and be connected to the first initial signal line 41, and the first initial connection block 41-1 is configured to be connected to the first region of the first active layer through a seventh connection electrode formed later.

[0205] In the example embodiment, the orthogonal projection of the first initial signal line 41 on the substrate at least partially overlaps the orthogonal projection of the second scan signal line 22 on the substrate, and the first initial signal line 41 transmitting a constant voltage can shield the second scan signal line 22 from affecting the pixel driving circuit, thereby improving the driving quality of the pixel driving circuit.

[0206] In the example embodiment, the first initial signal line 41 in at least one circuit unit can further be provided with a fourth initial connection block 44. The fourth initial connection block 44 can be in the shape of a block (e.g., a rectangle) and connected to the first initial signal line 41, and the fourth initial connection block 44 is configured to be connected to a first initial connection line formed later.

[0207] In the example embodiment, the fourth initial connection block 44 can be arranged between the N+3th unit column and the N+4th unit column.

[0208] In the example embodiment, the second initial signal line 42 can be in the shape of a straight line or a broken line with a main part extending along the first direction X, and the second initial signal line 42 can be located on the side of the first initial signal line 41 away from the second plate 32. The second initial signal line 42 in each circuit unit can be provided with a second initial connection block 42-1, which can be in the shape of a block (e.g., a rectangle) and connected to the second initial signal line 42, and the second initial connection block 42-1 is configured to be connected to the first region of the seventh active layer through an eighth connection electrode formed later.

[0209] In the example embodiment, the orthogonal projection of the second initial signal line 42 on the substrate at least partially overlaps the orthogonal projection of the third scan signal line 23 on the substrate, and the second initial signal line 42 transmitting a constant voltage can shield the third scan signal line 23 from affecting the pixel driving circuit, thereby improving the driving quality of the pixel driving circuit.

[0210] In the example embodiment, the second initial signal line 42 in at least one circuit unit can further be provided with a fifth initial connection block 45. The fifth initial connection block 45 can be in the shape of a block (e.g., a rectangle) and connected to the second initial signal line 42, and the fifth initial connection block 45 is configured to be connected to a second initial connection line formed later.

[0211] In the example embodiment, the fifth initial connection block 45 can be arranged between the N+5th unit column and the N+6th unit column.

[0212] In the example embodiment, the third initial signal line 43 can be in a straight line shape or a zigzag shape with the main body extending along the first direction X, and the third initial signal line 43 can be located between the second electrode plate 32 and the first initial signal line 41. The third initial signal line 43 of each circuit unit can be provided with a third initial connecting block 43-1 in a block shape (e.g., a rectangular shape) connected to the third initial signal line 43, and the third initial connecting block 43-1 is configured to be connected to the first region of the eighth active layer through the ninth connecting electrode formed later.

[0213] In the example embodiment, the orthographic projection of the third initial signal line 43 on the substrate at least partially overlaps with the orthographic projection of the light-emitting signal line 25 on the substrate, and the third initial signal line 43 transmitting a constant voltage can shield the influence of the light-emitting signal line 25 on the pixel driving circuit, thereby improving the driving quality of the pixel driving circuit.

[0214] In the example embodiment, the third initial signal line 43 of at least one circuit unit can be further provided with a sixth initial connecting block 46. The sixth initial connecting block 46 can be in a block shape (e.g., a rectangular shape) connected to the third initial signal line 43, and the sixth initial connecting block 46 is configured to be connected to the third initial connecting line formed later.

[0215] In the example embodiment, the sixth initial connecting block 46 can be arranged between the N+1 unit column and the N+2 unit column.

[0216] In the example embodiment, the third conductive layer of adjacent unit columns can be mirror-symmetrical relative to the column boundary line. For example, the third conductive layer of the N unit column and the third conductive layer of the N+1 unit column can be mirror-symmetrical relative to the column boundary line, and the third conductive layer of the N+1 unit column and the third conductive layer of the N+2 unit column can be mirror-symmetrical relative to the column boundary line. In the example embodiment, the position and shape of the third conductive layer in the plurality of unit rows can be substantially the same.

[0217] (7) Forming a sixth insulating layer pattern. In the example embodiment, forming the sixth insulating layer pattern can include: depositing a sixth insulating thin film on the substrate on which the aforementioned patterns are formed, and patterning the fifth insulating thin film by using a patterning process to form a sixth insulating layer covering the third conductive layer, and the sixth insulating layer is provided with a plurality of vias, as shown in FIG. 15.

[0218] In an example embodiment, the plurality of vias of each circuit unit in the display area at least includes: a first via V1, a second via V2, a third via V3, a fourth via V4, a fifth via V5, a sixth via V6, a seventh via V7, an eighth via V8, a ninth via V9, a tenth via V10, an eleventh via V11, a twelfth via V12, a thirteenth via V13, a fourteenth via V14, a fifteenth via V15, a sixteenth via V16, and a seventeenth via V17.

[0219] In an example embodiment, a normal projection of the first via V1 on the substrate is within a range of a normal projection of the first region of the first active layer on the substrate, the sixth insulating layer, the fifth insulating layer, the fourth insulating layer, the third insulating layer, and the second insulating layer within the first via V1 are etched away to expose a surface of the first region of the first active layer, and the first via V1 is configured to allow the seventh connection electrode formed subsequently to connect with the first region of the first active layer through the via.

[0220] In an example embodiment, a normal projection of the second via V2 on the substrate is within a range of a normal projection of the second region of the first active layer on the substrate, the sixth insulating layer, the fifth insulating layer, the fourth insulating layer, the third insulating layer, and the second insulating layer within the second via V2 are etched away to expose a surface of the second region of the first active layer, and the second via V2 is configured to allow the second connection electrode formed subsequently to connect with the second region of the first active layer through the via.

[0221] In an example embodiment, a normal projection of the third via V3 on the substrate is within a range of a normal projection of the first region of the second active layer on the substrate, the sixth insulating layer and the fifth insulating layer within the third via V3 are etched away to expose a surface of the first region of the second active layer, and the third via V3 is configured to allow the first connection electrode formed subsequently to connect with the first region of the second active layer through the via.

[0222] In an example embodiment, a normal projection of the fourth via V4 on the substrate is within a range of a normal projection of the second region of the second active layer on the substrate, the sixth insulating layer and the fifth insulating layer within the fourth via V4 are etched away to expose a surface of the second region of the second active layer, and the fourth via V4 is configured to allow the second connection electrode formed subsequently to connect with the second region of the second active layer through the via.

[0223] In an example embodiment, the fifth via V5 is configured such that a fifth connection electrode formed subsequently is connected to the first region of the third active layer (also the second region of the fourth active layer and the second region of the fifth active layer) through the via. The fifth via V5 is located within the range of the orthogonal projection of the first region of the third active layer (also the second region of the fourth active layer and the second region of the fifth active layer) on the substrate. The sixth insulating layer, the fifth insulating layer, the fourth insulating layer, the third insulating layer and the second insulating layer within the fifth via V5 are etched away, exposing the surface of the first region of the third active layer (also the second region of the fourth active layer and the second region of the fifth active layer).

[0224] In an example embodiment, the sixth via V6 is configured such that a second connection electrode formed subsequently is connected to the second region of the third active layer (also the first region of the sixth active layer) through the via. The sixth via V6 is located within the range of the orthogonal projection of the second region of the third active layer (also the first region of the sixth active layer) on the substrate. The sixth insulating layer, the fifth insulating layer, the fourth insulating layer, the third insulating layer and the second insulating layer within the sixth via V6 are etched away, exposing the surface of the second region of the third active layer (also the first region of the sixth active layer).

[0225] In an example embodiment, the seventh via V7 is configured such that a third connection electrode formed subsequently is connected to the first region of the fourth active layer through the via. The seventh via V7 is located within the range of the orthogonal projection of the first region of the fourth active layer on the substrate. The sixth insulating layer, the fifth insulating layer, the fourth insulating layer, the third insulating layer and the second insulating layer within the seventh via V7 are etched away, exposing the surface of the first region of the fourth active layer.

[0226] In an example embodiment, the eighth via V8 is configured such that a fourth connection electrode formed subsequently is connected to the first region of the fifth active layer through the via. The eighth via V8 is located within the range of the orthogonal projection of the first region of the fifth active layer on the substrate. The sixth insulating layer, the fifth insulating layer, the fourth insulating layer, the third insulating layer and the second insulating layer within the eighth via V8 are etched away, exposing the surface of the first region of the fifth active layer. In an example embodiment, since the first regions of the fifth active layers of some adjacent circuit units in a unit row are connected to each other, the some adjacent circuit units can share one eighth via V8.

[0227] In an example embodiment, the ninth via V9 is located within the range of the normal projection of the second region of the sixth active layer (also the second region of the seventh active layer) on the substrate, the sixth insulating layer, the fifth insulating layer, the fourth insulating layer, the third insulating layer and the second insulating layer within the ninth via V9 are etched away to expose the surface of the second region of the sixth active layer (also the second region of the seventh active layer), and the ninth via V9 is configured to allow the sixth connection electrode formed subsequently to connect with the second region of the sixth active layer (also the second region of the seventh active layer) through the via.

[0228] In an example embodiment, the tenth via V10 is located within the range of the normal projection of the first region of the seventh active layer on the substrate, the sixth insulating layer, the fifth insulating layer, the fourth insulating layer, the third insulating layer and the second insulating layer within the tenth via V10 are etched away to expose the surface of the first region of the seventh active layer, and the tenth via V10 is configured to allow the eighth connection electrode formed subsequently to connect with the first region of the seventh active layer through the via.

[0229] In an example embodiment, the eleventh via V11 is located within the range of the normal projection of the first region of the eighth active layer on the substrate, the sixth insulating layer, the fifth insulating layer, the fourth insulating layer, the third insulating layer and the second insulating layer within the eleventh via V11 are etched away to expose the surface of the first region of the eighth active layer, and the eleventh via V11 is configured to allow the ninth connection electrode formed subsequently to connect with the first region of the eighth active layer through the via. In an example embodiment, since the first regions of the eighth active layers of some adjacent circuit units in a unit row are connected with each other, the some adjacent circuit units can share one eleventh via V11.

[0230] In an example embodiment, the twelfth via V12 is located within the range of the normal projection of the second region of the eighth active layer on the substrate, the sixth insulating layer, the fifth insulating layer, the fourth insulating layer, the third insulating layer and the second insulating layer within the twelfth via V12 are etched away to expose the surface of the second region of the eighth active layer, and the twelfth via V12 is configured to allow the fifth connection electrode formed subsequently to connect with the second region of the eighth active layer through the via.

[0231] In an example embodiment, the thirteenth via V13 is located within the range of the normal projection of the opening 33 on the substrate, the sixth insulating layer, the fifth insulating layer, the fourth insulating layer and the third insulating layer within the thirteenth via V13 are etched away to expose the surface of the first plate 31, and the thirteenth via V13 is configured to allow the first connection electrode formed subsequently to connect with the first plate 31 through the via.

[0232] In the example embodiment, the fourth via V4 is configured to expose the surface of the first initial connection block 41-1 in the first initial signal line 41, and the fourth via V4 is configured to connect the fourth connection electrode formed subsequently therewith the first initial connection block 41-1 through the via.

[0233] In the example embodiment, the fifth via V5 is configured to expose the surface of the second initial connection block 42-1 in the second initial signal line 42, and the fifth via V5 is configured to connect the fifth connection electrode formed subsequently therewith the second initial connection block 42-1 through the via.

[0234] In the example embodiment, the sixth via V6 is configured to expose the surface of the third initial connection block 43-1 in the third initial signal line 43, and the sixth via V6 is configured to connect the sixth connection electrode formed subsequently therewith the third initial connection block 43-1 through the via.

[0235] In the example embodiment, the seventh via V7 is configured to expose the surface of the fourth initial connection block 44 in the first initial signal line 41, and the seventh via V7 is configured to connect the seventh connection electrode formed subsequently therewith the fourth initial connection block 44 through the via.

[0236] In the example embodiment, the plurality of vias of the display region can further include an eighteenth via V18, a nineteenth via V19, and a twentieth via V20.

[0237] In the example embodiment, the eighteenth via V18 is configured to expose the surface of the fourth initial connection block 44 in the first initial signal line 41, and the eighteenth via V18 is configured to connect the first initial connection line formed subsequently therewith the fourth initial connection block 44 through the via.

[0238] In the exemplary embodiment, the normal projection of the nineteenth via V19 on the substrate is located within the range of the normal projection of the fifth initial connection block 45 of the second initial signal line 42 on the substrate, the sixth insulating layer in the nineteenth via V19 is etched away to expose the surface of the fifth initial connection block 45, and the nineteenth via V19 is configured to enable the second initial connection line formed subsequently to connect with the fifth initial connection block 45 through the via.

[0239] In the exemplary embodiment, the normal projection of the twentieth via V20 on the substrate is located within the range of the normal projection of the sixth initial connection block 46 of the third initial signal line 43 on the substrate, the sixth insulating layer in the twentieth via V20 is etched away to expose the surface of the sixth initial connection block 46, and the twentieth via V20 is configured to enable the third initial connection line formed subsequently to connect with the sixth initial connection block 46 through the via.

[0240] (8) Forming a fourth conductive layer pattern. In the exemplary embodiment, forming the fourth conductive layer can include: on the substrate on which the aforementioned pattern is formed, depositing a fourth conductive thin film, patterning the fourth conductive thin film by using a patterning process, and forming the fourth conductive layer disposed on the sixth insulating layer, as shown in FIG. 16A and FIG. 16B, which is a plan view of the fourth conductive layer in FIG. 16A. In the exemplary embodiment, the fourth conductive layer can be referred to as a first source-drain metal (SD1) layer.

[0241] In the exemplary embodiment, the fourth conductive layer of each circuit unit in the display area at least includes: a first connection electrode 51, a second connection electrode 52, a third connection electrode 53, a fourth connection electrode 54, a fifth connection electrode 55, a sixth connection electrode 56, a seventh connection electrode 57, an eighth connection electrode 58, and a ninth connection electrode 59.

[0242] In the exemplary embodiment, the shape of the first connection electrode 51 can be a strip shape with the main body part extending along the second direction Y, the first end of the first connection electrode 51 is connected with the first region of the second active layer through the third via V3, and the second end of the first connection electrode 51 is connected with the first plate 31 through the thirteenth via V13 after extending along the second direction Y. In the exemplary embodiment, since the first plate 31 simultaneously serves as the gate electrode of the third transistor T3, the first connection electrode 51 realizes the interconnection between the first electrode of the second transistor T2, the gate electrode of the third transistor T3, and the first plate 31, and forms the first node N1 of the pixel driving circuit.

[0243] In an example embodiment, the second connection electrode 52 can have a strip shape with the main body extending along the second direction Y, the first end of the second connection electrode 52 is connected to the second region of the first active layer of the current circuit unit through the second via V2, the second end of the second connection electrode 52 extends along the second direction Y and is then connected to the second region of the third active layer (also the first region of the sixth active layer) of the next circuit unit through the sixth via V6, and the portion between the first end and the second end of the second connection electrode 52 is connected to the second region of the second active layer of the next circuit unit through the fourth via V4. In an example embodiment, the second connection electrode 52 realizes the interconnection between the second electrode of the first transistor T1, the second electrode of the second transistor T2, the second electrode of the third transistor T3, and the first electrode of the sixth transistor T6, and forms the third node N3 of the pixel driving circuit.

[0244] In an example embodiment, the third connection electrode 53 can have a block shape (e.g., a rectangular shape), the third connection electrode 53 is connected to the first region of the fourth active layer through the seventh via V7, and the third connection electrode 53 is configured to be connected to the eleventh connection electrode formed subsequently.

[0245] In an example embodiment, the fourth connection electrode 54 can have a strip shape extending along the second direction Y, the first end of the fourth connection electrode 54 is connected to the first region of the fifth active layer through the eighth via V8, and the second end of the fourth connection electrode 54 extends along the opposite direction of the second direction Y and is then connected to the plate connection strip 34 through the fourteenth via V14. Since the plate connection strip 34 is connected to the second plate 32, the interconnection between the first electrode of the fifth transistor T5 and the second plate 32 of the storage capacitor in the circuit unit is realized. In an example embodiment, the fourth connection electrode 54 can be used as the first power connection electrode of the present disclosure.

[0246] In an example embodiment, since one eighth via V8 and one fourteenth via V14 are shared by part of two adjacent circuit units in one unit row, part of the adjacent circuit units can share one fourth connection electrode 54.

[0247] In the example embodiment, the shape of the fifth connection electrode 55 can be a strip shape extending along the second direction Y, a first end of the fifth connection electrode 55 is connected with the first region of the third active layer through the fifth via V5, and a second end of the fifth connection electrode 55 is connected with the second region of the eighth active layer through the twelfth via V12. In the example embodiment, since the first region of the third active layer simultaneously serves as the second region of the fourth active layer and the second region of the fifth active layer, the fifth connection electrode 55 realizes that the first electrode of the third transistor T3, the second electrode of the fourth transistor T4, the second electrode of the fifth transistor T5, and the second electrode of the eighth transistor T8 have the same potential, forming the second node N2 of the pixel driving circuit.

[0248] In the example embodiment, the shape of the sixth connection electrode 56 can be a block shape (e.g., a rectangular shape), and the sixth connection electrode 56 is connected with the second region of the sixth active layer (also the second region of the seventh active layer) through the ninth via V9. In the example embodiment, the sixth connection electrode 56 can simultaneously serve as the second electrode of the sixth transistor T6 and the second electrode of the seventh transistor T7, and the sixth connection electrode 56 is configured to be connected with the thirteenth connection electrode formed subsequently.

[0249] In the example embodiment, the shape of the seventh connection electrode 57 can be a strip shape extending along the second direction Y, a first end of the seventh connection electrode 57 is connected with the first region of the first active layer through the first via V1, and a second end of the seventh connection electrode 57 is connected with the first initial connection block 41-1 through the fifteenth via V15. In the example embodiment, since the first initial connection block 41-1 is connected with the first initial signal line 41, the seventh connection electrode 57 realizes that the first initial signal transmitted by the first initial signal line 41 is written into the first electrode of the first transistor T1.

[0250] In the example embodiment, the shape of the eighth connection electrode 58 can be a strip shape extending along the second direction Y, a first end of the eighth connection electrode 58 is connected with the first region of the seventh active layer through the tenth via V10, and a second end of the eighth connection electrode 58 is connected with the second initial connection block 42-1 through the sixteenth via V16. In the example embodiment, since the second initial connection block 42-1 is connected with the second initial signal line 42, the eighth connection electrode 58 realizes that the second initial signal transmitted by the second initial signal line 42 is written into the first electrode of the seventh transistor T7.

[0251] In the example embodiment, the ninth connection electrode 59 can be in the shape of a broken line extending along the second direction Y, a first end of the ninth connection electrode 59 is connected to the first region of the eighth active layer through an eleventh via V11, and a second end of the ninth connection electrode 59 is connected to the third initial connection block 43-1 through a seventeenth via V17. In the example embodiment, since the third initial connection block 43-1 is connected to the third initial signal line 43, the ninth connection electrode 59 realizes writing of the third initial signal transmitted by the third initial signal line 43 to the first electrode of the eighth transistor T8.

[0252] In the example embodiment, since part of the two adjacent circuit units in one unit row share one eleventh via V11, part of the adjacent circuit units can share a first end of one ninth connection electrode 59, that is, the ninth connection electrodes 59 of part of the adjacent circuit units can be an integrated structure connected to each other, which can ensure that the first electrodes of the eighth transistors T8 of part of the adjacent circuit units have the same potential, and is beneficial to improving the uniformity of the panel, avoiding display defects of the display substrate, and ensuring the display effect of the display substrate.

[0253] In the example embodiment, the fourth conductive layer can further include a first initial connection line 47, a second initial connection line 48, and a third initial connection line 49.

[0254] In the example embodiment, the first initial connection line 47 can be in the shape of a straight line or a broken line with a main body extending along the second direction Y, and can be arranged between the N+3th unit column and the N+4th unit column. The first initial connection line 47 can be connected to the fourth initial connection block 44 through an eighteenth via V18. Since the fourth initial connection block 44 is connected to the first initial signal line 41, the first initial signal line 41 extending along the first direction X and the first initial connection line 47 extending along the second direction Y are connected to each other, and the first initial signal line 41 and the first initial connection line 47 form a meshed communication structure for transmitting the first initial signal, which can effectively reduce the resistance of the first initial signal line, reduce the voltage drop of the first initial signal, effectively improve the uniformity of the first initial signal in the display substrate, effectively improve the display uniformity, and improve the display quality and display performance.

[0255] In the example embodiment, the second initial connection line 48 can be in a straight line shape or a broken line shape with a main body extending along the second direction Y, can be arranged between the N+5th unit column and the N+6th unit column, and can be connected to the fifth initial connection block 45 through the nineteenth via V19. Since the fifth initial connection block 45 is connected to the second initial signal line 42, the second initial signal line 42 extending along the first direction X and the second initial connection line 48 extending along the second direction Y are connected to each other, and the second initial signal line 42 and the second initial connection line 48 form a meshed communication structure for transmitting the second initial signal, which can effectively reduce the resistance of the second initial signal line, reduce the voltage drop of the second initial signal, effectively improve the uniformity of the second initial signal in the display substrate, effectively improve the display uniformity, and improve the display quality and display performance.

[0256] In the example embodiment, the third initial connection line 49 can be in a straight line shape or a broken line shape with a main body extending along the second direction Y, can be arranged between the N+1th unit column and the N+2th unit column, and can be connected to the sixth initial connection block 46 through the twentieth via V20. Since the sixth initial connection block 46 is connected to the third initial signal line 43, the third initial signal line 43 extending along the first direction X and the third initial connection line 49 extending along the second direction Y are connected to each other, and the third initial signal line 43 and the third initial connection line 49 form a meshed communication structure for transmitting the third initial signal, which can effectively reduce the resistance of the third initial signal line, reduce the voltage drop of the third initial signal, effectively improve the uniformity of the third initial signal in the display substrate, effectively improve the display uniformity, and improve the display quality and display performance.

[0257] In the example embodiment, the fourth conductive layer can further include a power connection strip 60. The power connection strip 60 can be in a broken line shape extending along the first direction X and can be arranged in part of the circuit unit. A first end of the power connection strip 60 is connected to a second end of the fourth connection electrode 54, and a second end of the power connection strip 60 extends away from the fourth connection electrode 54 and is configured to be connected to a twelfth connection electrode to be formed later.

[0258] In the example embodiment, in at least one circuit unit, the fourth connection electrode 54 and the power connection strip 60 can be an integrated structure connected to each other.

[0259] In the example embodiment, in at least one unit row, all the circuit units can be provided with the power connection strip 60. For example, all the circuit units in the Mth unit row can be provided with the power connection strip 60. For another example, all the circuit units in the M+2th unit row can be provided with the power connection strip 60.

[0260] In the example embodiment, since part of the adjacent circuit units can share the same fourth connection electrode 54, the fourth connection electrode 54 and the two power connection strips 60 in part of the two adjacent circuit units can be an integrated structure connected to each other.

[0261] In the example embodiment, only part of the circuit units in at least one unit row are provided with the power connection strips 60. The power connection strips 60 can be provided in the circuit units in the odd-numbered unit columns, or the power connection strips 60 can be provided in the circuit units in the even-numbered unit columns. For example, in the (M+1)th unit row, the circuit units in the (N+1)th unit column, the (N+3)th unit column, the (N+5)th unit column, and the (N+6)th unit column are provided with the power connection strips 60, while the circuit units in the (N)th unit column, the (N+2)th unit column, the (N+4)th unit column, and the (N+6)th unit column are not provided with the power connection strips 60.

[0262] In the example embodiment, the unit rows in which all the circuit units are provided with the power connection strips and the unit rows in which part of the circuit units are provided with the power connection strips can be alternately arranged along the second direction Y.

[0263] In the example embodiment, since the power connection strips 60 have an overlapping area with the fourth scan signal line 24 on the substrate, there may be a foreign matter problem between the sixth insulating layer and the fourth conductive layer (SD1) in the third conductive layer (GATE3) during the manufacturing process, and thus short-circuit failure caused by foreign matter damage may occur. The present disclosure effectively reduces the number of power connection strips by providing the power connection strips in part of the circuit units, i.e., effectively reduces the overlapping area of the power connection strips and the fourth scan signal line 24, which can effectively avoid short-circuit failure caused by foreign matter damage, and can effectively improve product yield.

[0264] In the example embodiment, the fourth conductive layer (except the power connection strips) of the adjacent unit columns can be mirror-symmetrical relative to the column boundary. For example, the third conductive layer of the (N)th unit column and the fourth conductive layer of the (N+1)th unit column can be mirror-symmetrical relative to the column boundary, and the third conductive layer of the (N+1)th unit column and the fourth conductive layer of the (N+2)th unit column can be mirror-symmetrical relative to the column boundary. In the example embodiment, the positions and shapes of the fourth conductive layer (except the power connection strips) in the plurality of unit rows can be substantially the same.

[0265] (9) Forming a first planar layer pattern. In the example embodiment, forming the first planar layer pattern can include: on the substrate on which the aforementioned pattern is formed, coating a first planar film, and patterning the first planar film by using a patterning process to form a first planar layer covering the fourth conductive layer pattern, the first planar layer being provided with a plurality of vias, as shown in FIG. 17.

[0266] In an example embodiment, the plurality of vias in each circuit unit in the display area includes at least: a twenty-first via V21, a twenty-second via V22, and a twenty-third via V23.

[0267] In an example embodiment, the twenty-first via V21 has a projection on the substrate within the projection of the third connection electrode 53 on the substrate, the first planar layer in the twenty-first via V21 is etched away to expose the surface of the third connection electrode 53, and the twenty-first via V21 is configured to allow a subsequent eleventh connection electrode to connect to the third connection electrode 53 through the via.

[0268] In an example embodiment, the twenty-second via V22 has a projection on the substrate within the projection of the power connection strip 60 on the substrate, the first planar layer in the twenty-second via V22 is etched away to expose the surface of the power connection strip 60, and the twenty-second via V22 is configured to allow a subsequent twelfth connection electrode to connect to the power connection strip 60 through the via.

[0269] In an example embodiment, the twenty-second via V22 can be provided in some circuit units, and only in the circuit units provided with the power connection strip 60.

[0270] In an example embodiment, the twenty-third via V23 has a projection on the substrate within the projection of the sixth connection electrode 56 on the substrate, the first planar layer in the twenty-third via V23 is etched away to expose the surface of the sixth connection electrode 56, and the twenty-third via V23 is configured to allow a subsequent thirteenth connection electrode to connect to the sixth connection electrode 56 through the via.

[0271] (10) Forming a fifth conductive layer pattern. In an example embodiment, forming the fifth conductive layer can include: on the substrate on which the aforementioned pattern is formed, depositing a fifth conductive thin film, and patterning the fifth conductive thin film using a patterning process to form a fifth conductive layer disposed on the first planar layer, as shown in FIGS. 18A and 18B, where FIG. 18B is a plan view of the fifth conductive layer in FIG. 18A. In an example embodiment, the fifth conductive layer can be referred to as a second source-drain metal (SD2) layer.

[0272] In an example embodiment, the fifth conductive layer of each circuit unit in the display area includes at least: an eleventh connection electrode 61, a twelfth connection electrode 62, and a thirteenth connection electrode 63.

[0273] In an example embodiment, the shape of the eleventh connection electrode 61 can be a strip shape with a main body portion extending along the second direction Y, the eleventh connection electrode 61 is connected with the third connection electrode 53 through the twenty-first via V21, and the eleventh connection electrode 61 is configured to be connected with a data signal line formed subsequently.

[0274] In an example embodiment, the shape of the twelfth connection electrode 62 can be a broken line shape with a main body portion extending along the second direction Y, the twelfth connection electrode 62 is connected with the power supply connection bar 60 through the twenty-second via V22, and the twelfth connection electrode 62 is configured to be connected with a first power supply line formed subsequently. In an example embodiment, the twelfth connection electrode 62 can serve as a second power supply connection electrode of the present disclosure.

[0275] In an example embodiment, the orthographic projection of the twelfth connection electrode 62 on the substrate at least partially overlaps with the orthographic projection of the first connection electrode 51 on the substrate. Since the twelfth connection electrode 62 is connected with the first power supply line formed subsequently, the twelfth connection electrode 62 with a constant potential can effectively shield the influence of data voltage jump and other signals on the first node N1 in the pixel driving circuit, avoiding the influence of data voltage jump and other signals on the potential of the first node N1, and improving the driving performance of the pixel driving circuit.

[0276] In an example embodiment, the orthographic projection of the twelfth connection electrode 62 on the substrate at least partially overlaps with the orthographic projection of the second active layer of the second transistor T2 on the substrate. In an example embodiment, the twelfth connection electrode 62 can shield the second active layer, block the light emission of the light emitting device and the reflection of the film layer, and irradiate the light to the oxide of the second transistor T2, which can prevent the oxide transistor from characteristic drift due to light irradiation, and improve the electrical characteristics of the oxide transistor.

[0277] In an example embodiment, in one unit row, the twelfth connection electrodes 62 in part of two adjacent circuit units can be an integrated structure connected with each other, which can improve the shielding effect of the second transistor T2. For example, the twelfth connection electrodes 62 in the N+1th unit column and the N+2th unit column are connected with each other, and the twelfth connection electrodes 62 in the two adjacent circuit units are an integrated structure connected with each other. For another example, the twelfth connection electrodes 62 in the N+3th unit column and the N+4th unit column are connected with each other, and the twelfth connection electrodes 62 in the two adjacent circuit units are an integrated structure connected with each other.

[0278] In the example embodiment, since the second plate 32 in the partially adjacent two circuit units is an integral structure connected to each other, the twelfth connection electrode 62 in the partially adjacent two circuit units is an integral structure connected to each other, the twelfth connection electrode 62 is connected to the second plate 32 through the power supply connecting strip 60, and the integral structures in the two conductive layers are arranged in a staggered manner, thus the second plate 32 in the second conductive layer and the twelfth connection electrode 62 in the fifth conductive layer can form a transverse power supply connecting line extending along the first direction X, and the transverse power supply connecting line and the first power supply line extending along the second direction Y formed subsequently form a meshed communication structure for transmitting the first power supply signal in a meshed manner, which can effectively reduce the resistance of the first power supply signal line, reduce the voltage drop of the first power supply signal, effectively improve the uniformity of the first power supply signal in the display substrate, effectively improve the display uniformity, and improve the display quality and display performance. Although only some of the circuit units in some unit rows are provided with the power supply connecting strip 60, all the circuit units in some other unit rows are provided with the power supply connecting strip 60, thus the effect of the meshed communication structure is not affected.

[0279] In the example embodiment, the thirteenth connection electrode 63 can have a shape of a strip with a main body extending along the second direction Y, the thirteenth connection electrode 63 is connected to the sixth connection electrode 56 through the twenty-third via hole V23, and the thirteenth connection electrode 63 is configured to be connected to the anode connection electrode formed subsequently.

[0280] In the example embodiment, the fifth conductive layer of the display area can further include a first connecting line 81 and a first power supply trace 91, the first connecting line 81 and the first power supply trace 91 can have a shape of a straight line or a broken line with a main body extending along the first direction X, and can be located between the second initial signal line 42 and the third initial signal line 43.

[0281] In the example embodiment, the first connecting line 81 and the first power supply trace 91 can be arranged in at least one unit row of the first area, and a first break K1 can be arranged between the first connecting line 81 and the first power supply trace 91, the first break K1 can cut off the first connecting line 81 and the first power supply trace 91, so that the first connecting line 81 and the first power supply trace 91 on both sides of the first break K1 are insulated from each other. For example, the first connecting line 81 and the first power supply trace 91 can be arranged in the Mth unit row. For another example, the first connecting line 81 and the first power supply trace 91 can be arranged in the M+2th unit row.

[0282] In the example embodiment, only the first power supply trace 91 can be arranged in at least one unit row of the first area. For example, only the first power supply trace 91 can be arranged in the M+1th unit row, and no first connecting line is arranged.

[0283] In an example embodiment, a first power supply line 91 can be arranged between two first connection lines 81 adjacent to each other in the second direction Y in the first region.

[0284] In an example embodiment, the orthogonal projection of the first connection line 81 on the substrate at least partially overlaps with the orthogonal projection of the first initial signal line 41 on the substrate, so that the first initial signal line 41 with a constant potential can effectively shield the influence of voltage jump in the first connection line 81 on the pixel driving circuit.

[0285] In an example embodiment, the fifth conductive layer in the first region can further include a data connection block 83, a first data transfer strip 84, a first dummy electrode 85, a second data transfer strip 86, a wire connection block 93, a wire transfer strip 94, and a second dummy electrode 95.

[0286] In an example embodiment, the data connection block 83 can be in a block shape (e.g., a rectangular shape), and the data connection block 83 is configured to be connected with the subsequently formed second connection line. In the first direction X, the data connection block 83 can be arranged between two circuit units adjacent to each other, and in the second direction Y, the data connection block 83 can be arranged on the side of the first connection line 81 close to the second initial signal line 42. For example, the data connection block 83 can be arranged between the N+6th unit column and the N+7th unit column in the Mth unit row. For another example, the data connection block 83 can be arranged between the N+2th unit column and the N+3th unit column in the M+2th unit row.

[0287] In some possible embodiments, the data connection block 83 can be arranged on the side of the first connection line 81 away from the second initial signal line 42, which is not limited in the present disclosure.

[0288] In an example embodiment, the first data transfer strip 84 can be in a strip shape extending along the second direction Y, and can be arranged between the first connection line 81 and the data connection block 83. The first end of the first data transfer strip 84 is connected with the data connection block 83, and the second end of the first data transfer strip 84 is connected with the first connection line 81. For example, in the Mth unit row, the first data transfer strip 84 can be arranged between the N+6th unit column and the N+7th unit column, so as to realize the connection of the data connection block 83 with the first connection line 81 in the Mth unit row through the first data transfer strip 84. For another example, in the M+2th unit row, the first data transfer strip 84 can be arranged between the N+2th unit column and the N+3th unit column, so as to realize the connection of the data connection block 83 with the first connection line 81 in the M+2th unit row through the first data transfer strip 84. Since the data connection block 83 is configured to be connected with the subsequently formed second connection line, the data connection block 83 and the first data transfer strip 84 can realize the mutual connection between the first connection line and the second connection line.

[0289] In an example embodiment, in at least one circuit unit, the first connection line 81, the data connection block 83, and the first data transfer strip 84 can be an integrated structure connected with each other.

[0290] In an example embodiment, the first dummy electrode 85 can be in a block shape (e.g., a rectangular shape), and the first dummy electrode 85 is configured to be connected with a second connection line or a second power supply line formed subsequently. In the first direction X, the first dummy electrode 85 can be disposed between two adjacent circuit units, and in the second direction Y, the first dummy electrode 85 can be disposed on a side of the first connection line 81 close to the second initial signal line 42.

[0291] In an example embodiment, the second data transfer strip 86 can be in a strip shape extending along the second direction Y, and can be disposed between the first connection line 81 and the eleventh connection electrode 61 in a partial circuit unit. The first end of the second data transfer strip 86 is connected with the eleventh connection electrode 61, and the second end of the second data transfer strip 86 is connected with the first connection line 81. For example, the second data transfer strip 86 can be disposed in a circuit unit in the Mth unit row and the Nth unit column, so as to realize the connection between the eleventh connection electrode 61 and the first connection line 81 in the Mth unit row through the second data transfer strip 86. For another example, the second data transfer strip 86 can be disposed in a circuit unit in the M+2th unit row and the N+1th unit column, so as to realize the connection between the eleventh connection electrode 61 and the first connection line 81 in the M+2th unit row through the second data transfer strip 86. Since the eleventh connection electrode 61 is configured to be connected with a data signal line formed subsequently, the eleventh connection electrode 61 and the second data transfer strip 86 can realize the connection between the first connection line and the data signal line.

[0292] In an example embodiment, in at least one circuit unit, the eleventh connection electrode 61, the first connection line 81, and the second data transfer strip 86 can be an integrated structure connected with each other.

[0293] In an example embodiment, the wiring connection block 93 can be in a block shape (e.g., a rectangular shape), and the wiring connection block 93 is configured to be connected with a second power supply line formed subsequently. In the first direction X, the wiring connection block 93 can be disposed between two adjacent circuit units, and in the second direction Y, the wiring connection block 93 can be disposed on a side of the first power supply line 91 close to the second initial signal line 42. For example, the wiring connection block 93 can be disposed between the N+4th unit column and the N+5th unit column in the M+1th unit row.

[0294] In some possible embodiments, the wiring connection block 93 can be disposed on a side of the first power supply line 91 away from the second initial signal line 42, which is not limited in the present disclosure.

[0295] In an example embodiment, the shape of the wire transition bar 94 can be a bar shape extending along the second direction Y, which can be arranged between the wire connection block 93 and the first power supply wire 91. The first end of the wire transition bar 94 is connected with the wire connection block 93, and the second end of the wire transition bar 94 is connected with the first power supply wire 91. For example, in the M+1th unit row, the wire transition bar 94 can be arranged between the Nth unit column and the N+1th unit column and between the N+4th unit column and the N+5th unit column, so as to realize the connection of the wire connection block 93 with the first power supply wire 91 in the M+1th unit row through the wire transition bar 94. Since the wire connection block 93 is configured to be connected with the subsequently formed second power supply wire, the wire connection block 93 and the wire transition bar 94 can realize the mutual connection between the first power supply wire and the second power supply wire.

[0296] In an example embodiment, in at least one unit row, the first power supply wire 91, the wire connection block 93 and the wire transition bar 94 can be an integrated structure connected with each other.

[0297] In an example embodiment, the shape of the second dummy electrode 95 can be a block shape (such as a rectangular shape), and the second dummy electrode 95 is configured to be connected with the subsequently formed second connection wire or second power supply wire. In the first direction X, the second dummy electrode 95 can be arranged between part of two adjacent circuit units, and in the second direction Y, the second dummy electrode 95 can be arranged on the side of the first power supply wire 91 close to the second initial signal line 42.

[0298] In an example embodiment, the position, shape and connection structure of the data connection block 83 between one circuit unit can be substantially the same as the position, shape and connection structure of the first dummy electrode 85 between another circuit unit, except that the data connection block 83 is connected with the first connection wire 81 through the first data transition bar 84, while the first dummy electrode 85 is arranged in isolation and is not connected with the first connection wire 81, so as to realize substantially the same structure of the transition area.

[0299] In an example embodiment, the position, shape and connection structure of the wire connection block 93 between one circuit unit can be substantially the same as the position, shape and connection structure of the second dummy electrode 95 between another circuit unit, except that the wire connection block 93 is connected with the first power supply wire 91 through the wire transition bar 94, while the second dummy electrode 95 is arranged in isolation and is not connected with the first power supply wire 91, so as to realize substantially the same structure of the transition area.

[0300] In the example embodiment, the position, shape and connection structure of the data connection block 83 between one circuit unit can be substantially the same as the position, shape and connection structure of the wire connection block 93 between another circuit unit, except that the data connection block 83 is connected with the first connection line 81 through the first data transfer strip 84, and the wire connection block 93 is connected with the first power supply wire 91 through the wire transfer strip 94, achieving substantially the same structure of the transfer area.

[0301] In the example embodiment, the position, shape and connection structure of the first dummy electrode 85 between one circuit unit can be substantially the same as the position, shape and connection structure of the second dummy electrode 95 between another circuit unit, achieving substantially the same structure of the transfer area.

[0302] The present disclosure can not only improve the uniformity of subsequent etching process by the same design of the transfer area, but also achieve the same display effect under transmission and reflection light at different positions, realize the elimination of shadow, effectively avoid the occurrence of appearance defect and mura of the display substrate, and improve the display quality and display performance.

[0303] In the example embodiment, the fifth conductive layer (except the data transfer strip, the power supply transfer strip and the first break) of the adjacent unit columns can be mirror-symmetrical relative to the column boundary line. For example, the fifth conductive layer of the Nth unit column and the fourth conductive layer of the N+1th unit column can be mirror-symmetrical relative to the column boundary line, and the fifth conductive layer of the N+1th unit column and the fourth conductive layer of the N+2th unit column can be mirror-symmetrical relative to the column boundary line. In the example embodiment, the position and shape of the fifth conductive layer (except the data transfer strip, the power supply transfer strip and the first break) in the plurality of unit rows can be substantially the same.

[0304] (11) Forming a second planar layer pattern. In the example embodiment, forming the second planar layer pattern can include: on the substrate on which the aforementioned patterns are formed, coating a second planar film, patterning the second planar film by using a patterning process, forming a second planar layer covering the fifth conductive layer pattern, and the second planar layer being provided with a plurality of vias, as shown in FIG. 19.

[0305] In the example embodiment, the plurality of vias in each circuit unit in the display area at least include: a thirty-first via V31, a thirty-second via V32 and a thirty-third via V33.

[0306] In an example embodiment, the third thirty-one via V31 has a projection on the substrate within a projection of the eleventh connection electrode 61 on the substrate, the second planar layer in the third thirty-one via V31 is etched away to expose a surface of the eleventh connection electrode 61, and the third thirty-one via V31 is configured to enable a data signal line formed subsequently to connect to the eleventh connection electrode 61 through the via.

[0307] In an example embodiment, the third thirty-two via V32 has a projection on the substrate within a projection of the twelfth connection electrode 62 on the substrate, the second planar layer in the third thirty-two via V32 is etched away to expose a surface of the twelfth connection electrode 62, and the third thirty-two via V32 is configured to enable a first power supply line formed subsequently to connect to the twelfth connection electrode 62 through the via.

[0308] In an example embodiment, the third thirty-three via V33 has a projection on the substrate within a projection of the thirteenth connection electrode 63 on the substrate, the second planar layer in the third thirty-three via V33 is etched away to expose a surface of the thirteenth connection electrode 63, and the third thirty-three via V33 is configured to enable an anode connection electrode formed subsequently to connect to the thirteenth connection electrode 63 through the via.

[0309] In an example embodiment, the first region can further include a third thirty-four via V34, a third thirty-five via V35, and a third thirty-six via V36.

[0310] In an example embodiment, the third thirty-four via V34 has a projection on the substrate within a projection of the data connection block 83 on the substrate, the second planar layer in the third thirty-four via V34 is removed to expose a surface of the data connection block 83, and the third thirty-four via V34 is configured to enable a second connection line formed subsequently to connect to the data connection block 83 through the via.

[0311] In an example embodiment, the third thirty-five via V35 has a projection on the substrate within a projection of the wiring connection block 93 on the substrate, the second planar layer in the third thirty-five via V35 is removed to expose a surface of the wiring connection block 93, and the third thirty-five via V35 is configured to enable a second power supply wiring formed subsequently to connect to the wiring connection block 93 through the via.

[0312] In an exemplary embodiment, the orthogonal projection of the thirty-sixth via V36 on the substrate is within the orthogonal projection of the first dummy electrode 85 or the second dummy electrode 95 on the substrate, the second planar layer in the thirty-sixth via V36 is removed to expose the surface of the first dummy electrode 85 or the second dummy electrode 95, and the thirty-sixth via V36 is configured to connect a second connection line or a second power supply line formed subsequently therethrough to the first dummy electrode 85 or the second dummy electrode 95.

[0313] (12) Forming a sixth conductive layer pattern. In an exemplary embodiment, forming the sixth conductive layer can include: on the substrate on which the aforementioned pattern is formed, depositing a sixth conductive thin film, and patterning the sixth conductive thin film by using a patterning process to form a sixth conductive layer disposed on the second planar layer, as shown in FIGS. 20A and 20B, which is a plan view of the sixth conductive layer in FIG. 20A. In an exemplary embodiment, the sixth conductive layer can be referred to as a third source-drain metal (SD3) layer.

[0314] In an exemplary embodiment, the sixth conductive layer of each circuit unit in the display area at least includes: a data signal line 70, a first power supply line 71, and an anode connection electrode 72.

[0315] In an exemplary embodiment, the data signal line 70 can have a shape of a straight line or a broken line with a main body portion extending along the second direction Y, and the data signal line 70 is connected to the eleventh connection electrode 61 through the thirty-first via V31. Since the eleventh connection electrode 61 is connected to the third connection electrode 53 through a via, and the third connection electrode 53 is connected to the first region of the fourth active layer through a via, the connection of the data signal line 70 to the first electrode of the fourth transistor T4 is achieved, and the data signal line 70 can write a data signal to the first electrode of the fourth transistor T4.

[0316] In an exemplary embodiment, since the eleventh connection electrode 61 in part of the circuit units is connected to the first connection line 81 through the second data transfer bar 86, the connection of the first connection line 81 to the data signal line 70 is achieved, and the first connection line 81 can transmit a data signal to the data signal line 70. For example, the first connection line 81 disposed in the Mth unit row can transmit a data signal to the data signal line 70 in the Nth unit column. For another example, the first connection line 81 in the M+2th unit row can transmit a data signal to the data signal line 70 in the N+1th unit column.

[0317] In the example embodiment, since the data signal line is arranged in the third source-drain metal (SD3) layer, and the first planar layer and the second planar layer are arranged between the data signal line and the corresponding signal line, the distance between the data signal line and the corresponding signal line is increased, the parasitic capacitance between the data signal line and the corresponding signal line is reduced, and thus the capacitive load of the data signal line is effectively reduced.

[0318] In the example embodiment, the first power line 71 can have a shape of a straight line or a broken line with a main body extending along the second direction Y, and the first power line 71 is connected to the twelfth connection electrode 62 through the thirty-second via V32. Since the twelfth connection electrode 62 is connected to the fourth connection electrode 54, and the fourth connection electrode 54 is connected to the first region of the fifth active layer and the second plate of the storage capacitor respectively, the first power line 71 can write the first power signal to the fifth transistor T5 and the second plate of the storage capacitor.

[0319] In the example embodiment, the first power line 71 can have a non-constant-width broken line, which can not only facilitate the layout of the pixel structure, but also reduce the parasitic capacitance between the first power line and the data signal line.

[0320] In the example embodiment, in one unit row, the first power lines 71 in some adjacent two circuit units can be integrated structures connected to each other. For example, the first power lines 71 in the N+1th unit column and the N+2th unit column are connected to each other, and the first power lines 71 in the two adjacent circuit units are integrated structures connected to each other. For another example, the first power lines 71 in the N+3th unit column and the N+4th unit column are connected to each other, and the first power lines 71 in the two adjacent circuit units are integrated structures connected to each other.

[0321] In the example embodiment, the orthographic projection of the first power line 71 on the substrate at least partially overlaps the orthographic projection of the first break K1 on the substrate, so that the first power line 71 can cover the first break K1, effectively eliminating the film layer difference in different regions, facilitating shadow elimination, and avoiding appearance defects of the display substrate.

[0322] In the example embodiment, the anode connection electrode 72 can have a block shape (such as a rectangular shape), the anode connection electrode 72 is connected to the thirteenth connection electrode 63 through the thirty-third via V33, and the anode connection electrode 72 is configured to be connected to a subsequently formed anode. Since the thirteenth connection electrode 63 is connected to the sixth connection electrode 56 through a via, and the sixth connection electrode 56 is connected to the second region of the sixth active layer and the second region of the seventh active layer through a via, the subsequently formed anode can be connected to the second electrode of the sixth transistor T6 and the second electrode of the seventh transistor T7, and the pixel driving circuit can drive the light emitting device to emit light.

[0323] In the example embodiment, the sixth conductive layer of the display area can further include a second connection line 82 and a second power supply trace 92, the second connection line 82 and the second power supply trace 92 can be in a straight line shape or a zigzag shape with the main body part extending along the second direction Y, and can be located between two data signal lines 70 of adjacent unit columns.

[0324] In the example embodiment, the second connection line 82 and the second power supply trace 92 can be provided between at least one unit column of the first area, and a second break K2 can be provided between the second connection line 82 and the second power supply trace 92, the second break K2 can cut off the second connection line 82 and the second power supply trace 92 located between the second connection line 82 and the second power supply trace 92, so that the second connection line 82 and the second power supply trace 92 on both sides of the second break K2 are insulated from each other. One end of the second connection line 82 close to the second break K2 can be connected to the data connection block 83 through the thirty-fourth via hole V34, and the other end of the second connection line 82 away from the second break K2 can be extended to the binding area to be connected to the data lead-out line. For example, the second connection line 82 and the second power supply trace 92 can be provided between the N+2th unit column and the N+3th unit column. For another example, the second connection line 82 and the second power supply trace 92 can be provided between the N+6th unit column and the N+7th unit column.

[0325] In the example embodiment, since the second connection line 82 is connected to the first connection line 81 through the data connection block 83 and the first data transfer bar 84, and the first connection line 81 is connected to the data signal line 70 through the eleventh connection electrode 61 and the second data transfer bar 86, the second connection line 82 is connected to the data signal line 70 through the first connection line 81, and the second connection line 82 can transmit data signals to the data signal line 70. For example, the second connection line 82 provided between the N+6th unit column and the N+7th unit column can transmit data signals to the data signal line 70 in the Nth unit column through the first connection line 81 in the Mth unit row. For another example, the second connection line 82 provided between the N+2th unit column and the N+3th unit column can transmit data signals to the data signal line 70 in the N+1th unit column through the first connection line 81 in the M+2th unit row.

[0326] In the example embodiment, the second connection line 82 can also be connected to the first dummy electrode 85 through the thirty-sixth via hole V36, or the second connection line 82 can also be connected to the second dummy electrode 95 through the thirty-sixth via hole V36. Since the first dummy electrode 85 and the second dummy electrode 95 are isolated, such connection not only can improve the uniformity of the etching process, but also can make different positions achieve the same display effect under transmitted and reflected light, and realize shadow elimination.

[0327] In the example embodiment, the orthographic projection of the second break K2 on the substrate can be located within the range of the orthographic projection of the fourth connecting electrode 54 on the substrate, so that the fourth connecting electrode 54 can pad the second break K2 from below, effectively eliminating the film layer difference between different regions, facilitating the elimination of shadows, and avoiding the appearance of the display substrate being poor.

[0328] In the example embodiment, only the second power supply trace 92 can be arranged between at least one unit column in the first region. For example, only the second power supply trace 92 can be arranged between the N+4th unit column and the N+5th unit column, without arranging the second connecting line.

[0329] In the example embodiment, the second power supply trace 92 can be connected with the trace connection block 93 through the thirty-fifth via hole V35. Since the trace connection block 93 is connected with the first power supply trace 91 through the trace transfer bar 94, the mutual connection between the first power supply trace 91 extending along the first direction X and the second power supply trace 92 extending along the second direction Y is realized, and the first power supply trace 91 and the second power supply trace 92 form a meshed communication structure for transmitting the second power supply signal in the first region.

[0330] In the example embodiment, the second power supply trace 92 can also be connected with the first dummy electrode 85 through the thirty-sixth via hole V36, or the second power supply trace 92 can also be connected with the second dummy electrode 95 through the thirty-sixth via hole V36. Since the first dummy electrode 85 and the second dummy electrode 95 are arranged in isolation, such connection not only improves the uniformity of the etching process, but also enables the same display effect under transmitted and reflected light at different positions, realizing the elimination of shadows.

[0331] In the example embodiment, in the first region, one second power supply trace 92 can be arranged between adjacent second connecting lines 82.

[0332] In the example embodiment, the second power supply trace 92 located between adjacent two second connecting lines 82 can also be connected with the first power supply trace 91 located on one side of the first break K1 through a via hole, as a component of the meshed communication structure in the first region.

[0333] In the example embodiment, the first power supply trace 91 located between adjacent two first connecting lines 81 can also be connected with the second power supply trace 92 located on one side of the second break K2 through a via hole, as a component of the meshed communication structure in the first region.

[0334] In the example embodiment, only the second power supply wires 92 can be provided between the plurality of unit columns of the second region, and no second connection wires are provided. The second power supply wires 92 in the second region can be connected to the first power supply wires 91 in the second region through the wire connection blocks 93 and the wire transfer strips 94, and a meshed communication structure for transmitting the second power supply signal is formed in the second region.

[0335] In the example embodiment, the second power supply wires 92 in the first region can extend to the second region and be connected to the first power supply wires 91 in the second region through the wire connection blocks 93 and the wire transfer strips 94, and the first power supply wires 91 in the first region can extend to the second region and be connected to the second power supply wires 92 in the second region through the wire connection blocks 93 and the wire transfer strips 94, so that the meshed communication structure in the first region and the meshed communication structure in the second region are connected to each other.

[0336] In the example embodiment, the first power supply wires 91 can extend to the frame region or the second power supply wires 92 can extend to the binding region and be connected to the second power supply lead wires for transmitting the second power supply signal, so that the second power supply wires are located in the SIP structure. This not only effectively reduces the resistance of the second power supply wires, reduces the voltage drop of the second power supply signal, effectively improves the uniformity of the second power supply signal in the display substrate, effectively improves the display uniformity, improves the display quality and display quality, but also greatly reduces the width of the frame power supply lead wires, greatly reduces the frame width, improves the screen ratio, and is conducive to realizing the full-screen display.

[0337] In the example embodiment, the orthogonal projection of the second connection wires 82 on the substrate at least partially overlaps the orthogonal projection of the first data transfer strips 84 on the substrate, and the orthogonal projection of the second power supply wires 92 on the substrate at least partially overlaps the orthogonal projection of the wire transfer strips 94 on the substrate.

[0338] In the example embodiment, the orthogonal projection of at least one second connection wire 82 or at least one second power supply wire 92 on the substrate can at least partially overlap the orthogonal projection of the column boundary line on the substrate.

[0339] In the example embodiment, in the first direction X, the two data signal lines 70 located on both sides of the second connection wire 82 or the second power supply wire 92 can be mirror symmetrical relative to the column boundary line.

[0340] In the exemplary embodiments, in the first direction X, one second connection line 82 and two data signal lines 70 can be arranged between two first power supply lines 71 of adjacent unit columns, or one second power supply line 92 and two data signal lines 70 can be arranged between two first power supply lines 71 of adjacent unit columns, and the two first power supply lines 71 can be mirror-symmetrical relative to the column boundary line.

[0341] In the exemplary embodiments, since the second connection line is arranged in the third source-drain metal (SD3) layer and is spaced apart from the corresponding signal line by the thick first planar layer and the second planar layer, the distance between the second connection line and the corresponding signal line is increased, the parasitic capacitance between the second connection line and the corresponding signal line is reduced, and thus the capacitive load of the second connection line is effectively reduced.

[0342] In the exemplary embodiments, since the first connection line is arranged in the second source-drain metal (SD2) layer and the second connection line is arranged in the third source-drain metal (SD3) layer, the first connection line and the second connection line only need one planar layer via hole to realize connection, the occupied space is minimized, and high-resolution display is facilitated.

[0343] (13) A third planar layer covering the sixth conductive layer pattern is formed, and a plurality of anode via holes are arranged on the third planar layer, and the anode via holes expose the anode connection electrode. At this point, the driving structure layer is prepared on the substrate.

[0344] In the exemplary embodiments, in the plane parallel to the display substrate, the driving structure layer can include a plurality of circuit units, at least one circuit unit can include a pixel driving circuit, and a first scan signal line, a second scan signal line, a third scan signal line, a fourth scan signal line, a light-emitting signal line, a first initial signal line, a second initial signal line, a third initial signal line, a first power supply line, and a data signal line connected to the pixel driving circuit.

[0345] In a plane perpendicular to the display substrate, the driving structure layer can include, in sequence on the base, a shielding layer, a first insulating layer, a first semiconductor layer, a second insulating layer, a first conductive layer, a third insulating layer, a second conductive layer, a fourth insulating layer, a second semiconductor layer, a fifth insulating layer, a third conductive layer, a sixth insulating layer, a fourth conductive layer, a first planarization layer, a fifth conductive layer, a second planarization layer, a sixth conductive layer, and a third planarization layer. The first semiconductor layer can include at least active layers of a first transistor, a third transistor to an eighth transistor, the first conductive layer can include at least a first scan signal line, a second scan signal line, a third scan signal line, a light-emitting signal line, and a first plate of a storage capacitor, the second conductive layer can include at least a second plate of the storage capacitor, the second semiconductor layer can include at least an active layer of a second transistor, the third conductive layer can include at least a first initial signal line, a second initial signal line, a third initial signal line, and a fourth scan signal line, the fourth conductive layer can include at least a plurality of connection electrodes, the fifth conductive layer can include at least a first connection line and a first power supply trace, and the sixth conductive layer can include at least a first power supply line, a data signal line, a second connection line, and a second power supply trace.

[0346] In an exemplary embodiment, the base can be a flexible base, or can be a rigid base. The rigid base can include, but is not limited to, one or more of glass, quartz, and the flexible base can be, but is not limited to, one or more of polyethylene terephthalate, terephthalate, polyether ether ketone, polystyrene, polycarbonate, polyarylate, polyarylate, polyimide, polyvinyl chloride, polyethylene, and textile fibers. In an exemplary embodiment, the flexible base can include a first flexible material layer, a first inorganic material layer, a semiconductor layer, a second flexible material layer, and a second inorganic material layer stacked. The materials of the first and second flexible material layers can be polyimide (PI), polyethylene terephthalate (PET), or a surface-treated polymer soft film, and the like, and the materials of the first and second inorganic material layers can be silicon nitride (SiNx) or silicon oxide (SiOx), or the like, for improving the water and oxygen resistance of the base. The first and second inorganic material layers are also referred to as barrier layers, and the material of the semiconductor layer can be amorphous silicon (a-si).

[0347] In the example embodiments, the first conductive layer, the second conductive layer, the third conductive layer, the fourth conductive layer, the fifth conductive layer and the sixth conductive layer can be made of a metal material, such as any one or more of silver (Ag), copper (Cu), aluminum (Al) and molybdenum (Mo), or an alloy material of the above-mentioned metals, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb), and can be a single-layer structure or a multi-layer composite structure, such as Mo / Cu / Mo, etc. The first insulating layer, the second insulating layer, the third insulating layer, the fourth insulating layer, the fifth insulating layer and the sixth insulating layer can be made of any one or more of silicon oxide (SiOx), silicon nitride (SiNx) and silicon oxynitride (SiON), and can be a single layer, a multi-layer or a composite layer. The first planar layer, the second planar layer and the third planar layer can be made of an organic material, such as resin, etc.

[0348] In the example embodiments, the pixel driving circuits in two adjacent circuit units in one unit row can be substantially mirror-symmetrical with respect to the column boundary line. For example, the pixel driving circuit in the Nth unit column and the pixel driving circuit in the (N+1)th unit column can be mirror-symmetrical with respect to the column boundary line. For another example, the pixel driving circuit in the (N+1)th unit column and the pixel driving circuit in the (N+2)th unit column can be mirror-symmetrical with respect to the column boundary line.

[0349] In the example embodiments, after the preparation of the driving structure layer is completed, the light-emitting structure layer can be prepared on the driving structure layer, and the preparation process of the light-emitting structure layer can include: first forming an anode conductive layer, the anode conductive layer including a plurality of anodes, and the plurality of anodes can be connected to the anode connection electrodes of the circuit units through anode vias, respectively. Subsequently, a pixel definition layer is formed, and the pixel definition layer is provided with a plurality of pixel openings, and the plurality of pixel openings expose the anodes, respectively. Subsequently, an organic light-emitting layer is formed by using an evaporation or inkjet printing process, and then a cathode is formed on the organic light-emitting layer. Subsequently, an encapsulation structure layer is formed, and the encapsulation structure layer can include a first encapsulation layer, a second encapsulation layer and a third encapsulation layer which are stacked, the first encapsulation layer and the third encapsulation layer can be made of an inorganic material, the second encapsulation layer can be made of an organic material, and the second encapsulation layer is arranged between the first encapsulation layer and the third encapsulation layer, so as to ensure that external water vapor cannot enter the light-emitting structure layer.

[0350] The display substrate provided by the exemplary embodiments of the present disclosure can realize FIP structure by arranging data connection lines (first connection lines and second connection lines) in the display area, and the data lead-out lines of the binding area are connected with the data signal lines through the data connection lines, so that the fan-shaped inclined lines do not need to be arranged in the lead-out line area, the length of the lead-out line area is effectively reduced, the lower frame width is greatly reduced, the screen-to-body ratio is improved, and the full-screen display is facilitated. The first power supply lines and the second power supply lines are arranged in the display area, and the first power supply lines and the second power supply lines form a mesh communication structure, so that the SIP structure is realized, the resistance of the second power supply lines can be effectively reduced, the voltage drop of the second power supply signal can be reduced, and low power consumption is realized.

[0351] The first power supply lines and the second power supply lines are arranged in the first area (FIP area), the first power supply lines are arranged between two adjacent first connection lines, the second power supply lines are arranged between two adjacent second connection lines, the first power supply lines and the second power supply lines form a mesh communication structure in the FIP area, and the mesh communication structure of the FIP area is communicated with the mesh communication structure of the non-FIP area. Not only the uniformity of the second power supply signal in the FIP area is effectively improved, but also the uniformity of the second power supply signal in the entire display area is effectively improved, and the display quality and display performance are improved.

[0352] The SIP structure is formed in the display area, so that the width of the frame power supply lead line can be greatly reduced, the frame width is greatly reduced, the screen-to-body ratio is improved, and the full-screen display is facilitated.

[0353] The first initial connection lines, the second initial connection lines and the third initial connection lines are arranged, the first initial connection lines and the first initial signal lines form a mesh communication structure, the second initial connection lines and the second initial signal lines form a mesh communication structure, and the third initial connection lines and the third initial signal lines form a mesh communication structure. Not only the resistance of the initial signal lines can be effectively reduced, the voltage drop of the initial signal can be reduced, the uniformity of the initial signal in the display substrate can be effectively improved, the display uniformity can be effectively improved, and the display quality and display performance are improved.

[0354] The power supply connection strips are arranged in part of the circuit units, so that the number of the power supply connection strips is effectively reduced, the overlapping area of the power supply connection strips and the fourth scanning signal lines is effectively reduced, the short circuit caused by foreign object damage can be effectively avoided, and the product yield can be effectively improved.

[0355] The preparation process of the present disclosure can be well compatible with the existing preparation process, the process is simple to implement, high in production efficiency, low in production cost and high in yield.

[0356] FIG. 21 is a structural schematic diagram of another display substrate according to an exemplary embodiment of the present disclosure. As shown in FIG. 21, the main structure of the display substrate according to the present embodiment is basically the same as that of the embodiment shown in FIGS. 8A and 8B, except that the second plates in one unit row can form an integrated structure connected to each other through the plate connection strips, and the power connection strips 60 in the plurality of unit rows can be arranged in the partial circuit units.

[0357] In the exemplary implementation, the preparation process of the display substrate according to the present embodiment can include the following operations.

[0358] (21) to (24) form the shielding layer, the first semiconductor layer, the first conductive layer and the second conductive layer in sequence, and the preparation process and the patterns of the formed shielding layer, the first semiconductor layer, the first conductive layer and the second conductive layer are basically the same as those of the previous embodiments, except that the second plates in two adjacent circuit units in one unit row in the second conductive layer are connected to each other through the plate connection strips 34 to form an integrated structure connected to each other, as shown in FIG. 22.

[0359] In the exemplary implementation, since the second plates 32 are connected to the first power lines formed subsequently, the second plates of the integrated structure can form a transverse power connection line extending along the first direction X and arranged continuously, and the transverse power connection line and the first power lines extending along the second direction Y formed subsequently form a meshed communication structure for transmitting the first power signal in a meshed manner, which not only can effectively reduce the resistance of the first power signal line, reduce the voltage drop of the first power signal, effectively improve the uniformity of the first power signal in the display substrate, effectively improve the display uniformity, and improve the display quality and display performance.

[0360] (25) to (28) form the second semiconductor layer, the third conductive layer, the sixth insulating layer and the fourth conductive layer in sequence, and the preparation process and the patterns of the formed second semiconductor layer, the third conductive layer, the sixth insulating layer and the fourth conductive layer are basically the same as those of the previous embodiments, except that the power connection strips 60 are arranged in the partial circuit units in the plurality of unit rows, as shown in FIG. 21.

[0361] In the exemplary implementation, the power connection strips 60 are arranged in the partial circuit units in the plurality of unit rows of the display substrate. The power connection strips 60 can be arranged in the circuit units of the odd-numbered unit columns, or the power connection strips 60 can be arranged in the circuit units of the even-numbered unit columns. Although the power connection strips 60 are arranged in the partial circuit units in the plurality of unit rows, since the second plates in the second conductive layer form the transverse power connection line, and the transverse power connection line and the first power lines formed subsequently form the meshed communication structure, the effect of the meshed communication structure will not be affected.

[0362] (29) to (33) are sequentially formed, and the manufacturing process and the first planar layer, the fifth conductive layer, the second planar layer, the sixth conductive layer and the third planar layer formed are substantially the same as those of the foregoing embodiments, which will not be described herein.

[0363] The display substrate provided by the embodiment has substantially the same technical effects as the foregoing embodiments, and can further reduce the number of power connection strips, further avoid short circuit failure caused by foreign object damage, and further improve product yield.

[0364] In some possible embodiments, the structure shape and arrangement manner of the power connection strip can be changed as required. For example, in the embodiment shown in FIGS. 8A and 8AB, the number of unit rows in which all the circuit units are provided with the power connection strip can be reduced, and three or more unit rows in which part of the circuit units are provided with the power connection strip can be arranged between two adjacent unit rows in which all the circuit units are provided with the power connection strip. For another example, in the embodiment shown in FIG. 21, the power connection strip can be arranged in one adjacent unit column, and the power connection strip can not be arranged in another adjacent unit column, which is not limited in the disclosure.

[0365] FIG. 23 is a structural schematic view of another data connection line and power supply line according to an exemplary embodiment of the disclosure. As shown in FIG. 23, the structure of the data connection line and the power supply line in the embodiment can be substantially the same as that of the embodiment shown in FIG. 7, except that two second power supply lines 92 can be arranged between two adjacent second connection lines 82.

[0366] In the exemplary embodiments, in the first region 110, one first power supply line 91 (which can be referred to as an inserted first power supply line 91) can be arranged between two adjacent first connection lines 81, and two second power supply lines 92 (which can be referred to as inserted second power supply lines 92) can be arranged between two adjacent second connection lines 82. The inserted first power supply line 91 and the inserted second power supply line 92 can be connected to each other, and a meshed communication structure for transmitting power supply signals can be formed in the first region 110.

[0367] In the exemplary embodiments, the first power supply line 91 arranged in the same unit row as the first connection line 81 and disconnected from the first connection line 81 can be connected to the inserted second power supply line 92, and the second power supply line 92 arranged in the same unit column as the second connection line 82 and disconnected from the second connection line 82 can be connected to the inserted first power supply line 91, as a component of the meshed communication structure in the first region 110.

[0368] In the exemplary embodiments, the first power supply line 91 inserted in the first region 110 can extend to the second region 120 and be connected with the second power supply line 92 in the second region 120, and the second power supply line 92 inserted in the first region 110 can extend to the second region 120 and be connected with the first power supply line 91 in the second region 120, thereby realizing the interconnection between the meshed communication structure in the first region and the meshed communication structure in the second region.

[0369] The display substrate provided by the embodiments has substantially the same technical effects as the embodiment shown in FIG. 7, and because two second power supply lines are arranged between the two adjacent second connection lines, the uniformity of the second power supply signal in the FIP region can be further improved, the uniformity of the second power supply signal in the entire display region is further improved, and the display quality and display performance are improved.

[0370] In some possible embodiments, the arrangement of the second power supply line can be changed according to actual needs. For example, a plurality of (such as three or four) second power supply lines can be arranged between the two adjacent second connection lines. For another example, the two or more second connection lines can be arranged as a second connection line group, the two or more second connection lines in the second connection line group are arranged in sequence along the first direction X, no second power supply line is arranged between the two adjacent second connection lines, and one or more second power supply lines are arranged between the two adjacent second connection line groups. For another example, one or more second power supply lines can be arranged between the first second connection line close to the frame region and the frame region, which is not limited in the disclosure.

[0371] FIG. 24 is a structural schematic diagram of another data connection line and power supply line according to an exemplary embodiment of the disclosure. As shown in FIG. 24, the structure of the data connection line and the power supply line in the embodiment can be substantially the same as that of the embodiment shown in FIG. 7, except that two first power supply lines 91 can be arranged between the two adjacent first connection lines 81.

[0372] In the exemplary embodiments, in the first region 110, two first power supply lines 91 (which can be referred to as inserted first power supply lines 91) can be arranged between the two adjacent first connection lines 81, and one second power supply line 92 (which can be referred to as an inserted second power supply line 92) can be arranged between the two adjacent second connection lines 82, the inserted first power supply line 91 and the inserted second power supply line 92 can be interconnected, and a meshed communication structure for transmitting power supply signals in a meshed manner is formed in the first region 110.

[0373] In the example embodiment, the first power supply lines 91 arranged in the same unit row as the first connection lines 81 and disconnected from the first connection lines 81 can be connected with the inserted second power supply lines 92, and the second power supply lines 92 arranged in the same unit column as the second connection lines 82 and disconnected from the second connection lines 82 can be connected with the inserted first power supply lines 91, as a component of the meshed communication structure in the first region 110.

[0374] In the example embodiment, the first power supply lines 91 inserted in the first region 110 can extend to the second region 120 and be connected with the second power supply lines 92 in the second region 120, and the second power supply lines 92 inserted in the first region 110 can extend to the second region 120 and be connected with the first power supply lines 91 in the second region 120, realizing the interconnection between the meshed communication structure in the first region and the meshed communication structure in the second region.

[0375] The display substrate provided in the embodiment has substantially the same technical effects as the embodiment shown in FIG. 7, and because two first power supply lines are arranged between the two adjacent first connection lines, the uniformity of the second power supply signal in the FIP region can be further improved, the uniformity of the second power supply signal in the entire display region is further improved, and the display quality and display performance are improved.

[0376] In some possible embodiments, the arrangement of the first power supply lines can be changed according to actual needs. For example, a plurality of (e.g., three or four) first power supply lines can be arranged between the two adjacent first connection lines. For another example, the two or more first connection lines can be arranged as a first connection line group, the two or more first connection lines in the first connection line group are arranged in sequence along the second direction Y, and no first power supply line is arranged between the two adjacent first connection lines, but one or more first power supply lines are arranged between the two adjacent first connection line groups. For another example, one or more first power supply lines can be arranged between the first first connection line close to the bonding region and the bonding region, which is not limited in the disclosure.

[0377] FIG. 25 is a structural schematic diagram of another data connection line and power supply line in an example embodiment of the disclosure. As shown in FIG. 25, the structure of the data connection line and the power supply line in the embodiment can be substantially the same as that in the embodiment shown in FIG. 7, except that no first power supply line is arranged between the two adjacent first connection lines 81.

[0378] In the example embodiment, in the first region 110, one second power supply line 92 (which can be referred to as an inserted second power supply line 92) can be arranged between the two adjacent second connection lines 82, but a plurality of first connection lines 81 are arranged in sequence along the second direction Y, and no first power supply line is arranged between the two adjacent first connection lines 81.

[0379] In the example embodiment, the first power supply line 91 which is arranged in the same unit row as the first connection line 81 and is disconnected from the first connection line 81 can be connected with the inserted second power supply line 92, and a meshed communication structure for transmitting power supply signals in a meshed manner is formed in the first region 110.

[0380] In the example embodiment, the second power supply line 92 inserted in the first region 110 can extend to the second region 120 and be connected with the first power supply line 91 in the second region 120, and the interconnection between the meshed communication structure in the first region and the meshed communication structure in the second region is realized.

[0381] The display substrate provided by the embodiment has substantially the same technical effects as the embodiment shown in FIG. 7, and the area of the FIP region can be effectively reduced and the wiring structure of the FIP region can be simplified because no first power supply line is arranged between the two adjacent first connection lines.

[0382] In some possible embodiments, the arrangement mode of the second power supply line can be changed according to actual needs. For example, a plurality of (such as three or four) second power supply lines 92 can be arranged between the two adjacent second connection lines 82. For another example, one or more second power supply lines can be arranged between the first second connection line close to the frame region and the frame region, which is not limited in the disclosure.

[0383] FIG. 26 is a structural schematic view of another data connection line and power supply line according to an example embodiment of the disclosure. As shown in FIG. 26, the structure of the data connection line and the power supply line in the embodiment can be substantially the same as that of the embodiment shown in FIG. 7, except that no second power supply line is arranged between the two adjacent second connection lines 82.

[0384] In the example embodiment, in the first region 110, one first power supply line 91 (which can be referred to as an inserted first power supply line 91) can be arranged between the two adjacent first connection lines 81, but a plurality of second connection lines 82 are arranged along the first direction X in sequence, and no second power supply line is arranged between the two adjacent second connection lines 82.

[0385] In the example embodiment, the second power supply line 92 which is arranged in the same unit column as the second connection line 82 and is disconnected from the second connection line 82 can be connected with the inserted first power supply line 91, and a meshed communication structure for transmitting power supply signals in a meshed manner is formed in the first region 110.

[0386] In the example embodiment, the first power supply line 91 inserted in the first region 110 can extend to the second region 120, and connect with the second power supply line 92 in the second region 120, thereby realizing the interconnection between the meshed communication structure in the first region and the meshed communication structure in the second region.

[0387] The display substrate provided by the embodiment has substantially the same technical effects as the embodiment shown in FIG. 7, and since no second power supply line is arranged between the two adjacent second connection lines, the area of the FIP region can be effectively reduced, and the wiring structure of the FIP region is simplified.

[0388] In some possible embodiments, the arrangement of the first power supply line can be changed according to actual needs. For example, a plurality of (e.g., three or four) first power supply lines 91 can be arranged between the two adjacent first connection lines 81. For another example, one or more first power supply lines can be arranged between the first first connection line close to the binding region and the binding region, which is not limited in the disclosure.

[0389] The foregoing structures and preparation processes of the disclosure are only exemplary descriptions, and in the example embodiment, the corresponding structures can be changed, and the patterning process can be increased or reduced, which is not limited in the disclosure.

[0390] In the example embodiment, the display substrate of the disclosure can be applied to a display device with a pixel driving circuit, such as OLED, quantum dot display (QLED), light-emitting diode display (Micro LED or Mini LED), or quantum dot light-emitting diode display (QDLED), which is not limited in the disclosure.

[0391] The disclosure also provides a preparation method of a display substrate for manufacturing the display substrate provided in the above embodiments. In the example embodiment, the display substrate can include a plurality of circuit units forming a plurality of unit rows and a plurality of unit columns, at least one first connection line extending along a first direction, at least one first power supply line extending along the first direction, at least one second connection line extending along a second direction, at least one second power supply line extending along the second direction, and a plurality of data signal lines extending along the second direction, the first direction and the second direction intersecting; the preparation method includes:

[0392] The pixel driving circuit is formed in at least one circuit unit, the pixel driving circuit is connected with the data signal line, and the second connection line is connected with the data signal line through the first connection line; the display substrate is divided into a first region and a second region, the first region is a region in which the first connection line or the second connection line is arranged, and the second region is a region in which the first connection line and the second connection line are not arranged; in the second region, the first power supply line and the second power supply line are connected; and in the first region, at least one second power supply line is arranged between two second connection lines adjacent in the first direction, and / or at least one first power supply line is arranged between two first connection lines adjacent in the second direction.

[0393] While the embodiments disclosed by the present disclosure are as above, it should be noted that the above embodiments are merely exemplary but not limiting. Therefore, the present disclosure is not limited to what is specifically shown and described herein. Various modifications, substitutions, and omissions can be made without departing from the scope of the present disclosure.

Claims

1. A display substrate, characterized by, The display substrate comprises a plurality of circuit units forming a plurality of unit rows and a plurality of unit columns, at least one first connection line extending along a first direction, at least one first power supply line extending along the first direction, at least one second connection line extending along a second direction, at least one second power supply line extending along the second direction, and a plurality of data signal lines extending along the second direction, the first direction and the second direction intersecting; at least one circuit unit comprises a pixel driving circuit connected with the data signal line, the second connection line is connected with the data signal line through the first connection line; the display substrate is divided into a first region and a second region, the first region is a region where the first connection line or the second connection line is arranged, and the second region is a region where the first connection line and the second connection line are not arranged; in the second region, the first power supply line and the second power supply line are connected; in the first region, at least one second power supply line is arranged between two second connection lines adjacent in the first direction, and / or at least one first power supply line is arranged between two first connection lines adjacent in the second direction. 2.The display substrate of claim 1, wherein, The first power supply line arranged between two first connection lines in the first region extends to the second region and is connected with the second power supply line in the second region. 3.The display substrate of claim 1, wherein, The second power supply line arranged between two second connection lines in the first region extends to the second region and is connected with the first power supply line in the second region. 4.The display substrate of claim 1, wherein, In the first region, at least one second power supply line is arranged between two second connection lines adjacent in the first direction, at least one first connection line and at least one first power supply line are arranged in at least one unit row, a first break is arranged between the first connection line and the first power supply line, and the second power supply line arranged between two second connection lines is connected with the first power supply line on one side of the first break. 5.The display substrate of claim 1, wherein, In the first region, at least one first power supply line is arranged between two first connection lines adjacent in the second direction, at least one second connection line and at least one second power supply line are arranged in at least one unit column, a second break is arranged between the second connection line and the second power supply line, and the first power supply line arranged between two first connection lines is connected with the second power supply line on one side of the second break. 6.The display substrate of claim 1, wherein, In the first region, at least one second power supply line is arranged between two second connection lines adjacent in the first direction, at least one first power supply line is arranged between two first connection lines adjacent in the second direction, and the second power supply line arranged between two second connection lines is connected with the first power supply line arranged between two first connection lines. 7.The display substrate of claim 6, wherein, At least one unit row is provided with at least one first connection line and at least one first power supply line, a first break is arranged between the first connection line and the first power supply line, the second power supply line arranged between two second connection lines is connected with the first power supply line on one side of the first break; at least one unit column is provided with at least one second connection line and at least one second power supply line, a second break is arranged between the second connection line and the second power supply line, the first power supply line arranged between two first connection lines is connected with the second power supply line on one side of the second break. 8.The display substrate of claim 1, wherein, In the first area, two second power supply lines are arranged between two second connection lines adjacent in the first direction, and one first power supply line is arranged between two first connection lines adjacent in the second direction. 9.The display substrate of claim 1, wherein, In the first area, one second power supply line is arranged between two second connection lines adjacent in the first direction, and two first power supply lines are arranged between two first connection lines adjacent in the second direction. 10.The display substrate according to any one of claims 1 to 9, wherein In a direction perpendicular to the display substrate, the display substrate comprises a plurality of conductive layers, the first connection line and the first power supply line are arranged in the same conductive layer, the second connection line, the second power supply line and the data signal line are arranged in the same conductive layer, and the first connection line and the second connection line are arranged in different conductive layers. 11.The display substrate according to any one of claims 1 to 9, wherein The display substrate further comprises at least one first power supply line extending along the second direction, and the pixel driving circuit comprises at least a storage capacitor, the storage capacitor comprises a first plate and a second plate, and a projection of the second plate on a display substrate plane at least partially overlaps a projection of the first plate on the display substrate plane. In at least one circuit unit, the first power supply line is connected with the second plate through a power supply connection strip. In at least one unit row, the power supply connection strip is arranged in a part of the circuit units, and the power supply connection strip is not arranged in another part of the circuit units. 12.The display substrate of claim 11, wherein, In at least one unit row, the power supply connection strip is arranged in the circuit units of odd-numbered unit columns, or the power supply connection strip is arranged in the circuit units of even-numbered unit columns. 13.The display substrate of claim 11, wherein, At least one circuit unit further comprises a first power supply electrode and a second power supply electrode, the second plate is connected with the power supply connection strip through the first power supply electrode, and the first power supply line is connected with the power supply connection strip through the second power supply electrode; in at least one unit row, the second plates in some adjacent circuit units are an integrated structure connected with each other, the second power supply electrodes in some adjacent circuit units are an integrated structure connected with each other, the second plate and the second power supply electrode form a transverse power supply connection line extending along the first direction, and the transverse power supply connection line and the first power supply line form a meshed communication structure for transmitting a first power supply signal. 14.The display substrate of claim 13, wherein, In at least one unit row, all circuit units are provided with the power connection strip, and in at least another unit row, part of the circuit units are provided with the power connection strip. 15.The display substrate of claim 14, wherein, The unit row in which all circuit units are provided with the power connection strip and the unit row in which part of the circuit units are provided with the power connection strip are arranged alternately. 16.The display substrate of claim 11, wherein, In at least one unit row, the second plates in adjacent circuit units are connected to each other through the plate connection strip, forming a transverse power connection line extending along the first direction, and the transverse power connection line and the first power line form a meshed communication structure for transmitting the first power signal in a meshed manner. 17.The display substrate of claim 16, wherein, All the unit rows are the unit rows in which part of the circuit units are provided with the power connection strip.

18. A display device comprising the display substrate according to any one of claims 1 to 17.

19. A method for manufacturing a display substrate, comprising forming a plurality of circuit units in a plurality of unit rows and a plurality of unit columns, at least one first connection line extending along a first direction, at least one first power line extending along the first direction, at least one second connection line extending along a second direction, at least one second power line extending along the second direction, and a plurality of data signal lines extending along the second direction, the first direction and the second direction being crossed; the method comprising: forming a pixel driving circuit in at least one circuit unit, the pixel driving circuit being connected to the data signal line, and the second connection line being connected to the data signal line through the first connection line; the display substrate being divided into a first region and a second region, the first region being a region in which the first connection line or the second connection line is arranged, and the second region being a region in which the first connection line and the second connection line are not arranged; in the second region, the first power line and the second power line are connected; in the first region, at least one second power line is arranged between two second connection lines adjacent in the first direction, and / or at least one first power line is arranged between two first connection lines adjacent in the second direction.

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