Display substrate and display apparatus

Abstract

The present disclosure provides a display substrate and a display apparatus. The display substrate comprises a base and a driving module disposed on the base; the driving module comprises a plurality of stages of driving circuits; the driving circuits comprise a plurality of devices, and the devices include transistors and capacitors. The display substrate further comprises a plurality of signal lines disposed on the base, and the plurality of signal lines comprise at least three clock signal lines; the orthographic projection of the signal lines on the base at least partially overlaps the orthographic projection of at least one of the devices on the base; and at least one transistor in at least two stages of driving circuits comprised in the driving module is electrically connected to at least one transistor in the other stages of driving circuits by means of a corresponding clock signal line. In at least one embodiment of the present disclosure, the at least three clock signal lines are longitudinally arranged above the driving circuits, allowing for arrangement of the at least three clock signal lines without increasing the horizontal space, thereby realizing a narrow bezel.

Description

Display substrate and display device TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of display, and in particular, to a display substrate and a display device. BACKGROUND

[0002] With the development of intelligent display devices, consumers have higher and higher requirements for the display quality and power consumption of display devices. Therefore, it is important to improve the display quality and endurance of display devices. Improving and improving from the aspect of driving circuit is one of the directions. For example, reducing the loading of the clock signal line, improving the output capability of the driving circuit buffer tube through voltage adjustment, improving the stability of the output, and the like can improve the comprehensive performance of the display device.

[0003] SUMMARY

[0004] In one aspect, the display substrate provided by the embodiments of the present disclosure includes a substrate and a driving module disposed on the substrate, the driving module includes a plurality of stages of driving circuits; the driving circuit includes a plurality of devices, the device includes a transistor and a capacitor; the display substrate further includes a plurality of signal lines disposed on the substrate, the plurality of signal lines includes at least three clock signal lines;

[0005] The normal projection of the signal line on the substrate at least partially overlaps the normal projection of at least one of the devices on the substrate;

[0006] At least one transistor in at least two stages of driving circuits included in the driving module is electrically connected to at least one transistor in other stages of driving circuits through a corresponding clock signal line.

[0007] In at least one embodiment of the present disclosure, at least one transistor in each stage of driving circuit in the driving module is electrically connected to at least one transistor in other stages of driving circuit through a corresponding clock signal line.

[0008] In at least one embodiment of the present disclosure, the driving circuit includes an input circuit; the input circuit is electrically connected to a first clock signal line, an input terminal and a first node respectively, and is configured to control the potential of the first node according to an input signal provided by the input terminal under the control of a first clock signal provided by the first clock signal line;

[0009] The normal projection of the active pattern of at least one transistor included in the input circuit on the substrate at least partially overlaps the normal projection of the first column of clock signal lines on the substrate;

[0010] The normal projection of the active pattern of at least one transistor included in the input circuit on the substrate at least partially overlaps the normal projection of the second column of clock signal lines on the substrate.

[0011] In at least one embodiment of the present disclosure, the driving circuit comprises a second node control circuit; the second node control circuit is electrically connected with the first voltage line, the first node and the second node respectively, and is configured to control the communication between the first node and the second node under the control of the first voltage signal provided by the first voltage line;

[0012] The active pattern of at least one transistor included in the second node control circuit at least partially overlaps the orthogonal projection of the second column of clock signal lines on the substrate.

[0013] In at least one embodiment of the present disclosure, the driving circuit comprises a first node control circuit; the first node control circuit is electrically connected with the third clock signal line, the third node and the first node respectively, and is configured to control the communication between the third node and the first node under the control of the third clock signal provided by the third clock signal line;

[0014] The active pattern of at least one transistor included in the first node control circuit at least partially overlaps the orthogonal projection of the third clock signal line on the substrate.

[0015] In at least one embodiment of the present disclosure, the driving circuit comprises a third node control circuit; the third node control circuit is electrically connected with the fourth node, the second voltage line and the third node respectively, and is configured to write the second voltage signal provided by the second voltage line into the third node under the control of the potential of the fourth node;

[0016] The orthogonal projection of the gate of at least one transistor included in the third node control circuit on the substrate is arranged between the orthogonal projection of the fourth column of clock signal lines on the substrate and the orthogonal projection of the first first level line on the substrate;

[0017] The first first level line is arranged on the side of the fourth column of clock signal lines close to the display area.

[0018] In at least one embodiment of the present disclosure, the plurality of signal lines comprises a first first level line; the driving circuit comprises an output circuit; the output circuit is electrically connected with the fourth node, the second node and the driving output end respectively, and is configured to control the driving output end to output a driving signal under the control of the potential of the fourth node and the potential of the second node;

[0019] The orthogonal projection of the first first level line on the substrate at least partially overlaps the orthogonal projection of the active pattern of at least one transistor included in the output circuit on the substrate.

[0020] In at least one embodiment of the present disclosure, the plurality of signal lines further include a second first-level line; the driving circuit includes a fourth node control circuit; the fourth node control circuit is electrically connected with the first node, the second clock signal line and the fourth node respectively, and is configured to control communication between the second clock signal line and the fourth node under control of the potential of the first node; and the first first-level line is electrically connected with the second first-level line.

[0021] The active pattern of at least one transistor included in the fourth node control circuit has a projection on the substrate that at least partially overlaps with a projection of the second first-level line on the substrate.

[0022] In at least one embodiment of the present disclosure, the plurality of signal lines further include a third first-level line; the second first-level line and the third first-level line are arranged in different layers; and the second first-level line is electrically connected with the third first-level line.

[0023] The projection of the second first-level line on the substrate at least partially overlaps with a projection of the third first-level line on the substrate.

[0024] In at least one embodiment of the present disclosure, the plurality of signal lines further include a third first-level line and a first voltage line; the second first-level line is electrically connected with the third first-level line.

[0025] The projection of the third first-level line on the substrate at least partially overlaps with a projection of the first voltage line on the substrate.

[0026] In at least one embodiment of the present disclosure, the first first-level line, the second first-level line and the third first-level line are all arranged in a peripheral region.

[0027] The first first-level line is electrically connected with a grid-shaped low-level trace arranged in a display region.

[0028] In at least one embodiment of the present disclosure, the driving circuit includes a fourth node control circuit; the fourth node control circuit is electrically connected with the first node, the fourth node, the second clock signal line and the first voltage line respectively, and is configured to control communication between the fourth node and the second clock signal line under control of the potential of the first node, and control communication between the fourth node and the first voltage line under control of a second clock signal provided by the second clock signal line.

[0029] The active pattern of at least one transistor included in the fourth node control circuit has a projection on the substrate that at least partially overlaps with a projection of the second first-level line on the substrate.

[0030] A positive projection of an active pattern of at least one transistor of the fourth node control circuit on the substrate at least partially overlaps a positive projection of the third first-level line on the substrate.

[0031] A positive projection of an active pattern of at least one transistor of the fourth node control circuit on the substrate at least partially overlaps a positive projection of the first voltage line on the substrate.

[0032] In at least one embodiment of the present disclosure, the plurality of signal lines include a second voltage line; the driving circuit includes an output circuit; the output circuit is electrically connected with the fourth node, the second node and a driving output terminal respectively, and is configured to control the driving output terminal to output a driving signal under control of potentials of the fourth node and the second node.

[0033] A positive projection of an active pattern of at least one transistor of the output circuit on the substrate at least partially overlaps a positive projection of the second voltage line on the substrate.

[0034] In at least one embodiment of the present disclosure, the plurality of signal lines include a first starting voltage line.

[0035] The driving circuit includes an output circuit; the output circuit is electrically connected with the fourth node, the second node and a driving output terminal respectively, and is configured to control the driving output terminal to output a driving signal under control of potentials of the fourth node and the second node.

[0036] A positive projection of an active pattern of at least one transistor of the output circuit on the substrate at least partially overlaps a positive projection of the first starting voltage line on the substrate.

[0037] In at least one embodiment of the present disclosure, the plurality of signal lines include a second starting voltage line and a third starting voltage line.

[0038] The driving circuit includes a fourth node control circuit; the fourth node control circuit is electrically connected with the first node, the fourth node and a second clock signal line respectively, and is configured to control the fourth node to communicate with the second clock signal line under control of a potential of the first node.

[0039] At least part of an active pattern of at least one transistor of the fourth node control circuit is arranged between a positive projection of the second starting voltage line on the substrate and a positive projection of the third starting voltage line on the substrate.

[0040] In at least one embodiment of the present disclosure, the plurality of signal lines comprises an initial voltage line; the driving circuit comprises a first energy storage circuit and a second energy storage circuit; the first energy storage circuit is electrically connected with the second node and the driving output end respectively, and is configured to control the electric potential of the second node according to a driving signal provided by the driving output end; and the second energy storage circuit is configured to maintain the electric potential of the fourth node.

[0041] The first energy storage circuit comprises a capacitor, and a normal projection of a plate of the capacitor on a substrate at least partially overlaps a normal projection of the initial voltage line on the substrate.

[0042] The second energy storage circuit comprises a capacitor, and a normal projection of a plate of the capacitor on a substrate at least partially overlaps a normal projection of the initial voltage line on the substrate.

[0043] In at least one embodiment of the present disclosure, the driving circuit comprises a first node control circuit, and the first node control circuit comprises a first transistor.

[0044] The gate of the first transistor is integrally formed with a first connecting part.

[0045] The first connecting part and a second connecting part are arranged in different layers, and the first connecting part is electrically connected with the second connecting part.

[0046] The second connecting part is electrically connected with a first column of clock signal lines, and the second connecting part is arranged in a different layer from the first column of clock signal lines.

[0047] In at least one embodiment of the present disclosure, the driving circuit comprises a fourth node control circuit, and the fourth node control circuit comprises a second transistor and a third transistor.

[0048] The first electrode of the second transistor is electrically connected with a third connecting part, the third connecting part is arranged in a different layer from a second column of clock signal lines, and the third connecting part is electrically connected with the second column of clock signal lines.

[0049] The gate of the third transistor is integrally formed with a fourth connecting part, and the fourth connecting part is electrically connected with the third connecting part.

[0050] In at least one embodiment of the present disclosure, the driving circuit comprises a first node control circuit and an output circuit, the first node control circuit comprises a seventh transistor, and the output circuit comprises a fifth transistor.

[0051] The gate of the seventh transistor is integrally formed with a fifth connecting part, the fifth connecting part is arranged in a different layer from a third clock signal line, and the fifth connecting part is electrically connected with the third clock signal line.

[0052] The second electrode of the fifth transistor is arranged in a layer different from the fifth connection part, and the second electrode of the fifth transistor is electrically connected with the fifth connection part.

[0053] In at least one embodiment of the present disclosure, the input end of the nth-stage driving circuit included in the driving module is electrically connected with the driving output end of the n-mth-stage driving circuit, m is a positive integer; and n is an integer greater than m.

[0054] The input end of the first m-stage driving circuit included in the driving module is electrically connected with the first starting voltage line.

[0055] In at least one embodiment of the present disclosure, m is equal to 2; the driving output end of the a-th-stage driving circuit included in the driving module is electrically connected with the input end of the a+2-th-stage driving circuit; a is a positive integer; and the display substrate includes two-stage virtual driving circuits.

[0056] The input end of the first-stage virtual driving circuit and the input end of the second-stage virtual driving circuit are both electrically connected with the first starting voltage line.

[0057] The driving output end of the first-stage virtual driving circuit is electrically connected with the input end of the first-stage driving circuit included in the driving module.

[0058] The driving output end of the second-stage virtual driving circuit is electrically connected with the input end of the second-stage driving circuit included in the driving module.

[0059] In at least one embodiment of the present disclosure, m is equal to 2; the driving output end of the a-th-stage driving circuit included in the driving module is electrically connected with the input end of the a+2-th-stage driving circuit; a is a positive integer; and the display substrate includes one-stage virtual driving circuit.

[0060] The input end of the virtual driving circuit is electrically connected with the first starting voltage line.

[0061] The input end of the first-stage driving circuit included in the driving module is electrically connected with the first starting voltage line.

[0062] The input end of the second-stage driving circuit included in the driving module is electrically connected with the driving output end of the virtual driving circuit.

[0063] In at least one embodiment of the present disclosure, the plurality of signal lines includes four columns of clock signal lines.

[0064] The first clock signal line of the 4b-3th-stage driving circuit included in the driving module is electrically connected with the first column of clock signal lines, the second clock signal line of the 4b-3th-stage driving circuit included in the driving module is electrically connected with the second column of clock signal lines, and the third clock signal line of the 4b-3th-stage driving circuit included in the driving module is electrically connected with the third column of clock signal lines.

[0065] The first clock signal line of the fourth 4b-2 driving circuit included in the driving module is electrically connected with the second column clock signal line, the second clock signal line of the fourth 4b-2 driving circuit included in the driving module is electrically connected with the third column clock signal line, and the fourth clock signal line of the fourth 4b-2 driving circuit included in the driving module is electrically connected with the third column clock signal line.

[0066] The first clock signal line of the fourth 4b-1 driving circuit included in the driving module is electrically connected with the third column clock signal line, the second clock signal line of the fourth 4b-1 driving circuit included in the driving module is electrically connected with the fourth column clock signal line, and the third clock signal line of the fourth 4b-1 driving circuit included in the driving module is electrically connected with the first column clock signal line.

[0067] The first clock signal line of the fourth 4b driving circuit included in the driving module is electrically connected with the fourth column clock signal line, the second clock signal line of the fourth 4b driving circuit included in the driving module is electrically connected with the first column clock signal line, and the third clock signal line of the fourth 4b driving circuit included in the driving module is electrically connected with the second column clock signal line.

[0068] b is a positive integer.

[0069] In a second aspect, the display substrate is provided. BRIEF DESCRIPTION OF DRAWINGS

[0070] FIG. 1 is a structural diagram of at least one embodiment of the driving circuit in at least one embodiment of the present disclosure;

[0071] FIG. 2 is a circuit diagram of at least one embodiment of the driving circuit;

[0072] FIG. 3 is a circuit diagram of a four-stage driving circuit included in the display substrate in at least one embodiment of the present disclosure;

[0073] FIG. 4 is a circuit diagram of at least one embodiment of the driving circuit;

[0074] FIG. 5 is a layout diagram of the display substrate in at least one embodiment of the present disclosure;

[0075] FIG. 6 is a layout diagram of a semiconductor layer in FIG. 5;

[0076] FIG. 7 is a layout diagram of a first gate metal layer in FIG. 5;

[0077] FIG. 8 is a layout diagram of a second gate metal layer in FIG. 5;

[0078] FIG. 9 is a layout diagram of a first source-drain metal layer in FIG. 5;

[0079] FIG. 10 is a layout diagram of a second source-drain metal layer in FIG. 5;

[0080] FIG. 11 is a cross-sectional view of the semiconductor layer and the first gate metal layer in FIG. 5;

[0081] FIG. 12 is a cross-sectional view of the first gate metal layer and the second gate metal layer in FIG. 5;

[0082] FIG. 13 is a cross-sectional view of the second gate metal layer and the first source-drain metal layer;

[0083] FIG. 14 is a cross-sectional view of the first source-drain metal layer and the second source-drain metal layer;

[0084] FIG. 15 is a layout view of a display substrate according to at least one embodiment of the present disclosure;

[0085] FIG. 16 is a layout view of FIG. 15 with the anode layer removed;

[0086] FIG. 17 is a layout view of the semiconductor layer in FIG. 15;

[0087] FIG. 18 is a layout view of the first gate metal layer in FIG. 15;

[0088] FIG. 19 is a layout view of the second gate metal layer in FIG. 15;

[0089] FIG. 20 is a layout view of the first source-drain metal layer in FIG. 15;

[0090] FIG. 21 is a layout view of the second source-drain metal layer in FIG. 15;

[0091] FIG. 22 is a layout view of the anode layer in FIG. 15;

[0092] FIG. 23 is a layout view of the semiconductor layer and the first gate metal layer in FIG. 15;

[0093] FIG. 24 is a layout view of the first gate metal layer and the second gate metal layer in FIG. 15;

[0094] FIG. 25 is a layout view of the first source-drain metal layer and the second source-drain metal layer in FIG. 15;

[0095] FIG. 26 is a layout view of the second source-drain metal layer and the anode layer in FIG. 15;

[0096] FIGS. 27A, 27B, and 27C are layout views of a display substrate according to at least one embodiment of the present disclosure;

[0097] FIG. 28 is a layout view of the semiconductor layer in FIG. 27A;

[0098] FIG. 29 is a layout view of the first gate metal layer in FIG. 27A;

[0099] FIG. 30 is a layout view of the second gate metal layer in FIG. 27A;

[0100] FIG. 31 is a layout view of the first source-drain metal layer in FIG. 27A;

[0101] FIG. 32 is a layout view of the second source-drain metal layer in FIG. 27A;

[0102] FIG. 33 is a cross-sectional view of the semiconductor layer and the first gate metal layer in FIG. 27A;

[0103] FIG. 34 is a layout view of the first gate metal layer and the second gate metal layer in FIG. 27A;

[0104] FIG. 35 is a layout view of the second gate metal layer and the first source-drain metal layer in FIG. 27A;

[0105] FIG. 36 is a layout view of the first source-drain metal layer and the second source-drain metal layer in FIG. 27A;

[0106] FIG. 37 is a layout view of a display substrate according to at least one embodiment of the present disclosure;

[0107] FIG. 38 is a layout view of the semiconductor layer in FIG. 37;

[0108] FIG. 39 is a layout view of the first gate metal layer in FIG. 37;

[0109] FIG. 40 is a layout view of the second gate metal layer in FIG. 37;

[0110] FIG. 41 is a layout view of the first source-drain metal layer in FIG. 37;

[0111] FIG. 42 is a layout view of the second source-drain metal layer in FIG. 37;

[0112] FIG. 43 is a cross-sectional view of the semiconductor layer and the first gate metal layer in FIG. 37;

[0113] FIG. 44 is a cross-sectional view of the first gate metal layer and the second gate metal layer in FIG. 37;

[0114] FIG. 45 is a cross-sectional view of the second gate metal layer and the first source-drain metal layer in FIG. 37;

[0115] FIG. 46 is a cross-sectional view of the first source-drain metal layer and the second source-drain metal layer in FIG. 37;

[0116] FIG. 47 is a layout view of a display substrate according to at least one embodiment of the present disclosure;

[0117] FIG. 48 is a layout view of the semiconductor layer in FIG. 47;

[0118] FIG. 49 is a layout view of the first gate metal layer in FIG. 47;

[0119] FIG. 50 is a layout view of the second gate metal layer in FIG. 47;

[0120] FIG. 51 is a layout diagram of the first source-drain metal layer in FIG. 47;

[0121] FIG. 52 is a layout diagram of the second source-drain metal layer in FIG. 47;

[0122] FIG. 53 is a layout diagram of the semiconductor layer and the first gate metal layer in FIG. 47;

[0123] FIG. 54 is a layout diagram of the first gate metal layer and the second gate metal layer in FIG. 47;

[0124] FIG. 55 is a layout diagram of the second gate metal layer and the first source-drain metal layer in FIG. 47;

[0125] FIG. 56 is a layout diagram of the first source-drain metal layer and the second source-drain metal layer in FIG. 47;

[0126] FIG. 57 is a layout diagram of a display substrate according to at least one embodiment of the present disclosure;

[0127] FIG. 58 is a layout diagram of the semiconductor layer in FIG. 57;

[0128] FIG. 59 is a layout diagram of the first gate metal layer in FIG. 57;

[0129] FIG. 60 is a layout diagram of the second gate metal layer in FIG. 57;

[0130] FIG. 61 is a layout diagram of the first source-drain metal layer in FIG. 57;

[0131] FIG. 62 is a layout diagram of the second source-drain metal layer in FIG. 57;

[0132] FIG. 63 is a layout diagram of the semiconductor layer and the first gate metal layer in FIG. 57;

[0133] FIG. 64 is a layout diagram of the first gate metal layer and the second gate metal layer in FIG. 57;

[0134] FIG. 65 is a layout diagram of the second gate metal layer and the first source-drain metal layer in FIG. 57;

[0135] FIG. 66 is a layout diagram of the first source-drain metal layer and the second source-drain metal layer in FIG. 57;

[0136] FIG. 67 is a layout diagram of a display substrate according to at least one embodiment of the present disclosure;

[0137] FIG. 68 is a layout diagram of the semiconductor layer in FIG. 67;

[0138] FIG. 69 is a layout diagram of the first gate metal layer in FIG. 67;

[0139] FIG. 70 is a layout diagram of the second gate metal layer in FIG. 67;

[0140] FIG. 71 is a layout view of the first source-drain metal layer in FIG. 67;

[0141] FIG. 72 is a layout view of the second source-drain metal layer in FIG. 67;

[0142] FIG. 73 is a layout view of the semiconductor layer and the first gate metal layer in FIG. 67;

[0143] FIG. 74 is a layout view of the first gate metal layer and the second gate metal layer in FIG. 67;

[0144] FIG. 75 is a layout view of the second gate metal layer and the first source-drain metal layer in FIG. 67;

[0145] FIG. 76 is a layout view of the first source-drain metal layer and the second source-drain metal layer in FIG. 67;

[0146] FIG. 77 is a timing diagram of the clock signal provided by the first column clock signal line CLK1, the clock signal provided by the second column clock signal line CLK2, the clock signal provided by the third column clock signal line CLK3, and the clock signal provided by the fourth column clock signal line CLK4. DETAILED DESCRIPTION

[0147] The technical solutions in the embodiments of the present disclosure will be clearly and completely described below with reference to the drawings in the embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, rather than all the embodiments. Based on the embodiments in the present disclosure, all other embodiments obtained by those skilled in the art without creative labor fall within the scope of protection of the present disclosure.

[0148] The transistors used in all the embodiments of the present disclosure can be thin film transistors or field effect transistors or other devices with the same characteristics. In the embodiments of the present disclosure, to distinguish the two electrodes of the transistor other than the gate, one electrode is referred to as the first electrode and the other electrode is referred to as the second electrode.

[0149] In actual operation, when the transistor is a thin film transistor or a field effect transistor, the first electrode can be a drain electrode and the second electrode can be a source electrode; or the first electrode can be a source electrode and the second electrode can be a drain electrode.

[0150] The display substrate described in the embodiments of the present disclosure includes a substrate and a driving module disposed on the substrate, the driving module includes a multi-stage driving circuit; the driving circuit includes a plurality of devices, the devices include transistors and capacitors; the display substrate further includes a plurality of signal lines disposed on the substrate, the plurality of signal lines include at least three clock signal lines;

[0151] The normal projection of the signal line on the substrate at least partially overlaps the normal projection of at least one of the devices on the substrate.

[0152] At least one transistor in at least two-stage driving circuit included in the driving module is electrically connected with at least one transistor in other-stage driving circuit through corresponding clock signal line.

[0153] In at least one embodiment of the present disclosure, the at least three clock signal lines are arranged longitudinally above the driving circuit, so that the at least three clock signal lines can be arranged without increasing the horizontal space, which is conducive to realizing narrow frame.

[0154] In the specific implementation, in the at least two-stage driving circuit included in the driving module, at least one transistor is electrically connected with at least one transistor in other-stage driving circuit through corresponding clock signal line, so as to reduce the first source-drain metal trace when cascading the clock signals of the upper and lower-stage driving circuits (especially when cascading the upper and lower stages at the round corner position), while ensuring the loading consistency of the straight edge and the round corner position when accessing the clock signal, and optimizing the layout space.

[0155] In at least one embodiment of the present disclosure, at least one transistor in each-stage driving circuit in the driving module is electrically connected with at least one transistor in other-stage driving circuit through corresponding clock signal line.

[0156] As shown in FIG. 1, in at least one embodiment of the present disclosure, at least one embodiment of the driving circuit includes input circuit 11, second node control circuit 12, first node control circuit 10, third node control circuit 13, fourth node control circuit 14, output circuit 15, first energy storage circuit 21 and second energy storage circuit 22.

[0157] The input circuit 11 is electrically connected with the first clock signal line CK1, the input terminal I1 and the first node N1 respectively, and is used to control the potential of the first node N1 according to the input signal provided by the input terminal I1 under the control of the first clock signal provided by the first clock signal line CK1.

[0158] The second node control circuit 12 is electrically connected with the first voltage line V1, the first node N1 and the second node N2 respectively, and is used to control the communication between the first node N1 and the second node N2 under the control of the first voltage signal provided by the first voltage line V1.

[0159] The first node control circuit 10 is electrically connected with the third clock signal line CK3, the third node N3 and the first node N1 respectively, and is used to control the communication between the third node N3 and the first node N1 under the control of the third clock signal provided by the third clock signal line CK3.

[0160] The third node control circuit 13 is electrically connected with the fourth node N4, the second voltage line V2 and the third node N3 respectively, and is configured to write a second voltage signal provided by the second voltage line V2 into the third node N3 under control of a potential of the fourth node N4;

[0161] The fourth node control circuit 14 is electrically connected with the first node N1, the fourth node N4, the second clock signal line CK2 and the first voltage line V1 respectively, and is configured to control communication between the fourth node N4 and the second clock signal line CK2 under control of a potential of the first node N1, and control communication between the fourth node N4 and the first voltage line V1 under control of a second clock signal provided by the second clock signal line CK2;

[0162] The output circuit 15 is electrically connected with the fourth node N4, the second node N2 and the driving output terminal GT respectively, and is configured to control the driving output terminal GT to output a driving signal under control of potentials of the fourth node N4 and the second node N2.

[0163] The first energy storage circuit 21 is electrically connected with the second node N2 and the driving output terminal GT respectively, and is configured to control a potential of the second node N2 according to a driving signal provided by the driving output terminal GT.

[0164] The second energy storage circuit 22 is electrically connected with the fourth node N4, and is configured to maintain a potential of the fourth node N4.

[0165] In at least one embodiment of the present disclosure, the first voltage line can be a low voltage line, and the second voltage line can be a high voltage line.

[0166] As shown in FIG. 2, on the basis of at least one embodiment of the driving circuit shown in FIG. 1, the input circuit comprises a first transistor T1.

[0167] The gate of the T1 is electrically connected with the first clock signal line CK1, the first electrode of the T1 is electrically connected with the input terminal I1, and the second electrode of the T1 is electrically connected with the first node N1.

[0168] The fourth node control circuit comprises a second transistor T2 and a third transistor T3.

[0169] The gate of the T2 is electrically connected with the first node N1, the first electrode of the T2 is electrically connected with the second clock signal line CK2, and the second electrode of the T2 is electrically connected with the fourth node N4.

[0170] The gate of the T3 is electrically connected with the second clock signal line CK2, the first electrode of the T3 is electrically connected with the low voltage line VGL, and the second electrode of the T3 is electrically connected with the fourth node N4.

[0171] The output circuit comprises a fourth transistor T4 and a fifth transistor T5;

[0172] The gate of the fourth transistor T4 is electrically connected with the fourth node N4, the first electrode of the fourth transistor T4 is electrically connected with the high voltage line VGH, and the second electrode of the fourth transistor T4 is electrically connected with the driving output end GT;

[0173] The gate of the fifth transistor T5 is electrically connected with the second node N2, the first electrode of the fifth transistor T5 is electrically connected with the driving output end GT, and the second electrode of the fifth transistor T5 is electrically connected with the third clock signal end CK3;

[0174] The third node control circuit comprises a sixth transistor T6;

[0175] The gate of the sixth transistor T6 is electrically connected with the fourth node N4, the first electrode of the sixth transistor T6 is electrically connected with the high voltage line VGH, and the second electrode of the sixth transistor T6 is electrically connected with the third node N3;

[0176] The first node control circuit comprises a seventh transistor T7;

[0177] The gate of the seventh transistor T7 is electrically connected with the third clock signal line CK3, the first electrode of the seventh transistor T7 is electrically connected with the third node N3, and the second electrode of the seventh transistor T7 is electrically connected with the first node N1;

[0178] The second node control circuit comprises an eighth transistor T8;

[0179] The gate of the eighth transistor T8 is electrically connected with the low voltage line VGL, the first electrode of the eighth transistor T8 is electrically connected with the first node N1, and the second electrode of the eighth transistor T8 is electrically connected with the second node N2;

[0180] The first energy storage circuit comprises a first capacitor C1, and the second energy storage circuit comprises a second capacitor C2;

[0181] The first plate of the first capacitor C1 is electrically connected with the second node N2, and the second plate of the first capacitor C1 is electrically connected with the driving output end GT;

[0182] The first plate of the second capacitor C2 is electrically connected with the fourth node N4, and the second plate of the second capacitor C2 is electrically connected with the high voltage line VGH.

[0183] In at least one embodiment of the driving circuit shown in FIG. 2, all the transistors are p-type transistors.

[0184] As shown in FIG. 3, the display substrate according to at least one embodiment of the present disclosure can comprise a first column of clock signal lines CLK1, a second column of clock signal lines CLK2, a third column of clock signal lines CLK3, and a fourth column of clock signal lines CLK4;

[0185] The first-stage driving circuit P1 comprises a first first transistor T11, a first second transistor T12, a first third transistor T13, a first fourth transistor T14, a first fifth transistor T15, a first sixth transistor T16, a first seventh transistor T17, a first eighth transistor T18, a first first capacitor C11 and a first second capacitor C12;

[0186] The gate of the T11 is electrically connected with the first column clock signal line CLK1, the first electrode of the T11 is electrically connected with the first input end I11, and the second electrode of the T11 is electrically connected with the first first node N11;

[0187] The gate of the T12 is electrically connected with the first first node N11, the first electrode of the T12 is electrically connected with the second column clock signal line CLK2, and the second electrode of the T12 is electrically connected with the first fourth node N14;

[0188] The gate of the T13 is electrically connected with the second column clock signal line CLK2, the first electrode of the T13 is electrically connected with the low-voltage line VGL, and the second electrode of the T13 is electrically connected with the first fourth node N14;

[0189] The gate of the T14 is electrically connected with the first fourth node N14, the first electrode of the T14 is electrically connected with the high-voltage line VGH, and the second electrode of the T14 is electrically connected with the first driving output end GT1;

[0190] The gate of the T15 is electrically connected with the first second node N12, the first electrode of the T15 is electrically connected with the first driving output end GT1, and the second electrode of the T15 is electrically connected with the third column clock signal end CLK3;

[0191] The gate of the T16 is electrically connected with the first fourth node N14, the first electrode of the T16 is electrically connected with the high-voltage line VGH, and the second electrode of the T16 is electrically connected with the first third node N13;

[0192] The gate of the T17 is electrically connected with the third column clock signal line CLK3, the first electrode of the T17 is electrically connected with the first third node N13, and the second electrode of the T17 is electrically connected with the first first node N11;

[0193] The gate of the T18 is electrically connected with the low-voltage line VGL, the first electrode of the T18 is electrically connected with the first first node N11, and the second electrode of the T18 is electrically connected with the first second node N12;

[0194] The first plate of the C11 is electrically connected with the first second node N12, and the second plate of the C11 is electrically connected with the first driving output end GT1;

[0195] The first pole plate of C12 is electrically connected with the first fourth node N14, and the second pole plate of C12 is electrically connected with the high voltage line VGH;

[0196] The second stage driving circuit P2 comprises a second first transistor T21, a second second transistor T22, a second third transistor T23, a second fourth transistor T24, a second fifth transistor T25, a second sixth transistor T26, a second seventh transistor T27, a second eighth transistor T28, a second first capacitor C21 and a second second capacitor C22;

[0197] The gate of T21 is electrically connected with the second column clock signal line CLK2, the first electrode of T21 is electrically connected with the second input end I12, and the second electrode of T21 is electrically connected with the second first node N21;

[0198] The gate of T22 is electrically connected with the second first node N21, the first electrode of T22 is electrically connected with the third column clock signal line CLK3, and the second electrode of T22 is electrically connected with the second fourth node N24;

[0199] The gate of T23 is electrically connected with the third column clock signal line CLK3, the first electrode of T23 is electrically connected with the low voltage line VGL, and the second electrode of T23 is electrically connected with the second fourth node N24;

[0200] The gate of T24 is electrically connected with the second fourth node N24, the first electrode of T24 is electrically connected with the high voltage line VGH, and the second electrode of T24 is electrically connected with the second driving output end GT2;

[0201] The gate of T25 is electrically connected with the second second node N22, the first electrode of T25 is electrically connected with the second driving output end GT2, and the second electrode of T25 is electrically connected with the fourth column clock signal end CLK4;

[0202] The gate of T26 is electrically connected with the second fourth node N24, the first electrode of T26 is electrically connected with the high voltage line VGH, and the second electrode of T26 is electrically connected with the second third node N23;

[0203] The gate of T27 is electrically connected with the fourth column clock signal line CLK4, the first electrode of T27 is electrically connected with the second third node N23, and the second electrode of T27 is electrically connected with the second first node N21;

[0204] The gate of T28 is electrically connected with the low voltage line VGL, the first electrode of T28 is electrically connected with the second first node N21, and the second electrode of T28 is electrically connected with the second second node N22;

[0205] The first electrode plate of the C21 is electrically connected with the second node N22, and the second electrode plate of the C21 is electrically connected with the second driving output terminal GT2;

[0206] The first electrode plate of the C22 is electrically connected with the fourth node N24, and the second electrode plate of the C22 is electrically connected with the high voltage line VGH;

[0207] The third driving circuit P3 comprises a third first transistor T31, a third second transistor T32, a third third transistor T33, a third fourth transistor T34, a third fifth transistor T35, a third sixth transistor T36, a third seventh transistor T37, a third eighth transistor T38, a third first capacitor C31 and a third second capacitor C32;

[0208] The gate of the T31 is electrically connected with the third clock signal line CLK3, the first electrode of the T31 is electrically connected with the third input terminal I13, and the second electrode of the T31 is electrically connected with the third node N31.

[0209] The gate of the T32 is electrically connected with the third node N31, the first electrode of the T32 is electrically connected with the fourth clock signal line CLK4, and the second electrode of the T32 is electrically connected with the fourth node N34.

[0210] The gate of the T33 is electrically connected with the fourth clock signal line CLK4, the first electrode of the T33 is electrically connected with the low voltage line VGL, and the second electrode of the T33 is electrically connected with the fourth node N34.

[0211] The gate of the T34 is electrically connected with the fourth node N34, the first electrode of the T34 is electrically connected with the high voltage line VGH, and the second electrode of the T34 is electrically connected with the third driving output terminal GT3.

[0212] The gate of the T35 is electrically connected with the second node N32, the first electrode of the T35 is electrically connected with the third driving output terminal GT3, and the second electrode of the T35 is electrically connected with the first clock signal line CLK1.

[0213] The gate of the T36 is electrically connected with the fourth node N34, the first electrode of the T36 is electrically connected with the high voltage line VGH, and the second electrode of the T36 is electrically connected with the third node N33.

[0214] The gate of the T37 is electrically connected with the first clock signal line CLK1, the first electrode of the T37 is electrically connected with the third node N33, and the second electrode of the T37 is electrically connected with the third node N31.

[0215] The gate of the T38 is electrically connected with the low voltage line VGL, the first electrode of the T38 is electrically connected with the third first node N31, and the second electrode of the T38 is electrically connected with the third second node N32;

[0216] The first plate of the C31 is electrically connected with the third second node N32, and the second plate of the C31 is electrically connected with the third driving output end GT3;

[0217] The first plate of the C32 is electrically connected with the third fourth node N34, and the second plate of the C32 is electrically connected with the high voltage line VGH;

[0218] The fourth driving circuit P4 comprises a fourth first transistor T41, a fourth second transistor T42, a fourth third transistor T43, a fourth fourth transistor T44, a fourth fifth transistor T45, a fourth sixth transistor T46, a fourth seventh transistor T47, a fourth eighth transistor T48, a fourth first capacitor C41 and a fourth second capacitor C42;

[0219] The gate of the T41 is electrically connected with the fourth column clock signal line CLK4, the first electrode of the T41 is electrically connected with the fourth input end I14, and the second electrode of the T41 is electrically connected with the fourth first node N41;

[0220] The gate of the T42 is electrically connected with the fourth first node N41, the first electrode of the T42 is electrically connected with the first column clock signal line CLK1, and the second electrode of the T42 is electrically connected with the fourth fourth node N44;

[0221] The gate of the T43 is electrically connected with the first column clock signal line CLK1, the first electrode of the T43 is electrically connected with the low voltage line VGL, and the second electrode of the T43 is electrically connected with the fourth fourth node N44;

[0222] The gate of the T44 is electrically connected with the fourth fourth node N44, the first electrode of the T44 is electrically connected with the high voltage line VGH, and the second electrode of the T44 is electrically connected with the fourth driving output end GT4;

[0223] The gate of the T45 is electrically connected with the fourth second node N42, the first electrode of the T45 is electrically connected with the fourth driving output end GT4, and the second electrode of the T45 is electrically connected with the second column clock signal end CLK2;

[0224] The gate of the T46 is electrically connected with the fourth fourth node N44, the first electrode of the T46 is electrically connected with the high voltage line VGH, and the second electrode of the T46 is electrically connected with the fourth third node N43;

[0225] The gate of the T47 is electrically connected with the second clock signal line CLK2, the first electrode of the T47 is electrically connected with the fourth third node N43, and the second electrode of the T47 is electrically connected with the fourth first node N41;

[0226] The gate of the T48 is electrically connected with the low voltage line VGL, the first electrode of the T48 is electrically connected with the fourth first node N41, and the second electrode of the T48 is electrically connected with the fourth second node N42;

[0227] The first plate of the C41 is electrically connected with the fourth second node N42, and the second plate of the C41 is electrically connected with the fourth drive output end GT4;

[0228] The first plate of the C42 is electrically connected with the fourth fourth node N44, and the second plate of the C42 is electrically connected with the high voltage line VGH.

[0229] In at least one embodiment shown in FIG. 3, all the transistors are p-type transistors.

[0230] As shown in FIG. 3, in the first stage drive circuit, the gate of the T11 is electrically connected with CLK1, the first electrode of the T12 and the gate of the T13 are electrically connected with CLK2, and the gate of the T17 and the second electrode of the T15 are electrically connected with CLK3;

[0231] In the second stage drive circuit, the gate of the T21 is electrically connected with CLK2, the first electrode of the T22 and the gate of the T23 are electrically connected with CLK3, and the gate of the T27 and the second electrode of the T25 are electrically connected with CLK4;

[0232] In the third stage drive circuit, the gate of the T31 is electrically connected with CLK3, the first electrode of the T32 and the gate of the T33 are electrically connected with CLK4, and the gate of the T37 and the second electrode of the T35 are electrically connected with CLK1;

[0233] In the fourth stage drive circuit, the gate of the T41 is electrically connected with CLK4, the first electrode of the T42 and the gate of the T43 are electrically connected with CLK1, and the gate of the T47 and the second electrode of the T45 are electrically connected with CLK2;

[0234] One cycle of the four-stage drive circuit can reduce the toggle times, thereby reducing the power consumption of the clock signal line.

[0235] As shown in FIG. 4, in at least one embodiment of the drive circuit, the input circuit comprises a first transistor T1;

[0236] The gate of the T1 is electrically connected with the first clock signal line CLK1, the first electrode of the T1 is electrically connected with the input end I1, and the second electrode of the T1 is electrically connected with the first node N1;

[0237] The fourth node control circuit comprises a second transistor T2 and a third transistor T3;

[0238] The gate of the T2 is electrically connected with the first node N1, the first electrode of the T2 is electrically connected with the second column clock signal line CLK2, and the second electrode of the T2 is electrically connected with the fourth node N4;

[0239] The gate of the T3 is electrically connected with the second column clock signal line CLK2, the first electrode of the T3 is electrically connected with the low voltage line VGL, and the second electrode of the T3 is electrically connected with the fourth node N4;

[0240] The output circuit comprises a fourth transistor T4 and a fifth transistor T5;

[0241] The gate of the T4 is electrically connected with the fourth node N4, the first electrode of the T4 is electrically connected with the high voltage line VGH, and the second electrode of the T4 is electrically connected with the driving output end GT;

[0242] The gate of the T5 is electrically connected with the second node N2, the first electrode of the T5 is electrically connected with the driving output end GT, and the second electrode of the T5 is electrically connected with the third column clock signal end CLK3;

[0243] The third node control circuit comprises a sixth transistor T6;

[0244] The gate of the T6 is electrically connected with the fourth node N4, the first electrode of the T6 is electrically connected with the high voltage line VGH, and the second electrode of the T6 is electrically connected with the third node N3;

[0245] The first node control circuit comprises a seventh transistor T7;

[0246] The gate of the T7 is electrically connected with the third column clock signal line CLK3, the first electrode of the T7 is electrically connected with the third node N3, and the second electrode of the T7 is electrically connected with the first node N1;

[0247] The second node control circuit comprises an eighth transistor T8;

[0248] The gate of the T8 is electrically connected with the low voltage line VGL, the first electrode of the T8 is electrically connected with the first node N1, and the second electrode of the T8 is electrically connected with the second node N2;

[0249] The first energy storage circuit comprises a first capacitor C1, and the second energy storage circuit comprises a second capacitor C2;

[0250] The first plate of the C1 is electrically connected with the second node N2, and the second plate of the C1 is electrically connected with the driving output end GT;

[0251] The first plate of the C2 is electrically connected with the fourth node N4, and the second plate of the C2 is electrically connected with the high voltage line VGH.

[0252] FIG. 5 is a layout of a display substrate according to at least one embodiment of the present disclosure, FIG. 6 is a layout of a semiconductor layer in FIG. 5, FIG. 7 is a layout of a first gate metal layer in FIG. 5, FIG. 8 is a layout of a second gate metal layer in FIG. 5, FIG. 9 is a layout of a first source-drain metal layer in FIG. 5, and FIG. 10 is a layout of a second source-drain metal layer in FIG. 5;

[0253] FIG. 11 is a cross-sectional view of the semiconductor layer and the first gate metal layer in FIG. 5, FIG. 12 is a cross-sectional view of the first gate metal layer and the second gate metal layer in FIG. 5, FIG. 13 is a cross-sectional view of the second gate metal layer and the first source-drain metal layer, and FIG. 14 is a cross-sectional view of the first source-drain metal layer and the second source-drain metal layer;

[0254] In FIG. 5, the structure of the driving circuit included in the display substrate is as shown in FIG. 4.

[0255] In at least one embodiment of the present disclosure, the driving circuit includes an input circuit; the input circuit is electrically connected with a first clock signal line, an input terminal and a first node respectively, and is configured to control the electric potential of the first node according to an input signal provided by the input terminal under the control of a first clock signal provided by the first clock signal line.

[0256] The orthographic projection of the active pattern of at least one transistor included in the input circuit on the substrate at least partially overlaps the orthographic projection of the first column of clock signal lines on the substrate.

[0257] The orthographic projection of the active pattern of at least one transistor included in the input circuit on the substrate at least partially overlaps the orthographic projection of the second column of clock signal lines on the substrate.

[0258] As shown in FIG. 5, the input circuit includes a first transistor T1.

[0259] As shown in FIGS. 5-14, the orthographic projection of the active pattern A1 of T1 on the substrate at least partially overlaps the orthographic projection of the first column of clock signal lines CLK1 on the substrate.

[0260] The orthographic projection of the active pattern A1 of T1 on the substrate at least partially overlaps the orthographic projection of the second column of clock signal lines CLK2 on the substrate.

[0261] With the above arrangement, the horizontal space can be saved, which is conducive to realizing a narrow frame.

[0262] As shown in FIGS. 5-14, T1 is a double-gate transistor, the label G11 is the first gate of T1, and the label G12 is the second gate of T1.

[0263] In at least one embodiment of the present disclosure, the driving circuit comprises a second node control circuit; the second node control circuit is electrically connected with the first voltage line, the first node and the second node respectively, and is configured to control the communication between the first node and the second node under the control of the first voltage signal provided by the first voltage line.

[0264] The active pattern of at least one transistor included in the second node control circuit at least partially overlaps the orthogonal projection of the second column of clock signal lines on the substrate.

[0265] In at least one embodiment of the present disclosure, the driving circuit comprises a first node control circuit; the first node control circuit is electrically connected with the third clock signal line, the third node and the first node respectively, and is configured to control the communication between the third node and the first node under the control of the third clock signal provided by the third clock signal line.

[0266] The active pattern of at least one transistor included in the first node control circuit at least partially overlaps the orthogonal projection of the third clock signal line on the substrate.

[0267] As shown in FIGS. 5-14, the driving circuit comprises a seventh transistor T7.

[0268] The active pattern A7 of T7 at least partially overlaps the orthogonal projection of the third column of clock signal lines CLK3 on the substrate, so as to save the horizontal space and facilitate the realization of narrow frame.

[0269] In at least one embodiment of the present disclosure, the driving circuit comprises a third node control circuit; the third node control circuit is electrically connected with the fourth node, the second voltage line and the third node respectively, and is configured to write the second voltage signal provided by the second voltage line into the third node under the control of the potential of the fourth node.

[0270] The orthogonal projection of the gate of at least one transistor included in the third node control circuit on the substrate is arranged between the orthogonal projection of the fourth column of clock signal lines on the substrate and the orthogonal projection of the first first level line on the substrate.

[0271] The first first level line is arranged on the side of the fourth column of clock signal lines close to the display area.

[0272] In at least one embodiment of the present disclosure, the first first level line can be a first low level line.

[0273] As shown in FIGS. 5-14, the third node control circuit comprises a sixth transistor T6.

[0274] The normal projection of the gate G6 of the T6 on the substrate is arranged between the normal projection of the fourth column clock signal line CLK4 on the substrate and the normal projection of the first low level line VSS1 on the substrate, so as to arrange the T6 by using the space between the CLK4 and the VSS1, and facilitate the realization of narrow frame;

[0275] The first low level line VSS1 is arranged on the side of the fourth column clock signal line CLK4 close to the display area.

[0276] The VSS1 and the CLK4 can be formed in the second source-drain metal layer.

[0277] In at least one embodiment of the present disclosure, the plurality of signal lines comprises a first first level line; the driving circuit comprises an output circuit; the output circuit is electrically connected with the fourth node, the second node and the driving output end respectively, and is used for controlling the driving output end to output a driving signal under the control of the potential of the fourth node and the potential of the second node.

[0278] The normal projection of the first first level line on the substrate at least partially overlaps with the normal projection of the active pattern of at least one transistor included in the output circuit on the substrate.

[0279] As shown in FIGS. 5-14, the output circuit comprises a fourth transistor T4 and a fifth transistor T5.

[0280] The normal projection of the first low level line VSS1 on the substrate at least partially overlaps with the normal projection of the active pattern A4 of the T4 on the substrate.

[0281] The normal projection of the first low level line VSS1 on the substrate at least partially overlaps with the normal projection of the active pattern A5 of the T5 on the substrate.

[0282] Through the above arrangement, the transverse space can be saved, and the realization of narrow frame is facilitated.

[0283] In FIG. 6, A1 is the active pattern of the T1, A2 is the active pattern of the T2, A3 is the active pattern of the T3, A4 is the active pattern of the T4, A51 is the active pattern of the T5, A6 is the active pattern of the T6, A7 is the active pattern of the T7, and A8 is the active pattern of the T8.

[0284] FIG. 15 is a layout of a display substrate according to at least one embodiment of the present disclosure, and FIG. 16 is a layout of FIG. 15 without an anode layer. FIG. 17 is a layout of a semiconductor layer in FIG. 15, FIG. 18 is a layout of a first gate metal layer in FIG. 15, FIG. 19 is a layout of a second gate metal layer in FIG. 15, FIG. 20 is a layout of a first source-drain metal layer in FIG. 15, FIG. 21 is a layout of a second source-drain metal layer in FIG. 15, and FIG. 22 is a layout of the anode layer in FIG. 15;

[0285] FIG. 23 is a layout of the semiconductor layer and the first gate metal layer in FIG. 15, FIG. 24 is a layout of the first gate metal layer and the second gate metal layer in FIG. 15, FIG. 25 is a layout of the first source-drain metal layer and the second source-drain metal layer in FIG. 15, and FIG. 26 is a layout of the second source-drain metal layer and the anode layer in FIG. 15;

[0286] In at least one embodiment shown in FIG. 15, the display substrate includes a driving circuit having a structure as shown in FIG. 4.

[0287] In at least one embodiment of the present disclosure, the plurality of signal lines further include a second first-level line; the driving circuit includes a fourth node control circuit; the fourth node control circuit is electrically connected with the first node, a second clock signal line and a fourth node respectively, and is configured to control communication between the second clock signal line and the fourth node under control of an electric potential of the first node; and the first first-level line is electrically connected with the second first-level line.

[0288] A normal projection of an active pattern of at least one transistor included in the fourth node control circuit on a substrate at least partially overlaps a normal projection of the second first-level line on the substrate.

[0289] In at least one embodiment of the present disclosure, the second first-level line can be a second low-level line.

[0290] As shown in FIGS. 15-26, the output circuit includes a fourth transistor T4 and a fifth transistor T5.

[0291] A normal projection of the first low-level line VSS1 on the substrate at least partially overlaps a normal projection of an active pattern A4 of T4 on the substrate; a normal projection of the first low-level line VSS1 on the substrate at least partially overlaps a normal projection of an active pattern A5 of T5 on the substrate; and the first low-level line VSS1 can be formed in the second source-drain metal layer.

[0292] With the above arrangement, transverse space can be saved, which is conducive to achieving a narrow frame.

[0293] The plurality of signal lines can further include a second low-level line VSS2; VSS1 and VSS2 are electrically connected through a first connection pattern LX1, VSS2 can be formed in a second source-drain metal layer, and LX1 can be formed in a first source-drain metal layer;

[0294] The fourth node control circuit includes a second transistor T2.

[0295] A positive projection of an active pattern A2 of T2 on a substrate at least partially overlaps a positive projection of VSS2 on the substrate, so as to save a horizontal space and facilitate narrow frame implementation.

[0296] In at least one embodiment of the present disclosure, the plurality of signal lines further includes a third first-level line; the second first-level line and the third first-level line are arranged in different layers; and the second first-level line and the third first-level line are electrically connected.

[0297] A positive projection of the second first-level line on the substrate at least partially overlaps a positive projection of the third first-level line on the substrate.

[0298] In at least one embodiment of the present disclosure, the third first-level line can be a third low-level line.

[0299] As shown in FIGS. 15-26, the plurality of signal lines can further include a third low-level line VSS3; VSS3 can be formed in an anode layer;

[0300] VSS2 is formed in a second source-drain metal layer, and VSS2 is electrically connected with VSS3;

[0301] A positive projection of VSS2 on the substrate at least partially overlaps a positive projection of VSS3 on the substrate.

[0302] Through the above arrangement, a horizontal space can be saved, and narrow frame implementation is facilitated.

[0303] As shown in FIGS. 15-26, the plurality of signal lines includes a first low-level line VSS1, a second low-level line VSS2, and a third low-level line VSS3, so as to be able to improve the area of the low-level line, reduce the resistance of the low-level line, and reduce the load and voltage drop on each low-level line.

[0304] As shown in FIGS. 5-26, the first low-level line VSS1 is arranged on a side of the fourth transistor away from the substrate, so as to shield signal interference through a direct-current signal and stabilize output.

[0305] In at least one embodiment of the present disclosure, the plurality of signal lines further includes a third first-level line and a first voltage line; the second first-level line and the third first-level line are electrically connected;

[0306] The third first-level line is at least partially overlapped with the first voltage line on the substrate.

[0307] As shown in FIGS. 15-26, the plurality of signal lines can further include a third low-level line VSS3 and a low-voltage line VGL.

[0308] The third low-level line VSS3 is at least partially overlapped with the low-voltage line VGL on the substrate to save lateral space and facilitate narrow frame implementation.

[0309] In at least one embodiment shown in FIGS. 15-26, the third first-level line is the third low-level line VSS3, and the first voltage line is the low-voltage line VGL.

[0310] In at least one embodiment of the present disclosure, the first first-level line, the second first-level line, and the third first-level line are all arranged in the peripheral region.

[0311] The first first-level line is electrically connected to the grid-shaped low-level traces arranged in the display region.

[0312] As shown in FIGS. 15-26, the first low-level line VSS1, the second low-level line VSS2, and the third low-level line VSS3 can all be arranged in the peripheral region.

[0313] VSS1 can be electrically connected to the grid-shaped low-level traces arranged in the display region, which can reduce the voltage drop and load of the low-level line.

[0314] In at least one embodiment of the present disclosure, the driving circuit includes a fourth node control circuit; the fourth node control circuit is electrically connected to the first node, the fourth node, the second clock signal line, and the first voltage line, respectively, for controlling the communication between the fourth node and the second clock signal line under the control of the potential of the first node, and controlling the communication between the fourth node and the first voltage line under the control of the second clock signal provided by the second clock signal line.

[0315] The active pattern of at least one transistor of the fourth node control circuit is at least partially overlapped with the second first-level line on the substrate.

[0316] The active pattern of at least one transistor of the fourth node control circuit is at least partially overlapped with the third first-level line on the substrate.

[0317] The active pattern of at least one transistor of the fourth node control circuit is at least partially overlapped with the first voltage line on the substrate.

[0318] As shown in FIGS. 15-26, the fourth node control circuit includes a second transistor T2 and a third transistor T3;

[0319] A positive projection of an active pattern A2 of T2 on the substrate at least partially overlaps a positive projection of the second low-level line VSS2 on the substrate;

[0320] A positive projection of an active pattern A3 of T3 on the substrate at least partially overlaps a positive projection of the third low-level line VSS3 on the substrate;

[0321] A positive projection of the active pattern A3 of T3 on the substrate at least partially overlaps a positive projection of the low-voltage line VGL on the substrate;

[0322] By the above arrangement, lateral space can be saved, facilitating narrow frame implementation.

[0323] In FIG. 17, A2 is an active pattern of T2, A3 is an active pattern of T3, A4 is an active pattern of T4, and A5 is an active pattern of T5.

[0324] In FIG. 18, C1a is a first plate of C1, and C2a is a first plate of C2.

[0325] In FIG. 19, C1b is a second plate of C1, and C2b is a second plate of C2.

[0326] In FIG. 20, L0 is a lead, and VSS2 is electrically connected to VSS1 through L0.

[0327] In at least one embodiment of the present disclosure, the plurality of signal lines includes a second voltage line; the driving circuit includes an output circuit; the output circuit is electrically connected to the fourth node, the second node, and the driving output end, respectively, and is configured to control the driving output end to output a driving signal under control of potentials of the fourth node and the second node.

[0328] A positive projection of an active pattern of at least one transistor included in the output circuit on the substrate at least partially overlaps a positive projection of the second voltage line on the substrate.

[0329] As shown in FIGS. 5-14, the plurality of signal lines includes a high-voltage line VGH;

[0330] The output circuit includes a fourth transistor T4 and a fifth transistor T5;

[0331] A positive projection of an active pattern A4 of T4 on the substrate at least partially overlaps a positive projection of VGH on the substrate;

[0332] A projection of an active pattern A4 of T5 on the substrate at least partially overlaps with a projection of VGH on the substrate;

[0333] By the above arrangement, transverse space can be saved, and narrow frame can be achieved.

[0334] In at least one embodiment of the present disclosure, the plurality of signal lines comprises a first starting voltage line;

[0335] The driving circuit comprises an output circuit; the output circuit is electrically connected with the fourth node, the second node and the driving output terminal respectively, and is configured to control the driving output terminal to output a driving signal under the control of the potential of the fourth node and the potential of the second node.

[0336] A projection of an active pattern of at least one transistor included in the output circuit on the substrate at least partially overlaps with a projection of the first starting voltage line on the substrate.

[0337] As shown in FIGS. 5-14, the plurality of signal lines comprises a first starting voltage line GSTV;

[0338] The output circuit comprises a fourth transistor T4 and a fifth transistor T5.

[0339] A projection of an active pattern A4 of T4 on the substrate at least partially overlaps with a projection of GSTV on the substrate.

[0340] A projection of an active pattern A4 of T5 on the substrate at least partially overlaps with a projection of GSTV on the substrate.

[0341] By the above arrangement, transverse space can be saved, and narrow frame can be achieved.

[0342] In at least one embodiment of the present disclosure, the plurality of signal lines comprises a second starting voltage line and a third starting voltage line;

[0343] The driving circuit comprises a fourth node control circuit; the fourth node control circuit is electrically connected with the first node, the fourth node and a second clock signal line respectively, and is configured to control the fourth node to communicate with the second clock signal line under the control of the potential of the first node.

[0344] At least part of an active pattern of at least one transistor included in the fourth node control circuit is arranged between a projection of the second starting voltage line on the substrate and a projection of the third starting voltage line on the substrate.

[0345] As shown in FIGS. 5-14, the plurality of signal lines comprises a second starting voltage line NSTV and a third starting voltage line ESTV;

[0346] The fourth node control circuit includes a second transistor T2;

[0347] A part of the active pattern A2 of T2 in the orthographic projection on the substrate is arranged between the orthographic projection of NSTV on the substrate and the orthographic projection of ESTV on the substrate, so as to reasonably arrange T2, NSTV and ESTV and save the horizontal space.

[0348] In at least one embodiment of the present disclosure, the plurality of signal lines include an initial voltage line; the driving circuit includes a first energy storage circuit and a second energy storage circuit; the first energy storage circuit is electrically connected with the second node and the driving output end respectively, and is used for controlling the potential of the second node according to the driving signal provided by the driving output end; and the second energy storage circuit is used for maintaining the potential of the fourth node.

[0349] The orthographic projection of the pole plate of the capacitor included in the first energy storage circuit on the substrate at least partially overlaps with the orthographic projection of the initial voltage line on the substrate;

[0350] The orthographic projection of the pole plate of the capacitor included in the second energy storage circuit on the substrate at least partially overlaps with the orthographic projection of the initial voltage line on the substrate.

[0351] As shown in FIGS. 5-14, the first energy storage circuit includes a first capacitor C1, and the second energy storage circuit includes a second capacitor C2;

[0352] The plurality of signal lines include a first initial voltage line INT1 and a second initial voltage line INT2;

[0353] The orthographic projection of the first pole plate C1a of C1 on the substrate at least partially overlaps with the orthographic projection of the first initial voltage line INT1 on the substrate;

[0354] The orthographic projection of the second pole plate C1b of C1 on the substrate at least partially overlaps with the orthographic projection of the first initial voltage line INT1 on the substrate;

[0355] The orthographic projection of the first pole plate C1a of C1 on the substrate at least partially overlaps with the orthographic projection of the second initial voltage line INT2 on the substrate;

[0356] The orthographic projection of the second pole plate C1b of C1 on the substrate at least partially overlaps with the orthographic projection of the second initial voltage line INT2 on the substrate;

[0357] The orthographic projection of the first pole plate C2a of C2 on the substrate at least partially overlaps with the orthographic projection of the first initial voltage line INT1 on the substrate;

[0358] The orthographic projection of the second pole plate C2b of C2 on the substrate at least partially overlaps with the orthographic projection of the first initial voltage line INT1 on the substrate;

[0359] A normal projection of the first electrode plate C2a of C2 on the substrate at least partially overlaps with a normal projection of the second initial voltage line INT2 on the substrate;

[0360] A normal projection of the second electrode plate C2b of C2 on the substrate at least partially overlaps with a normal projection of the second initial voltage line INT2 on the substrate;

[0361] By the above arrangement, the transverse space can be saved, and a narrow frame can be realized.

[0362] In at least one embodiment of the present disclosure, the driving circuit comprises a first node control circuit, and the first node control circuit comprises a first transistor;

[0363] The gate of the first transistor is integrally formed with a first connecting part;

[0364] The first connecting part and a second connecting part are arranged in different layers, and the first connecting part is electrically connected with the second connecting part;

[0365] The second connecting part is electrically connected with a first column clock signal line, and the second connecting part is arranged in a different layer from the first column clock signal line.

[0366] As shown in FIGS. 5-14, the first node control circuit comprises a first transistor T1;

[0367] The first gate G11 of T1 and the second gate G12 of T1 are integrally formed with a first connecting part L1, and G1 and L1 are both formed in a first gate metal layer;

[0368] The second connecting part L2 is electrically connected with a first column clock signal line CLK1, CLK1 is formed in a second source-drain metal layer, and the second connecting part L2 is formed in a first source-drain metal layer; L2 is electrically connected with CLK1;

[0369] T1 is electrically connected with CLK1 through L1 and L2.

[0370] In at least one embodiment of the present disclosure, the driving circuit comprises a fourth node control circuit; the fourth node control circuit comprises a second transistor and a third transistor;

[0371] The first electrode of the second transistor is electrically connected with a third connecting part, the third connecting part is arranged in a different layer from a second column clock signal line, and the third connecting part is electrically connected with the second column clock signal line;

[0372] The gate of the third transistor is integrally formed with a fourth connecting part, and the fourth connecting part is electrically connected with the third connecting part.

[0373] As shown in FIGS. 5-14, the fourth node control circuit comprises a second transistor T2 and a third transistor T3;

[0374] The first electrode S2 of T2 is electrically connected with the third connection portion L3, and L3 is formed in the first source-drain metal layer;

[0375] The second column clock signal line CLK2 is formed in the second source-drain metal layer;

[0376] L3 is electrically connected with CLK2;

[0377] The gate G3 of T3 is integrally formed with the fourth connection portion L4, and the fourth connection portion L4 is electrically connected with the third connection portion L3, so that the gate G3 of T3 is electrically connected with the second column clock signal line CLK2; L4 is formed in the first gate metal layer;

[0378] That is, the first electrode S2 of T2 is electrically connected with CLK2 through L3, and the gate G3 of T3 is electrically connected with CLK2 through L4 and L3.

[0379] In at least one embodiment of the present disclosure, the driving circuit comprises a first node control circuit and an output circuit, the first node control circuit comprises a seventh transistor, and the output circuit comprises a fifth transistor;

[0380] The gate of the seventh transistor is integrally formed with a fifth connection portion, the fifth connection portion is disposed in a layer different from the third clock signal line, and the fifth connection portion is electrically connected with the third clock signal line;

[0381] The second electrode of the fifth transistor is disposed in a layer different from the fifth connection portion, and the second electrode of the fifth transistor is electrically connected with the fifth connection portion.

[0382] As shown in FIGS. 5-14, the first node control circuit comprises a seventh transistor T7, and the output circuit comprises a fifth transistor T5;

[0383] The gate G7 of T7 is integrally formed with a fifth connection portion L5, and both G7 and L5 are formed in the first gate metal layer; the third column clock signal line CLK3 is formed in the second source-drain metal layer; L5 is electrically connected with CLK3, so that the gate G7 of T7 is electrically connected with CLK3; that is, the gate of T7 is electrically connected with CLK3 through L5;

[0384] The second electrode D5 of T5 is formed in the first source-drain metal layer, and the second electrode D5 of T5 is electrically connected with L5, so that the second electrode D5 of T5 is electrically connected with CLK3; that is, the second electrode D5 of T5 is electrically connected with CLK3 through L5.

[0385] FIGS. 27A, 27B and 27C are layout diagrams of a display substrate according to at least one embodiment of the present disclosure. In FIGS. 27A, 27B and 27C, the display substrate comprises at least one embodiment of the driving circuit shown in FIG. 3.

[0386] As shown in FIG. 27C, the gate of T13 is electrically connected with the second column clock signal line CLK2 through the first via hole H1; the gate of T11 is electrically connected with the first column clock signal line CLK1 through the second via hole H2; the gate of T17 is electrically connected with the third column clock signal line CLK3 through the third via hole H3;

[0387] The gate of T23 is electrically connected with the third column clock signal line CLK3 through the fourth via hole H4; the gate of T21 is electrically connected with the second column clock signal line CLK2 through the fifth via hole H5; the gate of T27 is electrically connected with the fourth column clock signal line CLK4 through the sixth via hole H6;

[0388] The gate of T33 is electrically connected with the fourth column clock signal line CLK4 through the seventh via hole H7; the gate of T31 is electrically connected with the third column clock signal line CLK3 through the eighth via hole H8; the gate of T37 is electrically connected with the first column clock signal line CLK1 through the ninth via hole H9;

[0389] The gate of T43 is electrically connected with the first column clock signal line CLK1 through the tenth via hole H10, the gate of T41 is electrically connected with the fourth column clock signal line CLK4 through the eleventh via hole H11, and the gate of T47 is electrically connected with the second column clock signal line CLK2 through the twelfth via hole H12.

[0390] As shown in FIG. 27C, the gate of T17 is electrically connected with the third column clock signal line CLK3 through the third via hole H3; the gate of T23 is electrically connected with the third column clock signal line CLK3 through the fourth via hole H4; that is, T17 in the first stage driving circuit is electrically connected with CLK3 through H3, and T23 in the second stage driving circuit is electrically connected with CLK3 through H4;

[0391] The gate of T27 is electrically connected with the fourth column clock signal line CLK4 through the sixth via hole H6; the gate of T33 is electrically connected with the fourth column clock signal line CLK4 through the seventh via hole H7; that is, T27 in the second stage driving circuit is electrically connected with CLK4 through H6, and T33 in the third stage driving circuit is electrically connected with CLK4 through H7;

[0392] The gate of T37 is electrically connected with the first column clock signal line CLK1 through the ninth via hole H9; the gate of T43 is electrically connected with the first column clock signal line CLK1 through the tenth via hole H10; that is, the gate of T37 in the third stage driving circuit is electrically connected with CLK1 through H9, and the gate of T43 in the fourth stage driving circuit is electrically connected with CLK1 through H10.

[0393] In at least one embodiment shown in FIG. 27C, T13 in the first-stage driving circuit in the driving module is electrically connected with T21 in the second-stage driving circuit in the driving module through the second column clock signal line CLK2;

[0394] T11 in the first-stage driving circuit in the driving module is electrically connected with T43 in the fourth-stage driving circuit in the driving module through the first column clock signal line CLK1;

[0395] T17 in the first-stage driving circuit in the driving module is electrically connected with T23 in the second-stage driving circuit in the driving module through the third column clock signal line CLK3;

[0396] T27 in the second-stage driving circuit in the driving module is electrically connected with T33 in the third-stage driving circuit in the driving module through the fourth column clock signal line CLK4;

[0397] T31 in the third-stage driving circuit in the driving module is electrically connected with T23 in the second-stage driving circuit in the driving module through the third column clock signal line CLK3, and T37 in the third-stage driving circuit in the driving module is electrically connected with T11 in the first-stage driving circuit in the driving module through the first column clock signal line CLK1;

[0398] T41 in the fourth-stage driving circuit in the driving module is electrically connected with T33 in the third-stage driving circuit in the driving module through the fourth column clock signal line CLK4, and T47 in the fourth-stage driving circuit in the driving module is electrically connected with T13 in the first-stage driving circuit in the driving module through the second column clock signal line CLK2. As shown in FIG. 27C, instead of arranging a via to electrically connect a transistor in one stage driving circuit with a corresponding column clock signal line and then electrically connecting a transistor in another stage driving circuit with the transistor through a conductive pattern formed on the first source-drain metal layer to make the transistor in another stage driving circuit access a corresponding clock signal, a via is arranged in each stage driving circuit to electrically connect at least one transistor in each stage driving circuit with at least one transistor in another stage driving circuit through a corresponding column clock signal line, so as to reduce the wiring formed on the first source-drain metal layer when the clock signals of the upper and lower stage driving circuits are cascaded, and optimize the layout space. FIG. 28 is a layout diagram of the semiconductor layer in FIG. 27A, FIG. 29 is a layout diagram of the first gate metal layer in FIG. 27A, FIG. 30 is a layout diagram of the second gate metal layer in FIG. 27A, FIG. 31 is a layout diagram of the first source-drain metal layer in FIG. 27A, and FIG. 32 is a layout diagram of the second source-drain metal layer in FIG. 27A;

[0399] Fig. 33 is a layout of the semiconductor layer and the first gate metal layer in Fig. 27A, Fig. 34 is a layout of the first gate metal layer and the second gate metal layer in Fig. 27A, Fig. 35 is a layout of the second gate metal layer and the first source-drain metal layer in Fig. 27A, and Fig. 36 is a layout of the first source-drain metal layer and the second source-drain metal layer in Fig. 27A.

[0400] In Fig. 28, A11 is the active pattern of T11, A21 is the active pattern of T21, A31 is the active pattern of T31, and A41 is the active pattern of T41.

[0401] In Fig. 29, G17 is the gate of T17, G23 is the gate of T23, G27 is the gate of T27, G33 is the gate of T33, G37 is the gate of T37, and G43 is the gate of T43.

[0402] In Fig. 30, C12b is the second plate of C12, C11b is the second plate of C11, C22b is the second plate of C22, C21b is the second plate of C21, C32b is the second plate of C32, C31b is the second plate of C31, C42b is the second plate of C42, and C41b is the second plate of C41.

[0403] In Fig. 31, D15 is the second electrode of T15, D25 is the second electrode of T25, D35 is the second electrode of T35, and D45 is the second electrode of T45.

[0404] Fig. 37 is a layout of a display substrate according to at least one embodiment of the present disclosure.

[0405] Fig. 37 corresponds to the position of the top-left rounded corner of the display substrate, in which P2 is the second-stage driving circuit, P3 is the third-stage driving circuit, H13 is the thirteenth via, and H14 is the fourteenth via.

[0406] As shown in Fig. 37, when the upper and lower stage driving circuits are cascaded at the position of the rounded corner, T27 is electrically connected to CLK4 through H13, and T33 is electrically connected to CLK4 through H14, that is, the transistors in the adjacent two-stage driving circuits are respectively electrically connected to CLK4 through different vias, which can ensure the consistency of the load of the wiring when the clock signal is accessed.

[0407] Fig. 38 is a layout of the semiconductor layer in Fig. 37, Fig. 39 is a layout of the first gate metal layer in Fig. 37, Fig. 40 is a layout of the second gate metal layer in Fig. 37, Fig. 41 is a layout of the first source-drain metal layer in Fig. 37, and Fig. 42 is a layout of the second source-drain metal layer in Fig. 37.

[0408] In Fig. 38, A27 is the active pattern of T27, and A33 is the active pattern of T33.

[0409] In Fig. 39, G27 is the gate of T27, and G33 is the gate of T33.

[0410] In Fig. 40, C22b is the second plate of C22, C21b is the second plate of C21, and C32b is the second plate of C32.

[0411] In Fig. 41, D25 is the second electrode of T25.

[0412] Fig. 43 is a stack of the semiconductor layer and the first gate metal layer in Fig. 37, Fig. 44 is a stack of the first gate metal layer and the second gate metal layer in Fig. 37, Fig. 45 is a stack of the second gate metal layer and the first source-drain metal layer in Fig. 37, and Fig. 46 is a stack of the first source-drain metal layer and the second source-drain metal layer in Fig. 37.

[0413] In at least one embodiment of the present disclosure, the input end of the nth-stage driving circuit included in the driving module is electrically connected with the driving output end of the n-mth-stage driving circuit, m is a positive integer; and n is an integer greater than m.

[0414] The input end of the first m-stage driving circuit included in the driving module is electrically connected with the first starting voltage line.

[0415] In a specific implementation, the multiple-stage driving circuits included in the driving module are cascaded with each other, and the input end of the nth-stage driving circuit can be electrically connected with the driving output end of the n-mth-stage driving circuit.

[0416] In at least one embodiment of the present disclosure, m is equal to 2; the driving output end of the a-th-stage driving circuit included in the driving module is electrically connected with the input end of the a+2-th-stage driving circuit; a is a positive integer; and the display substrate includes two virtual driving circuits.

[0417] The input end of the first virtual driving circuit and the input end of the second virtual driving circuit are both electrically connected with the first starting voltage line.

[0418] The driving output end of the first virtual driving circuit is electrically connected with the input end of the first-stage driving circuit included in the driving module.

[0419] The driving output end of the second virtual driving circuit is electrically connected with the input end of the second driving circuit included in the driving module.

[0420] In a specific implementation, when m is equal to 2, the display substrate can include two-level virtual driving circuits, the input ends of the two-level virtual driving circuits can be electrically connected with a first starting voltage line, the driving output end of the first virtual driving circuit can be electrically connected with the input end of the first driving circuit included in the driving module, and the driving output end of the second virtual driving circuit can be electrically connected with the input end of the second driving circuit included in the driving module.

[0421] FIG. 47 is a layout diagram of a display substrate according to at least one embodiment of the present disclosure. FIG. 47 corresponds to the upper rounded corner position of the display substrate.

[0422] In FIG. 47, X1 represents a first virtual driving circuit, X2 represents a second virtual driving circuit, P1 represents a first driving circuit included in a driving module, and P2 represents a second driving circuit included in the driving module.

[0423] X1 and X2 are both electrically connected with a first starting voltage line GSTV.

[0424] FIG. 48 is a layout diagram of a semiconductor layer in FIG. 47.

[0425] In FIG. 48, the active pattern of a first transistor included in the first virtual driving circuit is denoted by AX11, the active pattern of a first transistor included in the second virtual driving circuit is denoted by AX21, the active pattern of a first transistor in the first driving circuit P1 is denoted by A11, and the active pattern of a second first transistor included in the second driving circuit is denoted by A21.

[0426] FIG. 49 is a layout diagram of a first gate metal layer in FIG. 47.

[0427] In FIG. 49, the first plate of a first capacitor included in the first virtual driving circuit is denoted by CX11a, and the first plate of a second capacitor included in the first virtual driving circuit is denoted by CX12a.

[0428] The first plate of a first capacitor included in the second virtual driving circuit is denoted by CX21a, and the first plate of a second capacitor included in the second virtual driving circuit is denoted by CX22a.

[0429] C11a represents the first plate of a first first capacitor in the first driving circuit, and C12a represents the first plate of a first second capacitor in the first driving circuit.

[0430] C21a is a first plate of a second first capacitor in the second stage driving circuit, and C22a is a first plate of a second second capacitor in the second stage driving circuit.

[0431] Fig. 50 is a layout of the second gate metal layer in Fig. 47.

[0432] In Fig. 50, a second plate of a first capacitor included in the first virtual driving circuit is labeled as CX11b, and a second plate of a second capacitor included in the first virtual driving circuit is labeled as CX12b;

[0433] A second plate of a first capacitor included in the second virtual driving circuit is labeled as CX21b, and a second plate of a second capacitor included in the second virtual driving circuit is labeled as CX22b;

[0434] C11b is a second plate of a first first capacitor in the first stage driving circuit, and C12b is a second plate of a second second capacitor in the first stage driving circuit;

[0435] C21b is a second plate of a first first capacitor in the second stage driving circuit, and C22b is a second plate of a second second capacitor in the second stage driving circuit.

[0436] Fig. 51 is a layout of the first source-drain metal layer in Fig. 47.

[0437] In Fig. 51, a second electrode of a first fifth transistor in the first stage driving circuit is labeled as D15, and a second electrode of a second fifth transistor in the second stage driving circuit is labeled as D25;

[0438] A second electrode of a fifth transistor in the first virtual driving circuit is labeled as DX15, and a second electrode of a fifth transistor in the first virtual driving circuit is labeled as DX25.

[0439] Fig. 52 is a layout of the second source-drain metal layer in Fig. 47.

[0440] In Fig. 52, a first starting voltage line is labeled as GSTV.

[0441] Fig. 53 is a layout of the semiconductor layer and the first gate metal layer in Fig. 47, Fig. 54 is a layout of the first gate metal layer and the second gate metal layer in Fig. 47, Fig. 55 is a layout of the second gate metal layer and the first source-drain metal layer in Fig. 47, and Fig. 56 is a layout of the first source-drain metal layer and the second source-drain metal layer in Fig. 47.

[0442] In at least one embodiment of the present disclosure, m is equal to 2; a driving output end of an a-th stage driving circuit included in the driving module is electrically connected with an input end of an a+2-th stage driving circuit; a is a positive integer; the display substrate includes a first virtual driving circuit;

[0443] The input end of the virtual drive circuit is electrically connected with the first starting voltage line;

[0444] The input end of the first-stage drive circuit included in the drive module is electrically connected with the first starting voltage line;

[0445] The input end of the second-stage drive circuit included in the drive module is electrically connected with the drive output end of the virtual drive circuit.

[0446] In a specific implementation, when m is equal to 2, the display substrate can include a first virtual drive circuit, the input end of the virtual drive circuit and the input end of the first-stage drive circuit can both be electrically connected with the first starting voltage line, and the input end of the second-stage drive circuit included in the drive module can be electrically connected with the drive output end of the virtual drive circuit.

[0447] FIG. 57 is a layout diagram of a display substrate according to at least one embodiment of the present disclosure. FIG. 57 corresponds to the upper rounded corner position of the display substrate.

[0448] In FIG. 57, X1 is a first virtual drive circuit, P1 is a first-stage drive circuit included in a drive module, P2 is a second-stage drive circuit included in the drive module, and P3 is a third-stage drive circuit included in the drive module.

[0449] X1 and P1 are both electrically connected with the first starting voltage line GSTV.

[0450] FIG. 58 is a layout diagram of a semiconductor layer in FIG. 57.

[0451] In FIG. 58, the active pattern of a first transistor included in the first virtual drive circuit is marked as AX11, the active pattern of a first first transistor in the first-stage drive circuit P1 is marked as A11, the active pattern of a second first transistor included in the second-stage drive circuit is marked as A21, and the active pattern of a third first transistor included in the third-stage drive circuit is marked as A31.

[0452] FIG. 59 is a layout diagram of a first gate metal layer in FIG. 57.

[0453] In FIG. 59, the first plate of a first capacitor included in the first virtual drive circuit is marked as CX11a, and the first plate of a second capacitor included in the first virtual drive circuit is marked as CX12a.

[0454] C11a is the first plate of a first first capacitor in the first-stage drive circuit, and C12a is the first plate of a first second capacitor in the first-stage drive circuit.

[0455] C21a is the first plate of a second first capacitor in the second stage of driving circuit, C22a is the first plate of a second second capacitor in the second stage of driving circuit;

[0456] C31a is the first plate of a third first capacitor in the third stage of driving circuit, C32a is the first plate of a third second capacitor in the third stage of driving circuit.

[0457] Fig. 60 is a layout of the first gate metal layer in Fig. 57.

[0458] In Fig. 60, the second plate of the first capacitor included in the first dummy driving circuit is labeled as CX11b, and the second plate of the second capacitor included in the first dummy driving circuit is labeled as CX12b;

[0459] C11b is the second plate of a first first capacitor in the first stage of driving circuit, C12b is the second plate of a first second capacitor in the first stage of driving circuit;

[0460] C21b is the second plate of a second first capacitor in the second stage of driving circuit, C22b is the second plate of a second second capacitor in the second stage of driving circuit;

[0461] C31b is the second plate of a third first capacitor in the third stage of driving circuit, C32b is the second plate of a third second capacitor in the third stage of driving circuit.

[0462] Fig. 61 is a layout of the first source-drain metal layer in Fig. 57.

[0463] In Fig. 61, the second electrode of a first fifth transistor in the first stage of driving circuit is labeled as D15, the second electrode of a second fifth transistor in the second stage of driving circuit is labeled as D25, and the second electrode of a third fifth transistor in the third stage of driving circuit is labeled as D35;

[0464] The second electrode of a fifth transistor in the first dummy driving circuit is labeled as DX15.

[0465] Fig. 62 is a layout of the second source-drain metal layer in Fig. 57.

[0466] In Fig. 62, the first starting voltage line is labeled as GSTV.

[0467] Fig. 63 is a layout of the semiconductor layer and the first gate metal layer in Fig. 57, Fig. 64 is a layout of the first gate metal layer and the second gate metal layer in Fig. 57, Fig. 65 is a layout of the second gate metal layer and the first source-drain metal layer in Fig. 57, and Fig. 66 is a layout of the first source-drain metal layer and the second source-drain metal layer in Fig. 57.

[0468] FIG. 67 is a layout diagram of a display substrate according to at least one embodiment of the disclosure. FIG. 57 corresponds to an upper rounded corner position of the display substrate.

[0469] In FIG. 67, P1 is a first-stage driving circuit included in a driving module, P2 is a second-stage driving circuit included in the driving module, P3 is a third-stage driving circuit included in the driving module, and P4 is a fourth-stage driving circuit included in the driving module.

[0470] P1 and P2 are electrically connected to a first starting voltage line GSTV.

[0471] FIG. 68 is a layout diagram of a semiconductor layer in FIG. 67.

[0472] In FIG. 68, an active pattern of a first first transistor in the first-stage driving circuit P1 is labeled as A11, an active pattern of a second first transistor included in the second-stage driving circuit is labeled as A21, an active pattern of a third first transistor included in the third-stage driving circuit is labeled as A31, and an active pattern of a fourth first transistor included in the fourth-stage driving circuit is labeled as A41.

[0473] FIG. 69 is a layout diagram of a first gate metal layer in FIG. 67.

[0474] In FIG. 69, C11a is a first plate of a first first capacitor in the first-stage driving circuit, and C12a is a first plate of a first second capacitor in the first-stage driving circuit.

[0475] C21a is a first plate of a second first capacitor in the second-stage driving circuit, and C22a is a first plate of a second second capacitor in the second-stage driving circuit.

[0476] C31a is a first plate of a third first capacitor in the third-stage driving circuit, and C32a is a first plate of a third second capacitor in the third-stage driving circuit.

[0477] C41a is a first plate of a fourth first capacitor in the fourth-stage driving circuit, and C42a is a first plate of a fourth second capacitor in the fourth-stage driving circuit.

[0478] FIG. 70 is a layout diagram of the first gate metal layer in FIG. 67.

[0479] In FIG. 70, C11b is a second plate of the first first capacitor in the first-stage driving circuit, and C12b is a second plate of the first second capacitor in the first-stage driving circuit.

[0480] C21b is a second plate of the second first capacitor in the second-stage driving circuit, and C22b is a second plate of the second second capacitor in the second-stage driving circuit.

[0481] C31b is the second plate of the third first capacitor in the third stage driving circuit, and C32b is the second plate of the third second capacitor in the third stage driving circuit;

[0482] C41b is the second plate of the fourth first capacitor in the fourth stage driving circuit, and C42b is the second plate of the fourth second capacitor in the fourth stage driving circuit.

[0483] Fig. 71 is a layout of the first source-drain metal layer in Fig. 67.

[0484] In Fig. 71, D15 is the second electrode of the first fifth transistor in the first stage driving circuit, D25 is the second electrode of the second fifth transistor in the second stage driving circuit, D35 is the second electrode of the third fifth transistor in the third stage driving circuit, and D45 is the second electrode of the fourth fifth transistor in the fourth stage driving circuit.

[0485] Fig. 72 is a layout of the second source-drain metal layer in Fig. 67.

[0486] In Fig. 72, GSTV is the first starting voltage line.

[0487] Fig. 73 is a layout of the semiconductor layer and the first gate metal layer in Fig. 67, Fig. 74 is a layout of the first gate metal layer and the second gate metal layer in Fig. 67, Fig. 75 is a layout of the second gate metal layer and the first source-drain metal layer in Fig. 67, and Fig. 76 is a layout of the first source-drain metal layer and the second source-drain metal layer in Fig. 67.

[0488] In at least one embodiment of the present disclosure, the plurality of signal lines includes four columns of clock signal lines;

[0489] The first clock signal line of the fourth 4b-3 driving circuit included in the driving module is electrically connected to the first column of clock signal lines, the second clock signal line of the fourth 4b-3 driving circuit included in the driving module is electrically connected to the second column of clock signal lines, and the third clock signal line of the fourth 4b-3 driving circuit included in the driving module is electrically connected to the third column of clock signal lines.

[0490] The first clock signal line of the fourth 4b-2 driving circuit included in the driving module is electrically connected to the second column of clock signal lines, the second clock signal line of the fourth 4b-2 driving circuit included in the driving module is electrically connected to the third column of clock signal lines, and the fourth clock signal line of the fourth 4b-2 driving circuit included in the driving module is electrically connected to the third column of clock signal lines.

[0491] The first clock signal line of the fourth 4b-1 driving circuit included in the driving module is electrically connected with the third column clock signal line, the second clock signal line of the fourth 4b-1 driving circuit included in the driving module is electrically connected with the fourth column clock signal line, and the third clock signal line of the fourth 4b-1 driving circuit included in the driving module is electrically connected with the first column clock signal line.

[0492] The first clock signal line of the fourth 4b driving circuit included in the driving module is electrically connected with the fourth column clock signal line, the second clock signal line of the fourth 4b driving circuit included in the driving module is electrically connected with the first column clock signal line, and the third clock signal line of the fourth 4b driving circuit included in the driving module is electrically connected with the second column clock signal line.

[0493] b is a positive integer.

[0494] In a specific implementation, the first clock signal line of the first driving circuit included in the driving module is electrically connected with the first column clock signal line, the second clock signal line of the first driving circuit included in the driving module is electrically connected with the second column clock signal line, and the third clock signal line of the first driving circuit included in the driving module is electrically connected with the third column clock signal line.

[0495] The first clock signal line of the second driving circuit included in the driving module is electrically connected with the second column clock signal line, the second clock signal line of the second driving circuit included in the driving module is electrically connected with the third column clock signal line, and the third clock signal line of the second driving circuit included in the driving module is electrically connected with the fourth column clock signal line.

[0496] The first clock signal line of the third driving circuit included in the driving module is electrically connected with the third column clock signal line, the second clock signal line of the third driving circuit included in the driving module is electrically connected with the fourth column clock signal line, and the third clock signal line of the third driving circuit included in the driving module is electrically connected with the first column clock signal line.

[0497] The first clock signal line of the fourth driving circuit included in the driving module is electrically connected with the fourth column clock signal line, the second clock signal line of the fourth driving circuit included in the driving module is electrically connected with the first column clock signal line, and the third clock signal line of the fourth driving circuit included in the driving module is electrically connected with the second column clock signal line.

[0498] As shown in FIG. 77, in at least one embodiment of the present disclosure, the first column clock signal line CLK1, the second column clock signal line CLK2, the third column clock signal line CLK3 and the fourth column clock signal line CLK4 output corresponding clock signals in turn.

[0499] In the first time period t1, CLK1 provides a low voltage signal.

[0500] In the second time period t2, CLK2 provides a low voltage signal;

[0501] In the third time period t3, CLK3 provides a low voltage signal;

[0502] In the fourth time period t4, CLK4 provides a low voltage signal;

[0503] A first interval stage tj1 is arranged between t1 and t2, a second interval stage tj2 is arranged between t2 and t3, and a third interval stage tj3 is arranged between t3 and t4;

[0504] The interval stages are arranged as above, so that after the potential of the current clock signal rises, the potential of the next clock signal starts to drop, avoiding that the adjacent column clock signal lines output low voltage signals at the same time.

[0505] The display device described in the embodiments of the present disclosure includes the display substrate described above.

[0506] The above describes the preferred embodiments of the present disclosure. It should be noted that, for those skilled in the art, without departing from the principles of the present disclosure, a number of improvements and refinements can be made, which should also be considered within the scope of protection of the present disclosure.

Claims

1. A display substrate, comprising a substrate and a driving module disposed on the substrate, the driving module comprising a plurality of stages of driving circuits; the driving circuit comprises a plurality of devices, the devices comprising transistors and capacitors; the display substrate further comprises a plurality of signal lines disposed on the substrate, the plurality of signal lines comprising at least three clock signal lines; a normal projection of the signal line on the substrate at least partially overlaps a normal projection of at least one of the devices on the substrate; at least one transistor in at least two stages of driving circuits of the driving module is electrically connected to at least one transistor in other stages of driving circuits through a corresponding clock signal line. 2.The display substrate of claim 1, wherein, at least one transistor in each stage of driving circuits in the driving module is electrically connected to at least one transistor in other stages of driving circuits through a corresponding clock signal line. 3.The display substrate of claim 1, wherein, the driving circuit comprises an input circuit; the input circuit is electrically connected to a first clock signal line, an input terminal and a first node respectively, and is configured to control a potential of the first node according to an input signal provided by the input terminal under control of a first clock signal provided by the first clock signal line; a normal projection of an active pattern of at least one transistor in the input circuit on the substrate at least partially overlaps a normal projection of a first column of clock signal lines on the substrate; a normal projection of an active pattern of at least one transistor in the input circuit on the substrate at least partially overlaps a normal projection of a second column of clock signal lines on the substrate. 4.The display substrate of claim 1, wherein, the driving circuit comprises a second node control circuit; the second node control circuit is electrically connected to a first voltage line, a first node and a second node respectively, and is configured to control communication between the first node and the second node under control of a first voltage signal provided by the first voltage line; a normal projection of an active pattern of at least one transistor in the second node control circuit on the substrate at least partially overlaps a normal projection of a second column of clock signal lines on the substrate. 5.The display substrate of claim 1, wherein, the driving circuit comprises a first node control circuit; the first node control circuit is electrically connected to a third clock signal line, a third node and a first node respectively, and is configured to control communication between the third node and the first node under control of a third clock signal provided by the third clock signal line; a normal projection of an active pattern of at least one transistor in the first node control circuit on the substrate at least partially overlaps a normal projection of the third clock signal line on the substrate. 6.The display substrate of claim 1, wherein, the driving circuit comprises a third node control circuit; the third node control circuit is electrically connected to a fourth node, a second voltage line and a third node respectively, and is configured to write a second voltage signal provided by the second voltage line into the third node under control of a potential of the fourth node; a normal projection of a gate of at least one transistor in the third node control circuit on the substrate is disposed between a normal projection of a fourth column of clock signal lines on the substrate and a normal projection of a first first voltage line on the substrate; the first first voltage line is disposed on a side of the fourth column of clock signal lines close to a display area. 7.The display substrate of claim 1, wherein, The plurality of signal lines comprises a first first-level line; the driving circuit comprises an output circuit; the output circuit is electrically connected with a fourth node, a second node and a driving output terminal respectively, and is configured to control the driving output terminal to output a driving signal under control of potentials of the fourth node and the second node; A normal projection of the first first-level line on a substrate at least partially overlaps with a normal projection of an active pattern of at least one transistor comprised in the output circuit on the substrate. 8.The display substrate of claim 7, wherein, The plurality of signal lines further comprises a second first-level line; the driving circuit comprises a fourth node control circuit; the fourth node control circuit is electrically connected with a first node, a second clock signal line and the fourth node respectively, and is configured to control communication between the second clock signal line and the fourth node under control of a potential of the first node; the first first-level line is electrically connected with the second first-level line; A normal projection of an active pattern of at least one transistor comprised in the fourth node control circuit on a substrate at least partially overlaps with a normal projection of the second first-level line on the substrate. 9.The display substrate of claim 8, wherein, The plurality of signal lines further comprises a third first-level line; The second first-level line and the third first-level line are arranged in different layers; the second first-level line is electrically connected with the third first-level line; A normal projection of the second first-level line on a substrate at least partially overlaps with a normal projection of the third first-level line on the substrate. 10.The display substrate of claim 8, wherein, The plurality of signal lines further comprises a third first-level line and a first voltage line; the second first-level line is electrically connected with the third first-level line; A normal projection of the third first-level line on a substrate at least partially overlaps with a normal projection of the first voltage line on the substrate. 11.The display substrate of claim 10, wherein, The first first-level line, the second first-level line and the third first-level line are all arranged in a peripheral region; The first first-level line is electrically connected with a grid-shaped low-level wire arranged in a display region. 12.The display substrate of claim 10, wherein, The driving circuit comprises a fourth node control circuit; the fourth node control circuit is electrically connected with a first node, a fourth node, a second clock signal line and a first voltage line respectively, and is configured to control communication between the fourth node and the second clock signal line under control of a potential of the first node, and control communication between the fourth node and the first voltage line under control of a second clock signal provided by the second clock signal line; A normal projection of an active pattern of at least one transistor comprised in the fourth node control circuit on a substrate at least partially overlaps with a normal projection of the second first-level line on the substrate. A normal projection of an active pattern of at least one transistor comprised in the fourth node control circuit on a substrate at least partially overlaps with a normal projection of the third first-level line on the substrate. A normal projection of an active pattern of at least one transistor comprised in the fourth node control circuit on a substrate at least partially overlaps with a normal projection of the first voltage line on the substrate. 13.The display substrate of claim 1, wherein, The plurality of signal lines comprises a second voltage line; the driving circuit comprises an output circuit; the output circuit is electrically connected with a fourth node, a second node and a driving output terminal respectively, and is configured to control the driving output terminal to output a driving signal under the control of potentials of the fourth node and the second node; A positive projection of an active pattern of at least one transistor included in the output circuit on the substrate at least partially overlaps a positive projection of the second voltage line on the substrate. 14.The display substrate of claim 1, wherein, The plurality of signal lines comprises a first starting voltage line; The driving circuit comprises an output circuit; the output circuit is electrically connected with a fourth node, a second node and a driving output terminal respectively, and is configured to control the driving output terminal to output a driving signal under the control of potentials of the fourth node and the second node; A positive projection of an active pattern of at least one transistor included in the output circuit on the substrate at least partially overlaps a positive projection of the first starting voltage line on the substrate. 15.The display substrate of claim 1, wherein, The plurality of signal lines comprises a second starting voltage line and a third starting voltage line; The driving circuit comprises a fourth node control circuit; the fourth node control circuit is electrically connected with a first node, a fourth node and a second clock signal line respectively, and is configured to control the fourth node to communicate with the second clock signal line under the control of a potential of the first node; At least part of an active pattern of at least one transistor included in the fourth node control circuit is arranged between a positive projection of the second starting voltage line on the substrate and a positive projection of the third starting voltage line on the substrate. 16.The display substrate of claim 1, wherein, The plurality of signal lines comprises an initial voltage line; the driving circuit comprises a first energy storage circuit and a second energy storage circuit; the first energy storage circuit is electrically connected with a second node and a driving output terminal respectively, and is configured to control a potential of the second node according to a driving signal provided by the driving output terminal; The second energy storage circuit is configured to maintain a potential of a fourth node; A positive projection of a plate of a capacitor included in the first energy storage circuit on the substrate at least partially overlaps a positive projection of the initial voltage line on the substrate; A positive projection of a plate of a capacitor included in the second energy storage circuit on the substrate at least partially overlaps a positive projection of the initial voltage line on the substrate.

17. The display substrate of claim 1 or 2, wherein, The driving circuit comprises a first node control circuit, and the first node control circuit comprises a first transistor; A gate of the first transistor is integrally formed with a first connecting part; The first connecting part and a second connecting part are arranged in different layers, and the first connecting part is electrically connected with the second connecting part; The second connecting part is electrically connected with a first column clock signal line, and the second connecting part is arranged in a different layer from the first column clock signal line.

18. The display substrate of claim 1 or 2, wherein, The driving circuit comprises a fourth node control circuit; the fourth node control circuit comprises a second transistor and a third transistor; A first electrode of the second transistor is electrically connected with a third connecting part, the third connecting part is arranged in a different layer from a second column clock signal line, and the third connecting part is electrically connected with the second column clock signal line; A gate of the third transistor is integrally formed with a fourth connecting part, and the fourth connecting part is electrically connected with the third connecting part. ​ 19. The display substrate of claim 1 or 2, wherein, The driving circuit comprises a first node control circuit and an output circuit, the first node control circuit comprises a seventh transistor, and the output circuit comprises a fifth transistor; The gate of the seventh transistor is integrally formed with a fifth connecting part; the fifth connecting part is arranged in a layer different from the third clock signal line; and the fifth connecting part is electrically connected with the third clock signal line; The second electrode of the fifth transistor is arranged in a layer different from the fifth connecting part; and the second electrode of the fifth transistor is electrically connected with the fifth connecting part.

20. The display substrate of any one of claims 1 to 16, wherein, The input end of the nth-stage driving circuit comprised in the driving module is electrically connected with the driving output end of the n-mth-stage driving circuit; m is a positive integer; and n is an integer greater than m; The input end of the first m-stage driving circuit comprised in the driving module is electrically connected with the first starting voltage line.

21. The display substrate of claim 20, wherein, m is equal to 2; the driving output end of the a-th-stage driving circuit comprised in the driving module is electrically connected with the input end of the a+2-th-stage driving circuit; a is a positive integer; and the display substrate comprises two virtual driving circuits; The input end of the first virtual driving circuit and the input end of the second virtual driving circuit are both electrically connected with the first starting voltage line; The driving output end of the first virtual driving circuit is electrically connected with the input end of the first-stage driving circuit comprised in the driving module; The driving output end of the second virtual driving circuit is electrically connected with the input end of the second-stage driving circuit comprised in the driving module.

22. The display substrate of claim 20, wherein, m is equal to 2; the driving output end of the a-th-stage driving circuit comprised in the driving module is electrically connected with the input end of the a+2-th-stage driving circuit; a is a positive integer; and the display substrate comprises one virtual driving circuit; The input end of the virtual driving circuit is electrically connected with the first starting voltage line; The input end of the first-stage driving circuit comprised in the driving module is electrically connected with the first starting voltage line; The input end of the second-stage driving circuit comprised in the driving module is electrically connected with the driving output end of the virtual driving circuit.

23. The display substrate of any one of claims 1 to 16, wherein, The plurality of signal lines comprises four clock signal lines; The first clock signal line of the 4b-3th-stage driving circuit comprised in the driving module is electrically connected with the first clock signal line; the second clock signal line of the 4b-3th-stage driving circuit comprised in the driving module is electrically connected with the second clock signal line; and the third clock signal line of the 4b-3th-stage driving circuit comprised in the driving module is electrically connected with the third clock signal line; The first clock signal line of the 4b-2th-stage driving circuit comprised in the driving module is electrically connected with the second clock signal line, The second clock signal line of the 4b-2th-stage driving circuit comprised in the driving module is electrically connected with the third clock signal line; and the third clock signal line of the 4b-2th-stage driving circuit comprised in the driving module is electrically connected with the fourth clock signal line; The first clock signal line of the 4b-1th-stage driving circuit comprised in the driving module is electrically connected with the third clock signal line; the second clock signal line of the 4b-1th-stage driving circuit comprised in the driving module is electrically connected with the fourth clock signal line; and the third clock signal line of the 4b-1th-stage driving circuit comprised in the driving module is electrically connected with the first clock signal line; The first clock signal line of the fourth 4b driving circuit in the driving module is electrically connected with the fourth column clock signal line, the second clock signal line of the fourth 4b driving circuit in the driving module is electrically connected with the first column clock signal line, and the third clock signal line of the fourth 4b driving circuit in the driving module is electrically connected with the second column clock signal line. b is a positive integer.

24. A display device comprising the display substrate according to any one of claims 1 to 23.

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