Signal processing method, circuit and chip and electronic device

Abstract

Provided in the embodiments of the present application are a signal processing method, circuit and chip and an electronic device. The signal processing method comprises: performing PWM modulation on an input signal to obtain a PWM positive signal and a PWM negative signal; and, on the basis of the PWM positive signal and the PWM negative signal, outputting a positive output signal and a negative output signal, wherein in response to the amplitude of the input signal being not equal to 0, the positive output signal and the negative output signal each comprise two pulses in one pulse period. The present solution can reduce the frequency requirements for passive filters processing positive output signals and negative output signals, thereby reducing the cost of signal processing systems.

Description

Signal processing method, circuit, chip and electronic device TECHNICAL FIELD

[0001] Embodiments of the present application relate to the technical field of electronics, and in particular to a signal processing method, circuit, chip and electronic device. BACKGROUND

[0002] Pulse-Width Modulation (PWM) is a technology for controlling analog circuits using digital outputs of a microprocessor, and a required waveform (including shape and amplitude) is obtained by modulating the width of a pulse, that is, by changing the duty cycle to adjust voltage and frequency.

[0003] At present, a D-class power amplifier (also referred to as a digital power amplifier or a switching power amplifier) using PWM technology is used to amplify an audio signal, the D-class power amplifier extracts the output differential component of a comparison unit and sends it to a power output module, and an output signal of the power output module drives an audio device after passing through a passive filter.

[0004] The signal frequency supported by a passive filter is inversely related to the cost, that is, the cost of a passive filter supporting a small frequency signal is higher than the cost of a passive filter supporting a large frequency signal, and the frequency of an output signal of a power output module in an existing D-class power amplifier is small, so a passive filter supporting a small frequency signal needs to be used, resulting in a high cost of a signal processing system.

[0005] SUMMARY

[0006] In view of this, embodiments of the present application provide a signal processing method, circuit, chip and electronic device to at least partially solve the above problems.

[0007] According to a first aspect of embodiments of the present application, a signal processing method is provided, including: performing PWM modulation on an input signal to obtain a PWM positive signal and a PWM negative signal; and outputting a positive output signal and a negative output signal according to the PWM positive signal and the PWM negative signal; wherein, in response to an amplitude of the input signal not being equal to 0, the positive output signal and the negative output signal each include 2 pulses in one pulse period.

[0008] According to a second aspect of embodiments of the present application, a signal processing circuit is provided, including: a modulation module configured to perform PWM modulation on an input signal to obtain a PWM positive signal and a PWM negative signal; and a power output module configured to output a positive output signal and a negative output signal according to the PWM positive signal and the PWM negative signal; wherein, in response to an amplitude of the input signal not being equal to 0, the positive output signal and the negative output signal each include 2 pulses in one pulse period.

[0009] According to a third aspect of the embodiments of the present application, a signal processing chip is provided, which is configured to perform the method according to the first aspect.

[0010] According to a fourth aspect of the embodiments of the present application, an electronic device is provided, which comprises a signal source, a signal receiving end and a signal processing device, wherein the signal processing device comprises the signal processing circuit according to the second aspect or the signal processing chip according to the third aspect; the signal processing device is connected between the signal source and the signal receiving end; the signal source is configured to transmit an input signal to the signal processing device; and the signal receiving end is configured to receive a positive output signal and a negative output signal output by the signal processing device.

[0011] According to the embodiments of the present application, the input signal is PWM modulated to obtain a PWM positive signal and a PWM negative signal, and the positive output signal and the negative output signal are output according to the PWM positive signal and the PWM negative signal. When the amplitude of the input signal is not equal to 0, the positive output signal and the negative output signal each comprise two pulses in one pulse period. When the amplitude of the input signal is not equal to 0, the positive output signal and the negative output signal output by the power output module each comprise two pulses, so that the frequency of the positive output signal and the negative output signal is high, and thus a passive filter supporting a large signal frequency can be used to process the positive output signal and the negative output signal, and the passive filter supporting the large signal frequency has a low cost, so that the cost of the signal processing system can be reduced. BRIEF DESCRIPTION OF DRAWINGS

[0012] In order to more clearly illustrate the technical solutions of the embodiments of the present application or the prior art, the drawings needed in the embodiments or the prior art description will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments described in the embodiments of the present application, and other drawings can also be obtained by those skilled in the art based on these drawings.

[0013] FIG. 1 is a flowchart of a signal processing method according to an embodiment of the present application;

[0014] FIG. 2 is a flowchart of a PWM modulation method according to an embodiment of the present application;

[0015] FIG. 3 is a schematic diagram of a PWM positive signal and a PWM negative signal when the amplitude of an input signal is equal to 0 according to an embodiment of the present application;

[0016] FIG. 4 is a schematic diagram of a PWM positive signal and a PWM negative signal when the amplitude of an input signal is equal to 0 according to another embodiment of the present application;

[0017] Fig. 5 is a schematic diagram of the PWM positive signal and the PWM negative signal when the absolute value of the input signal amplitude is small in one embodiment of the present application;

[0018] Fig. 6 is a schematic diagram of the PWM positive signal and the PWM negative signal when the absolute value of the input signal amplitude is large in one embodiment of the present application;

[0019] Fig. 7 is a schematic diagram of the PWM positive signal and the PWM negative signal when the absolute value of the input signal amplitude is small in another embodiment of the present application;

[0020] Fig. 8 is a schematic diagram of the PWM positive signal and the PWM negative signal when the absolute value of the input signal amplitude is large in another embodiment of the present application;

[0021] Fig. 9 is a schematic diagram of the PWM positive signal and the PWM negative signal when the absolute value of the input signal amplitude is small in yet another embodiment of the present application;

[0022] Fig. 10 is a schematic diagram of the PWM positive signal and the PWM negative signal when the absolute value of the input signal amplitude is large in yet another embodiment of the present application;

[0023] Fig. 11 is a schematic diagram of the PWM positive signal and the PWM negative signal when the absolute value of the input signal amplitude is small in still another embodiment of the present application;

[0024] Fig. 12 is a schematic diagram of the PWM positive signal and the PWM negative signal when the absolute value of the input signal amplitude is large in still another embodiment of the present application;

[0025] Fig. 13 is a flow chart of a method for generating the PWM positive signal and the PWM negative signal in one embodiment of the present application;

[0026] Fig. 14 is a schematic diagram of the process for generating the PWM positive signal and the PWM negative signal in one embodiment of the present application;

[0027] Fig. 15 is a schematic diagram of a signal processing circuit in one embodiment of the present application;

[0028] Fig. 16 is a schematic diagram of a signal processing circuit in another embodiment of the present application;

[0029] Fig. 17 is a schematic diagram of a signal processing circuit in yet another embodiment of the present application;

[0030] Fig. 18 is a schematic diagram of an electronic device in one embodiment of the present application. DETAILED DESCRIPTION

[0031] In the following, the technical solutions in the embodiments of the present application will be described clearly and completely in conjunction with the drawings of the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments of the present application, all the other embodiments obtained by a person of ordinary skill in the art shall fall within the scope of protection of the present application.

[0032] The terminology used in this application is for the purpose of describing particular embodiments only and is not intended to be limiting of the present application. As used in this application and the appended claims, the singular forms "a," "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and / or "comprising," when used in this application and the appended claims, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0033] It should be understood that, although the terms first, second, third, etc. can be used herein to describe various information, these terms are not intended to denote a particular order or relationship. These terms are used only to distinguish one from another. For example, without departing from the scope of the present application, the first information can be referred to as the second information, and similarly, the second information can be referred to as the first information. Depending on the context, the word "if' as used herein can be interpreted as meaning "when" or "in response to determining."

[0034] For the purpose of making the purposes, technical solutions and advantages of the present application more clear, the embodiments of the present application will be described in further detail in conjunction with the drawings.

[0035] Signal processing method

[0036] Fig. 1 is a flow chart of a signal processing method according to an embodiment of the present application. As shown in Fig. 1, the signal processing method comprises the following steps:

[0037] Step 101, PWM modulating the input signal to obtain a PWM positive signal and a PWM negative signal.

[0038] The input signal can comprise a positive input signal and a negative input signal, and the input signal can be an analog signal. The PWM modulation of the input signal can be performed in multiple steps, such as coupling the differential mode signal of the positive input signal and the negative input signal comprised in the input signal to the input end of a loop filter unit, delivering the filtered signal to a comparison unit and a triangular wave for comparison after comparison, and then performing logic processing on the comparison result to obtain the PWM positive signal and the PWM negative signal.

[0039] The input signal can be an audio signal or other signal having a PWM modulation requirement.

[0040] Step 102, outputting a positive output signal and a negative output signal according to the PWM positive signal and the PWM negative signal.

[0041] After obtaining the PWM positive signal and the PWM negative signal, the PWM positive signal and the PWM negative signal can be processed, such as amplification, inversion, etc., to obtain the positive output signal and the negative output signal, and then the positive output signal and the negative output signal are output. In an example, when the input signal is an audio signal, the output positive output signal and the output negative output signal can be used to drive a loudspeaker after being filtered by a passive filter (such as LC filtering).

[0042] The pulse width of the PWM positive signal and the PWM negative signal is related to the absolute value of the amplitude of the input signal, and the positive output signal and the negative output signal are obtained based on the PWM positive signal and the PWM negative signal, so the pulse width of the pulses included in the positive output signal and the negative output signal is related to the absolute value of the amplitude of the input signal. Specifically, in response to the amplitude of the input signal not being equal to 0, the positive output signal and the negative output signal each include 2 pulses in a pulse period. It should be noted that including 2 pulses in a pulse period means that there are only 2 pulses in a pulse period.

[0043] The amplitude of the input signal refers to the amplitude of the differential mode signal of the positive input signal and the negative input signal, and the copy of the input signal can be positive, negative or 0. The signal strength of the input signal is positively correlated with the absolute value of its amplitude. It should be noted that for ease of description, the amplitude of the input signal described hereinafter refers to the amplitude of the input signal.

[0044] The positive output signal and the negative output signal can be generated by a power output module according to the PWM positive signal and the PWM negative signal. The pulse width of the differential mode signal of the positive output signal and the negative output signal matches the pulse width of the differential mode signal of the PWM positive signal and the PWM negative signal.

[0045] In an example, the period (frequency) of the positive output signal and the negative output signal is the same as the period (frequency) of the PWM positive signal and the PWM negative signal, and the period (frequency) of the PWM positive signal and the PWM negative signal is the same as the period (frequency) of the triangular wave. When the amplitude of the input signal is not equal to 0, the positive output signal and the negative output signal each include 2 pulses in a clock period, that is, the pulse frequency of the positive output signal and the negative output signal remains unchanged when the amplitude of the input signal is not equal to 0.

[0046] In the embodiment of the present application, the input signal is PWM modulated to obtain a PWM positive signal and a PWM negative signal, and a positive output signal and a negative output signal are output according to the PWM positive signal and the PWM negative signal. When the amplitude of the input signal is not equal to 0, the positive output signal and the negative output signal each include two pulses in a pulse period. That is, for any input signal with an amplitude not equal to 0, the corresponding positive output signal and negative output signal each include two pulses, so that the frequency of the positive output signal and the negative output signal is relatively high. Therefore, a passive filter supporting a relatively large signal frequency can be used to process the positive output signal and the negative output signal, and the passive filter supporting a relatively large signal frequency has a relatively low cost, thereby reducing the cost of the signal processing system.

[0047] The pulse width of the differential mode signal of the PWM positive signal and the PWM negative signal is positively correlated with the absolute value of the amplitude of the input signal. When the absolute value of the amplitude of the input signal is relatively small, the pulse width of the differential mode signal of the PWM positive signal and the PWM negative signal is relatively small. When the amplitude of the input signal is not equal to 0, the positive output signal and the negative output signal each include two pulses. That is, even when the absolute value of the amplitude of the input signal is relatively small, the power output module can respond to the differential mode signal of the PWM positive signal and the PWM negative signal, so as to ensure the suppression effect of the loop on noise and system nonlinearity, thereby ensuring the performance of the processed signal.

[0048] In a possible implementation, when the amplitude of the input signal is not equal to 0, the pulse width of the pulse included in one of the positive output signal and the negative output signal is equal to a preset pulse width threshold, and the pulse width of the pulse included in the other of the positive output signal and the negative output signal is greater than the pulse width threshold.

[0049] When the amplitude of the input signal is not equal to 0, if the positive output signal includes two pulses with a pulse width equal to the pulse width threshold in a pulse period, the negative output signal includes two pulses with a pulse width greater than the pulse width threshold in a pulse period. If the negative output signal includes two pulses with a pulse width equal to the pulse width threshold in a pulse period, the positive output signal includes two pulses with a pulse width greater than the pulse width threshold in a pulse period.

[0050] In an example, the pulse included in the positive output signal has the same pulse width as the pulse included in the PWM positive signal or the PWM negative signal, and the pulse included in the negative output signal has the same pulse width as the pulse included in the PWM positive signal or the PWM negative signal. In order to enable the power output module to generate the positive output signal and the negative output signal according to the PWM positive signal and the PWM negative signal, the pulse width of the pulse included in the PWM positive signal and the PWM negative signal needs to be greater than the minimum pulse width that the power output module can respond to. Therefore, the pulse width threshold is greater than the minimum pulse width that the power output module can respond to.

[0051] In the embodiment of the present application, when the amplitude of the input signal is not equal to 0, the positive output signal and the negative output signal each include 2 pulses in a pulse period, and the pulse width of the pulse included in one of the positive output signal and the negative output signal is equal to the pulse width threshold, and the pulse width of the pulse included in the other of the positive output signal and the negative output signal is greater than the pulse width threshold, so that the differential mode signal of the positive output signal and the negative output signal includes a pulse, thereby matching the differential mode signal of the positive output signal and the negative output signal with the input signal, and ensuring the reliability and accuracy of signal processing.

[0052] In a possible implementation, when the amplitude of the input signal is not equal to 0, the falling edge of each pulse included in the positive output signal is time-aligned with the falling edge of a corresponding pulse included in the negative output signal, wherein the pulses included in the positive output signal and the negative output signal are in one-to-one correspondence.

[0053] When the amplitude of the input signal is not equal to 0, the positive output signal includes a first pulse in time in front and a second pulse in time behind in a pulse period, and the negative output signal includes a third pulse in time in front and a fourth pulse in time behind in a pulse period, the falling edge of the first pulse is time-aligned with the falling edge of the third pulse, and the falling edge of the second pulse is time-aligned with the falling edge of the fourth pulse. If the pulse width of the first pulse and the second pulse is greater than the pulse width threshold, the pulse width of the third pulse and the fourth pulse is equal to the pulse width threshold, and if the pulse width of the first pulse and the second pulse is equal to the pulse width threshold, the pulse width of the third pulse and the fourth pulse is greater than the pulse width threshold.

[0054] The falling edge of each pulse included in the positive output signal is time-aligned with the falling edge of a pulse included in the negative output signal, so that the pulse width of the 2 pulse signals included in the common mode signal of the positive output signal and the negative output signal is equal to the pulse width threshold. For example, when the pulse width of the first pulse and the second pulse in the above example is equal to the pulse width threshold, the positive output signal is the common mode signal of the positive output signal and the negative output signal, and when the pulse width of the third pulse and the fourth pulse in the above example is equal to the pulse width threshold, the negative output signal is the common mode signal of the positive output signal and the negative output signal.

[0055] In the embodiment of the present application, if the absolute value of the amplitude of the input signal is small when the amplitude of the input signal is not equal to 0, the pulse width of the pulse included in the differential mode signal of the PWM positive signal and the PWM negative signal is small, in order to enable the power output module to respond to the PWM positive signal and the PWM negative signal, the PWM positive signal and the PWM negative signal are added with common mode signals including two pulses with the pulse width threshold, when the positive output signal and the negative output signal are generated based on the PWM positive signal and the PWM negative signal, the positive output signal and the negative output signal also include the common mode signals, so that the power output module can also respond to the PWM positive signal and the PWM negative signal when the amplitude of the input signal is small, and the suppression effect of the loop on noise and system nonlinearity is ensured.

[0056] In a possible implementation, at least one reverse processing is required in the process of obtaining the positive output signal and the negative output signal by processing the input signal, so that the output positive signal matches the positive input signal included in the input signal, and the output negative signal matches the negative input signal included in the input signal. In the process of generating the positive output signal and the negative output signal based on the input signal, the number of reverse processing is a count, such as 1 or 3 times of reverse processing.

[0057] Based on the reverse processing in the signal processing process, if the positive input signal is greater than the negative input signal, the positive output signal includes two pulses with the pulse width equal to the pulse width threshold in a pulse period, and the negative output signal includes two pulses with the pulse width greater than the pulse width threshold in a pulse period, if the positive input signal is less than the negative input signal, the positive output signal includes two pulses with the pulse width greater than the pulse width threshold in a pulse period, and the negative output signal includes two pulses with the pulse width equal to the pulse width threshold in a pulse period.

[0058] In the embodiment of the present application, when the positive input signal is greater than the negative input signal, the pulse width of the pulse included in the negative output signal is greater than the pulse width threshold, when the negative input signal is greater than the positive input signal, the pulse width of the pulse included in the positive output signal is greater than the pulse width threshold, that is, the positive input signal corresponds to the negative output signal and the negative input signal corresponds to the positive output signal through the reverse processing. Reverse processing in the process of generating the positive output signal and the negative output signal based on the input signal can ensure correct system operation and ensure system stability.

[0059] In a possible implementation, when the amplitude of the input signal is equal to 0, the positive output signal and the negative output signal each include one pulse in one pulse period, the pulse width of the pulses included by the positive output signal and the negative output signal is equal to the pulse width threshold, and the pulse width of the differential mode signal of the positive output signal and the negative output signal is equal to 0, that is, the differential mode signal of the positive output signal and the negative output signal does not include any pulse.

[0060] The differential mode signal of the positive output signal and the negative output signal matches the amplitude of the input signal, and when the amplitude of the input signal changes, the differential mode signal of the positive output signal and the negative output signal needs to change accordingly, so as to ensure the correctness of signal processing. When the amplitude of the input signal is equal to 0, the positive output signal and the negative output signal each include one pulse in one pulse period, and the pulse width of the differential mode signal of the positive output signal and the negative output signal is equal to 0, so as to ensure that the differential mode signal of the positive output signal and the negative output signal matches the input signal, and ensure the reliability and accuracy of signal processing.

[0061] When the amplitude of the input signal is equal to 0, the pulse width of the pulses included by the positive output signal and the negative output signal is equal to the pulse width threshold, and the pulse width threshold can be the minimum pulse width that the power output module can output in response to the PWM positive signal and the PWM negative signal. In this way, the power output module can output pulses, the suppression effect of the loop on noise and system nonlinearity is ensured, and the power consumption in the standby state is low.

[0062] In the embodiment of the present application, the number and pulse width of the pulses included in the common mode signal of the positive output signal and the negative output signal are negatively related to the efficiency of the signal processing, which can indicate the power consumption. When the amplitude of the input signal is equal to 0, the positive output signal and the negative output signal each include one pulse in each pulse period, so that the common mode signal of the positive output signal and the negative output signal includes a smaller number of pulses, thereby ensuring lower power consumption in the standby state. When the amplitude of the input signal is equal to 0, the positive output signal and the negative output signal each include one pulse, thereby ensuring that the feedback loop in the signal processing process can operate normally, thereby ensuring the performance of the signal processing. The feedback loop is composed of a loop filter unit, a comparison unit, a logic processing unit and a power output module. The differential mode signal of the positive input signal and the negative input signal is coupled to the input end of the loop filter unit, and is transmitted to the comparison unit and the triangular wave after the filtering processing, and then the comparison result is logically processed to obtain the PWM positive signal and the PWM negative signal. The power output module generates the positive output signal and the negative output signal based on the PWM positive signal and the PWM negative signal. The power output module feeds back the positive output signal and the negative output signal to the loop filter unit, and the loop filter unit filters the input positive input signal and negative input signal based on the feedback positive output signal and negative output signal.

[0063] In a possible implementation, the pulse width of the differential mode signal of the positive output signal and the negative output signal is positively related to the absolute value of the amplitude of the input signal.

[0064] In the embodiment of the present application, when the amplitude of the input signal is equal to 0, the pulse width of the differential mode signal of the positive output signal and the negative output signal is equal to 0. When the amplitude of the input signal is not equal to 0, the pulse width of the differential mode signal of the positive output signal and the negative output signal is greater than 0, and the pulse width of the differential mode signal of the positive output signal and the negative output signal is positively related to the absolute value of the amplitude of the input signal, thereby ensuring that the change of the input signal can be correctly reflected on the differential mode signal of the positive output signal and the negative output signal after the input signal is processed, thereby ensuring the accuracy and reliability of the signal processing.

[0065] In a possible implementation, the processing of the input signal can be based on a preset pulse width threshold. According to the absolute value of the amplitude of the input signal, the pulse width of the pulses included in the positive output signal and the negative output signal satisfies the following relationship with the pulse width threshold:

[0066] (1) When the amplitude of the input signal is equal to 0, the pulse width of the pulses included in the positive output signal and the negative output signal is equal to the pulse width threshold.

[0067] (2) When the amplitude of the input signal is not equal to 0, the pulse width of the pulse included in one of the positive output signal and the negative output signal is greater than the pulse width threshold, and the pulse width of the pulse included in the other of the positive output signal and the negative output signal is equal to the pulse width threshold.

[0068] When the amplitude of the input signal is equal to 0, the positive output signal and the negative output signal each include one pulse with a pulse width equal to the pulse width threshold, and the pulse width of the differential mode signal of the positive output signal and the negative output signal is equal to 0, that is, the rising edge and the falling edge of the pulses included in the positive output signal and the negative output signal are time-aligned, so that the differential mode signal of the positive output signal and the negative output signal matches the input signal, ensuring the accuracy of signal processing.

[0069] When the amplitude of the input signal is not equal to 0, the positive output signal and the negative output signal each include two pulses. When the pulse width of the two pulses included in the positive output signal is greater than the pulse width threshold, the pulse width of the two pulses included in the negative output signal is equal to the pulse width threshold, and when the pulse width of the two pulses included in the negative output signal is greater than the pulse width threshold, the pulse width of the two pulses included in the positive output signal is equal to the pulse width threshold. When the amplitude of the input signal is not equal to 0, the falling edge of each pulse included in the positive output signal is time-aligned with the falling edge of a corresponding pulse included in the negative output signal, so that the pulse width of the differential mode signal of the positive output signal and the negative output signal is not equal to 0, and as the absolute value of the amplitude of the input signal increases (decreases), the pulse width of the differential mode signal of the positive output signal and the negative output signal correspondingly increases (decreases), so that the differential mode signal of the positive output signal and the negative output signal matches the input signal, ensuring the accuracy of signal processing.

[0070] In the embodiments of the present application, the pulse width of the pulses included in the positive output signal and the negative output signal is related to the preset pulse width threshold, and the performance of the output signal is related to the pulse width of the pulses included in the positive output signal and the negative output signal. A suitable pulse width threshold can be set according to the requirement for the performance of the output signal, such as the pulse width threshold can be 1 / 40 to 1 / 10 of the period of a triangular wave. On the premise of meeting the requirement for the performance of the output signal, a smaller delay duration is set, so that the pulse width of the pulses included in the positive output signal and the negative output signal is smaller when the amplitude of the input signal is equal to 0, thereby reducing standby power consumption.

[0071] In a possible implementation, when the input signal is PWM modulated, a square wave signal can be generated based on the input signal, and then PWM positive signals and PWM negative signals can be generated based on the generated square wave signal and the pulse width threshold. As shown in the flowchart of the PWM modulation method in FIG. 2, the input signal can be PWM modulated by a method including the following steps:

[0072] Step 201, filtering the input signal to obtain a first positive signal and a first negative signal.

[0073] The input signal includes a positive input signal and a negative input signal. By filtering the positive input signal and the negative input signal, the first positive signal and the first negative signal can be obtained. For example, the differential mode signal of the positive input signal and the negative input signal is coupled to the input end of the loop filter unit, and the positive input signal and the negative input signal are filtered by the loop filter unit to obtain the first positive signal and the first negative signal.

[0074] In one example, the loop filter unit does not perform reverse processing at its output end, the waveform of the first positive signal matches the waveform of the positive input signal, and the waveform of the first negative signal matches the waveform of the negative input signal.

[0075] In another example, the loop filter unit performs reverse processing at its output end, the waveform of the first positive signal matches the waveform of the negative input signal, and the waveform of the first negative signal matches the waveform of the positive input signal. The output end of the loop filter unit outputs the first positive signal and the first negative signal.

[0076] Step 202, comparing the first positive signal and the first negative signal with a triangular wave to generate a second positive signal and a second negative signal according to the comparison result.

[0077] After obtaining the first positive signal and the first negative signal, the first positive signal and the first negative signal can be input to the comparison unit, and the comparison unit compares the first positive signal and the first negative signal with the triangular wave respectively, generates the second positive signal according to the comparison result of the first positive signal and the triangular wave, and generates the second negative signal according to the comparison result of the first negative signal and the triangular wave.

[0078] When the comparison unit compares the first positive signal and the first negative signal with the triangular wave, the second positive signal / second negative signal is determined according to the size relationship between the first positive signal / first negative signal and the triangular wave.

[0079] In one example, as shown in the schematic diagram of the second positive signal and the second negative signal in FIG. 3, the first positive signal IN+ (the first negative signal IN-) is greater than the signal segment of the triangular wave, which corresponds to the high level of the second positive signal CMP+ (the second negative signal CMP-), and the first positive signal IN+ (the first negative signal IN-) is less than the signal segment of the triangular wave, which corresponds to the low level of the second positive signal CMP+ (the second negative signal CMP-).

[0080] In another example, as shown in the schematic diagram of the second positive signal and the second negative signal in FIG. 4, the first positive signal IN+ (the first negative signal IN-) greater than the signal segment of the triangular wave corresponds to the low level of the second positive signal CMP+ (the second negative signal CMP-), and the first positive signal IN+ (the first negative signal IN-) less than the signal segment of the triangular wave corresponds to the high level of the second positive signal CMP+ (the second negative signal CMP-).

[0081] It should be noted that FIG. 3 and FIG. 4 show the triangular wave of two pulse periods. For the convenience of the description, in the subsequent embodiments, the first positive signal is denoted as IN+, the first negative signal is denoted as IN-, the second positive signal is denoted as CMP+, the second negative signal is denoted as CMP-, the PWM positive signal is denoted as PWM+, and the PWM negative signal is denoted as PWM-.

[0082] When the IN+ and IN- signals are compared with the triangular wave to generate the CMP+ and CMP- signals, the reverse processing can be performed or not. In the case of not performing the reverse processing, the waveforms of the CMP+ and CMP- signals are shown in FIG. 3, and in the case of performing the reverse processing, the waveforms of the CMP+ and CMP- signals are shown in FIG. 4. Whether the reverse processing is performed when the CMP+ and CMP- signals are generated can be set according to the application scene requirement, so as to meet different requirements and improve the applicability of the signal processing method in the embodiments of the present application.

[0083] In step 203, the PWM positive signal and the PWM negative signal are generated according to the second positive signal, the second negative signal, and the pulse width threshold.

[0084] After the second positive signal and the second negative signal are generated, the second positive signal and the second negative signal can be logically processed based on the pulse width threshold, and then the PWM positive signal and the PWM negative signal are generated.

[0085] In the embodiments of the present application, the positive output signal and the negative output signal are generated based on the PWM positive signal and the PWM negative signal, and the PWM positive signal and the PWM negative signal are generated based on the second positive signal, the second negative signal, and the pulse width threshold. The PWM positive signal and the PWM negative signal are not generated in a feedback manner through a complex feedback network, so that the signal processing is simpler, the loop of the entire system is simpler, and the common-mode pulse width of PWM+ and PWM- is determined by the delay unit generating the pulse width threshold, and the fluctuation of the power supply voltage has less effect on the common-mode pulse width of PWM+ and PWM-.

[0086] In a possible implementation, when the amplitude of the input signal is equal to 0, the PWM positive signal and the PWM negative signal each include one pulse with a pulse width equal to the pulse width threshold in one pulse period, and the falling edges of the pulses included in the PWM positive signal and the PWM negative signal are time-aligned with the falling edges of the pulses included in the second positive signal and the second negative signal.

[0087] The pulses included in the second positive signal and the second negative signal can be low or high. In the second positive signal and the second negative signal, if the pulse is low, the leading edge of the pulse is the falling edge, and the trailing edge of the pulse is the rising edge; if the pulse is high, the leading edge of the pulse is the rising edge, and the trailing edge of the pulse is the falling edge. The PWM positive signal and the PWM negative signal are described below by taking the pulses included in the second positive signal (the second negative signal) as low or high as an example.

[0088] When no reverse processing is performed in generating the CMP+ and the CMP-, the PWM positive signal and the PWM negative signal are as shown in FIG. 3, the pulses included in the CMP+ and the CMP- are low, the pulses included in the PWM+ and the PWM- are high, the differential mode signal Diff of the CMP+ and the CMP- does not include a pulse, the falling edges of the pulses included in the PWM+ and the PWM- are time-aligned with the falling edges (leading edges) of the pulses included in the CMP+ and the CMP-, and the pulse widths of the pulses included in the PWM+ and the PWM- are each equal to the pulse width threshold T c .

[0089] When reverse processing is performed in generating the CMP+ and the CMP-, the PWM positive signal and the PWM negative signal are as shown in FIG. 4, the pulses included in the CMP+ and the CMP- are high, the pulses included in the PWM+ and the PWM- are high, the differential mode signal Diff of the CMP+ and the CMP- does not include a pulse, the falling edges of the pulses included in the PWM+ and the PWM- are time-aligned with the falling edges (trailing edges) of the pulses included in the CMP+ and the CMP-, and the pulse widths of the pulses included in the PWM+ and the PWM- are each equal to the pulse width threshold T c .

[0090] It should be noted that FIG. 3 and FIG. 4 show the PWM+ and the PWM- in two pulse periods.

[0091] In this embodiment, when the amplitude of the input signal is equal to 0, the pulse widths of the pulses included in the positive and negative PWM signals are equal to the pulse width threshold. Furthermore, the falling edges of the pulses included in both the positive and negative PWM signals are time-aligned with the falling edges of the pulses included in the second positive and second negative signals. This ensures that the differential mode signals of the positive and negative PWM signals do not contain any pulses, thus matching the differential mode signals of the positive and negative PWM signals with the input signal and guaranteeing the accuracy of signal processing. Additionally, by setting a smaller pulse width threshold, the pulse widths of the pulses included in the positive and negative PWM signals when the amplitude of the input signal is equal to 0 can be smaller, reducing standby power consumption while maintaining the suppression effect on loop nonlinearity and noise.

[0092] In one possible implementation, when the amplitude of the input signal is not equal to 0, both the positive and negative PWM signals consist of two pulses, and the falling edges of the two pulses in the positive PWM signal are time-aligned with the falling edges of the two pulses in the negative PWM signal. Based on the magnitude relationship between the first positive and first negative signals, the pulse widths of the differential signals of the positive and negative PWM signals are different.

[0093] No reverse processing is performed during the generation of CMP+ and CMP-. That is, when the pulses included in CMP+ and CMP- are low-level, if the amplitude of the input signal is not equal to 0, and IN+ is greater than IN-, then PWM+ and PWM- are as shown in Figures 5 and 6. Figure 5 shows the waveforms of PWM+ and PWM- when the absolute value of the input signal amplitude is small, and Figure 6 shows the waveforms of PWM+ and PWM- when the input signal amplitude is not equal to a large value. Referring to Figures 5 and 6, the pulses included in CMP+ and CMP- are low-level, and the pulses included in PWM+ and PWM- are high-level. The pulse widths of the two pulses included in PWM+ are T... diff1 +T c and T diff2 +T c PWM includes two pulses, both with a pulse width of T. c PWM+ includes a pulse width of T. diff1 +T c The rising edge of the pulse is aligned with the falling edge of the pulse included in CMP-, and the pulse width included in PWM+ is T. diff2 +T c The rising edge of the pulse is timed to the rising edge of the pulse included in CMP+. The rising edge of one pulse included in PWM- is timed to the falling edge of the pulse included in CMP+, and the rising edge of another pulse included in PWM- is timed to the rising edge of the pulse included in CMP-.

[0094] In the generation of CMP+ and CMP-, no reverse processing is performed, i.e. if the amplitude of the input signal is not equal to 0 and IN+ is less than IN- when the pulses included in CMP+ and CMP- are low, PWM+ and PWM- are as shown in Figs. 7 and 8. Fig. 7 shows the waveforms of PWM+ and PWM- when the absolute value of the amplitude of the input signal is small, and Fig. 8 shows the waveforms of PWM+ and PWM- when the absolute value of the amplitude of the input signal is large. Referring to Figs. 7 and 8, the pulses included in CMP+ and CMP- are low, the pulses included in PWM+ are high, the pulse width of the two pulses included in PWM+ is T c , the pulse width of the two pulses included in PWM- is T diff1 +T c and T diff2 +T c , respectively. The rising edge of the pulse included in PWM- with the pulse width of T diff1 +T c is time-aligned with the falling edge of the pulse included in CMP+, and the rising edge of the pulse included in PWM- with the pulse width of T diff2 +T c is time-aligned with the rising edge of the pulse included in CMP-. The rising edge of one of the pulses included in PWM+ is time-aligned with the falling edge of the pulse included in CMP-, and the rising edge of the other pulse included in PWM+ is time-aligned with the rising edge of the pulse included in CMP+.

[0095] It should be noted that, as shown in Figs. 6 and 8, when the absolute value of the amplitude of the input signal is large to a certain value, the two pulses included in PWM+ or PWM- with the pulse width of T diff1 +T c and T diff2 +T c may partially overlap, at this time, PWM+ or PWM- actually includes one pulse with the pulse width greater than T c , at this time, the output power is slightly limited, and the limiting effect on the output power is enhanced with the increase of T c , especially at high switching frequency, the limiting effect on the output power is more obvious, therefore, a smaller T c is required.

[0096] The generation of CMP+ and CMP- is reversed. That is, when the pulses included in CMP+ and CMP- are high-level, if the amplitude of the input signal is not equal to 0, and IN+ is greater than IN-, then PWM+ and PWM- are as shown in Figures 9 and 10. Figure 9 shows the waveforms of PWM+ and PWM- when the absolute value of the input signal amplitude is small, and Figure 10 shows the waveforms of PWM+ and PWM- when the absolute value of the input signal amplitude is large. Referring to Figures 9 and 10, the pulses included in CMP+ and CMP- are high-level, the pulses included in PWM+ and PWM- are high-level, and the pulse width of both pulses included in PWM+ is T. c PWM includes two pulses with pulse widths T and T, respectively. diff1 +T c and T diff2 +T c PWM includes pulse widths of T. diff1 +T c The rising edge of the pulse is aligned with the rising edge timing of the pulse included in CMP, and the pulse width included in PWM is T. diff2 +T c The rising edge of the pulse is timed to the falling edge of the pulse included in CMP+. The rising edge of one pulse included in PWM+ is timed to the rising edge of the pulse included in CMP+, and the rising edge of another pulse included in PWM+ is timed to the falling edge of the pulse included in CMP-.

[0097] The generation of CMP+ and CMP- is reversed. That is, when the pulses included in CMP+ and CMP- are high-level, if the amplitude of the input signal is not equal to 0, and IN+ is less than IN-, then PWM+ and PWM- are as shown in Figures 11 and 12. Figure 11 shows the waveforms of PWM+ and PWM- when the absolute value of the input signal amplitude is small, and Figure 12 shows the waveforms of PWM+ and PWM- when the absolute value of the input signal amplitude is large. Referring to Figures 11 and 12, the pulses included in CMP+ and CMP- are high-level, and the pulses included in PWM+ and PWM- are high-level. The pulse widths of the two pulses included in PWM+ are T... diff1 +T c and T diff2 +T c PWM includes two pulses, both with a pulse width of T. c PWM+ includes a pulse width of T. diff1 +T c The rising edge of the pulse is aligned with the rising edge timing of the pulse included in CMP+, and the pulse width included in PWM+ is T. diff2 +T cthe rising edge of one pulse of PWM- is time-aligned with the falling edge of a pulse of CMP+, and the rising edge of another pulse of PWM- is time-aligned with the rising edge of a pulse of CMP-.

[0098] It is noted that Figures 5-12 show two pulse periods of PWM+ and PWM-, Diff is used to represent the differential mode signal of CMP+ and CMP-, T diff1 and T diff2 is used to represent the pulse width of one pulse of PWM+.

[0099] Without inverting the process of generating CMP+ and CMP-, if IN+ is greater than IN- when the amplitude of the input signal is not equal to 0, see Figures 5 and 6, as the absolute value of the amplitude of the input signal increases, T diff1 and T diff2 increase, the pulse width of a pulse of PWM+ starts to increase from T c , the pulse width of a pulse of PWM- remains T c unchanged, and the sum of the pulse width of a pulse of the differential mode signal of PWM+ and PWM- is equal to T diff1 + T diff2 .

[0100] Without inverting the process of generating CMP+ and CMP-, if IN+ is less than IN- when the amplitude of the input signal is not equal to 0, see Figures 7 and 8, as the absolute value of the amplitude of the input signal increases, T diff1 and T diff2 increase, the pulse width of a pulse of PWM+ remains T c unchanged, the pulse width of a pulse of PWM- starts to increase from T c , and the sum of the pulse width of a pulse of the differential mode signal of PWM+ and PWM- is equal to T diff1 + T diff2 .

[0101] With inverting the process of generating CMP+ and CMP-, if IN+ is greater than IN- when the amplitude of the input signal is not equal to 0, see Figures 9 and 10, as the absolute value of the amplitude of the input signal increases, T diff1 and T diff2 increase, the pulse width of a pulse of PWM+ remains T c unchanged, the pulse width of a pulse of PWM- starts to increase from T c , and the sum of the pulse width of a pulse of the differential mode signal of PWM+ and PWM- is equal to T diff1 + T diff2 .

[0102] When the generation of CMP+ and CMP- is reversed, if the amplitude of the input signal is not equal to 0, and if IN+ is less than IN- (see Figures 11 and 12), as the absolute value of the input signal amplitude increases, T... diff1 and T diff2 Increase, PWM+ includes pulse width from T c Start increasing, PWM - the pulse width of the included pulse remains T c The sum of the pulse widths of the differential signals in PWM+ and PWM- remains unchanged and equal to T. diff1 +T diff2 .

[0103] In this embodiment, when the amplitude of the input signal is not equal to 0, both PWM+ and PWM- include 2 pulses, and the sum of the pulse widths of the differential mode signals of PWM+ and PWM- is equal to T. diff1 +T diff2 When the absolute value of the input signal amplitude changes, T diff1 +T diff2 The corresponding changes in the input signal are reflected in the differential signals of PWM+ and PWM-, thus ensuring the accuracy of signal processing. Furthermore, the pulses included in PWM+ and PWM- are both greater than or equal to T. c This enables the power output module to respond to all PWM+ and PWM- outputs, thereby ensuring the suppression of loop nonlinearity and noise.

[0104] In one possible implementation, based on CMP+, CMP-, and the pulse width threshold T c When generating PWM+ and PWM-, CMP+ and CMP- can be reverse-delayed and then logically processed to obtain PWM+ and PWM-. Figure 13 shows a flowchart of a method for generating PWM+ and PWM- according to an embodiment of this application. As shown in Figure 13, the method includes the following steps:

[0105] Step 1301: After delaying the second positive signal for a preset delay time, perform logical NOT processing to obtain the first delayed reverse signal;

[0106] Step 1302: Perform a logical OR-NOT operation on the first delayed inverse signal and the second negative signal to obtain the third positive signal;

[0107] Step 1303: Increase the pulse width threshold backward in the pulse width timing sequence of the pulses included in the third positive signal to obtain the fourth positive signal;

[0108] Step 1304: After delaying the second negative signal for a preset delay time, perform logical NOT processing to obtain the second delayed reverse signal;

[0109] Step 1305, performing logic or or-not processing on the second delay reverse signal and the second forward signal to obtain a third negative signal;

[0110] Step 1306, increasing the pulse width timing of the pulse included in the third negative signal by a pulse width threshold in the backward direction to obtain a fourth negative signal;

[0111] Step 1307, performing logic or processing on the fourth forward signal and the fourth negative signal to obtain a fifth signal;

[0112] Step 1308, performing logic or processing on the third forward signal and the fifth signal to obtain a PWM forward signal;

[0113] Step 1309, performing logic or processing on the third negative signal and the fifth signal to obtain a PWM negative signal.

[0114] It should be noted that steps 1301 to 1303 are sequentially executed, steps 1304 to 1306 are sequentially executed, and steps 1301 to 1303 can be executed synchronously with steps 1304 to 1306.

[0115] When the amplitude of the input signal is equal to 0, the differential mode signal of CMP+ and CMP- does not include a pulse, and by performing logic or or-not processing on CMP+ and CMP-, a first delay reverse signal and a second delay reverse signal are generated after a delay of a preset delay time, the first delay reverse signal and the second delay reverse signal are trigger signals of the common mode pulse width when the amplitude of the input signal is equal to 0, so that based on the first delay reverse signal and the second delay reverse signal, PWM+ and PWM- can include a pulse with a pulse width equal to the pulse width threshold T c , ensuring that the feedback loop can operate normally in the signal processing process, thereby ensuring the performance of the signal processing.

[0116] When the amplitude of the input signal is not equal to 0, the differential mode signal of CMP+ and CMP- includes a pulse, so the delay time is set to generate trigger signals of the common mode pulse width when the amplitude of the input signal is equal to 0, so a smaller delay time can meet the requirements, and the delay time can be in the range of [1ns, 10ns], for example, the delay time can be set to 5ns, where ns is nanosecond.

[0117] FIG. 14 shows a schematic diagram of a PWM+ and PWM- generation process according to an embodiment of the present application. As shown in FIG. 14, the PWM+ and PWM- generation process includes a differential mode pulse width extraction process, a common mode pulse width generation process, and an output pulse width generation process.

[0118] The differential mode pulse width extraction process includes differential mode pulse width extraction on CMP+ and CMP- to obtain a forward differential mode signal DM+ and a negative differential mode signal DM-.

[0119] The common-mode pulse width generation process comprises generating a common-mode pulse width, obtaining a positive common-mode signal CM+ and a negative common-mode signal CM-.

[0120] The output pulse width generation process comprises generating a PWM signal according to the positive differential-mode signal DM+, the negative differential-mode signal DM-, the positive common-mode signal CM+, the negative common-mode signal CM- and a preset pulse width threshold, and obtaining PWM+ and PWM-.

[0121] In the embodiments of the present application, the positive differential-mode signal DM+ and the negative differential-mode signal DM- are obtained by extracting differential-mode pulse widths based on CMP+ and CMP-, the positive common-mode signal CM+ and the negative common-mode signal CM- are generated by a common-mode pulse width generation process, and then PWM+ and PWM- are generated based on the positive differential-mode signal DM+, the negative differential-mode signal DM-, the positive common-mode signal CM+, the negative common-mode signal CM- and a preset pulse width threshold. Since there is no need to detect the differential-mode pulse width, the signal processing process is simple, and the quality and efficiency of signal processing are guaranteed.

[0122] In a possible implementation, the pulse width threshold T c is in the range of [T / 40, T / 10], where T represents the length of a pulse period. For example, the delay length can be T / 40, T / 30, T / 20, T / 10, etc.

[0123] It should be noted that the pulse width threshold can be a preset fixed value or dynamically changed. For example, when the input signal is an analog signal or a digital signal, the pulse width threshold is a preset fixed value. When the input signal is a digital signal, the pulse width threshold can be dynamically adjusted according to the power of the input signal, so as to balance the performance of the output signal and the efficiency of signal processing.

[0124] In an example, the delay length is matched with the frequency of the triangular wave. For example, when the frequency of the triangular wave is large, a smaller delay length can be set, and when the frequency of the triangular wave is small, a larger delay length can be set.

[0125] In the embodiments of the present application, when the amplitude of the input signal is equal to 0, the pulse width of the common-mode signal included in PWM+ and PWM- is negatively related to the signal processing efficiency, and at the same time, when the pulse width of the pulses included in PWM+ and PWM- is too small, the power output module cannot respond. Therefore, the pulse width of the pulses included in PWM+ and PWM- when the amplitude of the input signal is equal to 0 is determined by the pulse width threshold. Therefore, the value range of the pulse width threshold is set to [T / 40, T / 10], so as to ensure that the power output module can respond to the pulses included in PWM+ and PWM- when the amplitude of the input signal is equal to 0, and at the same time, ensure low power consumption in the standby state.

[0126] In a possible implementation, when the positive and negative output signals are output according to the PWM+ and the PWM-, the amplitude of the PWM+ can be amplified to obtain the negative output signal, and the amplitude of the PWM- can be amplified to obtain the positive output signal, or the amplitude of the PWM+ can be amplified to obtain the positive output signal, and the amplitude of the PWM- can be amplified to obtain the negative output signal.

[0127] The amplification of the amplitudes of the PWM+ and the PWM- refers to the amplification of the amplitudes of the pulses included in the PWM+ and the PWM-, without changing the number, the rising edge position, and the falling edge position of the pulses included in the PWM+ and the PWM-. For example, the voltage corresponding to the pulses included in the PWM+ is 5V, and the amplitude of the PWM+ is amplified to 20V to obtain the positive or negative output signal.

[0128] When the positive and negative output signals are output according to the PWM+ and the PWM-, the reverse processing can be performed or not be performed. If the reverse processing is performed, the negative output signal is obtained by amplifying the amplitude of the PWM+, and the positive output signal is obtained by amplifying the amplitude of the PWM-. If the reverse processing is not performed, the positive output signal is obtained by amplifying the amplitude of the PWM+, and the negative output signal is obtained by amplifying the amplitude of the PWM-.

[0129] It should be noted that the reverse processing is required once in the process of obtaining the positive and negative output signals by processing the input signal. The reverse processing can be performed in the process of generating the IN+ and the IN- according to the input signal, in the process of generating the CMP+ and the CMP- according to the IN+ and the IN-, in the process of generating the PWM+ and the PWM- according to the CMP+ and the CMP-, or in the process of generating the positive and negative output signals according to the PWM+ and the PWM-. The foregoing embodiments describe the process of performing the reverse processing in the process of generating the CMP+ and the CMP- according to the IN+ and the IN-. The implementation of performing the reverse processing in the process of generating the IN+ and the IN- according to the input signal, in the process of generating the PWM+ and the PWM- according to the CMP+ and the CMP-, or in the process of generating the positive and negative output signals according to the PWM+ and the PWM- is similar to the process of performing the reverse processing in the process of generating the CMP+ and the CMP- according to the IN+ and the IN-, and details are not described herein.

[0130] In the embodiments of the present application, when the positive and negative output signals are output according to the PWM+ and PWM-, the positive and negative output signals are obtained by amplifying the amplitudes of the PWM+ and PWM- so that the positive and negative output signals can drive devices such as a loudspeaker. The reverse processing can be performed or not performed in the process of outputting the positive and negative output signals according to the PWM+ and PWM-, thereby meeting the needs of different application scenarios and improving the applicability of the signal processing method in the embodiments of the present application.

[0131] In a possible implementation, the input signal can be an audio signal, and the positive and negative output signals can be used to drive a loudspeaker, and the loudspeaker is used to play the audio signal after signal processing. In an example, the positive output signal can be input to the positive terminal of the loudspeaker, and the negative output signal can be input to the negative terminal of the loudspeaker.

[0132] In the embodiments of the present application, the audio signal is processed by the signal processing method in the foregoing embodiments, which can make the efficiency of audio signal processing higher. While improving the efficiency, the entire audio system does not need to use advanced technology. By optimizing the number of switching and the switching mode, the efficiency of signal processing can also be improved on the audio system using ordinary technology.

[0133] Signal processing circuit

[0134] FIG. 15 shows a schematic diagram of a signal processing circuit according to an embodiment of the present application. As shown in FIG. 15, the signal processing circuit 150 includes a modulation module 151 and a power output module 152. The modulation module 151 is configured to perform PWM modulation on an input signal to obtain a PWM positive signal and a PWM negative signal. The power output module 152 is configured to output a positive output signal and a negative output signal according to the PWM positive signal and the PWM negative signal. In response to the amplitude of the input signal being not equal to 0, the positive output signal and the negative output signal each include two pulses in one pulse period.

[0135] In the embodiment of the present application, the modulation module 151 performs PWM modulation on the input signal to obtain a PWM positive signal and a PWM negative signal, and the power output module 152 outputs a positive output signal and a negative output signal according to the PWM positive signal and the PWM negative signal. When the amplitude of the input signal is not equal to 0, the positive output signal and the negative output signal each include two pulses in a pulse period, that is, for any input signal with an amplitude not equal to 0, the corresponding positive output signal and negative output signal each include two pulses, so that the frequency of the positive output signal and the negative output signal is relatively high, thereby the passive filter supporting a relatively large signal frequency can be used to process the positive output signal and the negative output signal, and the passive filter supporting a relatively large signal frequency has a relatively low cost, thereby the cost of the signal processing system can be reduced.

[0136] Since the pulse width of the differential mode signal of the PWM positive signal and the PWM negative signal is positively correlated with the absolute value of the amplitude of the input signal, the pulse width of the differential mode signal of the PWM positive signal and the PWM negative signal is small when the absolute value of the amplitude of the input signal is small. When the amplitude of the input signal is not equal to 0, the positive output signal and the negative output signal each include two pulses, so that the power output module can respond to the differential mode signal of the PWM positive signal and the PWM negative signal even when the absolute value of the amplitude of the input signal is small, and the suppression effect of the loop on noise and system nonlinearity is ensured, thereby the performance of the processed signal is ensured.

[0137] In a possible implementation, as shown in FIG. 16, the signal processing circuit 150 includes a loop filter unit 1511, a comparison unit 1512, and a logic processing unit 1513.

[0138] The loop filter unit 1511 is configured to perform filtering processing on the input signal to obtain a first positive signal and a first negative signal.

[0139] The comparison unit 1512 is configured to compare the first positive signal and the first negative signal with a triangular wave signal, and generate a second positive signal and a second negative signal according to a comparison result, where the period of the triangular wave is equal to a pulse period, and the second positive signal and the second negative signal are both square wave signals.

[0140] The logic processing unit 1513 is configured to generate a PWM positive signal and a PWM negative signal according to the second positive signal, the second negative signal, and a pulse width threshold.

[0141] The positive output signal and the negative output signal output by the power output module 152 can be fed back to the loop filter unit 1511, and the loop filter unit 1511 performs filtering processing on the positive input signal and the negative input signal based on the signal fed back by the power output module 152, to realize loop filtering.

[0142] In a possible implementation, as shown in FIG. 17, the signal processing circuit 150 includes a logic processing unit 1513, which includes a differential signal extraction subunit 171, a pulse width adjustment subunit 172, and a signal processing subunit 173.

[0143] The differential signal extraction subunit 171 is configured to perform logic NOT processing on the second forward signal, delay the second forward signal by a preset delay time length, obtain a first delay reverse signal, perform logic OR NOT processing on the first delay reverse signal and the second reverse signal, obtain a third forward signal, perform logic NOT processing on the second reverse signal, delay the second reverse signal by the preset delay time length, obtain a second delay reverse signal, and perform logic OR NOT processing on the second delay reverse signal and the second forward signal, to obtain a third reverse signal.

[0144] The pulse width adjustment subunit 172 is configured to increase the pulse width timing of a pulse included in the third forward signal by a pulse width threshold in the backward direction, to obtain a fourth forward signal, and increase the pulse width timing of a pulse included in the third reverse signal by the pulse width threshold in the backward direction, to obtain a fourth reverse signal.

[0145] The signal processing subunit 173 is configured to perform logic OR processing on the fourth forward signal and the fourth reverse signal, to obtain a fifth signal, perform logic OR processing on the third forward signal and the fifth signal, to obtain a PWM forward signal, and perform logic OR processing on the third reverse signal and the fifth signal, to obtain a PWM reverse signal.

[0146] In a possible implementation, the logic processing unit 1513 is configured to perform the following processing:

[0147] performing differential mode pulse width extraction on the second forward signal and the second reverse signal, to obtain a forward differential mode signal and a reverse differential mode signal;

[0148] performing common mode pulse width generation, to obtain a forward common mode signal and a reverse common mode signal;

[0149] performing PWM signal generation according to the forward differential mode signal, the reverse differential mode signal, the forward common mode signal, the reverse common mode signal, and a pulse width threshold, to obtain a PWM forward signal and a PWM reverse signal.

[0150] It should be noted that the signal processing circuit in the embodiments of the present application is configured to perform the signal processing method in the foregoing embodiments, and is based on the same concept as the foregoing signal processing method embodiments. For details and advantages, refer to the descriptions in the foregoing signal processing method embodiments, which will not be repeated here.

[0151] Signal processing chip

[0152] An embodiment of the present application provides a signal processing chip, which is used for executing the signal processing method in any of the foregoing embodiments, and can comprise the signal processing circuit 150 in any of the foregoing embodiments, i.e., the signal processing circuit 150 in the foregoing embodiments is packaged in a chip, and the signal processing chip can be arranged in an electronic device having a signal processing requirement such as an audio signal or a power supply signal, and is used for signal processing.

[0153] It should be noted that the signal processing chip in the embodiments of the present application is used for executing the signal processing method in the foregoing embodiments, and is based on the same concept as the foregoing signal processing method, and the specific content and advantages can be referred to the description of the foregoing signal processing method embodiments, which will not be described here.

[0154] Electronic device

[0155] FIG. 18 shows a schematic diagram of an electronic device according to an embodiment of the present application. As shown in FIG. 18, the electronic device 180 comprises a signal source 181, a signal receiving end 182 and a signal processing apparatus 183, and the signal processing apparatus 183 can comprise the signal processing circuit 150 or the signal processing chip in any of the foregoing embodiments.

[0156] The signal processing apparatus 183 is connected between the signal source 181 and the signal receiving end 182, the signal source 181 is used for transmitting an input signal to the signal processing apparatus 183, and the signal receiving end 182 is used for receiving a positive output signal and a negative output signal output by the signal processing apparatus 183.

[0157] The input signal transmitted by the signal source 181 to the signal processing apparatus 183 can be an audio signal, and after receiving the positive output signal and the negative output signal, the signal receiving end 182 can transmit the positive output signal and the negative output signal to a loudspeaker after LC filtering, so as to drive the loudspeaker to emit sound.

[0158] It should be noted that the electronic device in the embodiments of the present application is implemented based on the signal processing circuit 150 or the signal processing chip in the foregoing embodiments, and the specific application of the signal processing circuit 150 and the signal processing chip in the foregoing embodiments can be referred to the description of the foregoing signal processing unit embodiments and the signal processing chip embodiments, which will not be described here.

[0159] It should be understood that each embodiment in the specification is described in a progressive manner, and the same or similar parts between each embodiment can be referred to each other, and each embodiment mainly describes the difference from other embodiments. Especially for the method embodiments, since they are basically similar to the methods described in the device and system embodiments, the description is relatively simple, and the relevant parts can be referred to the description of other embodiments.

[0160] It should be understood that the foregoing description is only illustrative of the embodiments of the application. Various alternatives and modifications can be practiced within the scope of the claims. It is intended that the following claims cover all such alternatives and modifications as falling within the true scope of the application. In some cases, the actions recited in the claims can be performed in a different order and still achieve desirable results.

[0161] It is to be understood that the singular forms "a," "an," and "the" include plural referents unless the context clearly dictates otherwise. Pronouns in the masculine form include the feminine form, and vice versa, except as otherwise expressly specifically. The term "plurality" means two or more. The term "another" means one or more. The term "comprising" means "including, but not limited to." It is further to be understood that all the relationships, combinations and / or elements described herein are illustrative only and that any relationship, combination and / or element can be employed in accordance with the present application.

[0162] It is also to be understood that the terminology and phraseology employed herein are for the purpose of description and should not be regarded as limiting. The use of "including" and "comprising" and variations thereof is intended to cover both qualified and unqualified numbers in the claims. The recitation of "at least one" is intended to mean "one or more" in the claims. The use of "at least one" is intended to cover both qualified and unqualified numbers in the claims. The use of "one or more" is intended to mean "at least one" in the claims. The use of "including" and "comprising" and variations thereof is intended to cover both qualified and unqualified numbers in the claims. The use of "including" and "comprising" and variations thereof is intended to cover both qualified and unqualified numbers in the claims.

Claims

1. A signal processing method, characterized by, The method comprises: performing PWM modulation on the input signal to obtain a PWM positive signal and a PWM negative signal; outputting a positive output signal and a negative output signal according to the PWM positive signal and the PWM negative signal; wherein, in response to the amplitude of the input signal not being equal to 0, the positive output signal and the negative output signal each comprise 2 pulses in one pulse period.

2. The method of claim 1, wherein, when the amplitude of the input signal is not equal to 0, the pulse width of the pulse included in one of the positive output signal and the negative output signal is equal to a preset pulse width threshold, and the pulse width of the pulse included in the other of the positive output signal and the negative output signal is greater than the pulse width threshold.

3. The method of claim 2, wherein, when the amplitude of the input signal is not equal to 0, the falling edge of the pulse included in the positive output signal is time-aligned with the falling edge of the pulse included in the negative output signal.

4. The method of claim 2, wherein, the input signal comprises a positive input signal and a negative input signal, if the positive input signal is greater than the negative input signal, the positive output signal comprises 2 pulses with a pulse width equal to the pulse width threshold in one pulse period, and the negative output signal comprises 2 pulses with a pulse width greater than the pulse width threshold in one pulse period; if the positive input signal is less than the negative input signal, the positive output signal comprises 2 pulses with a pulse width greater than the pulse width threshold in one pulse period, and the negative output signal comprises 2 pulses with a pulse width equal to the pulse width threshold in one pulse period.

5. The method of claim 1, wherein, in response to the amplitude of the input signal being equal to 0, the positive output signal and the negative output signal each comprise 1 pulse with a pulse width equal to the pulse width threshold in one pulse period, and the pulse width of the differential mode signal of the positive output signal and the negative output signal is equal to 0.

6. The method of claim 1, wherein, the PWM modulation on the input signal to obtain a PWM positive signal and a PWM negative signal comprises: performing filtering processing on the input signal to obtain a first positive signal and a first negative signal; comparing the first positive signal and the first negative signal with a triangular wave signal to generate a second positive signal and a second negative signal according to a comparison result, wherein the period of the triangular wave is equal to the pulse period, and the second positive signal and the second negative signal are both square wave signals; generating the PWM positive signal and the PWM negative signal according to the second positive signal, the second negative signal, and a pulse width threshold.

7. The method of claim 6, wherein, when the amplitude of the input signal is equal to 0, the PWM positive signal and the PWM negative signal each comprise 1 pulse with a pulse width equal to the pulse width threshold in one pulse period, and the falling edge of the pulse included in the PWM positive signal and the PWM negative signal is time-aligned with the falling edge of the pulse included in the second positive signal and the second negative signal.

8. The method of claim 6, wherein, The PWM positive signal and the PWM negative signal each include two pulses in one pulse period when the amplitude of the input signal is not equal to 0, and the falling edges of the two pulses included in the PWM positive signal are time-aligned with the falling edges of the two pulses included in the PWM negative signal.

9. The method of claim 8, wherein, When the amplitude of the input signal is not equal to 0, If the pulse included in the second positive signal and the second negative signal is low, the PWM positive signal and the PWM negative signal satisfy: if the first positive signal is greater than the first negative signal, the pulse width of two pulses included in the PWM positive signal is T diff1 +T c and T diff2 +T c respectively, the pulse width of two pulses included in the PWM negative signal is T c , the rising edge of the pulse with the pulse width of T diff1 +T c included in the PWM positive signal is time-aligned with the falling edge of the pulse included in the second negative signal, and the rising edge of the pulse with the pulse width of T diff2 +T c included in the PWM positive signal is time-aligned with the rising edge of the pulse included in the second positive signal; if the first positive signal is less than the first negative signal, the pulse width of two pulses included in the PWM negative signal is T diff1 +T c and T diff2 +T c respectively, the pulse width of two pulses included in the PWM positive signal is T c , the rising edge of the pulse with the pulse width of T diff1 +T c included in the PWM negative signal is time-aligned with the falling edge of the pulse included in the second positive signal, and the rising edge of the pulse with the pulse width of T diff2 +T c included in the PWM negative signal is time-aligned with the rising edge of the pulse included in the second negative signal The rising edges of the two pulses are time-aligned. If the pulse included in the second positive signal and the second negative signal is high level, the PWM positive signal and the PWM negative signal satisfy: if the first positive signal is greater than the first negative signal, the pulse width of two pulses included in the PWM negative signal is T diff1 +T c respectively, the pulse width of two pulses included in the PWM positive signal is T diff2 +T c respectively, the rising edge of the pulse with the pulse width of T c +T diff1 included in the PWM negative signal is time-aligned with the rising edge of the pulse included in the second negative signal, and the rising edge of the pulse with the pulse width of T c +T diff2 included in the PWM positive signal is time-aligned with the falling edge of the pulse included in the second positive signal; if the first positive signal is less than the first negative signal, the pulse width of two pulses included in the PWM positive signal is T c +T diff1 and T c +T diff2 respectively, the pulse width of two pulses included in the PWM negative signal is T c +T c respectively, the rising edge of the pulse with the pulse width of T diff1 +T c included in the PWM positive signal is time-aligned with the rising edge of the pulse included in the second negative signal, and the rising edge of the pulse with the pulse width of T diff2 +T c included in the PWM negative signal is time-aligned with the falling edge of the pulse included in the second positive signal. wherein said T diff1 and T diff2 for characterizing a pulse width of 2 pulses comprising a differential mode signal of said second positive signal and said second negative signal, said T c for characterizing said pulse width threshold.

10. The method of claim 6, wherein, The generating of the PWM positive signal and the PWM negative signal according to the second positive signal, the second negative signal and a pulse width threshold value comprises: delaying the second positive signal by a preset delay time length and then performing logical NOT processing to obtain a first delay reverse signal; performing logical OR processing on the first delay reverse signal and the second negative signal to obtain a third positive signal; increasing the pulse width of the pulse included in the third positive signal by the pulse width threshold value to obtain a fourth positive signal; delaying the second negative signal by the delay time length and then performing logical NOT processing to obtain a second delay reverse signal; performing logical OR processing on the second delay reverse signal and the second positive signal to obtain a third negative signal; increasing the pulse width of the pulse included in the third negative signal by the pulse width threshold value to obtain a fourth negative signal; performing logical OR processing on the fourth positive signal and the fourth negative signal to obtain a fifth signal; performing logical OR processing on the third positive signal and the fifth signal to obtain the PWM positive signal; performing logical OR processing on the third negative signal and the fifth signal to obtain the PWM negative signal.

11. The method of claim 6, wherein, The generating of the PWM positive signal and the PWM negative signal according to the second positive signal, the second negative signal and a pulse width threshold value comprises: performing differential mode pulse width extraction on the second positive signal and the second negative signal to obtain a positive differential mode signal and a negative differential mode signal; performing common mode pulse width generation to obtain a positive common mode signal and a negative common mode signal; performing PWM signal generation according to the positive differential mode signal, the negative differential mode signal, the positive common mode signal, the negative common mode signal and the pulse width threshold value to obtain the PWM positive signal and the PWM negative signal.

12. The method of any one of claims 2-11, wherein, The pulse width threshold value is in a range of [T / 40, T / 10], and T is used to represent the length of the pulse period.

13. The method of any one of claims 6-11, wherein, The outputting of the positive output signal and the negative output signal according to the PWM positive signal and the PWM negative signal comprises: amplifying the amplitude of the PWM positive signal to obtain the negative output signal, and amplifying the amplitude of the PWM negative signal to obtain the positive output signal; or amplifying the amplitude of the PWM positive signal to obtain the positive output signal, and amplifying the amplitude of the PWM negative signal to obtain the negative output signal.

14. The method of any one of claims 1-11, wherein, The input signal is an audio signal, the positive output signal and the negative output signal are used to drive a loudspeaker, and the loudspeaker is used to play the audio signal after signal processing.

15. A signal processing circuit, characterized by comprising: The method comprises: modulation module, configured to perform PWM modulation on the input signal to obtain a PWM positive signal and a PWM negative signal; a power output module, configured to output a positive output signal and a negative output signal according to the PWM positive signal and the PWM negative signal; wherein, in response to the amplitude of the input signal not being equal to 0, the positive output signal and the negative output signal each include 2 pulses in one pulse period.

16. The circuit of claim 15, wherein, The modulation module includes a loop filter unit, a comparison unit and a logic processing unit. The loop filter unit is configured to perform filtering processing on the input signal to obtain a first positive signal and a first negative signal. The comparison unit is configured to compare the first positive signal and the first negative signal with a triangular wave signal to generate a second positive signal and a second negative signal according to a comparison result, wherein the period of the triangular wave is equal to the pulse period, and the second positive signal and the second negative signal are both square wave signals. The logic processing unit is configured to generate the PWM positive signal and the PWM negative signal according to the second positive signal, the second negative signal and a pulse width threshold.

17. The circuit of claim 16, wherein, The logic processing unit includes a differential signal extraction subunit, a pulse width adjustment subunit and a signal processing subunit. The differential signal extraction subunit is configured to delay a logic NOT processed second positive signal by a preset delay time length to obtain a first delay reverse signal, perform logic OR NOT processing on the first delay reverse signal and the second negative signal to obtain a third positive signal, delay the second negative signal by the delay time length to obtain a second delay reverse signal, and perform logic OR NOT processing on the second delay reverse signal and the second positive signal to obtain a third negative signal. The pulse width adjustment subunit is configured to increase the pulse width timing of a pulse included in the third positive signal by the pulse width threshold to obtain a fourth positive signal, and increase the pulse width timing of a pulse included in the third negative signal by the pulse width threshold to obtain a fourth negative signal. The signal processing subunit is configured to perform logic OR processing on the fourth positive signal and the fourth negative signal to obtain a fifth signal, perform logic OR processing on the third positive signal and the fifth signal to obtain the PWM positive signal, and perform logic OR processing on the third negative signal and the fifth signal to obtain the PWM negative signal.

18. The circuit of claim 16, wherein, The logic processing unit is configured to perform the following processing: perform differential mode pulse width extraction on the second positive signal and the second negative signal to obtain a positive differential mode signal and a negative differential mode signal; perform common mode pulse width generation to obtain a positive common mode signal and a negative common mode signal; perform PWM signal generation according to the positive differential mode signal, the negative differential mode signal, the positive common mode signal, the negative common mode signal and the pulse width threshold to obtain the PWM positive signal and the PWM negative signal.

19. A signal processing chip, characterized by The signal processing chip is configured to perform the method in any one of claims 1-14.

20. An electronic device, comprising: comprises: A signal source, a signal receiving end and a signal processing device, the signal processing device comprising a signal processing circuit as claimed in any one of claims 15-18 or a signal processing chip as claimed in claim 19; The signal processing device is connected between the signal source and the signal receiving end; The signal source is configured to transmit an input signal to the signal processing device; The signal receiving end is configured to receive a positive output signal and a negative output signal output by the signal processing device.

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