Receiver and associated signal processing method

Abstract

A receiver and a related signal processing method are disclosed. The receiver includes a filter, a signal detection circuit, and a synchronization processing circuit. The filter is configured to perform a filtering operation on a filter input signal to generate a filter output signal. The signal detection circuit is configured to determine whether the filter input signal or the filter output signal includes an interference signal based on the filter input signal and the filter output signal to generate an interference signal indicator, and determine whether the filter output signal includes a valid signal based on the interference signal indicator when the interference signal indicator indicates that the filter input signal or the filter output signal includes the interference signal to generate a valid signal indicator. The synchronization processing circuit is configured to process the filter output signal based on the interference signal indicator and the valid signal indicator.

Description

Technical Field

[0001] This invention relates to receivers and related signal processing methods. Background Technology

[0002] In typical wireless receivers, strong interference from adjacent channels in the environment can negatively impact the reception of valid signals. Furthermore, the backend synchronization processing circuitry may be unable to accurately distinguish between interfering and valid signals, leading to signal processing errors or delays. Therefore, to address adjacent channel interference, filters are typically incorporated into the radio frequency (RF) and baseband (BF) circuits of the wireless receiver, with the filter order increased to minimize interference. However, when the frequency of the interfering signal is very close to that of the valid signal, the filter cannot completely remove the interference, causing subsequent circuitry to be unable to distinguish between interfering and valid signals in real time. Summary of the Invention

[0003] Therefore, one of the objectives of this invention is to provide a method for detecting effective signals, which can accurately detect the time point when an effective signal appears in the presence of interference signals, thereby solving the problems described in the prior art.

[0004] In one embodiment of the present invention, a receiver is disclosed, comprising a filter, a signal detection circuit, and a synchronization processing circuit. The filter is used to filter an input signal to generate an output signal. The signal detection circuit is coupled to the filter and is used to determine whether the input signal or the output signal contains an interference signal based on the input signal and the output signal, thereby generating an interference signal index; and when the interference signal index indicates that the input signal or the output signal contains the interference signal, to determine whether the output signal contains a valid signal, thereby generating a valid signal index. The synchronization processing circuit is coupled to the filter and the signal detection circuit and is used to process the output signal based on the interference signal index and the valid signal index.

[0005] In another embodiment of the present invention, a signal processing method is disclosed, comprising the following steps: performing a filtering operation on a filter input signal to generate a filter output signal; determining whether the filter input signal or the filter output signal contains an interference signal based on the filter input signal and the filter output signal, thereby generating an interference signal index; when the interference signal index indicates that the filter input signal or the filter output signal contains the interference signal, determining whether the filter output signal contains a valid signal, thereby generating a valid signal index; and processing the filter output signal based on the interference signal index and the valid signal index. Attached Figure Description

[0006] Figure 1 This is a schematic diagram of a receiver according to an embodiment of the present invention.

[0007] Figure 2 This is a schematic diagram showing that the filter output signal still contains high-intensity interference signals.

[0008] Figure 3 This is a schematic diagram of an interference signal detection circuit included in a signal detection circuit according to an embodiment of the present invention.

[0009] Figure 4 This is a schematic diagram illustrating how to determine whether the input signal of a filter contains interference signals according to an embodiment of the present invention.

[0010] Figure 5 This is a schematic diagram of an effective signal detection circuit included in a signal detection circuit according to an embodiment of the present invention.

[0011] Figure 6 This is a schematic diagram illustrating how to determine whether the output signal of a filter contains a valid signal according to an embodiment of the present invention.

[0012] Figure 7 This is a schematic diagram illustrating the process of receiving a valid signal after first receiving an interference signal, according to an embodiment of the present invention.

[0013] Figure 8 This is a schematic diagram illustrating the process of receiving a valid signal after first receiving an interference signal, according to another embodiment of the present invention.

[0014] Symbol Explanation

[0015] 100: Receiver

[0016] 102: Antenna

[0017] 110: Low Noise Amplifier

[0018] 120: Mixer

[0019] 130: Transimpedance Amplifier

[0020] 140: Baseband Circuit

[0021] 150: Analog-to-digital converter

[0022] 160: Correction and compensation circuit

[0023] 170: Filter

[0024] 180: Signal detection circuit

[0025] 190: Synchronization Processing Circuit

[0026] 310, 320: Absolute value calculation circuit

[0027] 330, 340: Smoothing Calculation Circuit

[0028] 350: Comparator

[0029] 400-412: Steps

[0030] 510: Phase Calculation Circuit

[0031] 520: Unwinding Circuit

[0032] 530: Smoothing Calculation Circuit

[0033] 540: Judgment Circuit

[0034] 600-618: Steps

[0035] FIR_in: Filter input signal

[0036] FIR_out: Filter output signal

[0037] abs_in: First absolute value

[0038] abs_out: Second absolute value

[0039] smooth_in: The result of the first smoothing calculation

[0040] smooth_out: The result of the second smoothing calculation

[0041] intf_flag: Indicator of interference signals

[0042] angle_out: Phase value

[0043] unwrap_angle: Unwrap result

[0044] unwrap_angle_acc: Unwrap smoothing calculation result

[0045] sig_flag: Indicator of valid signal Detailed Implementation

[0046] Figure 1 This is a schematic diagram of a receiver 100 according to an embodiment of the present invention. Figure 1As shown, receiver 100 includes a low-noise amplifier 110, a mixer 120, a transimpedance amplifier 130, a baseband circuit 140, an analog-to-digital converter 150, a correction and compensation circuit 160, a filter 170, a signal detection circuit 180, and a synchronization processing circuit 190. In this embodiment, filter 170 is a finite impulse response (FIR) filter, and receiver 100 is used to receive and process radio frequency signals from antenna 102. Receiver 100 can be applied to any receiver used to receive radio frequency signals, such as receivers supporting Wi-Fi, Bluetooth, or ZigBee standards.

[0047] In the basic operation of receiver 100, low-noise amplifier 110 receives radio frequency signals from antenna 102 to generate an amplified signal. Mixer 120 performs a mixing operation on the amplified signal to down-convert the amplified signal to generate a baseband signal. The baseband signal is then processed by transimpedance amplifier 130 and baseband circuit 140, and then undergoes analog-to-digital conversion by analog-to-digital converter 150 to generate a digital signal. Next, correction and compensation circuit 160 performs in-phase and quadrature signal calibration (IQ calibration) and DC compensation on the digital signal to generate a filter input signal FIR_in to filter 170. Filter 170 filters the filter input signal FIR_in to generate a filter output signal FIR_out. Synchronization processing circuit 190 then processes the filter output signal FIR_out.

[0048] As described in the prior art, if there is a high-intensity adjacent channel interference signal in the environment, the filter 170 cannot completely remove the interference signal because the frequency of the interference signal is very close to the valid signal. This causes the subsequent synchronization processing circuit 190 to be unable to determine the interference signal and the valid signal in real time, and may also fail to correctly determine when the valid signal appears. Figure 2As shown, the frequency of the interference signal is very close to that of the valid signal, so the interference signal will be within the passband of filter 170, causing the filter output signal FIR_out to still contain a high intensity of interference signal. Therefore, to solve this problem, this embodiment proposes a signal detection circuit 180, which can accurately determine the interference signal and the valid signal based on the filter input signal FIR_in and the filter output signal FIR_out, especially accurately determining the time point of the valid signal when there is interference in the filter input signal FIR_in, so that the synchronization processing circuit 190 can correctly read the valid signal and perform synchronization processing. It should be noted that since the focus of this invention is on how the signal detection circuit 180 uses the filter input signal FIR_in and the filter output signal FIR_out of filter 170 to accurately determine the interference signal and the valid signal, Figure 1 The operation of the low-noise amplifier 110, mixer 120, transimpedance amplifier 130, baseband circuit 140, analog-to-digital converter 150 and correction and compensation circuit 160 is well known to those skilled in the art, so the following description is only for the filter 170, signal detection circuit 180 and synchronization processing circuit 190.

[0049] refer to Figure 3 This is a schematic diagram of an interference signal detection circuit 300 included in a signal detection circuit 180 according to an embodiment of the present invention. Figure 3 As shown, the interference signal detection circuit 300 includes two absolute value calculation circuits 310 and 320, two smoothing calculation circuits 330 and 340, and a comparator 350. In the operation of the interference signal detection circuit 300, the absolute value calculation circuit 310 receives the filter input signal FIR_in and takes the absolute value of the filter input signal FIR_in to generate a first absolute value abs_in; simultaneously, the absolute value calculation circuit 320 receives the filter output signal FIR_out and takes the absolute value of the filter output signal FIR_out to generate a second absolute value abs_out. Next, the smoothing calculation circuit 330 updates the output first smoothing calculation result smooth_in according to the first absolute value abs_in and a smoothing parameter F1; that is, the first smoothing calculation result smooth_in can be generated based on the first absolute values ​​abs_in at multiple previous time points. For example, the first smoothing calculation result smooth_in can be updated using the following formula:

[0050] smooth_in=smooth_in*(1-F1)+abs_in*F1……………………(1);

[0051] Where F1 can be any suitable value, such as (15 / 16) or (7 / 8). Similarly, the smoothing calculation circuit 340 updates the output second smoothing calculation result smooth_out based on the second absolute value abs_out and a smoothing parameter F2. For example, the second smoothing calculation result smooth_out can be updated using the following formula:

[0052] smooth_out=smooth_out*(1-F2)+abs_in*F2……………………(2);

[0053] F2 can be any suitable value, such as the same value as F1. Finally, comparator 350 determines whether the filter input signal FIR_in contains interference signals based on the first smoothing calculation result smooth_in and the second smoothing calculation result smooth_out. In one embodiment, comparator 350 can determine whether the filter input signal FIR_in contains interference signals by whether there is a significant difference between the first smoothing calculation result smooth_in and the second smoothing calculation result smooth_out. If the degree to which the first smoothing calculation result smooth_in is greater than the second smoothing calculation result smooth_out is higher than a threshold value, then it is determined that the filter input signal FIR_in contains interference signals, and comparator 350 sets an interference signal index intf_flag to "1"; if the degree to which the first smoothing calculation result smooth_in is greater than the second smoothing calculation result smooth_out is not higher than the threshold value, then it is determined that the filter input signal FIR_in does not contain interference signals, and comparator 350 sets an interference signal index intf_flag to "0".

[0054] Figure 4 This is a schematic diagram illustrating the determination of whether the filter input signal FIR_in contains interference signals according to an embodiment of the present invention. See also... Figure 3 , Figure 4 , Figure 4 The process is as follows.

[0055] Step 400: Process begins.

[0056] Step 402: Take the absolute value of the filter input signal FIR_in to generate the first absolute value abs_in, and take the absolute value of the filter output signal FIR_out to generate the second absolute value abs_out, that is, abs_in = abs(FIR_in) and abs_out = abs(FIR_out).

[0057] Step 404: Update the first smoothing calculation result smooth_in according to the first absolute value abs_in and the smoothing parameter F1, and update the second smoothing calculation result smooth_out according to the second absolute value abs_out and the smoothing parameter F2. It can be calculated using the above formulas (1) and (2).

[0058] Step 406: Determine whether the second absolute value abs_out is greater than a threshold value. If yes, proceed to step 408; otherwise, proceed to step 412. Since this embodiment mainly determines whether the filter input signal FIR_in contains interference signals from neighboring channels, step 406 is used to avoid misidentifying white noise as interference signals from neighboring channels.

[0059] Step 408: Determine whether the first smoothing calculation result smooth_in is greater than the second smoothing calculation result smooth_out multiplied by a critical value TH2, where the critical value TH2 can be any suitable value, such as 3, 10, 30, 100, etc. If yes, the process proceeds to step 410; if no, the process proceeds to step 412.

[0060] Step 410: Set the interference signal indicator intf_flag to "1" to indicate that the filter input signal FIR_in contains interference signals (interference signals from neighboring channels).

[0061] Step 412: Set the interference signal indicator intf_flag to "0" to indicate that the filter input signal FIR_in does not contain interference signals.

[0062] In addition, the signal detection circuit 180 also includes, for example, Figure 5The illustrated valid signal detection circuit 500 includes a phase calculation circuit 510, an unwrap circuit 520, a smoothing calculation circuit 530, and a judgment circuit 540. In the operation of the valid signal detection circuit 500, the phase calculation circuit 510 receives the filter output signal FIR_out and outputs a phase value angle_out of the filter output signal FIR_out. Then, the unwrap circuit 520 continuously unwraps the phase value output by the phase calculation circuit 510 to produce an unwrap result unwrap_angle. It should be noted that in this embodiment, since the operation of the phase calculation circuit 510 and the unwrap circuit 520 can be implemented using digital circuits with the Cordic algorithm and unwrap algorithm of the commercial mathematical software "Matlab," and the details of these algorithms are not the focus of this invention, related details are not described in this specification. Next, the smoothing calculation circuit 530 updates the output unwrap smoothing calculation result unwrap_angle_acc based on the unwrap result unwrap_angle and a smoothing parameter F3. That is, the unwrap smoothing calculation result unwrap_angle_acc can be generated based on the unwrap results unwrap_angle from previous time points. For example, the unwrap smoothing calculation result unwrap_angle_acc can be updated using the following formula:

[0063] unwrap_angle_acc=unwrap_angle_acc*(1-F3)+unwrap_angle*F3...(3);

[0064] F3 can be any suitable value, such as (1 / 8), (1 / 16), or (1 / 32).

[0065] Finally, the judgment circuit 540 determines whether a valid signal appears in the filter output signal FIR_out based on the unwrap smoothing calculation result unwrap_angle_acc. Specifically, the unwrap smoothing calculation result unwrap_angle_acc represents the phase characteristic of the filter output signal FIR_out. In this embodiment, if the filter input signal FIR_in only contains interference signals from adjacent channels, since the filter 170 is also linear in phase, the filter 170 will not change the phase characteristic of the processed signal. Therefore, the phase characteristic of the filter output signal FIR_out will be the same as or very similar to the phase characteristic of the filter input signal FIR_in, and the unwrap smoothing calculation result unwrap_angle_acc will reflect consistent characteristics. On the other hand, if a valid signal appears in the filter input signal FIR_in while containing interference signals, since the phase of the valid signal is non-linear, the phase characteristic of the filter output signal FIR_out will change, and the unwrap smoothing calculation result unwrap_angle_acc will show different trends or significant changes in value. In one example, if the unwrap smoothing calculation result unwrap_angle_acc is less than 0, and the unwrap smoothing calculation result unwrap_angle_acc is greater than the sum of the previous unwrap result unwrap_angle_last and a critical value TH3, then the determination circuit 540 can determine that a valid signal has been received and set a valid signal index sig_flag to "1"; and if the unwrap smoothing calculation result unwrap_angle_acc is greater than 0, and the unwrap smoothing calculation result unwrap_angle_acc is less than the difference between the previous unwrap result unwrap_angle_last and a critical value TH3, then the determination circuit 540 can determine that a valid signal has been received and set the valid signal index sig_flag to "1"; otherwise, the determination circuit 540 can set the valid signal index sig_flag to "0".

[0066] Figure 6 This is a schematic diagram illustrating the determination of whether the filter output signal FIR_out contains a valid signal according to an embodiment of the present invention. See also... Figure 5 , Figure 6 , Figure 6 The process is as follows.

[0067] Step 600: Process begins.

[0068] Step 602: Calculate the phase value angle_out of the output signal FIR_out of the output filter, that is, angle_out = cordic(FIR_out).

[0069] Step 604: Perform an unwrap operation on the phase value angle_out to produce the unwrap result unwrap_angle, that is, unwrap_angle = unwrap(angle_out).

[0070] Step 606: Update the output unwrap smoothing calculation result unwrap_angle_acc based on the unwrap result unwrap_angle and the smoothing parameter F3. It can be calculated using formula (3).

[0071] Step 608: Determine whether the unwrap smoothing calculation result unwrap_angle_acc is less than 0. If yes, proceed to step 610; otherwise, proceed to step 612.

[0072] Step 610: Determine whether the unwrap smoothing calculation result unwrap_angle_acc is greater than the difference between the previous unwrap result unwrap_angle_last and the critical value TH3. If yes, proceed to step 616; otherwise, proceed to step 618.

[0073] Step 612: Determine whether the unwrap smoothing calculation result unwrap_angle_acc is greater than 0. If yes, proceed to step 614; otherwise, proceed to step 618.

[0074] Step 614: Determine whether the unwrap smoothing calculation result unwrap_angle_acc is less than the difference between the previous unwrap result unwrap_angle_last and the critical value TH3. If yes, proceed to step 616; otherwise, proceed to step 618.

[0075] Step 616: Set the valid signal indicator sig_flag to "1" to indicate that the filter output signal FIR_out contains a valid signal.

[0076] Step 618: Set the valid signal indicator sig_flag to "0" to indicate that the filter output signal FIR_out does not contain a valid signal.

[0077] To better understand the judgment mechanism of the valid signal detection circuit 500, refer to... Figure 7 This is a schematic diagram illustrating the process of receiving a valid signal after first receiving an interference signal, according to an embodiment of the present invention. Figure 7 The diagram illustrates a simulation where the effective signal has a center frequency of 8 MHz and energy of -82 dB, while the interference signal has a frequency of -2 MHz and energy of -52 dB. Figure 7As shown, interference signals appear at time 10μs, and the unwrap_angle or unwrap_angle_acc result maintains a linear trend. However, if a valid signal appears at time 40μs, the unwrap_angle or unwrap_angle_acc result changes significantly, for example... Figure 7 The turning point is shown. Therefore, the judgment circuit 540 can determine whether the filter output signal FIR_out contains a valid signal based on the trend of the unwrap result unwrap_angle or the unwrap smoothing calculation result unwrap_angle_acc, and can also accurately determine the time point when the valid signal appears.

[0078] Similarly, refer to Figure 8 This is a schematic diagram illustrating the reception of a valid signal after an interference signal has been received first, according to another embodiment of the present invention. Figure 8 The diagram illustrates a simulation where the effective signal has a center frequency of 3MHz and energy of (-82)dB, while the interference signal has a frequency of 13MHz and energy of (-52)dB. Figure 8 As shown, interference signals appear at time 10μs, and the unwrap_angle or unwrap_angle_acc result maintains a linear trend. However, if a valid signal appears at time 40μs, the unwrap_angle or unwrap_angle_acc result changes significantly, for example... Figure 8 The turning point is shown. Therefore, the judgment circuit 540 can determine whether the filter output signal FIR_out contains a valid signal based on the trend of the unwrap result unwrap_angle or the unwrap smoothing calculation result unwrap_angle_acc, and can also accurately determine the time point when the valid signal appears.

[0079] It should be noted that, Figure 5 , Figure 6 The calculation details shown are merely illustrative and not intended to limit the invention. As long as the valid signal detection circuit 500 can determine whether a valid signal has appeared by detecting whether the phase characteristics of the filter output signal FIR_out change, the relevant calculation details can be appropriately modified, such as adding some parameters during the calculation process. These design changes should fall within the scope of this invention.

[0080] In another embodiment, the smoothing calculation circuit 530 can be removed from the effective signal detection circuit 500. That is, the judgment circuit 540 can determine whether the filter output signal FIR_out contains an effective signal based on the trend of the unwrap_angle result. These design changes should fall within the scope of the present invention.

[0081] In the operation of the synchronization processing circuit 190, its main function is to find the preamble field of the valid signal and begin processing. Since the synchronization operation requires a certain matching time, when to start the synchronization operation is an important issue. In this embodiment, if the interference signal indicator intf_flag changes from "0" to "1" first, and then the valid signal indicator sig_flag changes to "1", it can be determined that the receiver 100 is currently receiving a valid signal. Therefore, at this time, the synchronization processing circuit 190 can start the synchronization operation (that is, start finding the preamble field and begin processing).

[0082] On the other hand, this embodiment also allows the synchronization processing circuit 190 to correct erroneous synchronization operations in real time. For example, suppose the interference signal indicator intf_flag changes from "0" to "1" first, and then the synchronization processing circuit 190 starts synchronization operation due to the triggering of other mechanisms, and then the valid signal indicator sig_flag changes to "1". Then the synchronization processing circuit 190 can determine that the synchronization operation triggered by other mechanisms was erroneous, and can therefore immediately interrupt the previous synchronization operation and restart a new synchronization operation.

[0083] It should be noted that the synchronization processing circuit 190 has other mechanisms to determine whether a valid signal has been received to decide whether to perform synchronization operations. These mechanisms include detecting changes in the intensity of the filter output signal FIR_out or comparing signal patterns. Since these techniques are well-known to those skilled in the art, details will not be elaborated upon. In embodiments of the present invention, the signal detection circuit 180 can provide an interference signal index intf_flag and a valid signal index sig_flag to the synchronization processing circuit 190 in cases where the existing mechanism of the synchronization processing circuit 190 performs synchronization operations at an incorrect time due to interference signals, thereby restarting a new synchronization operation.

[0084] In summary, the receiver of this invention determines whether there is interference in the currently received signal and whether the phase characteristics of the filter output signal have changed. This allows for accurate detection of the time point when the valid signal appears even in the presence of interference, facilitating the operation of subsequent synchronization processing circuits.

[0085] The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made in accordance with the claims of the present invention should be included within the scope of the present invention.

Claims

1. A receiver comprising: A filter is used to filter an input signal to produce an output signal. A signal detection circuit, coupled to the filter, is used to determine whether the filter input signal or the filter output signal contains an interference signal based on the filter input signal and the filter output signal, thereby generating an interference signal index; and when the interference signal index indicates that the filter input signal or the filter output signal contains the interference signal, to determine whether the filter output signal contains a valid signal, thereby generating a valid signal index; and A synchronization processing circuit, coupled to the filter and the signal detection circuit, is used to process the output signal of the filter based on the interference signal index and the effective signal index.

2. The receiver as claimed in claim 1, wherein when the interference signal indicator indicates that the filter input signal or the filter output signal contains the interference signal, the signal detection circuit determines whether the filter output signal contains the valid signal based on the phase characteristics of the filter output signal, so as to generate the valid signal indicator.

3. The receiver as claimed in claim 2, wherein when the interference signal indication signal indicates that the filter input signal or the filter output signal contains the interference signal, and the signal detection circuit determines that the filter output signal has a linear phase characteristic, the signal detection circuit determines that the filter output signal does not contain the valid signal; and if the signal detection circuit determines that the filter output signal has a change in linear phase characteristic, the signal detection circuit determines that the filter output signal contains the valid signal.

4. The receiver of claim 2, wherein the signal detection circuit includes an effective signal detection circuit, and the effective signal detection circuit includes: A phase calculation circuit is used to generate a phase value of the filter output signal; An unwinding circuit, coupled to the phase calculation circuit, is used to unwind the phase value output by the phase calculation circuit to produce an unwinding result; and A judgment circuit, coupled to the unwinding circuit, is used to determine whether the phase characteristics of the filter output signal have changed based on the unwinding result, so as to determine whether the filter output signal contains the effective signal.

5. The receiver as claimed in claim 4, further comprising: A smoothing calculation circuit is coupled between the unwinding circuit and the judgment circuit to update the output unwinding smoothing calculation result based on the unwinding result and a smoothing parameter; The judgment circuit determines whether the phase characteristics of the filter output signal have changed based on the unwinding smoothing calculation result, so as to determine whether the filter output signal contains the effective signal.

6. The receiver of claim 4, wherein when the interference signal indicator indicates that the filter input signal or the filter output signal contains the interference signal, the determination circuit determines whether the unwinding result maintains a linear trend; if the unwinding result maintains the linear trend, the determination circuit determines that the phase characteristics of the filter output signal have not changed and the filter output signal does not contain the valid signal; and if the unwinding result does not maintain the linear trend, the determination circuit determines that the phase characteristics of the filter output signal have changed and the filter output signal contains the valid signal.

7. The receiver as claimed in claim 1, wherein if the interference signal indicator indicates whether the filter input signal or the filter output signal contains the interference signal, and the synchronization processing circuit starts a synchronization operation to process the filter output signal due to the triggering of other mechanisms, and then the valid signal indicator begins to indicate that the filter output signal contains the valid signal, then the synchronization processing circuit determines that the previous synchronization operation was incorrect and restarts a new synchronization operation to process the filter output signal.

8. The receiver of claim 1, wherein the signal detection circuit determines whether the filter input signal or the filter output signal contains the interference signal from a neighboring channel based on the filter input signal and the filter output signal, so as to generate the interference signal index.

9. The receiver of claim 8, wherein the filter is a finite impulse response filter and the receiver is a receiver that supports the Zigbee specification.

10. A signal processing method, comprising: To perform a filtering operation on the input signal of a filter to produce a filter output signal; Based on the filter input signal and the filter output signal, determine whether the filter input signal or the filter output signal contains an interference signal, and generate an interference signal index; When the interference signal indicator indicates that the filter input signal or the filter output signal contains the interference signal, it is determined whether the filter output signal contains a valid signal, so as to generate a valid signal indicator; and The output signal of the filter is processed based on the interference signal index and the effective signal index.

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