Display substrate and display device

Abstract

A display substrate and a display device. The display substrate comprises a substrate and a plurality of sub-pixels (Pxij) arranged on one side of the substrate; at least one sub-pixel (Pxij) comprises a pixel driving circuit (PDC), at least one PDC comprises a plurality of transistors, and each transistor comprises an active layer and at least one gate; in a same transistor, at least one gate at least partially overlaps with the active layer, and the at least one gate includes at least one of a top gate and a bottom gate; in the direction perpendicular to the plane where the substrate is located, the bottom gate is located on the side of the active layer close to the substrate, and the top gate is located on the side of the active layer away from the substrate; and the plurality of transistors at least include a driving transistor (T3), and gates in the driving transistor (T3) include a top gate (T3gt) and a bottom gate (T3gb).

Description

Display substrate and display device TECHNICAL FIELD

[0001] The present disclosure relates to, but is not limited to, the technical field of display, and in particular, to a display substrate and a display device. BACKGROUND

[0002] Organic light emitting diode (OLED) and quantum dot light emitting diode (QLED) are active light emitting display devices, which have the advantages of self-illumination, wide viewing angle, high contrast, low power consumption, extremely high response speed, thinness, flexibility, and low cost. With the continuous development of display technology, flexible display devices using OLED or QLED as light emitting devices and controlled by thin film transistors (TFT) have become the mainstream products in the current display field.

[0003] SUMMARY

[0004] The subject matter of the present text is outlined in this summary. This summary is not intended to limit the scope of protection of the claims.

[0005] In a first aspect, the embodiments of the present disclosure provide a display substrate, comprising: a substrate and a plurality of sub-pixels arranged on one side of the substrate, at least one sub-pixel comprising a pixel driving circuit, at least one pixel driving circuit comprising a plurality of transistors, the transistors comprising an active layer and at least one gate electrode; in the same transistor, the at least one gate electrode at least partially overlaps the active layer, and the at least one gate electrode comprises at least one of a top gate and a bottom gate; in a direction perpendicular to the plane in which the substrate is located, the bottom gate is located on the side of the active layer close to the substrate, and the top gate is located on the side of the active layer away from the substrate; the plurality of transistors at least comprises a driving transistor, and the gate electrode in the driving transistor comprises a top gate and a bottom gate.

[0006] In an exemplary embodiment, the plurality of transistors further comprises a first light emitting control transistor and a second light emitting control transistor, and the first light emitting control transistor and the second light emitting control transistor each comprise a top gate.

[0007] In the same pixel driving circuit, the second electrode of the first light emitting control transistor is connected to the first electrode of the driving transistor, and the first electrode of the second light emitting control transistor is connected to the second electrode of the driving transistor.

[0008] In an example embodiment, the sub-pixel further comprises an anode, the plurality of transistors further comprises an anode reset transistor, the gate of the anode reset transistor comprises a top gate;

[0009] In the same sub-pixel, the second electrode of the anode reset transistor and the second electrode of the second light emitting control transistor are connected to the anode; in a direction perpendicular to the plane where the substrate is located, the anode is located on the side of the pixel driving circuit away from the substrate.

[0010] In an example embodiment, the first light emitting control transistor, the second light emitting control transistor, and the anode reset transistor further comprise a bottom gate.

[0011] In an example embodiment, the plurality of transistors further comprises a data writing transistor and a first reset transistor, the gate of the data writing transistor and the first reset transistor comprises at least one of a top gate and a bottom gate, in the same sub-pixel, the second electrode of the data writing transistor and the second electrode of the first reset transistor are connected to the top gate of the driving transistor.

[0012] In an example embodiment, the pixel driving circuit further comprises at least one capacitor;

[0013] In a direction perpendicular to the plane where the substrate is located, the capacitor comprises: a first electrode plate located on one side of the substrate, a second electrode plate located on the side of the first electrode plate away from the substrate; the bottom gate is disposed in the same layer as the second electrode plate, and the active layer is located on the side of the second electrode plate away from the substrate; the transistor further comprises: a first electrode and a second electrode located on the side of the top gate away from the substrate; in the same capacitor, the orthographic projection of the first electrode plate on the substrate at least partially overlaps the orthographic projection of the second electrode plate on the substrate.

[0014] In an example embodiment, the pixel driving circuits of the plurality of sub-pixels form a plurality of rows, the plurality of rows of pixel driving circuits are arranged in sequence along a column direction, and the plurality of pixel driving circuits in the same row are arranged in sequence along a row direction, on a plane parallel to the plane where the substrate is located, the row direction intersects the column direction;

[0015] In the same pixel driving circuit, in the column direction, the first light emitting control transistor is located on one side of the driving transistor and the at least one capacitor, the second light emitting control transistor is located on the other side of the driving transistor and the at least one capacitor, the anode reset transistor is located on the side of the second light emitting control transistor away from the driving transistor and the at least one capacitor, and the orthographic projection of the driving transistor on the substrate at least partially overlaps the orthographic projection of the at least one capacitor on the substrate.

[0016] In an example embodiment, the plurality of transistors further comprises a first reset transistor and a data write transistor;

[0017] In the same pixel driving circuit, in the row direction, the first reset transistor and the data write transistor are located on the same side of the driving transistor, in the column direction, the data write transistor and the first light emitting control transistor are located on the same side of the driving transistor, and the first light emitting control transistor is located on the side of the data write transistor away from the driving transistor; the first reset transistor and the second light emitting control transistor are located on the same side of the driving transistor, and the second light emitting control transistor is located on the side of the first reset transistor away from the driving transistor; the second electrode of the first reset transistor and the second electrode of the data write transistor are connected with the top gate of the driving transistor.

[0018] In an example embodiment, the at least one capacitor comprises a first capacitor and a second capacitor, in the same pixel driving circuit, the first plate of the first capacitor and the first plate of the second capacitor are connected with each other, the second plate of the first capacitor is connected with the second electrode of the driving transistor, the second plate of the second capacitor is connected with the top gate of the driving transistor, the orthographic projection of the driving transistor on the substrate at least partially overlaps the orthographic projection of the first capacitor on the substrate, and the second plate of the first capacitor serves as the bottom gate of the driving transistor.

[0019] In an example embodiment, the plurality of transistors further comprises a second reset transistor, in the same pixel driving circuit, the second electrode of the second reset transistor is connected with the first plate of the first capacitor and the first plate of the second capacitor;

[0020] In the same pixel driving circuit, in the column direction, the second reset transistor is located on the side of the first reset transistor away from the data write transistor, and in the row direction, the second reset transistor and the first reset transistor are located on the same side of the driving transistor.

[0021] In an example embodiment, the display substrate further comprises a plurality of first reset control lines, a plurality of second reset control lines, a plurality of scan signal lines, and a plurality of anode reset control lines, the first reset control lines, the second reset control lines, the scan signal lines, and the anode reset control lines are arranged in the same layer as the first electrode and the second electrode; the gate of the first reset transistor, the gate of the second reset transistor, and the gate of the data write transistor comprise a top gate;

[0022] The first reset control line is connected to the top gate of at least part of the first reset transistor in at least one row of pixel driving circuits, the second reset control line is connected to the top gate of at least part of the second reset transistor in at least one row of pixel driving circuits, the scan signal line is connected to the top gate of at least part of the data writing transistor in at least one row of pixel driving circuits, and the anode reset control line is connected to the top gate of at least part of the anode reset transistor in at least one row of pixel driving circuits.

[0023] In the same pixel driving circuit, in the column direction, the first capacitor is located on the side of the second capacitor away from the second light-emitting control transistor, the second capacitor is located on the side of the first capacitor away from the first light-emitting control transistor, and the anode reset control line, the second reset control line, the first reset control line and the scan signal line are sequentially and spacedly arranged along the column direction.

[0024] In an exemplary embodiment, the first light-emitting control transistor, the second light-emitting control transistor and the anode reset transistor further comprise a bottom gate; and the anode reset control line is further connected to the bottom gate of at least part of the anode reset transistor in at least one row of pixel driving circuits.

[0025] In an exemplary embodiment, the first plate of the first capacitor and the first plate of the second capacitor are in an integral structure, the first plate and the second plate of the first capacitor and the first plate and the second plate of the second capacitor are in a rectangular structure, the second plate of the first capacitor and the second plate of the second capacitor are in the same area, the second plate of the second capacitor is provided with an opening, and the second electrode of the second reset transistor is connected to the first plate of the first capacitor and the first plate of the second capacitor through a via at the opening position.

[0026] In an exemplary embodiment, the pixel driving circuit further comprises a transfer connection electrode, the transfer connection electrode is arranged in the same layer as the first electrode and the second electrode; the top gate of the driving transistor comprises a first part and a second part, the first part is in a rectangular shape, and the second part is in a strip shape or a polyline shape extending along the column direction;

[0027] In the same driving transistor, the first part is connected to the second part, in the column direction, the second part is located on the side of the first part away from the first light-emitting control transistor, the orthographic projection of the first part on the substrate at least partially overlaps the orthographic projection of the first capacitor on the substrate, and the orthographic projection of the second part on the substrate at least partially overlaps the orthographic projection of the first capacitor and the second capacitor on the substrate; the transfer connection electrode is electrically connected to the second plate of the second capacitor and the second part through a via.

[0028] In an example embodiment, the display substrate further comprises a plurality of second power supply connection lines, the second power supply connection lines are arranged in the same layer as the first electrode and the second electrode, main body portions of the plurality of second power supply connection lines extend along the row direction and are arranged at intervals along the column direction;

[0029] In the same pixel driving circuit, in the column direction, the second power supply connection line is located on a side of the scan signal line away from the first reset control line, the second electrode of the first reset transistor, the second electrode of the data write transistor and the second electrode of the driving transistor are located between the scan signal line and the first reset control line, the switching connection electrode and the second electrode of the second reset transistor are located between the first reset control line and the second reset control line.

[0030] In an example embodiment, the display substrate further comprises a plurality of first reset control lines, a plurality of second reset control lines, a plurality of scan signal lines and a plurality of anode reset control lines, the first reset control lines, the second reset control lines and the scan signal lines are arranged in the same layer as the first electrode and the second electrode, the anode reset control lines are arranged in the same layer as the top gate; the first reset transistor, the second reset transistor, the data write transistor, the first light-emitting control transistor, the second light-emitting control transistor and the anode reset transistor each comprise a top gate and a bottom gate;

[0031] The first reset control line is connected with the top gate and the bottom gate of at least part of the first reset transistors in at least one row of pixel driving circuits, the second reset control line is connected with the top gate and the bottom gate of at least part of the second reset transistors in at least one row of pixel driving circuits, the scan signal line is connected with the top gate and the bottom gate of at least part of the data write transistors in at least one row of pixel driving circuits, and the anode reset control line is provided with the top gate of at least part of the anode reset transistors in at least one row of pixel driving circuits;

[0032] In the same pixel driving circuit, in the column direction, the first capacitor is located on a side of the second capacitor away from the first light-emitting control transistor, the second capacitor is located on a side of the first capacitor away from the second light-emitting control transistor, and the anode reset control line, the second reset control line, the first reset control line and the scan signal line are arranged at intervals along the column direction.

[0033] In an example embodiment, the first plate of the first capacitor and the first plate of the second capacitor are in an integral structure, the first plate and the second plate of the first capacitor and the first plate and the second plate of the second capacitor are in a block structure, and the second plate of the second capacitor has an area smaller than that of the second plate of the first capacitor; the first plate of the first capacitor is provided with a first connecting portion, the second plate of the first capacitor is provided with a second connecting portion, and the projections of the first connecting portion and the second connecting portion on the substrate at least partially do not overlap.

[0034] In the same pixel driving circuit, in the column direction, the first connecting portion and the second connecting portion are located on the side of the first capacitor away from the first light-emitting control transistor, the second electrode of the second reset transistor is connected to the first connecting portion through a via, and the second electrode of the driving transistor is connected to the second connecting portion through a via.

[0035] In an example embodiment, the display substrate further comprises a plurality of second power supply connecting lines, the second power supply connecting lines are provided in the same layer as the first electrode and the second electrode, and main portions of the plurality of second power supply connecting lines extend in the row direction and are arranged at intervals in the column direction.

[0036] In the same pixel driving circuit, in the column direction, the second power supply connecting line is located between the scan signal line and the first reset control line, the second electrode of the first reset transistor is located between the second power supply connecting line and the first reset control line, the second electrode of the data writing transistor is located between the scan signal line and the second power supply connecting line, and the second electrode of the driving transistor is located between the first reset control line and the second reset control line.

[0037] In an example embodiment, the display substrate further comprises a plurality of third shielding lines, the third shielding lines are provided in the same layer as the second electrode plate, and the plurality of third shielding lines are in a fold line shape or a strip shape with main portions extending in the row direction and arranged at intervals in the column direction.

[0038] The third shielding line is provided with a bottom gate of at least part of the anode reset transistor in at least one row of pixel driving circuits, and the projections of the third shielding line and the anode reset control line on the substrate at least partially overlap.

[0039] In an example embodiment, in the same row of pixel driving circuits, the projection of the third shielding line on the substrate covers the projection of the anode reset control line on the substrate.

[0040] In an example embodiment, the at least one capacitor includes a first capacitor and a second capacitor, in the same pixel driving circuit, a second electrode of the driving transistor is electrically connected with a second electrode plate of the first capacitor and a second electrode plate of the second capacitor, a first electrode plate of the first capacitor is connected with a top gate of the driving transistor, a projection of the driving transistor on the substrate at least partially overlaps with a projection of the second capacitor on the substrate, and the second electrode plate of the second capacitor serves as a bottom gate of the driving transistor.

[0041] In the same sub-pixel driving circuit, in the column direction, the first capacitor is located on a side of the second capacitor away from the first light-emitting control transistor, and the second capacitor is located on a side of the first capacitor away from the second light-emitting control transistor.

[0042] In an example embodiment, the display substrate further includes a plurality of first reset control lines, a plurality of scan signal lines, and a plurality of anode reset control lines, the first reset control lines, the scan signal lines, and the anode reset control lines are disposed in the same layer as the first electrode and the second electrode, and the anode reset control lines, the first reset control lines, and the scan signal lines are sequentially and spacedly arranged in the column direction in the same row of pixel driving circuits.

[0043] The first reset transistor, the data writing transistor, the first light-emitting control transistor, the second light-emitting control transistor, and the anode reset transistor include a bottom gate, the first reset control line is connected with the bottom gate of at least part of the first reset transistors in at least one row of pixel driving circuits, the scan signal line is connected with the bottom gate of at least part of the data writing transistors in at least one row of pixel driving circuits, and the anode reset control line is connected with the top gate and the bottom gate of at least part of the anode reset transistors in at least one row of pixel driving circuits.

[0044] In an example embodiment, the first reset transistor and the data writing transistor further include a top gate, the first reset control line is further connected with the top gate of at least part of the first reset transistors in at least one row of pixel driving circuits, and the scan signal line is further connected with the top gate of at least part of the data writing transistors in at least one row of pixel driving circuits.

[0045] In an example embodiment, the display substrate further includes a plurality of second power supply connection lines, the second power supply connection lines are disposed in the same layer as the first electrode and the second electrode, and main body portions of the second power supply connection lines extend in the row direction and are spacedly arranged in the column direction.

[0046] In the same pixel driving circuit, in the column direction, the second power connection line is located between the scan signal line and the first reset control line, and the second electrode of the first reset transistor, the second electrode of the data writing transistor and the second electrode of the driving transistor are located between the scan signal line and the second power connection line.

[0047] In an example embodiment, the display substrate further comprises a plurality of first light-emitting control lines and a plurality of second light-emitting control lines, which are arranged in the same layer as the top gate; the plurality of first light-emitting control lines and the plurality of second light-emitting control lines are in the shape of a broken line or a strip, and extend along the row direction, and are arranged in the column direction.

[0048] The first light-emitting control line is electrically connected to at least part of the first light-emitting control transistor in at least one row of pixel driving circuits, and the second light-emitting control line is electrically connected to at least part of the second light-emitting control transistor in at least one row of pixel driving circuits; the region where the first light-emitting control line overlaps with the active layer of the first light-emitting control transistor serves as the top gate of the first light-emitting control transistor, and the region where the second light-emitting control line overlaps with the active layer of the second light-emitting control transistor serves as the top gate of the second light-emitting control transistor.

[0049] In the same pixel driving circuit, in the column direction, the first light-emitting control line and the first light-emitting control transistor are located on the same side of the driving transistor, the second light-emitting control line and the second light-emitting control transistor are located on the same side of the driving transistor, the anode reset control line is located on the side of the second light-emitting control line away from the first light-emitting control line, and the first reset control line and the scan signal line are located between the first light-emitting control line and the second light-emitting control line.

[0050] In an example embodiment, the display substrate further comprises a plurality of first shielding lines and a plurality of second shielding lines, which are arranged in the same layer as the second electrode plate; the plurality of first shielding lines and the plurality of second shielding lines are in the shape of a broken line or a strip, and extend along the row direction, and are arranged in the column direction.

[0051] In the same row of pixel driving circuits, the first shielding line and the first light-emitting control line at least partially overlap in the orthographic projection on the substrate, and the second shielding line and the second light-emitting control line at least partially overlap in the orthographic projection on the substrate; the region where the first shielding line overlaps with the active layer of the first light-emitting control transistor serves as the bottom gate of the first light-emitting control transistor, and the region where the second shielding line overlaps with the active layer of the second light-emitting control transistor serves as the bottom gate of the second light-emitting control transistor.

[0052] In an example embodiment, in the same row pixel driving circuit, the first shielding line covers the orthogonal projection of the first light-emitting control line on the substrate, and the second shielding line covers the orthogonal projection of the second light-emitting control line on the substrate.

[0053] In a second aspect, the embodiments of the present disclosure further provide a display device, comprising the display substrate according to any one of the above embodiments.

[0054] Other aspects can become apparent from the following detailed description, when considered in conjunction with the accompanying drawings. BRIEF DESCRIPTION OF DRAWINGS

[0055] The accompanying drawings are included to provide a further understanding of the technical scheme of the present disclosure, and constitute a part of the specification, and are used to explain the technical scheme of the present disclosure together with the embodiments of the present disclosure, and do not constitute a limitation on the technical scheme of the present disclosure. The shape and size of each component in the drawings do not reflect the true proportion, and the purpose is only to schematically illustrate the present disclosure.

[0056] FIG. 1 is a structural schematic diagram of a display device;

[0057] FIG. 2 is a structural schematic diagram of a display substrate;

[0058] FIG. 3 is a schematic diagram of a cross-sectional structure of a display substrate;

[0059] FIG. 4 is a schematic diagram of an equivalent circuit of a pixel driving circuit;

[0060] FIG. 5a is a structural schematic diagram of a display substrate provided by an embodiment of the present disclosure;

[0061] FIG. 5b is a schematic diagram of a planar structure of a display substrate provided by an example embodiment of the present disclosure;

[0062] FIG. 5c is a schematic diagram of a planar structure of a display substrate provided by an example embodiment of the present disclosure;

[0063] FIG. 5d is a schematic diagram of a planar structure of a display substrate provided by an example embodiment of the present disclosure;

[0064] FIG. 5e is a schematic diagram of a planar structure of a display substrate provided by an example embodiment of the present disclosure;

[0065] FIG. 6a is a schematic diagram of an equivalent circuit of a pixel driving circuit provided by an example embodiment of the present disclosure;

[0066] FIG. 6b is a schematic diagram of an equivalent circuit of a pixel driving circuit provided by an example embodiment of the present disclosure;

[0067] FIG. 6c shows an equivalent circuit schematic diagram of a pixel driving circuit according to an exemplary embodiment of the present disclosure;

[0068] FIG. 6d shows an equivalent circuit schematic diagram of a pixel driving circuit according to an exemplary embodiment of the present disclosure;

[0069] FIG. 6e shows an equivalent circuit schematic diagram of a pixel driving circuit according to an exemplary embodiment of the present disclosure;

[0070] FIG. 7 shows a schematic diagram of a display substrate after forming a first conductive layer pattern according to an exemplary embodiment of the present disclosure;

[0071] FIG. 8a shows a schematic diagram of a display substrate after forming a second conductive layer pattern according to an exemplary embodiment of the present disclosure;

[0072] FIG. 8b shows a schematic diagram of a second conductive layer in a display substrate according to an exemplary embodiment of the present disclosure;

[0073] FIG. 9a shows a schematic diagram of a display substrate after forming a semiconductor layer pattern according to an exemplary embodiment of the present disclosure;

[0074] FIG. 9b shows a schematic diagram of a semiconductor layer in a display substrate according to an exemplary embodiment of the present disclosure;

[0075] FIG. 10a shows a schematic diagram of a display substrate after forming a third conductive layer pattern according to an exemplary embodiment of the present disclosure;

[0076] FIG. 10b shows a schematic diagram of a third conductive layer in a display substrate according to an exemplary embodiment of the present disclosure;

[0077] FIG. 11 shows a schematic diagram of a display substrate after forming a fourth insulating layer pattern according to an exemplary embodiment of the present disclosure;

[0078] FIG. 12a shows a schematic diagram of a display substrate after forming a fourth conductive layer pattern according to an exemplary embodiment of the present disclosure;

[0079] FIG. 12b shows a schematic diagram of a fourth conductive layer in a display substrate according to an exemplary embodiment of the present disclosure;

[0080] FIG. 13 shows a schematic diagram after forming a first planarization layer pattern according to an exemplary embodiment of the present disclosure;

[0081] FIG. 14a shows a schematic diagram of a display substrate after forming a fifth conductive layer pattern according to an exemplary embodiment of the present disclosure;

[0082] FIG. 14b shows a schematic diagram of a fifth conductive layer in a display substrate according to an exemplary embodiment of the present disclosure;

[0083] FIG. 15 shows a schematic diagram of a display substrate after forming a second planarization layer pattern according to an exemplary embodiment of the present disclosure;

[0084] FIG. 16a shows a schematic diagram of a display substrate after forming an anode conductive layer pattern according to an exemplary embodiment of the present disclosure;

[0085] FIG. 16b shows a schematic diagram of an anode conductive layer in a display substrate according to an exemplary embodiment of the present disclosure;

[0086] FIG. 17a shows a schematic diagram of a display substrate after forming a pixel definition layer pattern according to an exemplary embodiment of the present disclosure;

[0087] FIG. 17b shows a schematic diagram of a pixel definition layer pattern in a display substrate according to an exemplary embodiment of the present disclosure;

[0088] FIG. 18a shows a schematic diagram of a display substrate after forming a second conductive layer pattern according to an exemplary embodiment of the present disclosure;

[0089] FIG. 18b shows a schematic diagram of a second conductive layer in a display substrate according to an exemplary embodiment of the present disclosure;

[0090] FIG. 19a shows a schematic diagram of a display substrate after forming a third conductive layer pattern according to an exemplary embodiment of the present disclosure;

[0091] FIG. 19b shows a schematic diagram of a third conductive layer in a display substrate according to an exemplary embodiment of the present disclosure;

[0092] FIG. 20 shows a schematic diagram of a display substrate after forming a fourth insulating layer pattern according to an exemplary embodiment of the present disclosure;

[0093] FIG. 21a shows a schematic diagram of a display substrate after forming a fourth conductive layer pattern according to an exemplary embodiment of the present disclosure;

[0094] FIG. 21b shows a schematic diagram of a fourth conductive layer in a display substrate according to an exemplary embodiment of the present disclosure;

[0095] FIG. 21c shows a schematic diagram of a display substrate after forming a pixel definition layer pattern according to an exemplary embodiment of the present disclosure;

[0096] FIG. 22 shows a schematic diagram of a display substrate after forming a first conductive layer pattern according to an exemplary embodiment of the present disclosure;

[0097] FIG. 23a shows a schematic diagram of a display substrate after forming a second conductive layer pattern according to an exemplary embodiment of the present disclosure;

[0098] FIG. 23b shows a schematic view of a second conductive layer in a display substrate according to an example embodiment of the present disclosure;

[0099] FIG. 24a shows a schematic view of a display substrate after forming a semiconductor layer pattern according to an example embodiment of the present disclosure;

[0100] FIG. 24b shows a schematic view of a semiconductor layer in a display substrate according to an example embodiment of the present disclosure;

[0101] FIG. 25a shows a schematic view of a display substrate after forming a third conductive layer pattern according to an example embodiment of the present disclosure;

[0102] FIG. 25b shows a schematic view of a third conductive layer in a display substrate according to an example embodiment of the present disclosure;

[0103] FIG. 26 shows a schematic view of a display substrate after forming a fourth insulating layer pattern according to an example embodiment of the present disclosure;

[0104] FIG. 27a shows a schematic view of a display substrate after forming a fourth conductive layer pattern according to an example embodiment of the present disclosure;

[0105] FIG. 27b shows a schematic view of a fourth conductive layer in a display substrate according to an example embodiment of the present disclosure;

[0106] FIG. 28 shows a schematic view of a display substrate after forming a first planarization layer pattern according to an example embodiment of the present disclosure;

[0107] FIG. 29a shows a schematic view of a display substrate after forming a fifth conductive layer pattern according to an example embodiment of the present disclosure;

[0108] FIG. 29b shows a schematic view of a fifth conductive layer in a display substrate according to an example embodiment of the present disclosure;

[0109] FIG. 30 shows a schematic view of a display substrate after forming a second planarization layer pattern according to an example embodiment of the present disclosure;

[0110] FIG. 31a shows a schematic view of a display substrate after forming an anode conductive layer pattern according to an example embodiment of the present disclosure;

[0111] FIG. 31b shows a schematic view of an anode conductive layer in a display substrate according to an example embodiment of the present disclosure;

[0112] FIG. 32a shows a schematic view of a display substrate after forming a pixel definition layer pattern according to an example embodiment of the present disclosure;

[0113] FIG. 32b shows a schematic view of a pixel definition layer pattern in a display substrate according to an example embodiment of the present disclosure;

[0114] FIG. 33 shows a schematic diagram of a display substrate after forming a first conductive layer pattern according to an example embodiment of the present disclosure;

[0115] FIG. 34a shows a schematic diagram of a display substrate after forming a second conductive layer pattern according to an example embodiment of the present disclosure;

[0116] FIG. 34b shows a schematic diagram of a second conductive layer in a display substrate according to an example embodiment of the present disclosure;

[0117] FIG. 35a shows a schematic diagram of a display substrate after forming a semiconductor layer pattern according to an example embodiment of the present disclosure;

[0118] FIG. 35b shows a schematic diagram of a semiconductor layer in a display substrate according to an example embodiment of the present disclosure;

[0119] FIG. 36a shows a schematic diagram of a display substrate after forming a third conductive layer pattern according to an example embodiment of the present disclosure;

[0120] FIG. 36b shows a schematic diagram of a third conductive layer in a display substrate according to an example embodiment of the present disclosure;

[0121] FIG. 37 shows a schematic diagram of a display substrate after forming a fourth insulating layer pattern according to an example embodiment of the present disclosure;

[0122] FIG. 38a shows a schematic diagram of a display substrate after forming a fourth conductive layer pattern according to an example embodiment of the present disclosure;

[0123] FIG. 38b shows a schematic diagram of a fourth conductive layer in a display substrate according to an example embodiment of the present disclosure;

[0124] FIG. 39 shows a schematic diagram of a display substrate after forming a first planarization layer pattern according to an example embodiment of the present disclosure;

[0125] FIG. 40a shows a schematic diagram of a display substrate after forming a fifth conductive layer pattern according to an example embodiment of the present disclosure;

[0126] FIG. 40b shows a schematic diagram of a fifth conductive layer in a display substrate according to an example embodiment of the present disclosure;

[0127] FIG. 41 shows a schematic diagram of a display substrate after forming a second planarization layer pattern according to an example embodiment of the present disclosure;

[0128] FIG. 42a shows a schematic diagram of a display substrate after forming an anode conductive layer pattern according to an example embodiment of the present disclosure;

[0129] FIG. 42b shows a schematic view of an anode conductive layer in a display substrate according to an example embodiment of the present disclosure;

[0130] FIG. 43a shows a schematic view of a display substrate after forming a pixel definition layer pattern according to an example embodiment of the present disclosure;

[0131] FIG. 43b shows a schematic view of a pixel definition layer pattern in a display substrate according to an example embodiment of the present disclosure;

[0132] FIG. 44 shows a schematic view of a display substrate after forming a first conductive layer pattern according to an example embodiment of the present disclosure;

[0133] FIG. 45a shows a schematic view of a display substrate after forming a second conductive layer pattern according to an example embodiment of the present disclosure;

[0134] FIG. 45b shows a schematic view of a second conductive layer in a display substrate according to an example embodiment of the present disclosure;

[0135] FIG. 46a shows a schematic view of a display substrate after forming a third conductive layer pattern according to an example embodiment of the present disclosure;

[0136] FIG. 46b shows a schematic view of a third conductive layer in a display substrate according to an example embodiment of the present disclosure;

[0137] FIG. 47 shows a schematic view of a display substrate after forming a fourth insulating layer pattern according to an example embodiment of the present disclosure;

[0138] FIG. 48a shows a schematic view of a display substrate after forming a fourth conductive layer pattern according to an example embodiment of the present disclosure;

[0139] FIG. 48b shows a schematic view of a fourth conductive layer in a display substrate according to an example embodiment of the present disclosure;

[0140] FIG. 49 shows a schematic view of a display substrate after forming a pixel definition layer pattern according to an example embodiment of the present disclosure;

[0141] FIG. 50 shows a schematic view of a display device according to an example embodiment of the present disclosure. DETAILED DESCRIPTION

[0142] Embodiments of the present disclosure will be described below in detail with reference to the accompanying drawings. The embodiments can be implemented in various forms. It should be easily understood by those of ordinary skill in the art that the embodiments and the contents can be changed into various forms without departing from the spirit and scope of the present disclosure. Therefore, the present disclosure should not be construed as being limited to the contents described in the following embodiments. The embodiments in the present disclosure and the features in the embodiments can be arbitrarily combined with each other without conflict unless otherwise specified. In order to keep the following description of the embodiments of the present disclosure clear and concise, detailed description of some known functions and known components will be omitted. The drawings of the embodiments of the present disclosure only involve structures related to the embodiments of the present disclosure, and other structures can be referred to the generally designed

[0143] The scale of the drawings in the present disclosure can be used as a reference in the actual process, but is not limited thereto. For example, the thickness and interval of each film layer, the width and interval of each signal line, can be adjusted according to the actual situation. The drawings described in the present disclosure are only schematic structural diagrams, and one embodiment of the present disclosure is not limited to the shapes or values shown in the drawings.

[0144] In the present specification, ordinal numbers such as "first", "second", "third", and the like are set in order to avoid confusion of the components, and are not intended to be limiting in terms of numbers.

[0145] In the present specification, in order to facilitate the description and simplify the description, words indicating the orientation or positional relationship such as "middle", "upper", "lower", "front", "rear", "vertical", "horizontal", "top", "bottom", "inner", "outer", and the like are used to describe the positional relationship of the components with reference to the drawings, and are not intended to indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be construed as a limitation on the present disclosure. The positional relationship of the components is appropriately changed according to the direction of describing each component. Therefore, it is not limited to the words described in the specification, and can be appropriately changed according to the situation.

[0146] In the present specification, unless explicitly specified and limited, the terms "mount", "connect", "connection" should be interpreted broadly. For example, it can be fixedly connected, or detachably connected, or integrally connected; it can be mechanically connected, or electrically connected; it can be directly connected, or indirectly connected through an intermediate, or the communication inside two elements. For those of ordinary skill in the art, the specific meaning of the above terms in the present disclosure can be understood according to the specific circumstances.

[0147] In this specification, a transistor refers to an element including at least a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between a drain electrode (a drain electrode terminal, a drain region, or a drain electrode) and a source electrode (a source electrode terminal, a source region, or a source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that, in this specification, a channel region refers to a region where current flows mainly.

[0148] In this specification, a first electrode can be a drain electrode and a second electrode can be a source electrode, or a first electrode can be a source electrode and a second electrode can be a drain electrode. In the case of using a transistor whose polarity is reversed or in the case where the direction of current flowing in a circuit is changed, the functions of the "source electrode" and the "drain electrode" are sometimes interchanged with each other. Thus, in this specification, the "source electrode" and the "drain electrode" can be interchanged with each other, and the "source terminal" and the "drain terminal" can be interchanged with each other. In this embodiment of the disclosure, a gate electrode can be referred to as a control electrode.

[0149] In this specification, "electrically connected" includes the case where components are connected through an element having some function of electricity. An element having some function of electricity is not particularly limited as long as electric signals can be transmitted and received between components to be connected. Examples of an element having some function of electricity include not only an electrode and a wiring but also a switching element such as a transistor, a resistor, an inductor, a capacitor, and an element having another function.

[0150] In this specification, "parallel" refers to a state where an angle formed between two straight lines is greater than or equal to -10° and less than or equal to 10°, and thus a state where the angle is greater than or equal to -5° and less than or equal to 5° is also included. In addition, "perpendicular" refers to a state where an angle formed between two straight lines is greater than or equal to 80° and less than or equal to 100°, and thus a state where the angle is greater than or equal to 85° and less than or equal to 95° is also included.

[0151] In this specification, a "film" and a "layer" can be interchanged with each other. For example, a "conductive layer" can be replaced with a "conductive film". Similarly, an "insulating film" can be replaced with an "insulating layer".

[0152] In this specification, a triangle, a rectangle, a trapezoid, a pentagon, or a hexagon is not strictly a triangle, a rectangle, a trapezoid, a pentagon, or a hexagon, but can be an approximately triangle, a rectangle, a trapezoid, a pentagon, or a hexagon, and can have some small deformation due to a tolerance, a rounded corner, a rounded side, or deformation.

[0153] In this embodiment of the disclosure, "approximately" means that a limit is not strictly defined, and a value within a range of a process and measurement error is allowed.

[0154] FIG. 1 shows a structural schematic diagram of a display device, a display substrate can include a timing controller, a data signal driving circuit, a scan signal driving circuit, a light emission signal driving circuit, and a pixel array, the timing controller is connected with the data signal driving circuit, the scan signal driving circuit, and the light emission signal driving circuit respectively, the data signal driving circuit is connected with a plurality of data signal lines (D1 to Dn) respectively, the scan signal driving circuit is connected with a plurality of scan signal lines (G1 to Gm) respectively, and the light emission signal driving circuit is connected with a plurality of light emission signal lines (E1 to Eo) respectively. The pixel array can include a plurality of sub-pixels Pxij, i and j can be natural numbers, at least one sub-pixel Pxij can include a circuit unit and a light emitting device connected with the circuit unit, the circuit unit can include a pixel driving circuit, and the pixel driving circuit can be connected with a scan signal line, a light emission signal line, and a data signal line (which can be referred to as a data line) respectively. In an exemplary embodiment, the timing controller can provide a gray value and a control signal suitable for the specification of the data signal driving circuit to the data signal driving circuit, can provide a clock signal, a scan start signal, and the like suitable for the specification of the scan signal driving circuit to the scan signal driving circuit, and can provide a clock signal, an emission stop signal, and the like suitable for the specification of the light emission signal driving circuit to the light emission signal driving circuit. The data signal driving circuit can generate a data voltage to be provided to the data signal lines D1, D2, D3, …, and Dn using the gray value and the control signal received from the timing controller. For example, the data signal driving circuit can sample the gray value using the clock signal, and apply a data voltage corresponding to the gray value to the data signal lines D1 to Dn in units of a pixel row. n can be a natural number. The scan signal driving circuit can generate a scan signal to be provided to the scan signal lines G1, G2, G3, …, and Gm by receiving the clock signal, the scan start signal, and the like from the timing controller. For example, the scan signal driving circuit can sequentially provide a scan signal having an on-level pulse to the scan signal lines G1 to Gm. For example, the scan signal driving circuit can be configured in the form of a shift register, and can generate a scan signal in such a manner that an emission stop signal provided in the form of an off-level pulse is sequentially transferred to a next stage circuit under the control of a clock signal. m can be a natural number. The light emission signal driving circuit can generate an emission signal to be provided to the light emission signal lines E1, E2, E3, …, and Eo by receiving the clock signal, the emission stop signal, and the like from the timing controller. For example, the light emission signal driving circuit can sequentially provide an emission signal having an off-level pulse to the light emission signal lines E1 to Eo. For example, the light emission driver can be configured in the form of a shift register, and can generate an emission signal in such a manner that an emission stop signal provided in the form of an off-level pulse is sequentially transferred to a next stage circuit under the control of a clock signal. o can be a natural number.

[0155] FIG. 2 is a schematic diagram of a planar structure of a display substrate. As shown in FIG. 2, the display substrate can include a plurality of pixel units P arranged in a matrix manner, at least one of the plurality of pixel units P including a first sub-pixel P1 emitting first color light, a second sub-pixel P2 emitting second color light, and a third sub-pixel P3 emitting third color light, the first sub-pixel P1, the second sub-pixel P2, and the third sub-pixel P3 each including a pixel driving circuit and a light emitting device. The pixel driving circuit in the first sub-pixel P1, the second sub-pixel P2, and the third sub-pixel P3 is respectively connected with a scan signal line, a data signal line, and a light emitting signal line, and is configured to receive a data voltage transmitted by the data signal line under the control of the scan signal line and the light emitting signal line, and output a corresponding current to the light emitting device. The light emitting device in the first sub-pixel P1, the second sub-pixel P2, and the third sub-pixel P3 is respectively connected with the pixel driving circuit in the sub-pixel where the light emitting device is located, and is configured to emit light with a corresponding brightness in response to the current output by the pixel driving circuit in the sub-pixel where the light emitting device is located.

[0156] In an example embodiment, the pixel unit P can include a red (R) sub-pixel, a green (G) sub-pixel, and a blue (B) sub-pixel. In an example embodiment, the shape of the sub-pixels in the pixel unit can be rectangular, diamond, pentagonal, or hexagonal, and the three sub-pixels can be arranged in a horizontal parallel, vertical parallel, or triangular manner, which is not limited in the present disclosure.

[0157] FIG. 3 is a schematic diagram of a cross-sectional structure of a display substrate, illustrating the structure of three sub-pixels of an OLED display substrate. As shown in FIG. 5b, in a plane perpendicular to the display substrate, the display substrate can include a driving circuit layer 102 disposed on a substrate 101, a light emitting structure layer 103 disposed on a side of the driving circuit layer 102 away from the substrate 101, and an encapsulation layer 104 disposed on a side of the light emitting structure layer 103 away from the substrate 101. In some possible implementations, the display substrate can include other film layers, such as a spacer, which is not limited in the present disclosure.

[0158] In the example embodiment, the substrate 101 can be a flexible substrate, or can be a rigid substrate. The driving circuit layer 102 of each sub-pixel can include a plurality of transistors and a storage capacitor constituting a pixel driving circuit. The light-emitting structure layer 103 can include an anode 301 connected to the drain electrode of the driving transistor 210 through a via, an organic light-emitting layer 302 connected to the anode 301, and a cathode 303 connected to the organic light-emitting layer 302, the organic light-emitting layer 302 emitting light of a corresponding color under the driving of the anode 301 and the cathode 303. The encapsulation layer 104 can include a first encapsulation layer 401, a second encapsulation layer 402, and a third encapsulation layer 403 stacked together, the first encapsulation layer 401 and the third encapsulation layer 403 can be made of inorganic material, the second encapsulation layer 402 can be made of organic material, and the second encapsulation layer 402 is arranged between the first encapsulation layer 401 and the third encapsulation layer 403, so as to prevent external water vapor from entering the light-emitting structure layer 103.

[0159] In the example embodiment, the organic light-emitting layer 302 can include a hole injection layer (HIL), a hole transport layer (HTL), an electron block layer (EBL), an emitting layer (EML), a hole block layer (HBL), an electron transport layer (ETL), and an electron injection layer (EIL) stacked together. In the example embodiment, the hole injection layer of all sub-pixels can be a common layer connected together, the electron injection layer of all sub-pixels can be a common layer connected together, the hole transport layer of all sub-pixels can be a common layer connected together, the electron transport layer of all sub-pixels can be a common layer connected together, the hole block layer of all sub-pixels can be a common layer connected together, the emitting layer of adjacent sub-pixels can have a small amount of overlap, or can be isolated, and the electron block layer of adjacent sub-pixels can have a small amount of overlap, or can be isolated.

[0160] In an exemplary embodiment, the pixel driving circuit can be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, 7T1C, 8T1C or 7T2C structure. FIG. 4 is a schematic diagram of an equivalent circuit of a pixel driving circuit. As shown in FIG. 4, the pixel driving circuit can include 7 transistors (first transistor T1 to seventh transistor T7) and 2 capacitors C (first capacitor C1 and second capacitor C2), and can be connected with 11 signal lines (data signal line D, scan signal line Gate, first reset control line Reset1, second reset control line Reset2, third reset control line Reset3, first emission control line EM1, second emission control line EM2, first initial signal line Vinit1, second initial signal line Vinit2, first power supply line VDD and second power supply line VSS).

[0161] In an exemplary embodiment, the pixel driving circuit can include a first node N1, a second node N2, a third node N3, a fourth node N4 and a fifth node N5. The first node N1 is connected with the control electrode of the third transistor T3, the second electrode of the fourth transistor T4, the second end of the second capacitor C2 and the second electrode of the first transistor T1 respectively. The second node N2 is connected with the first electrode of the third transistor T3 and the second electrode of the fifth transistor T5 respectively. The third node N3 is connected with the second end of the first capacitor C1, the second electrode of the third transistor T3 and the first electrode of the sixth transistor T6 respectively. The fourth node N4 is connected with the first end of the first capacitor C1, the first end of the second capacitor C2 and the second electrode of the second transistor T2 respectively. The fifth node N5 is connected with the second electrode of the sixth transistor T6, the second electrode of the seventh transistor T7 and the anode of the light emitting device EL respectively.

[0162] In an exemplary embodiment, the first end of the first capacitor C1 is connected with the fourth node N4, and the second end of the first capacitor C1 is connected with the third node N3. The first end of the second capacitor C2 is connected with the fourth node N4, and the second end of the second capacitor C2 is connected with the first node N1.

[0163] The control electrode of the first transistor T1 is connected with the first reset control line Reset1, the first electrode of the first transistor T1 is connected with the first initial signal line Vinit1, and the second electrode of the first transistor is connected with the first node N1. When the turn-on level reset signal is applied to the first reset control line Reset1, the first transistor T1 transmits the initialization voltage to the control electrode of the third transistor T3, so as to initialize the charge amount of the control electrode of the third transistor T3.

[0164] The control electrode of the second transistor T2 is connected with the second reset control line Reset2, the first electrode of the second transistor T2 is connected with the first initial signal line Vinit1, and the second electrode of the second transistor T2 is connected with the fourth node N4.

[0165] The control electrode of the third transistor T3 is connected to the first node N1, the first electrode of the third transistor T3 is connected to the second node N2, and the second electrode of the third transistor T3 is connected to the third node N3. The third transistor T3 can be referred to as a drive transistor, and the third transistor T3 determines the amount of drive current flowing between the first power supply line VDD and the second power supply line VSS according to a potential difference between the control electrode and the first electrode thereof.

[0166] The control electrode of the fourth transistor T4 is connected to the scan signal line Gate, the first electrode of the fourth transistor T4 is connected to the data signal line D, and the second electrode of the fourth transistor T4 is connected to the first node N1. The fourth transistor T4 can be referred to as a switch transistor, and the fourth transistor T4 inputs a data voltage of the data signal line D to the pixel drive circuit when an on-level scan signal is applied to the scan signal line Gate.

[0167] The control electrode of the fifth transistor T5 is connected to the first emission control line EM1, the first electrode of the fifth transistor T5 is connected to the first power supply line VDD, and the second electrode of the fifth transistor T5 is connected to the second node N2. The control electrode of the sixth transistor T6 is connected to the second emission control line EM2, the first electrode of the sixth transistor T6 is connected to the third node N3, and the second electrode of the sixth transistor T6 is connected to the first electrode of the light emitting device (also the fifth node N5). The fifth transistor T5 and the sixth transistor T6 can be referred to as emission transistors. When on-level emission signals are applied to the first emission control line EM1 and the second emission control line EM2, the fifth transistor T5 and the sixth transistor T6 are turned on, and a drive current path is formed between the first power supply line VDD and the second power supply line VSS to cause the light emitting device to emit light.

[0168] The control electrode of the seventh transistor T7 is connected to the third reset control line Reset3, the first electrode of the seventh transistor T7 is connected to the second initial signal line Vinit2, and the second electrode of the seventh transistor T7 is connected to the first electrode of the light emitting device (also the fifth node N5). When an on-level reset signal is applied to the third reset control line Reset3, the seventh transistor T7 transmits an initialization voltage to the first electrode of the light emitting device to initialize the amount of charge accumulated in the first electrode of the light emitting device or release the amount of charge accumulated in the first electrode of the light emitting device.

[0169] In an example embodiment, the second electrode of the light emitting device is connected to a second power line VSS, and the signal of the second power line VSS is a low level signal, and the signal of the first power line VDD is a high level signal continuously provided. In an example embodiment, the first transistor T1 to the seventh transistor T7 can be P-type transistors, or can be N-type transistors. Using the same type of transistors in the pixel driving circuit can simplify the process flow, reduce the process difficulty of the display panel, and improve the yield of the product. In some possible implementations, the first transistor T1 to the seventh transistor T7 can include P-type transistors and N-type transistors.

[0170] In an example embodiment, the first transistor T1 to the seventh transistor T7 can be low temperature poly-silicon thin film transistors (which can be referred to as P-type transistors), or can be oxide thin film transistors (which can be referred to as N-type transistors), or can be low temperature poly-silicon thin film transistors and oxide thin film transistors. Using the same type of transistors in the pixel driving circuit can simplify the process flow, reduce the process difficulty of the display panel, and improve the yield of the product. The active layer of the low temperature poly-silicon thin film transistor uses low temperature poly-silicon (LTPS), and the active layer of the oxide thin film transistor uses oxide semiconductor (Oxide). The low temperature poly-silicon thin film transistor has the advantages of high mobility and fast charging, and the oxide thin film transistor has the advantages of low leakage current, low frequency driving, and low power consumption. Integrating the low temperature poly-silicon thin film transistor and the oxide thin film transistor on one display substrate forms a low temperature poly-crystalline oxide (LTPO) display substrate, which can take advantage of both, can realize low frequency driving, can reduce power consumption, and can improve display quality.

[0171] In an example embodiment, the light emitting device EL can be an organic light emitting diode (OLED) including a first electrode (anode), an organic light emitting layer, and a second electrode (cathode) stacked.

[0172] In a structure in which the pixel driving circuit uses all oxide transistors, the bias voltage of the single-gate structure transistor is unstable (English full name: Bias Temperature Stability, abbreviated as BTS), which causes the threshold voltage (Vth) of the transistor to shift, the stability of the transistor is low, and the stability of the pixel driving circuit is low; the double-gate structure transistor has an additional gate electrode, which on the one hand has a larger coupling capacitance (parasitic capacitance) and affects the luminance of the sub-pixel, and on the other hand, the pixel density (English full name: Pixels Per Inch, abbreviated as PPI) of the double-gate structure is reduced.

[0173] The display substrate provided by the example embodiments of the present disclosure can include a substrate and a plurality of sub-pixels arranged on one side of the substrate, at least one of the sub-pixels including a pixel driving circuit, at least one of the pixel driving circuits including a plurality of transistors, the transistors including an active layer and at least one gate electrode; in the same transistor, the at least one gate electrode at least partially overlaps the active layer, and the at least one gate electrode includes at least one of a top gate and a bottom gate; in a direction perpendicular to a plane in which the substrate is located, the bottom gate is located on a side of the active layer close to the substrate, and the top gate is located on a side of the active layer away from the substrate; the plurality of transistors includes at least a driving transistor, and a gate electrode of the driving transistor includes a top gate and a bottom gate.

[0174] The display substrate provided by the example embodiments of the present disclosure can include a substrate and a plurality of sub-pixels arranged on one side of the substrate, at least one of the sub-pixels including a pixel driving circuit, at least one of the pixel driving circuits including a plurality of transistors, the transistors including an active layer and at least one gate electrode; in the same transistor, the at least one gate electrode at least partially overlaps the active layer, and the at least one gate electrode includes at least one of a top gate and a bottom gate; the plurality of transistors includes at least a driving transistor, and a gate electrode of the driving transistor includes a top gate and a bottom gate.

[0175] As shown in FIGS. 5a-5e, the display substrate provided by the example embodiments of the present disclosure can include a substrate and a plurality of sub-pixels Pxij arranged on one side of the substrate, at least one of the sub-pixels Pxij including a pixel driving circuit pdc, at least one of the pixel driving circuits pdc including a plurality of transistors, the transistors including an active layer and at least one gate electrode; in the same transistor, the at least one gate electrode at least partially overlaps the active layer, and the at least one gate electrode includes at least one of a top gate and a bottom gate; in a direction perpendicular to a plane in which the substrate is located, the bottom gate is located on a side of the active layer close to the substrate, and the top gate is located on a side of the active layer away from the substrate; the plurality of transistors includes at least a driving transistor T3, and a gate electrode of the driving transistor T3 includes a top gate T3gt and a bottom gate T3gb.

[0176] In the example embodiments, the plurality of transistors can further include a first light-emitting control transistor T5 and a second light-emitting control transistor T6, and the first light-emitting control transistor T5 and the second light-emitting control transistor T6 each include a top gate.

[0177] In the same pixel driving circuit pdc, a second electrode of the first light-emitting control transistor T5 is connected to a first electrode of the driving transistor T3, and a first electrode of the second light-emitting control transistor T6 is connected to a second electrode of the driving transistor T3.

[0178] In the example embodiments, the sub-pixel Pxij can further include an anode AN, and the plurality of transistors can further include an anode reset transistor, and a gate electrode of the anode reset transistor includes a top gate.

[0179] In the same sub-pixel Pxij, the second electrode of the anode reset transistor and the second electrode of the second light-emitting control transistor T6 are connected with the anode AN, and the anode AN is located on the side of the pixel driving circuit pdc away from the substrate in the direction perpendicular to the plane where the substrate is located.

[0180] In the exemplary embodiments, as shown in FIGS. 5b-5e, the first light-emitting control transistor T5, the second light-emitting control transistor T6, and the anode reset transistor can also include a bottom gate.

[0181] In the exemplary embodiments, the plurality of transistors can also include a data writing transistor T4 and a first reset transistor T1, the gate of the data writing transistor T4 and the first reset transistor T1 includes at least one of a top gate and a bottom gate, and in the same sub-pixel Pxij, the second electrode of the data writing transistor T4 and the second electrode of the first reset transistor T1 are connected with the top gate of the driving transistor T3.

[0182] In the exemplary embodiments, as shown in FIGS. 5a-5e, the pixel driving circuit pdc can also include at least one capacitor;

[0183] In the direction perpendicular to the plane where the substrate is located, the capacitor can include: a first plate located on one side of the substrate, and a second plate located on the side of the first plate away from the substrate; the bottom gate can be disposed in the same layer as the second plate, and the active layer can be located on the side of the second plate away from the substrate; the transistor can also include: a first electrode and a second electrode located on the side of the top gate away from the substrate; in the same capacitor, the orthographic projection of the first plate on the substrate at least partially overlaps the orthographic projection of the second plate on the substrate.

[0184] In the exemplary embodiments, as shown in FIGS. 5a-5e, the pixel driving circuits pdc of the plurality of sub-pixels Pxij form a plurality of rows, the plurality of rows of pixel driving circuits pdc are arranged in sequence along the column direction Y, the plurality of pixel driving circuits pdc in the same row are arranged in sequence along the row direction X, and the row direction X intersects the column direction Y in the plane parallel to the plane where the substrate is located.

[0185] In the same pixel driving circuit pdc, in the column direction Y, the first light-emitting control transistor T5 is located on one side of the driving transistor T3 and the at least one capacitor, the second light-emitting control transistor T6 is located on the other side of the driving transistor T3 and the at least one capacitor, the anode reset transistor is located on the side of the second light-emitting control transistor T6 away from the driving transistor T3 and the at least one capacitor, and the orthographic projection of the driving transistor T3 on the substrate at least partially overlaps the orthographic projection of the at least one capacitor on the substrate.

[0186] In the example embodiment, as shown in FIGS. 5a-5e, the plurality of transistors can include a first reset transistor T1 and a data write transistor T4.

[0187] In the same pixel driving circuit pdc, in the row direction X, the first reset transistor T1 and the data write transistor T4 are located on the same side of the driving transistor T3, in the column direction Y, the data write transistor T4 and the first light-emitting control transistor T5 are located on the same side of the driving transistor T3, and the first light-emitting control transistor T5 is located on the side of the data write transistor T4 away from the driving transistor T3; the first reset transistor T1 and the second light-emitting control transistor T6 are located on the same side of the driving transistor T3, and the second light-emitting control transistor T6 is located on the side of the first reset transistor T1 away from the driving transistor T3; the second electrode of the first reset transistor T1 and the second electrode of the data write transistor T4 are connected to the top gate T3gt of the driving transistor T3.

[0188] In the example embodiment, the equivalent circuit diagram of the pixel driving circuit in FIG. 5a can be as shown in FIG. 6a, the equivalent circuit diagram of the pixel driving circuit in FIG. 5b can be as shown in FIG. 6b, the equivalent circuit diagram of the pixel driving circuit in FIG. 5c can be as shown in FIG. 6c, the equivalent circuit diagram of the pixel driving circuit in FIG. 5d can be as shown in FIG. 6d, and the equivalent circuit diagram of the pixel driving circuit in FIG. 5e can be as shown in FIG. 6e. As shown in FIGS. 5a-6e, the gate of the driving transistor T3 can include a top gate T3gt and a bottom gate T3gb, which can improve the stability of the pixel driving circuit and avoid threshold voltage shift caused by unstable bias voltage of the oxide type driving transistor T3.

[0189] In the example embodiment, as shown in FIGS. 5a-6e, the first transistor T1 in the pixel driving circuit can be a first reset transistor, the third transistor T3 can be a driving transistor, the fourth transistor T4 can be a data write transistor, the fifth transistor T5 can be a first light-emitting control transistor, and the sixth transistor T6 can be a second light-emitting control transistor. In the structure shown in FIGS. 5a-5c, 6a-6c, the second transistor T2 can be a second reset control transistor, the seventh transistor T7 can be an anode reset transistor, and the third reset control line Reset3 can be an anode reset control line; in the structure shown in FIGS. 5d-5e, 6d-6e, the second transistor T2 can be an anode reset transistor, and the second reset control line Reset2 can be an anode reset control line.

[0190] In an example embodiment, as shown in FIGS. 5a-5c, the at least one capacitor can include a first capacitor C1 and a second capacitor C2, in the same pixel driving circuit pdc, a first plate C11 of the first capacitor C1 and a first plate C21 of the second capacitor C2 are connected to each other, a second plate C12 of the first capacitor C1 is connected to a second electrode of the driving transistor T3, a second plate C22 of the second capacitor C2 is connected to a top gate T3gt of the driving transistor T3, a normal projection of the driving transistor T3 on the substrate at least partially overlaps a normal projection of the first capacitor C1 on the substrate, and the second plate C12 of the first capacitor C1 can serve as a bottom gate T3gb of the driving transistor T3.

[0191] In an example embodiment, as shown in FIGS. 5a-5c, the plurality of transistors in the pixel driving circuit can include a second reset transistor T2, in the same pixel driving circuit pdc, a second electrode of the second reset transistor T2 is connected to the first plate C11 of the first capacitor C1 and the first plate C21 of the second capacitor C2.

[0192] In the same pixel driving circuit pdc, in the column direction Y, the second reset transistor T2 is located on a side of the first reset transistor T1 away from the data writing transistor T4, and in the row direction X, the second reset transistor T2 is located on the same side of the driving transistor T3 as the first reset transistor T1.

[0193] In an example embodiment, as shown in FIGS. 5a-5b, the display substrate can further include a plurality of first reset control lines Reset1, a plurality of second reset control lines Reset2, a plurality of scan signal lines Gate, and a plurality of anode reset control lines Reset3, the first reset control lines Reset1, the second reset control lines Reset2, the scan signal lines Gate, and the anode reset control lines Reset3 are disposed in the same layer as the first electrode and the second electrode, and the gates of the first reset transistor T1, the second reset transistor T2, and the data writing transistor T4 include top gates.

[0194] The first reset control lines Reset1 are connected to the top gates T1gt of at least some of the first reset transistors T1 in at least one row of pixel driving circuits, the second reset control lines Reset2 are connected to the top gates T2gt of at least some of the second reset transistors T2 in at least one row of pixel driving circuits, the scan signal lines Gate are connected to the top gates T4gt of at least some of the data writing transistors T4 in at least one row of pixel driving circuits, and the anode reset control lines Reset3 are connected to the top gates T7gt of at least some of the anode reset transistors T7 in at least one row of pixel driving circuits pdc.

[0195] In the same pixel driving circuit pdc, in the column direction Y, the first capacitor C1 is located on the side of the second capacitor C2 away from the second light-emitting control transistor T6, the second capacitor C2 is located on the side of the first capacitor C1 away from the first light-emitting control transistor T5, and the anode reset control line Reset3, the second reset control line Reset2, the first reset control line Reset1 and the scan signal line Gate can be arranged in sequence along the column direction Y.

[0196] In the exemplary embodiments, in the structure shown in FIG. 5b, the first light-emitting control transistor T5, the second light-emitting control transistor T6 and the anode reset transistor T7 can also include a bottom gate; and the anode reset control line Reset3 can also be connected to the bottom gate T7gb of at least part of the anode reset transistor T7 in at least one row of pixel driving circuits pdc.

[0197] In the exemplary embodiments, in the structures shown in FIG. 5a and FIG. 5b, the first plate C11 of the first capacitor C1 and the first plate C21 of the second capacitor C2 can be an integral structure, the shapes of the first plate C11 and the second plate C12 of the first capacitor C1 and the first plate C21 and the second plate C22 of the second capacitor C2 can be rectangular structures, the area of the second plate C12 of the first capacitor C1 is consistent with the area of the second plate C22 of the second capacitor C2, the second plate C22 of the second capacitor C2 is provided with an opening K11, and the second electrode of the second reset transistor T2 is connected to the first plate C11 of the first capacitor C1 and the first plate C21 of the second capacitor C2 through a via at the position of the opening K11.

[0198] In the exemplary embodiments, in the structures shown in FIG. 5a and FIG. 5b, the pixel driving circuit pdc can further include a relay connection electrode L4, and the relay connection electrode L4 can be arranged in the same layer as the first electrode and the second electrode; the top gate T3gt of the driving transistor T3 can include a first part T3gt1 and a second part T3gt2, the shape of the first part T3gt1 is rectangular, and the shape of the second part T3gt2 is a strip shape or a polyline shape extending along the column direction Y.

[0199] In the same driving transistor T3, the first part T3gt1 is connected to the second part T3gt2, in the column direction Y, the second part T3gt2 is located on the side of the first part T3gt1 away from the first light-emitting control transistor T5, the orthogonal projection of the first part T3gt1 on the substrate at least partially overlaps the orthogonal projection of the first capacitor C1 on the substrate, and the orthogonal projection of the second part T3gt2 on the substrate at least partially overlaps the orthogonal projection of the first capacitor C1 and the second capacitor C2 on the substrate; the relay connection electrode L4 is electrically connected to the second plate C22 of the second capacitor C2 and the second part T3gt2 through a via.

[0200] In the structure shown in FIGS. 5a and 5b, the display substrate can further include a plurality of second power supply connection lines VSSL, which are arranged in the same layer as the first electrode and the second electrode, and the main body portions of the plurality of second power supply connection lines VSSL extend along the row direction X and are arranged at intervals along the column direction Y.

[0201] In the same pixel driving circuit pdc, along the column direction Y, the second power supply connection line VSSL is located on the side of the scan signal line Gate away from the first reset control line Reset1, the second electrode of the first reset transistor T1, the second electrode of the data writing transistor T4, and the second electrode of the driving transistor T3 are located between the scan signal line Gate and the first reset control line Reset1, and the switching connection electrode L4 and the second electrode of the second reset transistor T2 are located between the first reset control line Reset1 and the second reset control line Reset2.

[0202] In the structure shown in FIG. 5c, the display substrate can include a plurality of first reset control lines Reset1, a plurality of second reset control lines Reset2, a plurality of scan signal lines Gate, and a plurality of anode reset control lines Reset3, which extend along the row direction X, the first reset control line Reset1, the second reset control line Reset2, the scan signal line Gate, and the anode reset control line Reset3 are arranged in the same layer as the first electrode and the second electrode, and the anode reset control line Reset3 is arranged in the same layer as the top gate; the first reset transistor T1, the second reset transistor T2, the data writing transistor T4, the first light-emitting control transistor T5, the second light-emitting control transistor T6, and the anode reset transistor T7 all include a top gate and a bottom gate.

[0203] The first reset control line Reset1 is connected with the top gate T1gt and the bottom gate T1gb of at least part of the first reset transistors T1 in at least one row of pixel driving circuits, the second reset control line Reset2 is connected with the top gate T2gt and the bottom gate T2gb of at least part of the second reset transistors T2 in at least one row of pixel driving circuits, the scan signal line Gate is connected with the top gate T4gt and the bottom gate T4gb of at least part of the data writing transistors T4 in at least one row of pixel driving circuits, and the anode reset control line Reset3 is provided with the top gate T7gt of at least part of the anode reset transistors T7 in at least one row of pixel driving circuits.

[0204] In the same pixel driving circuit pdc, along the column direction Y, the first capacitor C1 is located on the side of the second capacitor C2 away from the first light-emitting control transistor T5, the second capacitor C2 is located on the side of the first capacitor C1 away from the second light-emitting control transistor T6, and the anode reset control line Reset3, the second reset control line Reset2, the first reset control line Reset1, and the scan signal line Gate are arranged at intervals along the column direction Y.

[0205] In the structure shown in FIG. 5c, in an exemplary embodiment, the first plate C11 of the first capacitor C1 and the first plate C21 of the second capacitor C2 can be an integral structure, the first plate C11 and the second plate C12 of the first capacitor C1 and the first plate C21 and the second plate C22 of the second capacitor C2 are in the shape of a block structure, and the area of the second plate C22 of the second capacitor C2 is smaller than the area of the second plate C12 of the first capacitor C1; the first plate C11 of the first capacitor C1 is provided with a first connecting portion CL1, the second plate C12 of the first capacitor C1 is provided with a second connecting portion CL2, and the orthographic projections of the first connecting portion CL1 and the second connecting portion CL2 on the base at least partially do not overlap.

[0206] In the same pixel driving circuit pdc, in the column direction Y, the first connecting portion CL1 and the second connecting portion CL2 are located on the side of the first capacitor C1 away from the first light-emitting control transistor T5, the second electrode of the second reset transistor T2 is connected to the first connecting portion CL1 through a via, and the second electrode of the driving transistor T3 is connected to the second connecting portion CL2 through a via.

[0207] In the structure shown in FIG. 5c, in an exemplary embodiment, the display substrate can further include a plurality of second power supply connecting lines VSSL, the second power supply connecting lines VSSL are provided in the same layer as the first electrode and the second electrode, and the main body portions of the plurality of second power supply connecting lines VSSL extend in the row direction X and are arranged at intervals in the column direction Y.

[0208] In the same pixel driving circuit pdc, in the column direction Y, the second power supply connecting line VSSL is located between the scan signal line Gate and the first reset control line Reset1, the second electrode of the first reset transistor T1 is located between the second power supply connecting line VSSL and the first reset control line Reset1, the second electrode of the data writing transistor T4 is located between the scan signal line Gate and the second power supply connecting line VSSL, and the second electrode of the driving transistor T3 is located between the first reset control line Reset1 and the second reset control line Reset2.

[0209] In the structure shown in FIG. 5c, in an exemplary embodiment, the display substrate can further include a plurality of third shielding lines BL3, the third shielding lines BL3 are provided in the same layer as the second electrode plate, and the plurality of third shielding lines BL3 can be in the shape of a fold line or a strip with the main body portion extending in the row direction X and arranged at intervals in the column direction Y.

[0210] The third shielding line BL3 is provided with at least one bottom gate T7gb of at least part of the anode reset transistor T7 in at least one row of pixel driving circuits pdc, and the orthographic projections of the third shielding line BL3 and the anode reset control line Reset3 on the base at least partially overlap.

[0211] In the structure shown in FIG. 5c, in an exemplary embodiment, in the same row of pixel driving circuits pdc, the third shielding line BL3 covers the orthogonal projection of the anode reset control line Reset3 on the substrate.

[0212] In the structures shown in FIG. 5d and FIG. 5e, in an exemplary embodiment, the at least one capacitor includes a first capacitor C1 and a second capacitor C2, in the same pixel driving circuit pdc, the second electrode of the driving transistor T3 is electrically connected with the second electrode plate C12 of the first capacitor C1 and the second electrode plate C22 of the second capacitor C2, the first electrode plate C11 of the first capacitor C1 is connected with the top gate of the driving transistor T3, the orthogonal projection of the driving transistor T3 on the substrate at least partially overlaps with the orthogonal projection of the second capacitor C2 on the substrate, and the second electrode plate C22 of the second capacitor C2 serves as the bottom gate T3gb of the driving transistor T3.

[0213] In the same pixel driving circuit pdc, in the column direction Y, the first capacitor C1 is located on the side of the second capacitor C2 away from the first light-emitting control transistor T5, and the second capacitor C2 is located on the side of the first capacitor C1 away from the second light-emitting control transistor T6.

[0214] In the structures shown in FIG. 5d and FIG. 5e, in an exemplary embodiment, the display substrate can further include a plurality of first reset control lines Reset1, a plurality of scanning signal lines Gate, and a plurality of anode reset control lines Reset2, the first reset control lines Reset1, the scanning signal lines Gate, and the anode reset control lines Reset2 are arranged in the same layer as the first electrode and the second electrode; in the same row of pixel driving circuits pdc, the anode reset control lines Reset2, the first reset control lines Reset1, and the scanning signal lines Gate are arranged in sequence in the column direction Y.

[0215] The first reset transistor T1, the data writing transistor T4, the first light-emitting control transistor T5, the second light-emitting control transistor T6, and the anode reset transistor T2 can include a bottom gate T2gb; the first reset control line Reset1 is connected with the bottom gate T1gb of at least part of the first reset transistors T1 in at least one row of pixel driving circuits, the scanning signal line Gate is connected with the bottom gate T4gb of at least part of the data writing transistors T4 in at least one row of pixel driving circuits, and the anode reset control line Reset2 is connected with the top gate T2gt and the bottom gate T2gb of at least part of the anode reset transistors T2 in at least one row of pixel driving circuits pdc.

[0216] In an exemplary embodiment, in the structure shown in FIG. 5d, the first reset transistor T1 and the data write transistor T4 can further include a top gate; the first reset control line Reset1 is further connected to the top gate T1gt of at least part of the first reset transistor T1 in at least one row of pixel driving circuits pdc, and the scan signal line Gate is further connected to the top gate T4gt of at least part of the data write transistor T4 in at least one row of pixel driving circuits.

[0217] In an exemplary embodiment, in the structure shown in FIG. 5d and FIG. 5e, the display substrate can further include a plurality of second power supply connection lines VSSL, the second power supply connection lines VSSL are arranged in the same layer as the first electrode and the second electrode, and the main body part of the plurality of second power supply connection lines VSSL extends along the row direction X and is arranged at intervals along the column direction Y.

[0218] In the same pixel driving circuit pdc, along the column direction Y, the second power supply connection line VSSL is located between the scan signal line Gate and the first reset control line Reset1, and the second electrode of the first reset transistor T1, the second electrode of the data write transistor T4 and the second electrode of the driving transistor T3 are located between the scan signal line Gate and the second power supply connection line VSSL.

[0219] In an exemplary embodiment, in the structure shown in FIG. 5a to FIG. 5e, the display substrate can further include a plurality of first light emitting control lines EM1 and a plurality of second light emitting control lines EM2, the first light emitting control lines EM1 and the second light emitting control lines EM2 are arranged in the same layer as the top gate; the plurality of first light emitting control lines EM1 and the plurality of second light emitting control lines EM2 are polyline or strip-shaped with the main body part extending along the row direction X and arranged at intervals along the column direction Y.

[0220] The first light emitting control line EM1 is electrically connected to at least part of the first light emitting control transistor T5 in at least one row of pixel driving circuits pdc, and the second light emitting control line EM2 is electrically connected to at least part of the second light emitting control transistor T6 in at least one row of pixel driving circuits pdc; the area where the first light emitting control line EM1 overlaps with the active layer of the first light emitting control transistor T5 can be used as the top gate T5gt of the first light emitting control transistor T5, and the area where the second light emitting control line EM2 overlaps with the active layer of the second light emitting control transistor T6 can be used as the top gate T6gt of the second light emitting control transistor T6.

[0221] In the same pixel driving circuit pdc, in the column direction Y, the first light-emitting control line EM1 and the first light-emitting control transistor T5 are located on the same side of the driving transistor T3, the second light-emitting control line EM2 and the second light-emitting control transistor T6 are located on the same side of the driving transistor T3, the anode reset control line is located on the side of the second light-emitting control line EM2 away from the first light-emitting control line EM1, and the first reset control line Reset1 and the scan signal line Gate are located between the first light-emitting control line EM1 and the second light-emitting control line EM2.

[0222] In the structure shown in FIGS. 5b-5e, the display substrate can further include a plurality of first shielding lines BL1 and a plurality of second shielding lines BL2, the plurality of first shielding lines BL1 and the plurality of second shielding lines BL2 are disposed in the same layer as the second plate; the plurality of first shielding lines BL1 and the plurality of second shielding lines BL2 are fold line-shaped or strip-shaped and extend along the row direction X, and are arranged at intervals along the column direction Y.

[0223] In the same row of pixel driving circuits pdc, the first shielding line BL1 and the first light-emitting control line EM1 at least partially overlap in the orthographic projection on the substrate, and the second shielding line BL2 and the second light-emitting control line EM2 at least partially overlap in the orthographic projection on the substrate; the region where the first shielding line BL1 overlaps with the active layer of the first light-emitting control transistor T5 can be used as the bottom gate T5gb of the first light-emitting control transistor T5, and the region where the second shielding line BL2 overlaps with the active layer of the second light-emitting control transistor T6 can be used as the bottom gate T6gb of the second light-emitting control transistor T6.

[0224] In the structure shown in FIGS. 5b-5e, in the same row of pixel driving circuits pdc, the orthographic projection of the first shielding line BL1 on the substrate covers the orthographic projection of the first light-emitting control line EM1 on the substrate, and the orthographic projection of the second shielding line BL2 on the substrate covers the orthographic projection of the second light-emitting control line EM2 on the substrate.

[0225] In the structure shown in FIGS. 5a and 6a, the driving transistor T3 in the pixel driving circuit is a double-gate structure (including a top gate T3gt and a bottom gate T3gb), and the first reset transistor T1, the second reset transistor T2, the data writing transistor T4, the first light-emitting control transistor T5, the second light-emitting control transistor T6, and the anode reset transistor T7 are all single-gate structures (the gate includes a top gate). Under the premise of the stability of the driving transistor T3, high PPI and the influence of the coupling capacitance on the light-emitting brightness can be considered; in the case of the same PPI, the space is larger, and a larger capacitance can be designed, which is conducive to stabilizing the voltage jump node voltage, reducing the influence of parasitic capacitance, and the bias voltage instability is slightly lower than that of the structure of FIGS. 5b and 5e.

[0226] In the structures shown in FIGS. 5b, 5e, 6b and 6e, in an example embodiment, the driving transistor T3, the first light-emitting control transistor T5, the second light-emitting control transistor T6 and the anode reset transistor in the pixel driving circuit are all double-gate structures, and the other transistors are single-gate structures. Compared with the structures shown in FIGS. 5a and 6a, the stability of the pixel driving circuit is improved, the coupling capacitance is relatively increased (the influence of the coupling capacitance on the light-emitting brightness is relatively increased), and the pixel density is relatively decreased. By using the double-gate structure for the local transistors in the pixel driving circuit, the relatively high PPI and the relatively small influence of the coupling capacitance can be considered under the premise of improving the stability of the pixel driving circuit.

[0227] In the structures shown in FIGS. 5c, 5d, 6c and 6d, in an example embodiment, the transistors in the pixel driving circuit are all double-gate structures. Compared with the structures shown in FIGS. 5b, 5e, 6b and 6e, the stability of the pixel driving circuit is improved, the coupling capacitance is relatively increased (the influence of the coupling capacitance on the light-emitting brightness is relatively increased), and the pixel density is relatively decreased. In the same PPI, it is difficult to design a large capacitance value, and the capacitance shape is usually irregular.

[0228] In an example embodiment, in the structure of the local transistors with double-gate structures shown in FIG. 5e, compared with the structure in which all the transistors are double-gate structures shown in FIG. 5d, the area of the first capacitor C1 can be increased by 5% to 12%, and the area of the second capacitor C2 can be increased by 10% to 15%. The increase in the capacitance is beneficial to the stability of the node voltage.

[0229] By simulating the pixel driving circuit of the 7T2C, the influence of the parasitic capacitance of the double-gate structure on the brightness change of the sub-pixel is analyzed. The parasitic capacitance of the first reset transistor T1, the second reset transistor T2 and the data writing transistor T4 has a greater influence on the brightness change of the sub-pixel. Therefore, in some display substrates, the first reset transistor T1, the second reset transistor T2 and the data writing transistor T4 are designed as single-gate structures, and the parasitic capacitance of the other transistors has little influence on the brightness of the sub-pixel, and is suitable for double-gate structures, thereby enhancing the stability of the pixel driving circuit. In order to improve the stability of the bias voltage of the transistor with a single-gate structure, a shielding structure can be appropriately arranged on the side of the transistor with a single-gate structure away from the substrate.

[0230] Generally, the parasitic capacitance of a transistor can include a gate-source capacitance and a gate-drain capacitance. The parasitic capacitance of a double-gate structure is approximately twice that of a single-gate structure. The influence of the parasitic capacitance on the node in the 7T2C pixel driving circuit shown in FIGS. 5a to 5c, 6a to 6c is analyzed as follows:

[0231] The parasitic capacitance of the first reset transistor T1 increases, the capacitance voltage is larger, and the voltage of the first node N1 jumps down by a larger amount when the first reset control line Reset1 provides a turn-off signal. Therefore, the parasitic capacitance of the second reset transistor T2 has a greater impact on the voltage of the first node N1 when the voltage jumps, thereby having a greater impact on the brightness of the sub-pixel.

[0232] The parasitic capacitance of the second reset transistor T1 increases, the capacitance voltage is larger, and the voltage of the fourth node N4 jumps down by a larger amount when the second reset control line Reset2 provides a turn-off signal. Due to the capacitive coupling, the voltage of the first node N1 jumps down by a larger amount. Therefore, the parasitic capacitance of the second reset transistor T2 has a greater impact on the voltage of the first node N1 when the voltage jumps, thereby having a greater impact on the brightness of the sub-pixel.

[0233] The parasitic capacitance of the data write transistor T4 increases, the capacitance voltage is larger, and the voltage of the first node N1 jumps down by a larger amount when the scan signal line Gate provides a turn-off signal. Therefore, the parasitic capacitance of the data write transistor T4 has a greater impact on the voltage of the first node N1 when the voltage jumps, thereby having a greater impact on the brightness of the sub-pixel.

[0234] Tables 1 to 3 are simulation data of the value CV of the parasitic capacitance of the first reset transistor T1, the second reset transistor T2, and the data write transistor T4 of the 7T2C pixel driving circuit and the impact on the brightness of the sub-pixel.

[0235] Table 1

[0236] Table 2

[0237] Table 3

[0238] As can be seen from the simulation analysis results of Tables 1 to 2, the greater the value CV of the parasitic capacitance of the first reset transistor T1, the second reset transistor T2, and the data write transistor T4 of the 7T2C pixel driving circuit, the greater the impact on the brightness of the sub-pixel.

[0239] In the example embodiment, the above-described row direction X can be referred to as a first direction X, and the above-described column direction Y can be referred to as a second direction Y.

[0240] In the example embodiment, the English full name of the pixel driving circuit is pixel driving circuit (abbreviated as pdc).

[0241] In the structure shown in FIGS. 5a-5e, in an exemplary embodiment, the plurality of sub-pixels Pxij can include a first sub-pixel P1, a second sub-pixel P2, and a third sub-pixel P3, in the same pixel unit, the normal projection of the anode AN3 of the third sub-pixel P3 on the substrate at least partially overlaps the normal projection of the pixel driving circuit pdc of the first sub-pixel P1, the normal projection of the pixel driving circuit pdc of the second sub-pixel P2, and the normal projection of the pixel driving circuit pdc of the third sub-pixel P3 on the substrate; the normal projection of the anode AN1 of the first sub-pixel P1 on the substrate at least partially overlaps the normal projection of the pixel driving circuit pdc of the first sub-pixel P1 on the substrate; and the normal projection of the anode AN2 of the second sub-pixel P2 on the substrate at least partially overlaps the normal projection of the pixel driving circuit pdc of the second sub-pixel P2 on the substrate.

[0242] The preparation process of the display substrate is exemplarily illustrated below. The "patterning process" in the present disclosure includes coating photoresist, mask exposure, development, etching, stripping photoresist, etc. for metal materials, inorganic materials, or transparent conductive materials, and includes coating organic materials, mask exposure, and development, etc. for organic materials. The deposition can adopt any one or more of sputtering, evaporation, and chemical vapor deposition, the coating can adopt any one or more of spraying, spin coating, and inkjet printing, and the etching can adopt any one or more of dry etching and wet etching, which are not limited in the present disclosure. The "thin film" refers to a thin film of a certain material on a substrate (or a substrate substrate) made by deposition, coating, or other processes. If the "thin film" does not need a patterning process during the entire manufacturing process, the "thin film" can also be referred to as a "layer". If the "thin film" needs a patterning process during the entire manufacturing process, it is referred to as a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern". The "A and B are disposed in the same layer" in the present disclosure means that A and B are formed at the same time by the same patterning process. The "thickness" of the film layer is the size of the film layer in the direction perpendicular to the display substrate. In the exemplary embodiments of the present disclosure, "the normal projection of B is within the range of the normal projection of A" or "the normal projection of A contains the normal projection of B" means that the boundary of the normal projection of B falls within the boundary range of the normal projection of A, or the boundary of the normal projection of A overlaps the boundary of the normal projection of B.

[0243] In an exemplary embodiment, taking 3 sub-pixels (1 row of pixel driving circuits of 1 sub-pixel, 3 columns of pixel driving circuits of 3 sub-pixels, and pixel driving circuits adopting a 7T2C structure) in a display area (AA) as an example, the preparation process of one kind of display substrate can include the following operations:

[0244] (101) A substrate is prepared on a glass carrier. In an example embodiment, the substrate can be a flexible substrate, or can be a rigid substrate. The rigid substrate can include, but is not limited to, one or more of glass, quartz, and the flexible substrate can be, but is not limited to, one or more of polyethylene terephthalate, polyether ether ketone, polystyrene, polycarbonate, polyarylate, polyarylate, polyimide, polyvinyl chloride, polyethylene, and textile fibers. In an example embodiment, the flexible substrate can include a first flexible material layer, a first inorganic material layer, a bonding layer, a second flexible material layer, and a second inorganic material layer stacked together. The materials of the first and second flexible material layers can be polyimide (PI), polyethylene terephthalate (PET), or a surface-treated polymer soft film, and the like, and the materials of the first and second inorganic material layers can be silicon nitride (SiNx) or silicon oxide (SiOx), and the like, for improving the water and oxygen resistance of the substrate, and the first and second inorganic material layers are also referred to as barrier layers, and the material of the bonding layer can be amorphous silicon (a-si). In an example embodiment, taking the stacked structure PI1 / Barrier1 / a-si / PI2 / Barrier2 as an example, the preparation process can include: first coating a layer of polyimide on the glass carrier, and after curing into a film, a first flexible material (PI1) layer is formed; then depositing a barrier film on the first flexible layer to form a first barrier (Barrier1) layer covering the first flexible material layer; then depositing an amorphous silicon film on the first barrier layer to form an amorphous silicon (a-si) layer covering the first barrier layer; then coating a layer of polyimide on the amorphous silicon layer, and after curing into a film, a second flexible material (PI2) layer is formed; then depositing a barrier film on the second flexible layer to form a second barrier (Barrier2) layer covering the second flexible layer, and the preparation of the substrate is completed.

[0245] (102) A first conductive layer pattern is formed. In an example embodiment, forming the first conductive layer pattern can include: depositing a first conductive film on the substrate, and patterning the first conductive film by a patterning process to form a first conductive layer pattern on the substrate, as shown in FIG. 7, which is a schematic diagram of the planar structure of three sub-pixels after the formation of the first conductive layer, and the first conductive layer can be referred to as a first gate metal (GATE1) layer.

[0246] In an example embodiment, the first conductive layer pattern can include at least: a first plate C11 of a first capacitor C1, and a first plate C21 of a second capacitor C2; in the same sub-pixel, the first plate C11 of the first capacitor C1 and the first plate C21 of the second capacitor C2 are connected to each other, for example, the first plate C11 of the first capacitor C1 and the first plate C21 of the second capacitor C2 are integrally formed, and the shapes of the first plate C11 of the first capacitor C1 and the first plate C21 of the second capacitor C2 can be rectangular.

[0247] In an example embodiment, in the same sub-pixel, in the second direction, the first plate C21 of the second capacitor C2 and the first plate C11 of the first capacitor C1 are arranged in sequence.

[0248] Taking the Mth row and Nth column sub-pixel as an example, in the second direction Y, the first plate C11 of the first capacitor C1 can be located on the side of the first plate C21 of the second capacitor C2 of the sub-pixel close to the (M-1)th row sub-pixel.

[0249] In an example embodiment, the first conductive layer of the Nth column sub-pixel and the first conductive layer of the (N+1)th column sub-pixel can be mirror-symmetrical relative to a first center line, the first conductive layer of the (N+1)th column sub-pixel and the first conductive layer of the (N+2)th column sub-pixel can be mirror-symmetrical relative to a second center line, and the first conductive layer of the (N+2)th column sub-pixel and the first conductive layer of the (N+3)th column sub-pixel can be mirror-symmetrical relative to a third center line. The first center line, the second center line and the third center line can be straight lines extending along the second direction Y between adjacent columns of sub-pixels, for example, the first center line can be a straight line extending along the second direction Y between the Nth column and the (N+1)th column of sub-pixels, the second center line can be a straight line extending along the second direction Y between the (N+1)th column and the (N+2)th column of sub-pixels, and the third center line can be a straight line extending along the second direction Y between the (N+2)th column and the (N+3)th column of sub-pixels.

[0250] (103) Forming a second conductive layer pattern. In an example embodiment, forming the second conductive layer pattern can include: sequentially depositing a first insulating film and a second conductive film on the substrate on which the aforementioned pattern is formed, patterning the second conductive film by a patterning process, forming a first insulating layer covering the first conductive layer, and a second conductive layer pattern disposed on the first insulating layer, as shown in FIGS. 8a and 8b, FIG. 8a is a planar structure diagram of three sub-pixels after the second conductive layer is formed, and FIG. 8b is a planar schematic diagram of the second conductive layer in FIG. 8a. In an example embodiment, the second conductive layer can be referred to as a second gate metal (GATE2) layer.

[0251] In an exemplary embodiment, the second conductive layer pattern comprises at least: the second plate C12 of the first capacitor C1, the second plate C22 of the second capacitor C2. In the second direction Y, the second plate C12 of the first capacitor C1 can be located on one side of the second plate C22 of the second capacitor C2 in the same sub-pixel, for example, the second plate C22 of the second capacitor C2 and the second plate C12 of the first capacitor C1 can be arranged in sequence along the second direction Y in the same sub-pixel. In an exemplary embodiment, the second plate C22 of the second capacitor C2 can shield the channel region of the third transistor T3, thereby improving the stability of the third transistor T3. In an exemplary embodiment, the second plate C22 of the second capacitor C2 can serve as the bottom gate T3gb of the third transistor T3.

[0252] In an exemplary embodiment, the second plate C12 of the first capacitor C1 and the second plate C22 of the second capacitor C2 can have a rectangular profile, and the orthographic projection of the second plate C12 of the first capacitor C1 and the second plate C22 of the second capacitor C2 on the substrate can overlap with the orthographic projection of the first plate C11 of the first capacitor C1 and the first plate C21 of the second capacitor C2 on the substrate, for example, the orthographic projection of the second plate C12 of the first capacitor C1 and the second plate C22 of the second capacitor C2 on the substrate can be located within the range of the orthographic projection of the first plate C11 of the first capacitor C1 and the first plate C21 of the second capacitor C2 on the substrate. In an exemplary embodiment, the first plate C11 of the first capacitor C1 and the second plate C12 of the first capacitor C1 form the first capacitor C1, and the first plate C21 of the second capacitor C2 and the second plate C22 of the second capacitor C2 form the second capacitor C2.

[0253] In an exemplary embodiment, an opening K11 can be provided on the second plate C22 of the second capacitor C2, and the opening K11 can be located at the middle or edge position of the second plate C22 of the second capacitor C2 (for example, the opening K11 can be located at the corner of the second plate C22 of the second capacitor C2). The profile of the opening K11 can be rectangular, and the opening K11 exposes the first insulating layer covering the first plate C21 of the second capacitor C2, and the orthographic projection of the first plate C21 of the second capacitor C2 on the substrate contains the orthographic projection of the opening K11 on the substrate. In an exemplary embodiment, the opening K11 is configured to accommodate the subsequently formed ninth via, and the ninth via is located within the opening K11 and exposes the first plate C21 of the second capacitor C2 (also the first plate C11 of the first capacitor C1), so that the second electrode of the second transistor T2 formed subsequently is connected to the first plate C21 of the second capacitor C2 (also the first plate C11 of the first capacitor C1).

[0254] In an example embodiment, the second conductive layer of the Nth column of sub-pixels and the second conductive layer of the N+1th column of sub-pixels can be mirror-symmetrical relative to the first center line, the second conductive layer of the N+1th column of sub-pixels and the second conductive layer of the N+2th column of sub-pixels can be mirror-symmetrical relative to the second center line, and the second conductive layer of the N+2th column of sub-pixels and the second conductive layer of the N+3th column of sub-pixels can be mirror-symmetrical relative to the third center line.

[0255] (104) Forming a semiconductor layer pattern. In an example embodiment, forming a semiconductor layer pattern can include: on a substrate on which the aforementioned pattern is formed, sequentially depositing a second insulating thin film and a semiconductor thin film, patterning the semiconductor thin film through a patterning process, forming a second insulating layer covering the substrate, and a semiconductor layer pattern disposed on the second insulating layer, as shown in FIGS. 9a and 9b, FIG. 9a is a plan view of three sub-pixels after forming a semiconductor layer, and FIG. 9b is a plan view of the semiconductor layer in FIG. 9a.

[0256] In an example embodiment, the semiconductor layer pattern in at least part of the sub-pixels at least includes: an active layer AT1 of the first transistor T1 to an active layer AT7 of the seventh transistor T7.

[0257] In an example embodiment, in the same sub-pixel, the active layer AT1 of the first transistor T1, the active layer AT2 of the second transistor T2, and the active layer AT4 of the fourth transistor T4 are connected to each other, and the active layer AT3 of the third transistor T3, the active layer AT5 of the fifth transistor T5, the active layer AT6 of the sixth transistor T6, and the active layer AT7 of the seventh transistor T7 are connected to each other, for example, the active layer AT1 of the first transistor T1, the active layer AT2 of the second transistor T2, and the active layer AT4 of the fourth transistor T4 can be an integrated structure connected to each other, and the active layer AT3 of the third transistor T3, the active layer AT5 of the fifth transistor T5, the active layer AT6 of the sixth transistor T6, and the active layer AT7 of the seventh transistor T7 can be an integrated structure connected to each other.

[0258] In the exemplary embodiments, in the same sub-pixel, in the first direction X, the active layer of the first transistor T1, the active layer AT2 of the second transistor T2, and the active layer AT4 of the fourth transistor T4 are located on the same side of the active layer AT3 of the third transistor T3, the active layer AT5 of the fifth transistor T5, and the active layer AT6 of the sixth transistor T6; in the second direction Y, the active layer AT4 of the fourth transistor T4 and the active layer AT2 of the second transistor T2 are located on the two sides of the active layer AT1 of the first transistor T1, the active layer AT5 of the fifth transistor T5 and the active layer AT6 of the sixth transistor T6 are located on the two sides of the active layer AT3 of the third transistor T3, and the active layer AT7 of the seventh transistor T7 is located on the side of the active layer AT6 of the sixth transistor T6 away from the active layer AT3 of the third transistor T3.

[0259] In the exemplary embodiments, taking the sub-pixel in the Mth row and the Nth column as an example, in the first direction X, the active layer AT1 of the first transistor T1, the active layer AT2 of the second transistor T2, and the active layer AT4 of the fourth transistor T4 are located on the side of the active layer AT3 of the third transistor T3, the active layer AT5 of the fifth transistor T5, and the active layer AT6 of the sixth transistor T6 away from the sub-pixel in the N+1th column; in the second direction Y, the active layer AT4 of the fourth transistor T4 is located on the side of the active layer AT1 of the first transistor T1 away from the sub-pixel in the M+1th row, the active layer AT2 of the second transistor T2 is located on the side of the active layer AT1 of the first transistor T1 away from the sub-pixel in the M-1th row, the active layer AT7 of the seventh transistor T7 is located on the side of the active layer AT6 of the sixth transistor T6 close to the sub-pixel in the M+1th row, the active layer AT5 of the fifth transistor T5 is located on the side of the active layer AT3 of the third transistor T3 away from the sub-pixel in the M+1th row, and the active layer AT6 of the sixth transistor T6 is located on the side of the active layer AT3 of the third transistor T3 away from the sub-pixel in the M-1th row.

[0260] In the exemplary embodiments, the shapes of the active layer AT1 of the first transistor T1, the active layer AT2 of the second transistor T2, the active layer AT3 of the third transistor T3, the active layer AT4 of the fourth transistor T4, and the active layer AT5 of the fifth transistor T5 can be in the shape of an “I” character, the shape of the active layer AT6 of the sixth transistor T6 can be in the shape of an “I” character or a “mountain” character, and the shape of the active layer 27 of the seventh transistor T7 can be in the shape of an “L” character.

[0261] In the example embodiment, the active layer of at least part of the transistors can include a first region, a second region, and a channel region between the first region and the second region. In the example embodiment, the first region AT11 of the active layer AT1 of the first transistor T1 can serve as the first region AT21 of the active layer AT2 of the second transistor T2, the second region AT12 of the active layer AT1 of the first transistor T1 can serve as the second region AT42 of the active layer AT4 of the fourth transistor T4, the first region AT31 of the active layer AT3 of the third transistor T3 can serve as the second region AT52 of the active layer AT5 of the fifth transistor T5, the second region AT32 of the active layer AT3 of the third transistor T3 can serve as the first region AT61 of the active layer AT6 of the sixth transistor T6, the second region AT62 of the active layer AT6 of the sixth transistor T6 can serve as the second region AT72 of the active layer AT7 of the seventh transistor T7, and the first region AT41 of the active layer AT4 of the fourth transistor T4, the first region AT51 of the active layer AT5 of the fifth transistor T5, and the first region AT71 of the active layer AT7 of the seventh transistor T7 can be separately provided.

[0262] In the example embodiment, as shown in FIG. 9b, the first region AT51 of the active layer AT5 of the fifth transistor T5 in the Nth column is connected to the first region AT51 of the active layer AT5 of the fifth transistor T5 in the N+1th column, the first region AT21 of the active layer AT2 of the second transistor T2 in the N+1th column (also the first region AT11 of the active layer AT1 of the first transistor T1) is connected to the first region AT21 of the active layer AT2 of the second transistor T2 in the N+2th column (also the first region AT11 of the active layer AT1 of the first transistor T1), and the first region AT71 of the active layer AT7 of the seventh transistor T7 in the N+1th column is connected to the first region AT71 of the active layer AT7 of the seventh transistor T7 in the N+2th column. In the example embodiment, since the first region of the active layer of the fifth transistor T5 in the sub-pixel is connected to the first power supply line formed subsequently, by forming the first regions of the active layers of the fifth transistors T5 of adjacent sub-pixels into an integrated structure connected to each other, the first electrode of the fifth transistor T5 of the adjacent sub-pixels can have substantially the same potential, which is conducive to improving the uniformity of the panel display, avoiding display defects of the display substrate, and ensuring the display effect of the display substrate. In the example embodiment, since the first region of the active layer of the first transistor T1 and the first region of the second transistor T2 in the sub-pixel are connected to the first initial signal line formed subsequently, by forming the first regions AT21 of the active layers AT2 of the second transistors T2 of adjacent sub-pixels (also the first regions AT11 of the active layers AT1 of the first transistors T1) into an integrated structure connected to each other, the first electrode of the second transistor T2 of the adjacent sub-pixels (also the first electrode of the first transistor T1) can have substantially the same potential, which is conducive to improving the uniformity of the panel display, avoiding display defects of the display substrate, and ensuring the display effect of the display substrate. In the example embodiment, since the first region of the active layer of the seventh transistor T7 in the sub-pixel is connected to the second initial signal line formed subsequently, by forming the first regions AT71 of the active layers AT7 of the seventh transistors T7 of adjacent sub-pixels into an integrated structure connected to each other, the first electrode of the seventh transistor T7 of the adjacent sub-pixels can have substantially the same potential, which is conducive to improving the uniformity of the panel display, avoiding display defects of the display substrate, and ensuring the display effect of the display substrate.

[0263] In the example embodiment, the semiconductor layer in the Nth column and the semiconductor layer in the N+1th column can be mirror-symmetrical relative to the first center line, the semiconductor layer in the N+1th column and the semiconductor layer in the N+2th column can be mirror-symmetrical relative to the second center line, and the semiconductor layer in the N+2th column and the semiconductor layer in the N+3th column can be mirror-symmetrical relative to the third center line.

[0264] In an example embodiment, the conductor layer can employ an oxide, i.e., the first transistor T1 to the seventh transistor T7 are oxide thin film transistors. In an example embodiment, the oxide can be any one or more of the following: indium gallium zinc oxide (InGaZnO), indium gallium zinc nitride oxide (InGaZnON), zinc oxide (ZnO), zinc nitride oxide (ZnON), zinc tin oxide (ZnSnO), cadmium tin oxide (CdSnO), gallium tin oxide (GaSnO), titanium tin oxide (TiSnO), copper aluminum oxide (CuAlO), strontium copper oxide (SrCuO), lanthanum copper sulfur oxide (LaCuOS), gallium nitride (GaN), indium gallium nitride (InGaN), aluminum gallium nitride (AlGaN), and indium gallium aluminum nitride (InGaAlN). In some possible implementations, the semiconductor thin film can employ indium gallium zinc oxide (IGZO), which has a higher electron mobility than amorphous silicon. Since the leakage current of the IGZO TFT is relatively small, the use of N-type transistors can avoid leakage of the first node N1 during the light emitting stage.

[0265] (105) Forming a third conductive layer pattern. In an example embodiment, forming the third conductive layer pattern can include: on the substrate on which the aforementioned patterns are formed, sequentially depositing a third insulating thin film and a third conductive thin film, patterning the third conductive thin film using a patterning process, forming a third insulating layer covering the semiconductor layer, and a third conductive layer pattern disposed on the third insulating layer, as shown in FIGS. 10a to 10b, FIG. 10a is a plan view of the three sub-pixels after the third conductive layer is formed, and FIG. 10b is a plan view of the third conductive layer in FIG. 10a. In an example embodiment, the third conductive layer can be referred to as a third gate metal (GATE3) layer.

[0266] In an example embodiment, the third conductive layer pattern at least includes: a first emission control line EM1, a second emission control line EM2, a top gate T1gt of the first transistor T1 to a top gate T4gt of the fourth transistor T4, and a top gate T7gt of the seventh transistor T7. The first emission control line EM1 and the second emission control line EM2 can be polyline-shaped or strip-shaped extending along the first direction X, in the same sub-pixel row, the second emission control line EM2 and the first emission control line EM1 can be arranged at intervals along the second direction Y, in the second direction Y, in the same sub-pixel, the top gate T1gt of the first transistor T1 to the top gate T4gt of the fourth transistor T4 are located between the first emission control line EM1 and the second emission control line EM2, and the top gate T7gt of the seventh transistor T7 is located on the side of the second emission control line EM2 away from the first emission control line EM1.

[0267] In the exemplary embodiments, the region where the first light-emitting control line EM1 overlaps with the active layer AT5 of the fifth transistor T5 can serve as a top gate of the fifth transistor T5, and the region where the second light-emitting control line EM2 overlaps with the active layer AT6 of the sixth transistor T6 can serve as a top gate of the sixth transistor T6.

[0268] In the exemplary embodiments, the orthographic projection of the top gate T1gt of the first transistor T1 on the substrate at least partially overlaps with the orthographic projection of the active layer AT1 of the first transistor T1 on the substrate; the orthographic projection of the top gate T2gt of the second transistor T2 on the substrate at least partially overlaps with the orthographic projection of the active layer AT2 of the second transistor T2 on the substrate; the orthographic projection of the top gate T3gt of the third transistor T3 on the substrate at least partially overlaps with the orthographic projection of the active layer AT3 of the third transistor T3 on the substrate; the orthographic projection of the top gate T4gt of the fourth transistor T4 on the substrate at least partially overlaps with the orthographic projection of the active layer AT4 of the fourth transistor T4 on the substrate; and the orthographic projection of the top gate T7gt of the seventh transistor T7 on the substrate at least partially overlaps with the orthographic projection of the active layer AT7 of the seventh transistor T7 on the substrate.

[0269] In the exemplary embodiments, the top gate T1gt of the first transistor T1, the top gate T2gt of the second transistor T2, the top gate T4gt of the fourth transistor T4, and the top gate T7gt of the seventh transistor T7 are substantially rectangular structures, and the top gate T3gt of the third transistor T3 is substantially an “L”-shaped structure. In the same sub-pixel, in the second direction Y, the top gate T1gt of the first transistor T1, the top gate T2gt of the second transistor T2, the top gate T3gt of the third transistor T3, and the top gate T4gt of the fourth transistor T4 are located between the first light-emitting control line EM1 and the second light-emitting control line EM2, the top gate T7gt of the seventh transistor T7 is located on the side of the second light-emitting control line EM2 away from the first light-emitting control line EM1, and the top gate T1gt of the first transistor T1 is located between the top gate T2gt of the second transistor T2 and the top gate T4gt of the fourth transistor T4; in the first direction X, in the same sub-pixel, the top gate T1gt of the first transistor T1, the top gate T2gt of the second transistor T2, and the top gate T4gt of the fourth transistor T4 are located on the same side of the top gate T3gt of the third transistor T3.

[0270] In the example embodiment, in the same row of sub-pixels, the top gate T1gt of the first transistor T1 of the N+1th column of sub-pixels and the top gate T1gt of the first transistor T1 of the N+2th column of sub-pixels are connected to each other, for example, the top gate T1gt of the first transistor T1 of the N+1th column of sub-pixels and the top gate T1gt of the first transistor T1 of the N+2th column of sub-pixels can be an integrated structure connected to each other. In the example embodiment, since the top gate T1gt of the first transistor T1 in the sub-pixel is connected to the first reset control line Reset1 formed subsequently, by forming the top gates T1gt of the first transistors T1 of adjacent sub-pixels into an integrated structure connected to each other, it can be ensured that the top gates T1gt of the first transistors T1 of adjacent sub-pixels have substantially the same potential, which is conducive to improving the uniformity of panel display, avoiding display defects of the display substrate, and ensuring the display effect of the display substrate

[0271] In the example embodiment, the top gate T3gt of the third transistor T3 can include a first part T3gt1 and a second part T3gt2, the first part T3gt1 is in the shape of a rectangle, and the second part T3gt2 is in the shape of a strip or a broken line extending in the column direction Y; in the same third transistor T3, the first part T3gt1 is connected to the second part T3gt2, in the column direction Y, the second part T3gt2 is located on the side of the first part T3gt1 away from the fifth transistor T5, the orthogonal projection of the first part T3gt1 on the base at least partially overlaps the orthogonal projection of the first capacitor C1 on the base, and the orthogonal projection of the second part T3gt2 on the base at least partially overlaps the orthogonal projection of the first capacitor C1 and the second capacitor C2 on the base.

[0272] In the example embodiment, the third conductive layer of the Nth column and the third conductive layer of the N+1th column can be mirror symmetrical with respect to the first center line, the third conductive layer of the N+1th column and the third conductive layer of the N+2th column can be mirror symmetrical with respect to the second center line, and the third conductive layer of the N+2th column and the third conductive layer of the N+3th column can be mirror symmetrical with respect to the third center line.

[0273] In the example embodiment, after forming the third conductive layer pattern, the third conductive layer can be used as a shield to conduct the semiconductor layer, the semiconductor layer in the area shielded by the third conductive layer forms the channel region of the first transistor T1 to the seventh transistor T7, and the semiconductor layer in the area not shielded by the third conductive layer is conductive, that is, the first region and the second region of the active layer AT1 of the first transistor T1 to the active layer AT7 of the seventh transistor T7 are conductive.

[0274] (106) A fourth insulating layer pattern is formed. In an exemplary embodiment, forming the fourth insulating layer pattern can include: on the substrate on which the aforementioned patterns are formed, depositing a fourth insulating thin film, patterning the fourth insulating thin film using a patterning process, forming a fourth insulating layer covering the third conductive layer, the fourth insulating layer being provided with a plurality of vias, as shown in FIG. 11, which is a planar structure diagram of the three sub-pixels after the fourth insulating layer is formed.

[0275] In an exemplary embodiment, the plurality of vias in at least some of the sub-pixels at least include: a first via V1, a second via V2, a third via V3, a fourth via V4, a fifth via V5, a sixth via V6, a seventh via V7, an eighth via V8, a ninth via V9, a tenth via V10, an eleventh via V11, a twelfth via V12, a thirteenth via V13, a fourteenth via V14, a fifteenth via V15, a sixteenth via V16, and a seventeenth via V17.

[0276] In an exemplary embodiment, the first via V1 is located within the range of the normal projection of the active layer AT1 of the first transistor T1 on the substrate, and the fourth insulating layer and the third insulating layer in the first via V1 are etched away, exposing the surface of the first region AT11 of the active layer AT1 of the first transistor T1 (also the first region AT21 of the active layer AT2 of the second transistor T2). The first via V1 is configured to allow the first electrode of the subsequently formed first transistor T1 to connect with the active layer AT1 of the first transistor T1 through the via, and allow the first electrode of the subsequently formed second transistor T2 to connect with the active layer AT2 of the second transistor T2 through the via.

[0277] In an exemplary embodiment, the second via V2 is located within the range of the normal projection of the active layer AT1 of the first transistor T1 on the substrate, and the fourth insulating layer, the third insulating layer and the second region AT12 of the active layer AT1 of the first transistor T1 (also the second region AT42 of the active layer AT4 of the fourth transistor T4) in the second via V2 are etched away. The second via V2 is configured to allow the second electrode of the subsequently formed first transistor T1 to connect with the active layer AT1 of the first transistor T1 through the via, and allow the second electrode of the subsequently formed fourth transistor T4 to connect with the active layer AT4 of the fourth transistor T4 through the via.

[0278] In an example embodiment, the third via V3 is configured such that a second electrode of the second transistor T2 is connected to the active layer AT2 of the second transistor T2 through the via V3.

[0279] In an example embodiment, the fourth via V4 is configured such that a second electrode of the third transistor T3 is connected to the active layer AT3 of the third transistor T3 through the via V4, and a first electrode of the sixth transistor T6 is connected to the active layer AT6 of the sixth transistor T6 through the via V4.

[0280] In an example embodiment, the fifth via V5 is configured such that a first electrode of the fourth transistor T4 is connected to the active layer AT4 of the fourth transistor T4 through the via V5.

[0281] In an example embodiment, the sixth via V6 is configured such that a first electrode of the fifth transistor T5 is connected to the active layer AT5 of the fifth transistor T5 through the via V6.

[0282] In the example embodiment, the seventh via V7 is located within the range of the active layer AT6 of the sixth transistor T6 on the substrate, the fourth insulating layer, the third insulating layer within the seventh via V7 are etched away, exposing the surface of the second region AT62 of the active layer AT6 of the sixth transistor T6 (also the first region AT71 of the active layer AT7 of the seventh transistor T7). The seventh via V7 is configured to connect the second electrode of the subsequently formed sixth transistor T6 to the active layer AT6 of the sixth transistor T6 through the via, and to connect the second electrode of the subsequently formed seventh transistor T7 to the active layer AT7 of the seventh transistor T7 through the via.

[0283] In the example embodiment, the eighth via V8 is located within the range of the active layer AT7 of the seventh transistor T7 on the substrate, the fourth insulating layer, the third insulating layer within the eighth via V8 are etched away, exposing the surface of the first region AT71 of the active layer AT7 of the seventh transistor T7. The eighth via V8 is configured to connect the first electrode of the subsequently formed seventh transistor T7 to the active layer AT7 of the seventh transistor T7 through the via, and to connect the subsequently formed second initial signal line Vinit2 to the active layer AT7 of the seventh transistor T7 through the via.

[0284] In the example embodiment, the ninth via V9 is located within the range of the first plate C21 of the second capacitor C2 on the substrate (the ninth via V9 can be located within the range of the opening K11 on the substrate), the fourth insulating layer, the third insulating layer, the second insulating layer, the first insulating layer within the ninth via V9 are etched away, exposing the surface of the first plate C21 of the second capacitor C2 (also the first plate C11 of the first capacitor C1). The ninth via V9 is configured to connect the second electrode of the subsequently formed second transistor T2 to the first plate C21 of the second capacitor C2 (also the first plate C11 of the first capacitor C1) through the via.

[0285] In the example embodiment, the tenth via V10 is located within the range of the second plate C12 of the first capacitor C1 on the substrate, the fourth insulating layer, the third insulating layer and the second insulating layer within the tenth via V10 are etched away, exposing the surface of the second plate C12 of the first capacitor C1. The tenth via V10 is configured to connect the second electrode of the subsequently formed third transistor T3 (also the first electrode of the sixth transistor T6) to the second plate C12 of the first capacitor C1 through the via.

[0286] In an example embodiment, the eleventh via V11 is configured such that a fourth connection electrode formed subsequently is connected to the second plate C22 of the second capacitor C2 through the via.

[0287] In an example embodiment, the twelfth via V12 is configured such that a first reset control line Resetl formed subsequently is connected to the top gate T1gt of the first transistor T1 through the via.

[0288] In an example embodiment, the thirteenth via V13 is configured such that a second reset control line Reset2 formed subsequently is connected to the top gate T2gt of the second transistor T2 through the via.

[0289] In an example embodiment, the fourteenth via V14 is configured such that a second electrode of the first transistor T1 (also a second electrode of the fourth transistor T4) formed subsequently is connected to the top gate T3gt of the third transistor T3 through the via.

[0290] In an example embodiment, the fifteenth via V15 is configured such that a fourth connection electrode formed subsequently is connected to the top gate T3gt of the third transistor T3 through the via.

[0291] In the exemplary embodiment, the fourth transistor T4 has a top gate T4gt. The fourth transistor T4 has a first source-drain electrode T4s1, a second source-drain electrode T4s2, and a third source-drain electrode T4s3. The first source-drain electrode T4s1 is connected to the first connection electrode L1. The second source-drain electrode T4s2 is connected to the second connection electrode L2. The third source-drain electrode T4s3 is connected to the third connection electrode L3. The fourth transistor T4 has a first gate electrode T4g1 and a second gate electrode T4g2. The first gate electrode T4g1 is connected to the first initial signal line Vinit1. The second gate electrode T4g2 is connected to the second initial signal line Vinit2-1.

[0292] In the exemplary embodiment, the seventh transistor T7 has a top gate T7gt. The seventh transistor T7 has a first source-drain electrode T7s1, a second source-drain electrode T7s2, and a third source-drain electrode T7s3. The first source-drain electrode T7s1 is connected to the fourth connection electrode L4. The second source-drain electrode T7s2 is connected to the fifth connection electrode L5. The third source-drain electrode T7s3 is connected to the sixth connection electrode L6. The seventh transistor T7 has a first gate electrode T7g1 and a second gate electrode T7g2. The first gate electrode T7g1 is connected to the third reset control line Reset3. The second gate electrode T7g2 is connected to the fourth initial signal line Vinit2-2.

[0293] (107) Forming a fourth conductive layer pattern. In the exemplary embodiment, forming the fourth conductive layer can include: on the substrate on which the aforementioned patterns are formed, depositing a fourth conductive thin film, and patterning the fourth conductive thin film by using a patterning process to form a fourth conductive layer disposed on the fourth insulating layer, as shown in FIGS. 12a and 12b. FIG. 12a is a planar structural diagram of three sub-pixels after the fourth conductive layer is formed, and FIG. 12b is a planar schematic diagram of the fourth conductive layer in FIG. 12a. In the exemplary embodiment, the fourth conductive layer can be referred to as a first source-drain metal (SD1) layer.

[0294] In the exemplary embodiment, the fourth conductive layer at least includes: a first power connection line VDDL, a second power connection line VSSL, a scan signal line Gate, a first reset control line Reset1, a first initial signal line Vinit1, a second reset control line Reset2, a first second initial signal line Vinit2-1, a third reset control line Reset3, a first connection electrode L1, a second connection electrode L2, a third connection electrode L3, a fourth connection electrode L4, a fifth connection electrode L5, and a sixth connection electrode L6.

[0295] In the example embodiment, the main body of the first power connection line VDDL, the second power connection line VSSL, the scan signal line Gate, the first reset control line Reset1, the first initial signal line Vinit1, the second reset control line Reset2, the first second initial signal line Vinit2-1, and the third reset control line Reset3 can be in a strip shape or a zigzag shape extending along the first direction X, and the first power connection line VDDL, the second power connection line VSSL, the scan signal line Gate, the first reset control line Reset1, the first initial signal line Vinit1, the second reset control line Reset2, the first second initial signal line Vinit2-1, and the third reset control line Reset3 can be arranged in sequence along the opposite direction of the second direction Y.

[0296] In the example embodiment, in the same sub-pixel, along the second direction Y, the first connection electrode L1 is located between the first power connection line VDDL and the second power connection line VSSL, the second connection electrode L2 and the third connection electrode L3 are located between the scan signal line Gate and the first reset control line Reset1, the third connection electrode L3 and the second connection electrode L2 are arranged in sequence along the second direction Y, the fourth connection electrode L4 is located between the first reset control line Reset1 and the first initial signal line Vinit1, the fifth connection electrode L5 is located between the first initial signal line Vinit1 and the main body of the second reset control line Reset2, and the sixth connection electrode L6 is located between the second reset control line Reset2 and the second initial signal line Vinit2.

[0297] In the example embodiment, the first power connection line VDDL can be connected to the first area AT51 of the active layer AT5 of the fifth transistor T5 in the row of sub-pixels through the sixth via V6 in the row of sub-pixels. In the example embodiment, the first power connection line VDDL can be used as the first electrode of the fifth transistor T5, and is configured to provide the first power voltage to the plurality of fifth transistors T5 in the sub-pixel.

[0298] In the example embodiment, the scan signal line Gate can be connected to the top gate T4gt of the fourth transistor T4 in the row of sub-pixels through the sixteenth via V16 in the row of sub-pixels, and is configured to provide the scan signal to the plurality of fourth transistors T4 in the row of sub-pixels.

[0299] In the example embodiment, the second power connection line VSSL can be connected with a plurality of second power lines formed subsequently, at least part of the second power connection line VSSL is electrically connected with the plurality of second power lines, at least part of the second power lines is electrically connected with the plurality of second power connection lines VSSL located in the plurality of rows of pixel driving circuits, at least part of the second power connection line VSSL and at least part of the second power lines are connected to form a grid structure, which can reduce the voltage drop of the second power lines and improve the display uniformity of the display substrate.

[0300] In the example embodiment, the first reset control line Reset1 can be connected with the top gate T1gt of the first transistor T1 in the row of sub-pixels through the twelfth via V12 in the row of sub-pixels, and is configured to provide the first reset control signal to the plurality of first transistors T1 in the row of sub-pixels.

[0301] In the example embodiment, the first initial signal line Vinit1 can be connected with the first region AT11 of the active layer AT1 of the first transistor T1 (also the first region AT21 of the active layer AT2 of the second transistor T2) in the row of sub-pixels through the first via V1 in the row of sub-pixels, and is configured to provide the first initial signal to the first transistor T1 and the second transistor T2 in the row of sub-pixels. In the example embodiment, the first initial signal line Vinit1 can serve as the first electrode of the first transistor T1 and as the first electrode of the second transistor T2.

[0302] In the example embodiment, the second reset control line Reset2 can be connected with the top gate T2gt of the second transistor T2 in the row of sub-pixels through the thirteenth via V13 in the row of sub-pixels, and is configured to provide the second reset control signal to the plurality of second transistors T2 in the row of sub-pixels.

[0303] In the example embodiment, the second initial signal line Vinit2 can be connected with the first region AT71 of the active layer AT7 of the seventh transistor T7 located in the row of sub-pixels through the eighth via V8 in the row of sub-pixels, and is configured to provide the second initial signal to the seventh transistor T7 in the row of sub-pixels. In the example embodiment, the second initial signal line Vinit2 can serve as the first electrode of the seventh transistor T7.

[0304] In the example embodiment, the third reset control line Reset3 can be connected with the top gate T7gt of the seventh transistor T7 in the row of sub-pixels through the seventeenth via V17 in the row of sub-pixels, and is configured to provide the third reset control signal to the plurality of seventh transistors T7 in the row of sub-pixels.

[0305] In the example embodiment, the first connection electrode L1 is connected with the first region AT41 of the active layer AT4 of the fourth transistor T4 through the fifth via V5. In the example embodiment, the first connection electrode L1 can be configured as the first electrode of the fourth transistor T4 and connected with the subsequently formed data signal line.

[0306] In the example embodiment, the main body portion of the second connection electrode L2 extends along the first direction X, one end is connected with the second region AT12 of the active layer AT1 of the first transistor T1 (also the second region AT42 of the active layer AT4 of the fourth transistor T4) through the second via V2, and the other end is connected with the top gate T3gt of the third transistor T3 through the fourteenth via V14. The second region AT12 of the active layer AT1 of the first transistor T1 (also the second region AT42 of the active layer AT4 of the fourth transistor T4) is electrically connected with the top gate T3gt of the third transistor T3 through the second connection electrode L2, so that the second electrode of the first transistor T1, the second electrode of the fourth transistor T4, and the top gate T4gt of the third transistor T3 have the same potential. In the example embodiment, the second connection electrode L2 can be configured as the second electrode of the first transistor T1 and the second electrode of the fourth transistor T4.

[0307] In the example embodiment, the main body portion of the third connection electrode L3 extends along the first direction X, one end is connected with the second region AT32 of the active layer AT3 of the third transistor T3 (also the first region AT61 of the active layer AT6 of the sixth transistor T6) through the fourth via V4, and the other end is connected with the second plate C12 of the first capacitor C1 through the tenth via V10. The second region AT32 of the active layer AT3 of the third transistor T3 (also the first region AT61 of the active layer AT6 of the sixth transistor T6) is electrically connected with the second plate C12 of the first capacitor C1 through the third connection electrode L3. In the example embodiment, the third connection electrode L3 can be configured as the second electrode of the third transistor T3 and the first electrode of the sixth transistor T6.

[0308] In the example embodiment, the main body portion of the fourth connection electrode L4 (which can be configured as the above-mentioned switching connection electrode L4) extends along the first direction X, one end is connected with the second plate C22 of the second capacitor C2 through the eleventh via V11, and the other end is connected with the top gate T3gt of the third transistor T3 through the fifteenth via V15. The second plate C22 of the second capacitor C2 is electrically connected with the top gate T3gt of the third transistor T3 through the third connection electrode L3, so that the third connection electrode L3 and the second plate C22 of the second capacitor C2 have the same potential.

[0309] In the example embodiment, the fifth connection electrode L5 extends along the first direction X, one end of which is connected to the second region AT22 of the active layer AT2 of the second transistor T2 through the third via V3, and the other end of which is connected to the first plate C21 of the second capacitor C2 (also the first plate C11 of the first capacitor C1) through the ninth via V9. The second region AT22 of the active layer AT2 of the second transistor T2 and the first plate C21 of the second capacitor C2 (also the first plate C11 of the first capacitor C1) are connected through the fifth connection electrode L5. In the example embodiment, the fifth connection electrode L5 can serve as the second electrode of the second transistor T2.

[0310] In the example embodiment, the sixth connection electrode L6 is connected to the second region AT62 of the active layer AT6 of the sixth transistor T6 (also the second region AT72 of the active layer AT7 of the seventh transistor T7) through the seventh via V7. In the example embodiment, the sixth connection electrode L6 can serve as the second electrode of the sixth transistor T6 and the second electrode of the seventh transistor T7, and is configured to be connected to the anode connection electrode of the light-emitting element formed subsequently.

[0311] (108) The fifth insulating layer and the first planar layer pattern are formed. In the example embodiment, forming the fifth insulating layer and the first planar layer pattern can include: on the substrate on which the aforementioned patterns are formed, first depositing a fifth insulating thin film, then coating a first planar thin film, and patterning the first planar thin film and the fifth insulating thin film by using a patterning process to form the fifth insulating layer covering the fourth conductive layer pattern and the first planar layer disposed on the fifth insulating layer, the fifth insulating layer and the first planar layer being provided with a plurality of vias. As shown in FIG. 13, which is a planar structure diagram of the three sub-pixels after the first planar layer is formed.

[0312] In the example embodiment, the plurality of vias in each sub-pixel can at least include: a nineteenth via V19, a twentieth via V20, a twenty-first via V21, a twenty-second via V22, a twenty-third via V23, and a twenty-fourth via V24.

[0313] In the example embodiment, the orthographic projection of the nineteenth via V19 on the substrate is within the range of the orthographic projection of the first initial signal line Vinit1 on the substrate. The first planar layer and the fifth insulating layer in the nineteenth via V19 are etched away, exposing the surface of the first initial signal line Vinit1. The nineteenth via V19 is configured to allow the first initial signal connection line formed subsequently to be connected to the first initial signal line Vinit1 through the via.

[0314] In an exemplary embodiment, the second twenty via V20 has a projection on the substrate within the projection of the sixth connection electrode L6 on the substrate, the first planar layer and the fifth insulating layer in the second twenty via V20 are etched away, exposing the surface of the sixth connection electrode L6. The second twenty via V20 is configured to allow the anode connection electrode of the light emitting element formed subsequently to be electrically connected to the sixth connection electrode L6 through the via.

[0315] In an exemplary embodiment, the twenty first via V21 has a projection on the substrate within the projection of the first power supply connection line VDDL on the substrate, the first planar layer and the fifth insulating layer in the twenty first via V21 are etched away, exposing the surface of the first power supply connection line VDDL. The twenty first via V21 is configured to allow the first power supply line formed subsequently to be connected to the first power supply connection line VDDL through the via.

[0316] In an exemplary embodiment, the twenty second via V22 has a projection on the substrate within the projection of the first connection electrode L1 on the substrate, the first planar layer and the fifth insulating layer in the twenty second via V22 are etched away, exposing the surface of the first connection electrode L1. The twenty second via V22 is configured to allow the data signal line formed subsequently to be electrically connected to the first connection electrode L1 through the via.

[0317] In an exemplary embodiment, the twenty third via V23 has a projection on the substrate within the projection of the second initial signal line Vinit2 on the substrate, the first planar layer and the fifth insulating layer in the twenty third via V23 are etched away, exposing the surface of the second initial signal line Vinit2. The twenty third via V23 is configured to allow the second initial signal connection line Vinit2L formed subsequently to be electrically connected to the second initial signal line Vinit2 through the via.

[0318] In an exemplary embodiment, the twenty fourth via V24 has a projection on the substrate within the projection of the second power supply connection line VSSL on the substrate, the first planar layer and the fifth insulating layer in the twenty fourth via V24 are etched away, exposing the surface of the second power supply connection line VSSL. The twenty fourth via V24 is configured to allow the second power supply line formed subsequently to be connected to the second power supply connection line VSSL through the via.

[0319] (109) A fifth conductive layer pattern is formed. In an exemplary embodiment, forming the fifth conductive layer can include: on the substrate on which the aforementioned patterns are formed, depositing a fifth conductive thin film, patterning the fifth conductive thin film by using a patterning process, and forming the fifth conductive layer disposed on the first planar layer, as shown in FIGS. 14a and 14b, FIG. 14a is a plan view of three sub-pixels after the fifth conductive layer is formed, and FIG. 14b is a plan view of the fifth conductive layer in FIG. 14a. In an exemplary embodiment, the fifth conductive layer can be referred to as a second source-drain metal (SD2) layer.

[0320] In an exemplary embodiment, the fifth conductive layer at least includes: a data signal line D, a first power supply line VDD, a second power supply line VSS, a first initial signal connection line Vinit1L, an anode connection electrode ZL, and a second initial signal connection line Vinit2.

[0321] In an exemplary embodiment, the data signal line D is in a polyline shape with a main body portion extending along the second direction Y, and the data signal line D is connected to the first connection electrode L1 through the twenty-second via V22. Since the first connection electrode L1 is connected to the first area AT41 of the active layer AT4 of the fourth transistor T4 through the via, the connection of the data signal line D to the first electrode of the fourth transistor T4 is achieved, and the data signal is written into the fourth transistor T4.

[0322] In an exemplary embodiment, the first power supply line VDD is in a polyline shape with a main body portion extending along the second direction Y, and the first power supply line VDD is connected to the first power supply connection line VDDL through the twenty-first via V21. Since the first power supply connection line VDDL is connected to the first area AT51 of the active layer AT5 of the fifth transistor T5 through the via, the connection of the first power supply line VDD to the fifth transistor T5 is achieved, and the power supply signal is written into the first electrode of the fifth transistor T5. In an exemplary embodiment, at least part of the first power supply connection line VDDL is electrically connected to a plurality of first power supply lines VDD, at least part of the first power supply line VDD is electrically connected to a plurality of first power supply connection lines VDDL, and at least part of the first power supply line is connected to at least part of the first power supply connection line VDDL to form a grid-like structure, which can reduce the voltage drop of the first power supply line VDD, so that the first power supply signals received by a plurality of sub-pixels in the display substrate are substantially consistent, and the display uniformity of the display substrate is improved; for example, each first power supply connection line VDDL is electrically connected to a plurality of first power supply lines VDD in a plurality of pixel driving circuits, each first power supply line VDD is electrically connected to a plurality of first power supply connection lines VDDL, and a plurality of first power supply lines are connected to a plurality of first power supply connection lines VDDL to form a grid-like structure.

[0323] In the example embodiment, the shape of the anode connecting electrode ZL in the first sub-pixel is an "I" shape or an "L" shape, the shape of the anode connecting electrode ZL in the second and third sub-pixels is an "I" shape, and the anode connecting electrode ZL is connected with the sixth connecting electrode L6 through the twentieth via hole V20. Since the sixth connecting electrode L6 is connected with the second region AT62 of the active layer AT6 of the sixth transistor T6 (also the second region AT72 of the active layer AT7 of the seventh transistor T7) through the via hole, the connection of the anode connecting electrode ZL with the second electrode of the sixth transistor T6 and the second electrode of the seventh transistor T7 is realized.

[0324] In the example embodiment, the first initial signal connection line Vinit1L is a polyline shape with a main body extending along the second direction Y, the first initial signal connection line Vinit1L is connected with the first initial signal connection line Vinit1 through the nineteenth via hole V19, and the plurality of first initial signal connection lines Vinit1L and the plurality of first initial signal lines Vinit1 form a grid structure, so that the first initial signals received by the first and second transistors T1 and T2 in adjacent sub-pixels are basically consistent, which is beneficial to improve the uniformity of panel display, avoid display defects of the display substrate, and ensure the display effect of the display substrate.

[0325] In the example embodiment, the second initial signal connection line Vinit2L is a polyline shape with a main body extending along the second direction Y, the second initial signal connection line Vinit2L is connected with the second initial signal line Vinit2 through the twenty-third via hole V23, and the plurality of second initial signal connection lines Vinit2L and the plurality of second initial signal lines Vinit2 form a grid structure, so that the second initial signals received by the adjacent seventh transistors T7 are basically consistent, which is beneficial to improve the uniformity of panel display, avoid display defects of the display substrate, and ensure the display effect of the display substrate.

[0326] In an example embodiment, the second power supply lines VSS are in a shape of a broken line extending along the second direction, the second power supply lines VSS can be connected to the second power supply connection lines VSSL through the twenty-fourth via holes V24, at least part of the second power supply connection lines VSSL are electrically connected to the plurality of second power supply lines VSS, at least part of the second power supply lines VSS are electrically connected to the plurality of second power supply connection lines VSSL located in the plurality of pixel driving circuits, at least part of the second power supply connection lines VSSL and at least part of the second power supply lines VSS are connected to each other to form a grid structure, which can reduce the voltage drop of the second power supply lines VSS and improve the display uniformity of the display substrate; for example, each of the second power supply connection lines VSSL is electrically connected to the plurality of second power supply lines VSS, each of the second power supply lines VSS is electrically connected to the plurality of second power supply connection lines VSSL located in the plurality of pixel driving circuits, and the plurality of second power supply connection lines VSSL and the plurality of second power supply lines VSS are connected to each other to form a grid structure. In an example embodiment, the display substrate can include a display area and a frame area located at the periphery of the display area, the display area can be provided with a plurality of sub-pixels, and the frame area can be provided with a second power supply signal line, in the first direction X, the second power supply connection line VSSL can be electrically connected to the second power supply signal line located in the frame area on both sides of the display area; in the second direction Y, the second power supply line VSS can be electrically connected to the second power supply signal line located in the frame area on both sides of the display area. The second power supply line VSS can be electrically connected to the cathode formed subsequently in the display area, which can reduce the voltage drop of the cathode and improve the display effect.

[0327] In an example embodiment, in the same pixel unit, the first initial signal connection line Vinit1L, the second power supply line VSS, the two first power supply lines VDD, and the second initial signal connection line Vinit2L can be arranged in sequence along the first direction X, in the first direction X, the data signal line D of the first sub-pixel is located on the side of the first initial signal connection line Vinit1L away from the second power supply line VSS, the data signal line D of the second sub-pixel and the data signal line D of the third sub-pixel can be located between the two second power supply lines VDD, one of the two second power supply lines VDD is located in the second sub-pixel, and the other is located in the third sub-pixel; the anode connection electrode ZL in the first sub-pixel is located between the first initial signal connection line Vinit1L and the second power supply line VSS, the anode connection electrode ZL in the second sub-pixel is located between the first power supply line VDD and the second power supply line VSS, and the anode connection electrode ZL in the third sub-pixel is located between the second initial signal connection line Vinit2L and the first power supply line VDD.

[0328] In the example embodiment, the size of the second power supply line VSS and the second initial signal connection line Vinit2L along the first direction X is greater than the size of the other signal lines along the first direction X, which can reduce the impedance of the first power supply line VSS and the second initial signal connection line Vinit2L in the display area.

[0329] So far, the driving circuit layer is prepared on the substrate, and the driving circuit layer is provided with the pixel driving circuit of the plurality of sub-pixels. FIGS. 7 to 14b show the planar structure schematic diagram of the pixel driving circuit of the sub-pixel in the display substrate. In the example embodiment, in the direction perpendicular to the plane of the display substrate, the driving circuit layer can include the first conductive layer, the second conductive layer, the semiconductor layer, the third conductive layer, the fourth conductive layer, and the fifth conductive layer which are sequentially arranged on the substrate.

[0330] In the example embodiment, in the direction perpendicular to the plane of the display substrate, the driving circuit layer can include the first insulating layer, the second insulating layer, the third insulating layer, the fourth insulating layer, the fifth insulating layer, and the first planar layer. The first insulating layer is arranged between the first conductive layer and the second conductive layer. The second insulating layer is arranged between the second conductive layer and the semiconductor layer. The third insulating layer is arranged between the semiconductor layer and the third conductive layer. The fourth insulating layer is arranged between the third conductive layer and the fourth conductive layer. The fifth insulating layer and the first planar layer are arranged between the fourth conductive layer and the fifth conductive layer.

[0331] In the example embodiment, after the driving circuit layer is prepared, the light-emitting structure layer is prepared on the driving circuit layer. The preparation process of the light-emitting structure layer can include the following operations. The second planar layer pattern is formed, and the second planar layer is provided with at least an anode via hole. The anode pattern (i.e., the anode conductive layer) is formed, and the anode is connected to the anode connection electrode through the anode via hole. The anode pixel definition layer is formed, and the pixel definition layer is provided with a pixel opening which exposes the anode. The organic light-emitting layer is formed by using the evaporation or inkjet printing process. The cathode is formed on the organic light-emitting layer. The encapsulation layer is formed, and the encapsulation layer can include the first encapsulation layer, the second encapsulation layer, and the third encapsulation layer which are stacked. The first encapsulation layer and the third encapsulation layer can be made of inorganic material, and the second encapsulation layer can be made of organic material. The second encapsulation layer is arranged between the first encapsulation layer and the third encapsulation layer, which can prevent the external water vapor from entering the light-emitting structure layer. The step of forming the anode conductive layer is as follows:

[0332] (110) The second planar layer pattern is formed. In the example embodiment, forming the second planar layer pattern can include: on the substrate on which the aforementioned pattern is formed, coating a second planar film, and patterning the second planar film by using a patterning process to form a second planar layer covering the fifth conductive layer pattern, and the second planar layer is provided with a plurality of via holes. As shown in FIG. 15, FIG. 15 is a planar structure diagram of three sub-pixels after the second planar layer is formed.

[0333] In an example embodiment, the plurality of vias can include at least a twenty-sixth via V26.

[0334] In an example embodiment, the via of each sub-pixel includes at least the twenty-sixth via V26. The orthogonal projection of the twenty-sixth via V26 on the substrate is within the range of the orthogonal projection of the anode connecting electrode ZL on the substrate, the second planar layer within the twenty-sixth via V26 is removed to expose the surface of the anode connecting electrode ZL, and the twenty-sixth via V26 is configured to allow the subsequently formed anode to be electrically connected to the anode connecting electrode ZL through the via.

[0335] (111) Forming an anode conductive layer pattern. In an example embodiment, forming the anode conductive layer pattern can include: depositing an anode conductive thin film on the substrate on which the aforementioned pattern is formed, and patterning the anode conductive thin film using a patterning process to form the anode conductive layer pattern disposed on the second planar layer, as shown in FIGS. 16a and 16b, FIG. 16a is a schematic diagram of the planar structure of three sub-pixels after forming the anode conductive layer, and FIG. 16b is a planar schematic diagram of the anode conductive layer in FIG. 16a.

[0336] In an example embodiment, the anode conductive layer pattern can include at least a plurality of anodes AN, and the plurality of anodes AN can include: a first anode AN1, a second anode AN2, and a third anode AN3. The area where the first anode AN1 is located can form a red light emitting unit that emits red light, the area where the second anode AN2 is located can form a green light emitting unit that emits green light, and the area where the third anode AN3 is located can form a blue light emitting unit that emits blue light.

[0337] In an example embodiment, the first anode AN1, the second anode AN2, and the third anode AN3 can be connected to the anode connecting electrode ZL in the corresponding sub-pixel through the twenty-sixth via V26, respectively. Since the anode connecting electrode ZL in the sub-pixel is electrically connected to the second electrode of the sixth transistor T6 (also the second electrode of the seventh transistor T7) through the via, the first anode AN1, the second anode AN2, and the third anode AN3 can be connected to the second electrode of the sixth transistor T6 and the second electrode of the seventh transistor T7 through the anode connecting electrode ZL, respectively, thereby realizing the driving of the light emitting device by the pixel driving circuit.

[0338] In the example embodiment, the anode AN can include an anode main body AN01 and an anode connecting portion AN02. The anode main body AN01 can be in a rectangular structure. The anode connecting portion AN02 is connected to the anode main body AN01 at one end and is electrically connected to the anode connecting electrode ZL through the twenty-sixth via hole V26 at the other end. The anode connecting portion AN02 can be in a strip structure or a block structure extending in the first direction X or the second direction Y. The anode connecting portion AN02 can be configured to compensate for the difference in parasitic capacitance between the plurality of sub-pixels due to the signal traces. By providing the anode connecting portion AN02, the parasitic capacitances of the plurality of sub-pixels can be substantially consistent, thereby improving the display uniformity of the display substrate.

[0339] (112) Forming a pixel definition layer pattern. In the example embodiment, forming the pixel definition layer pattern can include: depositing a pixel definition layer film on the substrate on which the aforementioned pattern is formed, and patterning the pixel definition layer using a patterning process to form a pixel definition layer pattern disposed on the anode conductive layer. As shown in FIGS. 17a and 17b, FIG. 17a is a schematic diagram of the planar structure of three sub-pixels after the pixel definition layer is formed, and FIG. 17b is a schematic diagram of the planar structure of the pixel definition layer in FIG. 17a.

[0340] In the example embodiment, the pixel definition layer pattern can include a plurality of pixel openings K0, and the pixel openings K0 expose the anode AN. In the example embodiment, the orthographic projection of the pixel openings K0 on the substrate is within the range of the orthographic projection of the anode AN on the substrate. In the example embodiment, the pixel openings K0 can include a pixel opening K01 of the first sub-pixel, a pixel opening K02 of the second sub-pixel, and a pixel opening K03 of the third sub-pixel. The orthographic projection of the pixel opening K01 of the first sub-pixel on the substrate overlaps with the orthographic projection of the first anode AN1 on the substrate. The orthographic projection of the pixel opening K02 of the second sub-pixel on the substrate overlaps with the orthographic projection of the second anode AN2 on the substrate. The orthographic projection of the pixel opening K03 of the third sub-pixel on the substrate overlaps with the orthographic projection of the third anode AN3 on the substrate.

[0341] In the example embodiment, the shielding layer, the first conductive layer, the second conductive layer, the third conductive layer, the fourth conductive layer, and the fifth conductive layer can be made of a metal material, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), and molybdenum (Mo), or an alloy material of the above-mentioned metals, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb), which can be a single-layer structure or a multi-layer composite structure, such as Mo / Cu / Mo, Ti / Al / Ti, etc. The first insulating layer, the second insulating layer, the third insulating layer, the fourth insulating layer, and the fifth insulating layer can be made of any one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON), which can be a single layer, multiple layers, or a composite layer.

[0342] In an exemplary embodiment, taking 3 sub-pixels (1 sub-pixel pixel driving circuit row, 3 sub-pixels pixel driving circuit column, pixel driving circuit using 7T2C structure) in the display area (AA) as an example, another preparation process of the display substrate can include the steps (101) to (112) as described above, and the difference from the steps (101) to (112) is as follows:

[0343] The second conductive layer formed in the step (103) can be as shown in FIGS. 18a and 18b. The second conductive layer shown in FIG. 18b is different from the second conductive layer shown in FIG. 8b in that the first shielding line BL1, the second shielding line BL2 and the bottom gate T7gb of the seventh transistor T7 are newly added in the second conductive layer. The first shielding line BL1 and the second shielding line BL2 can be in a broken line shape or a strip shape extending along the first direction X. In the same sub-pixel row, the second shielding line BL2 and the first shielding line BL1 can be arranged at intervals along the second direction Y. In the same sub-pixel, in the second direction Y, the bottom gate T7gb of the seventh transistor T7 is located on the side of the second shielding line BL2 away from the first shielding line BL1. The first shielding line BL1 and the second shielding line BL2 are located on both sides of the second plate C12 of the first capacitor C1 and the second plate C22 of the second capacitor C2. The orthographic projection of the bottom gate T7gb of the seventh transistor T7 on the base at least partially overlaps the orthographic projection of the top gate T7gt and the active layer AT7 of the seventh transistor T7 on the base. The top gate T7gt and the bottom gate T7gb of the seventh transistor T7 are connected to the third reset control line Reset3, that is, the bottom gate T7gb of the seventh transistor T7 is connected in parallel with the top gate T7gt of the seventh transistor T7, both of which are connected to the same signal source, forming a double-gate structure of the seventh transistor T7. The orthographic projection of the first shielding line BL1 on the base at least partially overlaps the orthographic projection of the first light-emitting control line EM1 on the base. The orthographic projection of the second shielding line BL2 on the base at least partially overlaps the orthographic projection of the second light-emitting control line EM2 on the base. The region where the first shielding line BL1 overlaps the active layer AT5 of the fifth transistor T5 can be used as a bottom gate of the fifth transistor T5. The signal of the first shielding line BL1 can be the same as that of the first light-emitting control line EM1, that is, the first shielding line BL1 is connected in parallel with the first light-emitting control line EM1, both of which are connected to the same signal source, forming a double-gate structure of the fifth transistor T5. The region where the second shielding line BL2 overlaps the active layer AT6 of the sixth transistor T6 can be used as a bottom gate of the sixth transistor T6. The signal of the second shielding line BL2 can be the same as that of the second light-emitting control line EM2, that is, the second shielding line BL2 is connected in parallel with the second light-emitting control line EM2, both of which are connected to the same signal source, forming a double-gate structure of the sixth transistor T6.In the example embodiment, in the same row of sub-pixels, the bottom gate T7gb of the seventh transistor T7 of the N+1th column of sub-pixels is connected with the bottom gate T7gb of the seventh transistor T7 of the N+2th column of sub-pixels, for example, the bottom gate T7gb of the seventh transistor T7 of the N+1th column of sub-pixels and the bottom gate T1gb of the seventh transistor T7 of the N+2th column of sub-pixels can be an integrated structure connected with each other. Since the bottom gate T7gb of the seventh transistor T7 in the sub-pixel is connected with the third reset control line Reset3 formed subsequently, by forming the bottom gate T7gb of the seventh transistor T7 of adjacent sub-pixels into an integrated structure connected with each other, it can be ensured that the bottom gate T7gb of the seventh transistor T7 of adjacent sub-pixels has substantially the same potential, which is conducive to improving the uniformity of panel display, avoiding display defects of the display substrate, and ensuring the display effect of the display substrate.

[0344] The fourth insulating layer formed in the step (106) can be as shown in FIG. 20. The difference between the fourth insulating layer pattern shown in FIG. 20 and the fourth insulating layer pattern shown in FIG. 11 is that in the fourth insulating layer pattern shown in FIG. 20, an eighteenth via hole V18 is newly added, the orthographic projection of the eighteenth via hole V18 on the substrate is located within the range of the orthographic projection of the bottom gate T1gb of the seventh transistor T7 on the substrate, the fourth insulating layer, the third insulating layer and the second insulating layer in the eighteenth via hole V18 are etched away, and the surface of the bottom gate T1gb of the seventh transistor T7 is exposed. The eighteenth via hole V18 is configured to enable the third reset control line Reset3 formed subsequently to be connected with the bottom gate T1gb of the seventh transistor T7 through the via hole.

[0345] The fourth conductive layer formed in the step (107) can be as shown in FIGS. 21a and 21b. FIG. 21a is a planar structural diagram of three sub-pixels after the fourth conductive layer is formed, and FIG. 21b is a planar schematic diagram of the fourth conductive layer in FIG. 21a. The difference between the fourth conductive layer pattern shown in FIG. 21b and the fourth conductive layer pattern shown in FIG. 12b is that in the fourth conductive layer pattern shown in FIG. 21b, the third reset control line Reset3 can also be connected with the bottom gate T7gb of the seventh transistor T7 through the eighteenth via hole V18. The planar structural schematic diagram after the fifth insulating layer and the first planar layer pattern, the fifth conductive layer, the second planar layer, the anode conductive layer and the pixel definition layer are sequentially formed on the basis of FIG. 21a is shown in FIG. 21c.

[0346] In the example embodiment, taking 3 sub-pixels (1 row of pixel driving circuit of sub-pixels, 3 columns of pixel driving circuit of sub-pixels, and the pixel driving circuit adopts a 7T2C structure) in the display area (AA) as an example, another preparation process of the display substrate can include the steps (101) to (112) as described above, wherein the difference from the steps (101) to (112) is as follows (V15 and V17 are not provided, and V27-V30 are newly added):

[0347] The first conductive layer formed by the step (102) can be as shown in FIG. 22. The first conductive layer shown in FIG. 22 is different from the first conductive layer shown in FIG. 7 in that a first connecting portion CL1 is arranged on the first plate C11 of the first capacitor C1 in FIG. 22. In the same sub-pixel, the first plate C11 of the first capacitor C1 and the first plate C21 of the second capacitor C2 are arranged in the second direction Y in sequence. In the second direction Y, the first connecting portion CL1 is located on the side of the first plate C11 of the first capacitor C1 away from the first plate C21 of the second capacitor C2. The first connecting portion CL1 can be in the shape of a strip extending in the second direction Y or in the shape of a broken line. The contour of the first plate C11 of the first capacitor C1 and the first plate C21 of the second capacitor C2 can be a polygon or a rectangle with at least one side being a broken line.

[0348] The second conductive layer formed in step (103) can be as shown in FIGS. 23a and 23b. FIG. 23a is a plan view of three sub-pixels after the second conductive layer is formed, and FIG. 23b is a plan view of the second conductive layer in FIG. 23a. The semiconductor layer shown in FIG. 23b is different from the semiconductor layer shown in FIG. 8b in that: the second plate C22 of the second capacitor C2 is not provided with an opening K11, the second plate C12 of the first capacitor C1 is provided with a second connecting portion CL2, the first shielding line BL1, the second shielding line BL2, the third shielding line BL3, the bottom gate T1gb of the first transistor T1, the bottom gate T2gb of the second transistor T2, the bottom gate T4gb of the fourth transistor T4, and the bottom gate T7gb of the seventh transistor T7 are newly added. The outlines of the second plate C12 of the first capacitor C1 and the second plate C22 of the second capacitor C2 can be polygonal or rectangular with at least one side being a broken line; in the same sub-pixel, in the second direction Y, the second connecting portion CL2 is located on the side of the second plate C12 of the first capacitor C1 away from the second plate C22 of the second capacitor C2, in the first direction X, the first connecting portion CL1 and the second connecting portion CL2 are located on both sides of the second plate C12 of the first capacitor C1, the second connecting portion CL2 can be in the shape of a strip or a block structure extending in the first direction X, and the second plate C12 of the first capacitor C1 and the second plate C22 of the second capacitor C2 are arranged in sequence in the second direction Y; the first shielding line BL1, the second shielding line BL2, and the third shielding line BL3 can be in the shape of a broken line or a strip with the main body extending in the first direction X, in the same row of pixel driving circuits, the third shielding line BL3, the second shielding line BL2, and the first shielding line BL1 can be arranged at intervals in the second direction Y, in the second direction Y, in the same sub-pixel, the bottom gate T1gb of the first transistor T1, the bottom gate T2gb of the second transistor T2, and the bottom gate T4gb of the fourth transistor T4 can be located between the first shielding line BL1 and the second shielding line BL2, and the bottom gate T7gb of the seventh transistor T7 can be located on the side of the second shielding line BL2 away from the first shielding line BL1, and the first shielding line BL1 and the second shielding line BL2 are located on both sides of the second plate C12 of the first capacitor C1 and the second plate C22 of the second capacitor C2; in the same sub-pixel, in the first direction X, the bottom gate T1gb of the first transistor T1, the bottom gate T2gb of the second transistor T2, the bottom gate T4gb of the fourth transistor T4, and the bottom gate T7gb of the seventh transistor T7 can be located on the same side of the second plate C12 of the first capacitor C1 and the second plate C22 of the second capacitor C2.The orthogonal projection of the bottom gate T1gb of the first transistor T1 on the substrate at least partially overlaps the orthogonal projection of the top gate T1gt of the first transistor T1 and the active layer AT1 of the first transistor T1 on the substrate, the bottom gate T1gb of the first transistor T1 and the top gate T1gt of the first transistor T1 are connected with the first reset control line Reset1, that is, the bottom gate T1gb of the first transistor T1 and the top gate of the first transistor T1 are connected in parallel, both of which are connected to the same signal source, forming a double-gate structure of the first transistor T1; the orthogonal projection of the bottom gate T2gb of the second transistor T2 on the substrate at least partially overlaps the orthogonal projection of the top gate T2gt of the second transistor T2 and the active layer AT2 of the second transistor T2 on the substrate, the bottom gate T2gb of the second transistor T2 and the top gate T2gt of the second transistor T2 are connected with the second reset control line Reset2, that is, the bottom gate T2gb of the second transistor T2 and the top gate T2gt of the second transistor T2 are connected in parallel, both of which are connected to the same signal source, forming a double-gate structure of the second transistor T2; the orthogonal projection of the bottom gate T4gb of the fourth transistor T4 on the substrate at least partially overlaps the orthogonal projection of the top gate T4gt of the fourth transistor T4 and the active layer AT4 of the fourth transistor T4 on the substrate, the bottom gate T4gb of the fourth transistor T4 and the top gate T4gt of the fourth transistor T4 are connected with the scan signal line Gate, that is, the bottom gate T4gb of the fourth transistor T4 and the top gate T4gt of the fourth transistor T4 are connected in parallel, both of which are connected to the same signal source, forming a double-gate structure of the fourth transistor T4; the orthogonal projection of the bottom gate T7gb of the seventh transistor T7 on the substrate at least partially overlaps the orthogonal projection of the top gate T7gt of the seventh transistor T7 and the active layer AT7 of the seventh transistor T7 on the substrate, the bottom gate T7gb of the seventh transistor T7 and the top gate T7gt of the seventh transistor T7 are connected with the third reset control line Reset3, that is, the bottom gate T7gb of the seventh transistor T7 and the top gate T7g of the seventh transistor T7 are connected in parallel, both of which are connected to the same signal source, forming a double-gate structure of the seventh transistor T7; the bottom gate T7gb of the seventh transistor T7 in a row of pixel driving circuits can be arranged on the side of the third shielding line BL3 of the row of pixel driving circuits close to the second shielding line BL2; the orthogonal projection of the first shielding line BL1 on the substrate at least partially overlaps the orthogonal projection of the first light-emitting control line EM1 on the substrate, and the orthogonal projection of the second shielding line BL2 on the substrate at least partially overlaps the orthogonal projection of the second light-emitting control line EM2 on the substrate; the area where the first shielding line BL1 overlaps the active layer AT5 of the fifth transistor T5 can be used as the bottom gate of the fifth transistor T5, and the signal of the first light-emitting control line EM1 can be the same, that is, the first shielding line BL1 and the first light-emitting control line EM1 are connected in parallel, both of which are connected to the same signal source, forming a double-gate structure of the fifth transistor T5;The region where the second shielding line BL2 overlaps with the active layer AT6 of the sixth transistor T6 can be used as the bottom gate of the sixth transistor T6, and the signal of the second shielding line BL2 and the second light-emitting control line EM2 can be the same, that is, the second shielding line BL2 and the second light-emitting control line EM2 are connected in parallel and connected to the same signal source, forming a double-gate structure of the sixth transistor T6. In the exemplary embodiment, in the same row of sub-pixels, the bottom gate T1gb of the first transistor T1 of the N+1th column of sub-pixels and the bottom gate T1gb of the first transistor T1 of the N+2th column of sub-pixels are connected to each other, the bottom gate T2gb of the second transistor T2 of the N+1th column of sub-pixels and the bottom gate T2gb of the second transistor T2 of the N+2th column of sub-pixels are connected to each other, and the bottom gate T4gb of the fourth transistor T4 of the N+1th column of sub-pixels and the bottom gate T4gb of the fourth transistor T4 of the N+2th column of sub-pixels are connected to each other. For example, the bottom gate T1gb of the first transistor T1 of the N+1th column of sub-pixels and the bottom gate T1gb of the first transistor T1 of the N+2th column of sub-pixels can be an integrated structure connected to each other, the bottom gate T2gb of the second transistor T2 of the N+1th column of sub-pixels and the bottom gate T2gb of the second transistor T2 of the N+2th column of sub-pixels can be an integrated structure connected to each other, and the bottom gate T4gb of the fourth transistor T4 of the N+1th column of sub-pixels and the bottom gate T4gb of the fourth transistor T4 of the N+2th column of sub-pixels can be an integrated structure connected to each other. Since the bottom gate T1gb of the first transistor T1 in the sub-pixel is connected to the first reset control line Reset1 formed subsequently, by forming the bottom gate T1gb of the first transistor T1 of the adjacent sub-pixels into an integrated structure connected to each other, it can be ensured that the bottom gate T1gb of the first transistor T1 of the adjacent sub-pixels has substantially the same potential. Since the bottom gate T2gb of the second transistor T2 in the sub-pixel is connected to the second reset control line Reset2 formed subsequently, by forming the bottom gate T2gb of the second transistor T2 of the adjacent sub-pixels into an integrated structure connected to each other, it can be ensured that the bottom gate T2gb of the second transistor T2 of the adjacent sub-pixels has substantially the same potential. Since the bottom gate T4gb of the fourth transistor T4 in the sub-pixel is connected to the scan signal line Gate formed subsequently, by forming the bottom gate T4gb of the fourth transistor T4 of the adjacent sub-pixels into an integrated structure connected to each other, it can be ensured that the bottom gate T4gb of the fourth transistor T4 of the adjacent sub-pixels has substantially the same potential, which is conducive to improving the uniformity of panel display, avoiding display defects of the display substrate, and ensuring the display effect of the display substrate.

[0349] The semiconductor layer formed in the step (104) can be as shown in FIGS. 24a and 24b. FIG. 24a is a plan view of three sub-pixels after the semiconductor layer is formed, and FIG. 24b is a plan view of the semiconductor layer in FIG. 24a. The semiconductor layer shown in FIG. 24b is different from the semiconductor layer shown in FIG. 9b in that the active layer AT6 of the sixth transistor T6 has an "I" shape in the semiconductor layer pattern, and the active layers AT5 of two adjacent fifth transistors T5 are not connected in the same row of pixel driving circuits.

[0350] The third conductive layer formed in the step (105) can be as shown in FIGS. 25a and 25b. FIG. 25a is a plan view of three sub-pixels after the second conductive layer is formed, and FIG. 25b is a plan view of the third conductive layer in FIG. 25a. The semiconductor layer shown in FIG. 25b is different from the third conductive layer shown in FIG. 10b in that the top gate T3gt of the third transistor T3 has a substantially rectangular structure.

[0351] The fourth insulating layer formed in step (106) can be as shown in FIG. 26. The fourth insulating layer pattern shown in FIG. 26 is different from the fourth insulating layer pattern shown in FIG. 11 in that: the fifteenth via hole V15 and the seventeenth via hole V17 are not provided in the fourth insulating layer pattern shown in FIG. 26, the twenty-seventh via hole V27, the twenty-eighth via hole V28, the twenty-ninth via hole V29, and the thirtieth via hole V30 are newly added, the orthogonal projection of the twenty-seventh via hole V27 on the substrate is located within the range of the orthogonal projection of the bottom gate T1gb of the first transistor T1 on the substrate, the fourth insulating layer, the third insulating layer, and the second insulating layer in the twenty-seventh via hole V27 are etched away, exposing the surface of the bottom gate T1gb of the first transistor T1, the twenty-seventh via hole V27 is configured to enable the first reset control line Reset1 formed later to be connected to the bottom gate T1gb of the first transistor T1 through the via hole; the orthogonal projection of the twenty-eighth via hole V28 on the substrate is located within the range of the orthogonal projection of the bottom gate T2gb of the second transistor T2 on the substrate, the fourth insulating layer, the third insulating layer, and the second insulating layer in the twenty-eighth via hole V28 are etched away, exposing the surface of the bottom gate T2gb of the second transistor T2, the twenty-eighth via hole V28 is configured to enable the second reset control line Reset2 formed later to be connected to the bottom gate T2gb of the second transistor T2 through the via hole; the orthogonal projection of the twenty-ninth via hole V29 on the substrate is located within the range of the orthogonal projection of the bottom gate T4gb of the fourth transistor T4 on the substrate, the fourth insulating layer, the third insulating layer, and the second insulating layer in the twenty-ninth via hole V29 are etched away, exposing the surface of the bottom gate T4gb of the fourth transistor T4, the twenty-ninth via hole V29 is configured to enable the scan signal line Gate formed later to be connected to the bottom gate T4gb of the fourth transistor T4 through the via hole; the orthogonal projection of the thirtieth via hole V30 on the substrate is located within the range of the orthogonal projection of the second region AT42 of the active layer AT4 of the fourth transistor T4 (also the second region AT12 of the active layer AT1 of the first transistor T1) on the substrate, the fourth insulating layer and the third insulating layer in the thirtieth via hole V30 are etched away, exposing the surface of the second region AT42 of the fourth transistor T4 (also the second region AT12 of the active layer AT1 of the first transistor T1), the thirtieth via hole V30 is configured to enable the fourth connection electrode L4 formed later to be connected to the second region AT42 of the fourth transistor T4 (also the second region AT12 of the active layer AT1 of the first transistor T1) through the via hole.The orthogonal projection of the ninth via V9 on the substrate is located within the range of the orthogonal projection of the first connecting portion CL1 on the substrate, the fourth insulating layer, the third insulating layer, the second insulating layer and the first insulating layer in the ninth via V9 are etched away, exposing the surface of the first connecting portion CL1, the ninth via V9 is configured to connect the second electrode of the second transistor T2 formed subsequently therewith the first connecting portion CL1 through the via; the orthogonal projection of the eleventh via V11 on the substrate is located within the range of the orthogonal projection of the second connecting portion CL2 on the substrate, the fourth insulating layer, the third insulating layer and the second insulating layer in the eleventh via V11 are etched away, exposing the surface of the second connecting portion CL2, the eleventh via V11 is configured to connect the fourth connecting electrode formed subsequently therewith the second connecting portion CL2 through the via.

[0352] The fourth conductive layer formed in the step (107) can be as shown in FIGS. 27a and 27b, FIG. 27a is a planar structural diagram of three sub-pixels after the fourth conductive layer is formed, and FIG. 27b is a planar schematic diagram of the fourth conductive layer in FIG. 27a. The difference between the fourth conductive layer pattern shown in FIG. 27b and the fourth conductive layer pattern shown in FIG. 12b is that: in the fourth conductive layer pattern shown in FIG. 27b, the third reset control line Reset3 is not provided, in the same row of pixel driving circuits, the scanning signal line Gate is located between the first power connection line VDDL and the second power connection line VSSL, in the same pixel driving circuit, in the second direction Y, the second connection line L2 is located between the second power connection line VSSL and the first reset control line Reset1, the third connection line L3 is located between the first reset control line Reset1 and the first initial signal line Vinit1, and the fourth connection line L4 is located between the second power connection line VSSL and the scanning signal line Gate; the first reset control line Reset1 can be connected with the bottom gate T1gb of the first transistor T1 through the twenty-seventh via V27, the second reset control line Reset2 can be connected with the bottom gate T2gb of the second transistor T2 through the twenty-eighth via V28, the scanning signal line Gate can be connected with the bottom gate T4gb of the fourth transistor T4 through the twenty-ninth via V29, and the fourth connection line L4 is connected with the second region AT42 of the active layer AT4 of the fourth transistor T4 (which is also the second region AT12 of the active layer AT1 of the first transistor T1) through the thirtieth via V30.

[0353] The fifth insulating layer and the first planarization layer pattern formed in the step (108) can be as shown in FIG. 28; the fifth conductive layer formed in the step (109) can be as shown in FIGS. 29a and 29b, FIG. 29a is a planar structure diagram of three sub-pixels after the fifth conductive layer is formed, and FIG. 29b is a planar diagram of the fifth conductive layer in FIG. 29a. The difference between the fifth conductive layer pattern shown in FIG. 29b and the fifth conductive layer pattern shown in FIG. 14b is that, in the same pixel unit, the first initial signal connection line Vinit1L, the first second power line VSS, the second initial signal connection line Vinit2L, the first power line VDD and the second second power line VSS can be arranged in the first direction X in turn, and in the first direction X, the data signal line D of the first sub-pixel is located on the side of the first initial signal connection line Vinit1L away from the first second power line VSS, the data signal line D of the second sub-pixel and the data signal line D of the third sub-pixel can be located between the second initial signal connection line Vinit2L and the first power line VDD, and the first power line VDD can be located between the data signal line D and the second second power line VSS; the anode connection electrode ZL in the second sub-pixel is located between the second initial signal connection line Vinit1L and the first second power line VSS, the anode connection electrode ZL in the third sub-pixel is located between the first power line VDD and the second second power line VSS, and the shape of the anode connection electrode ZL in the second sub-pixel and the third sub-pixel is "L" shape.

[0354] The second planar layer is formed on the basis of FIG. 29a as shown in FIG. 30; the anode conductive layer is formed on the basis of FIG. 30 as shown in FIG. 31a, and FIG. 31b is a planar structure diagram of the anode conductive layer in FIG. 31a; the pixel definition layer is formed on the basis of FIG. 31a as shown in FIG. 32a, and FIG. 32b is a planar structure diagram of the pixel definition layer in FIG. 31a.

[0355] In the exemplary embodiment, taking 3 sub-pixels (1 pixel driving circuit row of 1 sub-pixel, 3 pixel driving circuit columns of 3 sub-pixels, and the pixel driving circuit adopts a 6T2C structure) in the display area (AA) as an example, another preparation process of the display substrate can include the following operations:

[0356] (201)A substrate is prepared on a glass carrier. In an example embodiment, the substrate can be a flexible substrate, or can be a rigid substrate. The rigid substrate can include, but is not limited to, one or more of glass, quartz, and the flexible substrate can be, but is not limited to, one or more of polyethylene terephthalate, polyether ether ketone, polystyrene, polycarbonate, polyarylate, polyarylate, polyimide, polyvinyl chloride, polyethylene, and textile fibers. In an example embodiment, the flexible substrate can include a first flexible material layer, a first inorganic material layer, a bonding layer, a second flexible material layer, and a second inorganic material layer stacked. The material of the first and second flexible material layers can be polyimide (PI), polyethylene terephthalate (PET), or a surface-treated polymer soft film, etc., and the material of the first and second inorganic material layers can be silicon nitride (SiNx) or silicon oxide (SiOx), etc., for improving the water and oxygen resistance of the substrate, and the first and second inorganic material layers are also called barrier layers, and the material of the bonding layer can be amorphous silicon (a-si). In an example embodiment, taking the stacked structure PI1 / Barrier1 / a-si / PI2 / Barrier2 as an example, the preparation process can include: first coating a layer of polyimide on the glass carrier, and after curing to form a film, a first flexible material (PI1) layer is formed; then depositing a barrier film on the first flexible layer to form a first barrier (Barrier1) layer covering the first flexible material layer; then depositing an amorphous silicon film on the first barrier layer to form an amorphous silicon (a-si) layer covering the first barrier layer; then coating a layer of polyimide on the amorphous silicon layer, and after curing to form a film, a second flexible material (PI2) layer is formed; then depositing a barrier film on the second flexible layer to form a second barrier (Barrier2) layer covering the second flexible layer, and the preparation of the substrate is completed.

[0357] (202)A first conductive layer pattern is formed. In an example embodiment, forming the first conductive layer pattern can include: depositing a first conductive film on the substrate, patterning the first conductive film by a patterning process, and forming a first conductive layer pattern on the substrate, as shown in FIG. 33, which is a planar structure schematic diagram of three sub-pixels after the first conductive layer is formed. The first conductive layer can be referred to as a first gate metal (GATE1) layer.

[0358] In an example embodiment, the first conductive layer pattern can include at least: a first plate C11 of a first capacitor C1, and a first plate C21 of a second capacitor C2.

[0359] In the example embodiment, the first plate C11 of the first capacitor C1 and the first plate C21 of the second capacitor C2 can be in a block structure, and the block structure can be in a polygonal shape. In the example embodiment, at least one edge of the polygonal block structure is a broken line. For example, the block structure can be in a rectangular shape, and at least one edge of the rectangle is a broken line. In the example embodiment, the first plate C11 of the first capacitor C1 and the first plate C21 of the second capacitor C2 can be arranged in sequence in the second direction Y.

[0360] In the example embodiment, the first plate C11 of the first capacitor C1 is provided with a first connecting portion CL1, the first connecting portion CL1 is configured to accommodate a twelfth via hole formed subsequently, the orthogonal projection of the twelfth via hole on the substrate is within the range of the orthogonal projection of the first connecting portion CL1 on the substrate, and the surface of the first connecting portion CL1 is exposed, so that the second electrode of the first transistor T1 and the second electrode of the fourth transistor T4 formed subsequently are connected to the first plate C11 of the first capacitor C1 through the twelfth via hole and the first connecting portion CL1.

[0361] In the example embodiment, the first plate C21 of the second capacitor C1 is provided with a second connecting portion CL2, the second connecting portion CL2 is configured to accommodate a thirteenth via hole formed subsequently, the orthogonal projection of the thirteenth via hole on the substrate is within the range of the orthogonal projection of the second connecting portion CL2 on the substrate, and the surface of the second connecting portion CL2 is exposed, so that the first power connection line VDDL formed subsequently is connected to the first plate C21 of the second capacitor C2 through the thirteenth via hole and the second connecting portion CL2.

[0362] Taking the Mth row and the Nth column sub-pixel as an example, in the second direction Y, the first plate C11 of the first capacitor C1 in the Mth row can be located on the side of the first plate C21 of the second capacitor C2 in the sub-pixel close to the M+1th row sub-pixel.

[0363] (203) Forming a second conductive layer pattern. In the example embodiment, forming the second conductive layer pattern can include: sequentially depositing a first insulating film and a second conductive film on the substrate on which the aforementioned pattern is formed, patterning the second conductive film by a patterning process, forming a first insulating layer covering the first conductive layer, and a second conductive layer pattern disposed on the first insulating layer, as shown in FIGS. 34a and 34b, FIG. 34a is a planar structure diagram of three sub-pixels after the second conductive layer is formed, and FIG. 34b is a planar schematic diagram of the second conductive layer in FIG. 34a. In the example embodiment, the second conductive layer can be referred to as a second gate metal (GATE2) layer.

[0364] In an example embodiment, the second conductive layer pattern comprises at least: the second plate C12 of the first capacitor C1, the second plate C22 of the second capacitor C2, the first shielding line BL1, the second shielding line BL2, the bottom gate T1gb of the first transistor T1, the bottom gate T2gb of the second transistor T2, and the bottom gate T4gb of the fourth transistor T4. In an example embodiment, the second plate C22 of the second capacitor C2 can shield the channel region of the third transistor T3, thereby improving the stability of the third transistor T3. In an example embodiment, the second plate C22 of the second capacitor C2 can serve as the bottom gate T3gb of the third transistor T3.

[0365] In an example embodiment, in the second direction Y, the second plate C12 of the first capacitor C1 can be located on one side of the second plate C22 of the second capacitor C2 in the same sub-pixel, and the second plate C12 of the first capacitor C1 and the second plate C22 of the second capacitor C2 are located between the first shielding line BL1 and the second shielding line BL2. For example, in the same sub-pixel, the second shielding line BL2, the second plate C12 of the first capacitor C1, the second plate C22 of the second capacitor C2, and the first shielding line BL1 can be arranged in sequence along the second direction Y.

[0366] In an example embodiment, in the same sub-pixel, in the second direction Y, the bottom gate T1gb of the first transistor T1 is located between the second plate C22 of the second capacitor C2 and the second shielding line BL2, the bottom gate T2gb of the second transistor T2 is located on the side of the second shielding line BL2 away from the second plate C22 of the second capacitor C2, and the bottom gate T4gb of the fourth transistor T4 is located between the second plate C22 of the second capacitor C2 and the first shielding line BL1. In the first direction X, the bottom gate T4gb of the fourth transistor T4 is located on one side of the second plate C22 of the second capacitor C2. Taking the Mth row and Nth column sub-pixel as an example, the bottom gate T4gb of the fourth transistor T4 in the Nth column sub-pixel is located on the side of the second capacitor C2 in the column sub-pixel away from the N+1th column sub-pixel.

[0367] In an example embodiment, the first shielding line BL1 can be in the shape of a strip or a polyline, and the main body portion can extend along the first direction X. The first shielding line BL1 is configured to serve as a shielding layer of the fifth transistor T5, shielding the channel of the fifth transistor T5, and ensuring the electrical performance of the oxide fifth transistor T5. In an example embodiment, the signal of the first shielding line BL1 and the first light-emitting control line EM1 formed subsequently can be the same, that is, the first shielding line BL1 and the first light-emitting control line EM1 formed subsequently are connected in parallel, both of which are connected to the same signal source, so that the first shielding line BL1 can serve as the bottom gate (i.e., the bottom control electrode) of the fifth transistor T5, forming a double-gate structure of the fifth transistor T5.

[0368] In an example embodiment, the second shielding line BL2 can have a strip shape or a broken line shape, and the main body portion can extend along the first direction X. The second shielding line BL2 is configured to serve as a shielding layer of the sixth transistor T6, shield the channel of the sixth transistor T6, and ensure the electrical performance of the oxide sixth transistor T6. In an example embodiment, the second shielding line BL2 can have the same signal as the second emission control line EM2 formed subsequently, i.e., the second shielding line BL2 and the second emission control line EM2 formed subsequently are connected in parallel and connected to the same signal source, so that the second shielding line BL2 can serve as the bottom gate (i.e., the bottom control electrode) of the sixth transistor T6, forming a double-gate structure of the sixth transistor T6.

[0369] In an example embodiment, the bottom gate T1gb of the first transistor T1 can have a strip shape or a broken line shape extending along the first direction X, and is configured to serve as a shielding layer of the first transistor T1, shield the channel of the first transistor T1, and ensure the electrical performance of the oxide first transistor T1. In an example embodiment, the bottom gate T1gb of the first transistor T1 and the top gate of the first transistor T1 formed subsequently are connected to the first reset control line Reset1, i.e., the bottom gate T1gb of the first transistor T1 and the top gate of the first transistor T1 formed subsequently are connected in parallel and connected to the same signal source, so that the bottom gate T1gb of the first transistor T1 can serve as the bottom gate electrode (i.e., the bottom control electrode) of the first transistor T1, forming a double-gate structure of the first transistor T1.

[0370] In an example embodiment, the bottom gate T2gb of the second transistor T2 can have a strip shape or a broken line shape extending along the first direction X, and is configured to serve as a shielding layer of the second transistor T2, shield the channel of the second transistor T2, and ensure the electrical performance of the oxide second transistor T2. In an example embodiment, the bottom gate T2gb of the second transistor T2 and the top gate of the second transistor T2 formed subsequently are connected to the second reset control line Reset2, i.e., the bottom gate T2gb of the second transistor T2 and the top gate of the second transistor T2 formed subsequently are connected in parallel and connected to the same signal source, so that the bottom gate T2gb of the second transistor T2 can serve as the bottom gate electrode (i.e., the bottom control electrode) of the second transistor T2, forming a double-gate structure of the second transistor T2.

[0371] In the example embodiment, the bottom gate T4gb of the fourth transistor T4 can be a strip structure or a zigzag structure extending along the first direction X, configured as a shielding layer of the fourth transistor T4, shielding the channel of the fourth transistor T4, and ensuring the electrical performance of the oxide fourth transistor T4. In the example embodiment, the bottom gate T4gb of the fourth transistor T4 and the top gate of the fourth transistor T4 formed subsequently are connected to the scan signal line Gate, i.e., the bottom gate T4gb of the fourth transistor T4 and the top gate of the fourth transistor T4 formed subsequently are connected in parallel, both of which are connected to the same signal source, so that the bottom gate T4gb of the fourth transistor T4 can serve as the bottom gate (i.e., the bottom control electrode) of the fourth transistor T4, forming a double-gate structure of the fourth transistor T4.

[0372] In the example embodiment, the profile of the second plate C12 of the first capacitor C1 can be consistent with the profile of the first plate C11 of the first capacitor C1, and the profile of the second plate C22 of the second capacitor C2 can be consistent with the profile of the first plate C21 of the second capacitor C2, for example, the profile of the second plate C12 of the first capacitor C1 and the profile of the second plate C22 of the second capacitor C2 can be polygonal (such as rectangular, and at least one edge of the rectangle is a zigzag). In the example embodiment, the orthographic projection of the second plate C12 of the first capacitor C1 on the substrate overlaps with the orthographic projection of the first plate C11 of the first capacitor C1 on the substrate, and the orthographic projection of the second plate C22 of the second capacitor C2 on the substrate overlaps with the orthographic projection of the first plate C21 of the second capacitor C2 on the substrate, for example, the orthographic projection of the second plate C12 of the first capacitor C1 on the substrate can be within the range of the orthographic projection of the first plate C11 of the first capacitor C1 on the substrate, and the orthographic projection of the second plate C22 of the second capacitor C2 on the substrate can be within the range of the orthographic projection of the first plate C21 of the second capacitor C2 on the substrate. In the example embodiment, the first plate C11 of the first capacitor C1 and the second plate C12 of the first capacitor C1 constitute the first capacitor C1, and the first plate C21 of the second capacitor C2 and the second plate C22 of the second capacitor C2 constitute the second capacitor C2.

[0373] In the example embodiment, the third connection part CL3 can be provided on the second plate C22 of the second capacitor C2, and the third connection part CL3 is configured to accommodate the fourteenth via hole formed subsequently, the orthographic projection of the fourteenth via hole on the substrate is within the range of the orthographic projection of the third connection part CL3 on the substrate, and exposes the surface of the third connection part CL3, so that the second electrode of the third transistor T3 formed subsequently is connected to the second plate of the second capacitor C2 through the fourteenth via hole and the third connection part CL3.

[0374] In the example embodiment, the second plate C22 of the second capacitor C2 can shield the channel of the third transistor T3, ensuring the electrical performance of the oxide third transistor T3.

[0375] (204) Forming a semiconductor layer pattern. In the example embodiment, forming a semiconductor layer pattern can include: on the substrate on which the aforementioned pattern is formed, sequentially depositing a second insulating thin film and a semiconductor thin film, patterning the semiconductor thin film through a patterning process, forming a second insulating layer covering the substrate, and a semiconductor layer pattern disposed on the second insulating layer, as shown in FIGS. 35a and 35b, FIG. 35a is a planar structure diagram of three sub-pixels after forming a semiconductor layer, and FIG. 35b is a planar schematic diagram of the semiconductor layer in FIG. 35a.

[0376] In the example embodiment, the semiconductor layer pattern in at least part of the sub-pixels at least includes: an active layer AT1 of the first transistor T1 to an active layer AT6 of the sixth transistor T6.

[0377] In the example embodiment, in the same sub-pixel, the active layer AT2 of the second transistor T2 and the active layer AT6 of the sixth transistor T6 are connected to each other, and the active layer AT3 of the third transistor T3 and the active layer AT5 of the fifth transistor T5 can be connected to each other, for example, the active layer AT2 of the second transistor T2, the active layer AT6 of the sixth transistor T6, the active layer AT3 of the third transistor T3, and the active layer AT5 of the fifth transistor T5 can be an integrated structure connected to each other.

[0378] In the example embodiment, in the same sub-pixel, in the first direction X, the active layer of the first transistor T1 and the active layer AT4 of the fourth transistor T4 are located on the same side of the active layer AT2 of the second transistor T2, the active layer AT3 of the third transistor T3, the active layer AT5 of the fifth transistor T5, and the active layer AT6 of the sixth transistor T6; in the second direction Y, the active layer AT4 of the fourth transistor T4 and the active layer AT5 of the fifth transistor T5 are located on the same side of the active layer AT1 of the first transistor T1 and the active layer AT2 of the second transistor T2, the active layer AT5 of the fifth transistor T5 and the active layer AT6 of the sixth transistor T6 are located on both sides of the active layer AT3 of the third transistor T3, and the active layer AT2 of the second transistor T2 is located on the side of the active layer AT6 of the sixth transistor T6 away from the active layer AT3 of the third transistor T3.

[0379] In the exemplary embodiments, the active layer AT1 of the first transistor T1, the active layer AT2 of the second transistor T2, the active layer AT3 of the third transistor T3, the active layer AT4 of the fourth transistor T4, the active layer AT5 of the fifth transistor T5, and the active layer AT6 of the sixth transistor T6 can be in the shape of an "I" letter or a strip.

[0380] In the exemplary embodiments, the active layer AT1 of the first transistor T1, the active layer AT2 of the second transistor T2, the active layer AT3 of the third transistor T3, the active layer AT4 of the fourth transistor T4, the active layer AT5 of the fifth transistor T5, and the active layer AT6 of the sixth transistor T6 can be in the shape of an "I" letter or a strip.

[0381] In the exemplary embodiments, the active layer of at least part of the transistors can include a first region, a second region, and a channel region between the first region and the second region. In the exemplary embodiments, the first region AT31 of the active layer AT3 of the third transistor T3 can serve as the second region AT52 of the active layer AT5 of the fifth transistor T5, the second region AT32 of the active layer AT3 of the third transistor T3 can serve as the first region AT61 of the active layer AT6 of the sixth transistor T6, the second region AT62 of the active layer AT6 of the sixth transistor T6 can serve as the second region AT22 of the active layer AT2 of the second transistor T2, and the first region AT11 and the second region AT12 of the active layer AT1 of the first transistor T1, the first region AT21 of the active layer AT2 of the second transistor T2, the first region AT41 and the second region AT42 of the active layer AT4 of the fourth transistor T4, and the first region AT51 of the active layer AT5 of the fifth transistor T5 can be separately provided.

[0382] In an example embodiment, the conductor layer can employ an oxide, i.e., the first to sixth transistors T1-T6 are oxide thin film transistors. In an example embodiment, the oxide can be any one or more of the following: indium gallium zinc oxide (InGaZnO), indium gallium zinc nitride oxide (InGaZnON), zinc oxide (ZnO), zinc nitride oxide (ZnON), zinc tin oxide (ZnSnO), cadmium tin oxide (CdSnO), gallium tin oxide (GaSnO), titanium tin oxide (TiSnO), copper aluminum oxide (CuAlO), strontium copper oxide (SrCuO), lanthanum copper sulfur oxide (LaCuOS), gallium nitride (GaN), indium gallium nitride (InGaN), aluminum gallium nitride (AlGaN), and indium gallium aluminum nitride (InGaAlN). In some possible implementations, the semiconductor thin film can employ indium gallium zinc oxide (IGZO), which has a higher electron mobility than amorphous silicon. Since the leakage current of the IGZO TFT is relatively small, the use of N-type transistors can avoid leakage of the first node N1 during the light emitting stage.

[0383] (205) Forming a third conductive layer pattern. In an example embodiment, forming the third conductive layer pattern can include: on the substrate on which the aforementioned patterns are formed, sequentially depositing a third insulating thin film and a third conductive thin film, patterning the third conductive thin film using a patterning process, forming a third insulating layer covering the semiconductor layer, and a third conductive layer pattern disposed on the third insulating layer, as shown in FIGS. 36a and 36b, FIG. 36a is a plan view of the three sub-pixels after the third conductive layer is formed, and FIG. 36b is a plan view of the third conductive layer in FIG. 36a. In an example embodiment, the third conductive layer can be referred to as a third gate metal (GATE3) layer.

[0384] In an example embodiment, the third conductive layer pattern includes at least: a first light emitting control line EM1, a second light emitting control line EM2, a top gate T1gt of the first transistor T1, a top gate T2gt of the second transistor T2, a top gate T3gt of the third transistor T3, and a top gate T4gt of the fourth transistor T4. The first light emitting control line EM1 and the second light emitting control line EM2 can be polyline-shaped or strip-shaped extending along the first direction X, and in the same sub-pixel row, the second light emitting control line EM2 and the first light emitting control line EM1 can be arranged at intervals along the second direction Y, and in the same sub-pixel, the top gate T1gt of the first transistor T1, the top gate T3gt of the third transistor T3, and the top gate T4gt of the fourth transistor T4 are located between the first light emitting control line EM1 and the second light emitting control line EM2, and the top gate T2gt of the second transistor T2 is located on the side of the second light emitting control line EM2 away from the first light emitting control line EM1.

[0385] In the example embodiment, the region where the first light-emitting control line EM1 overlaps with the active layer AT5 of the fifth transistor T5 can serve as the control electrode of the fifth transistor T5 (i.e., the top gate of the fifth transistor T5), and the region where the second light-emitting control line EM2 overlaps with the active layer AT6 of the sixth transistor T6 can serve as the control electrode of the sixth transistor T6 (i.e., the top gate of the sixth transistor T6). In the example embodiment, the orthographic projection of the first light-emitting control line EM1 on the substrate at least partially overlaps with the orthographic projection of the first shielding line BL1 on the substrate, and the orthographic projection of the second light-emitting control line EM2 on the substrate at least partially overlaps with the orthographic projection of the second shielding line BL2 on the substrate, for example, the orthographic projection of the first light-emitting control line EM1 on the substrate can be within the range of the orthographic projection of the first shielding line BL1 on the substrate, and the orthographic projection of the second light-emitting control line EM2 on the substrate can be within the range of the orthographic projection of the second shielding line BL2 on the substrate, which can save the space of the display substrate and improve the utilization rate of the space of the display substrate.

[0386] In the example embodiment, the orthographic projection of the top gate T1gt of the first transistor T1 on the substrate at least partially overlaps with the orthographic projection of the active layer AT1 of the first transistor T1 and the orthographic projection of the bottom gate T1gb of the first transistor T1 on the substrate; the orthographic projection of the top gate T2gt of the second transistor T2 on the substrate at least partially overlaps with the orthographic projection of the active layer AT2 of the second transistor T2 and the orthographic projection of the bottom gate T2gb of the second transistor T2 on the substrate; the orthographic projection of the top gate T3gt of the third transistor T3 on the substrate at least partially overlaps with the orthographic projection of the active layer AT3 of the third transistor T3 and the orthographic projection of the second plate C22 of the second capacitor C2 on the substrate; and the orthographic projection of the top gate T4gt of the fourth transistor T4 on the substrate at least partially overlaps with the orthographic projection of the active layer AT4 of the fourth transistor T4 and the orthographic projection of the bottom gate T4gb of the fourth transistor T4 on the substrate.

[0387] In the example embodiment, in the same sub-pixel, in the second direction Y, the top gate T1gt of the first transistor T1, the top gate T3gt of the third transistor T3, and the top gate T4gt of the fourth transistor T4 are located between the first light-emitting control line EM1 and the second light-emitting control line EM2, the top gate T2gt of the second transistor T2 is located on the side of the second light-emitting control line EM2 away from the first light-emitting control line EM1, the top gate T1gt of the first transistor T1 is located between the second light-emitting control line EM2 and the top gate T4gt of the fourth transistor T4, and the top gate T3gt of the third transistor T3 is located between the top gate T1gt of the first transistor T1 and the top gate T4gt of the fourth transistor T4; in the first direction X, in the same sub-pixel, the top gate T1gt of the first transistor T1 and the top gate T4gt of the fourth transistor T4 are located on the same side of the top gate T3gt of the third transistor T3.

[0388] In the exemplary embodiments, after the third conductive layer pattern is formed, the semiconductor layer can be subjected to a conductorization process using the third conductive layer as a shield, the semiconductor layer in the region shielded by the third conductive layer forms the channel region of the first transistor T1 to the sixth transistor T6, and the semiconductor layer in the region not shielded by the third conductive layer is conductorized, i.e., the first region and the second region of the active layer AT1 of the first transistor T1 to the active layer AT6 of the sixth transistor T6 are conductorized.

[0389] (206) The fourth insulating layer pattern is formed. In the exemplary embodiments, forming the fourth insulating layer pattern can include: depositing a fourth insulating thin film on the substrate on which the aforementioned patterns are formed, and patterning the fourth insulating thin film to form the fourth insulating layer covering the third conductive layer, the fourth insulating layer being provided with a plurality of vias, as shown in FIG. 47, which is a planar structure diagram of the three sub-pixels after the fourth insulating layer is formed.

[0390] In the exemplary embodiments, the plurality of vias in at least part of the sub-pixels at least include: a first via V1, a second via V2, a third via V3, a fourth via V4, a fifth via V5, a sixth via V6, a seventh via V7, an eighth via V8, a ninth via V9, a tenth via V10, an eleventh via V11, a twelfth via V12, a thirteenth via V13, a fourteenth via V14, a fifteenth via V15, a sixteenth via V16, a seventeenth via V17, an eighteenth via V18, and a nineteenth via V19.

[0391] In the exemplary embodiments, the orthographic projection of the first via V1 on the substrate is located within the orthographic projection of the active layer AT1 of the first transistor T1 on the substrate, the fourth insulating layer and the third insulating layer in the first via V1 are etched away, and the surface of the first region AT11 of the active layer AT1 of the first transistor T1 is exposed. The first via V1 is configured to enable the first electrode of the first transistor T1 formed subsequently to be connected to the active layer AT1 of the first transistor T1 through the via.

[0392] In the exemplary embodiments, the orthographic projection of the second via V2 on the substrate is located within the orthographic projection of the active layer AT1 of the first transistor T1 on the substrate, the fourth insulating layer, the third insulating layer, and the second region AT12 of the active layer AT1 of the first transistor T1 in the second via V2 are etched away, and the surface of the second region AT12 of the active layer AT1 of the first transistor T1 is exposed. The second via V2 is configured to enable the second electrode of the first transistor T1 formed subsequently to be connected to the active layer AT1 of the first transistor T1 through the via.

[0393] In an example embodiment, the third via V3 has a footprint on the substrate within a footprint of the active layer AT2 of the second transistor T2 on the substrate, the fourth insulating layer and the third insulating layer within the third via V3 are etched away, exposing a surface of the second region AT22 of the active layer AT2 of the second transistor T2. The third via V3 is configured to enable a first electrode of the second transistor T2 formed subsequently to be connected to the active layer AT2 of the second transistor T2 through the via.

[0394] In an example embodiment, the fourth via V4 has a footprint on the substrate within a footprint of the active layer AT2 of the second transistor T2 (also a second region AT62 of the active layer AT6 of the sixth transistor T6) on the substrate, the fourth insulating layer and the third insulating layer within the fourth via V4 are etched away, exposing a surface of the second region AT22 of the active layer AT2 of the second transistor T2 (also the second region AT62 of the active layer AT6 of the sixth transistor T6). The fourth via V4 is configured to enable a second electrode of the second transistor T2 formed subsequently to be connected to the active layer AT2 of the second transistor T2 through the via, and to enable a second electrode of the sixth transistor T6 formed subsequently to be connected to the active layer AT6 of the sixth transistor T6 through the via.

[0395] In an example embodiment, the fifth via V5 has a footprint on the substrate within a footprint of the active layer AT3 of the third transistor T3 on the substrate, the fourth insulating layer and the third insulating layer within the fifth via V5 are etched away, exposing a surface of the second region AT32 of the active layer AT3 of the third transistor T3 (also a first region AT61 of the active layer AT6 of the sixth transistor T6). The fifth via V5 is configured to enable a second electrode of the third transistor T3 formed subsequently to be connected to the active layer AT3 of the third transistor T3 through the via, and to enable a first electrode of the sixth transistor T6 formed subsequently to be connected to the active layer AT6 of the sixth transistor T6 through the via.

[0396] In an example embodiment, the sixth via V6 has a footprint on the substrate within a footprint of the active layer AT4 of the fourth transistor T4 on the substrate, the fourth insulating layer and the third insulating layer within the sixth via V6 are etched away, exposing the first region AT41 of the active layer AT4 of the fourth transistor T4. The sixth via V6 is configured to enable a first electrode of the fourth transistor T4 formed subsequently to be connected to the active layer AT4 of the fourth transistor T4 through the via.

[0397] In the exemplary embodiment, the seventh via V7 is located within the footprint of the active layer AT4 of the fourth transistor T4 on the substrate, and the fourth insulating layer and the third insulating layer within the seventh via V7 are etched away to expose the second region AT42 of the active layer AT4 of the fourth transistor T4. The seventh via V7 is configured to enable the second electrode of the fourth transistor T4 formed subsequently to be connected to the active layer AT4 of the fourth transistor T4 through the via.

[0398] In the exemplary embodiment, the eighth via V8 is located within the footprint of the active layer AT5 of the fifth transistor T5 on the substrate, and the fourth insulating layer and the third insulating layer within the eighth via V8 are etched away to expose the surface of the first region AT51 of the active layer AT5 of the fifth transistor T5. The eighth via V8 is configured to enable the first electrode of the fifth transistor T5 formed subsequently to be connected to the active layer AT5 of the fifth transistor T5 through the via.

[0399] In the exemplary embodiment, the ninth via V9 is located within the footprint of the bottom gate T1gb of the first transistor T1 on the substrate, and the fourth insulating layer, the third insulating layer, and the second insulating layer within the ninth via V9 are etched away to expose the surface of the bottom gate T1gb of the first transistor T1. The ninth via V9 is configured to enable the first reset control line Reset1 formed subsequently to be connected to the bottom gate T1gb of the first transistor T1 through the via.

[0400] In the exemplary embodiment, the tenth via V10 is located within the footprint of the bottom gate T2gb of the second transistor T2 on the substrate, and the fourth insulating layer, the third insulating layer, and the second insulating layer within the tenth via V10 are etched away to expose the surface of the bottom gate T2gb of the second transistor T2. The tenth via V10 is configured to enable the second reset control line Reset2 formed subsequently to be connected to the bottom gate T2gb of the second transistor T2 through the via.

[0401] In the exemplary embodiment, the eleventh via V11 is located within the footprint of the bottom gate T4gb of the fourth transistor T4 on the substrate, and the fourth insulating layer, the third insulating layer, and the second insulating layer within the eleventh via V11 are etched away to expose the surface of the bottom gate T4gb of the fourth transistor T4. The eleventh via V11 is configured to enable the first electrode of the fourth transistor T4 formed subsequently to be connected to the bottom gate T4gb of the fourth transistor T4 through the via.

[0402] In the example embodiment, the orthogonal projection of the twelfth via V12 on the substrate is located within the range of the orthogonal projection of the first plate C11 of the first capacitor C1 on the substrate (the orthogonal projection of the twelfth via V12 on the substrate can be located within the range of the orthogonal projection of the first connecting portion CL1 on the substrate), the fourth insulating layer, the third insulating layer, the second insulating layer and the first insulating layer within the twelfth via V12 are etched away, and the surface of the first plate C11 of the first capacitor C1 is exposed. The twelfth via V12 is configured to enable the second electrode of the first transistor T1 (also the second electrode of the fourth transistor T4) formed subsequently to be connected to the first plate C11 of the first capacitor C1 through the via.

[0403] In the example embodiment, the orthogonal projection of the thirteenth via V13 on the substrate is located within the range of the orthogonal projection of the first plate C21 of the second capacitor C2 on the substrate (the orthogonal projection of the thirteenth via V13 on the substrate can be located within the range of the orthogonal projection of the second connecting portion CL2 on the substrate), the fourth insulating layer, the third insulating layer, the second insulating layer and the first insulating layer within the thirteenth via V13 are etched away, and the surface of the first plate C21 of the second capacitor C2 is exposed. The thirteenth via V13 is configured to enable the first power supply connecting line VDDL formed subsequently to be connected to the first plate C21 of the second capacitor C2 through the via.

[0404] In the example embodiment, the orthogonal projection of the fourteenth via V14 on the substrate is located within the range of the orthogonal projection of the second plate C22 of the second capacitor C2 on the substrate (the orthogonal projection of the fourteenth via V14 on the substrate can be located within the range of the orthogonal projection of the third connecting portion CL3 on the substrate), the fourth insulating layer, the third insulating layer and the second insulating layer within the fourteenth via V14 are etched away, and the surface of the second plate C22 of the second capacitor C2 is exposed. The fourteenth via V14 is configured to enable the second electrode of the third transistor T3 (also the first electrode of the sixth transistor T6) formed subsequently to be connected to the second plate C22 of the second capacitor C2 through the via.

[0405] In the example embodiment, the orthogonal projection of the fifteenth via V15 on the substrate is located within the range of the orthogonal projection of the second plate C12 of the first capacitor C1 on the substrate, the fourth insulating layer, the third insulating layer and the second insulating layer within the fifteenth via V15 are etched away, and the surface of the second plate C12 of the first capacitor C1 is exposed. The fifteenth via V15 is configured to enable the second electrode of the third transistor T3 (also the first electrode of the sixth transistor T6) formed subsequently to be connected to the second plate C12 of the first capacitor C1 through the via.

[0406] In the exemplary embodiment, the normal projection of the sixteenth via V16 on the substrate is located within the normal projection of the top gate T1gt of the first transistor T1 on the substrate, the fourth insulating layer within the sixteenth via V16 is etched away, exposing the surface of the top gate T1gt of the first transistor T1. The sixteenth via V16 is configured to enable the first reset control line Reset1 formed subsequently to connect with the top gate T1gt of the first transistor T1 through the via.

[0407] In the exemplary embodiment, the normal projection of the seventeenth via V17 on the substrate is located within the normal projection of the top gate T2gt of the second transistor T2 on the substrate, the fourth insulating layer within the seventeenth via V17 is etched away, exposing the surface of the top gate T2gt of the second transistor T2. The seventeenth via V17 is configured to enable the second reset control line Reset2 formed subsequently to connect with the top gate T2gt of the second transistor T2 through the via.

[0408] In the exemplary embodiment, the normal projection of the eighteenth via V18 on the substrate is located within the normal projection of the top gate T3gt of the third transistor T3 on the substrate, the fourth insulating layer within the eighteenth via V18 is etched away, exposing the surface of the top gate T3gt of the third transistor T3. The eighteenth via V18 is configured to enable the second electrode of the first transistor T1 (also the second electrode of the fourth transistor T4) formed subsequently to connect with the top gate T3gt of the third transistor T3 through the via.

[0409] In the exemplary embodiment, the normal projection of the nineteenth via V19 on the substrate is located within the normal projection of the top gate T4gt of the fourth transistor T4 on the substrate, the fourth insulating layer within the nineteenth via V19 is etched away, exposing the surface of the top gate T4gt of the fourth transistor T4. The nineteenth via V19 is configured to enable the scan signal line Gate formed subsequently to connect with the top gate T4gt of the fourth transistor T4 through the via.

[0410] (207) Forming a fourth conductive layer pattern. In the exemplary embodiment, forming the fourth conductive layer can include: on the substrate on which the aforementioned pattern is formed, depositing a fourth conductive thin film, and patterning the fourth conductive thin film by using a patterning process, to form a fourth conductive layer disposed on the fourth insulating layer, as shown in FIGS. 38a and 38b, FIG. 38a is a planar structure diagram of three sub-pixels after forming the fourth conductive layer, and FIG. 38b is a planar schematic diagram of the fourth conductive layer in FIG. 38a. In the exemplary embodiment, the fourth conductive layer can be referred to as a first source-drain metal (SD1) layer.

[0411] In the example embodiment, the fourth conductive layer at least includes: a first power connection line VDDL, a scanning signal line Gate, a second power connection line VSSL, a first reset control line Reset1, a first initial signal line Vinit1, a second reset control line Reset2, a second initial signal line Vinit2, a first connection electrode L1, a second connection electrode L2, a third connection electrode L3, and a fourth connection electrode L4.

[0412] In the example embodiment, the main body part of the first power connection line VDDL, the scanning signal line Gate, the second power connection line VSSL, the first reset control line Reset1, the first initial signal line Vinit1, the second reset control line Reset2, and the second initial signal line Vinit2 can be a strip-shaped structure or a broken line-shaped structure extending along the first direction X, and the first power connection line VDDL, the scanning signal line Gate, the second power connection line VSSL, the first reset control line Reset1, the first initial signal line Vinit1, the second reset control line Reset2, and the second initial signal line Vinit2 can be arranged in sequence along the opposite direction of the second direction Y.

[0413] In the example embodiment, in the same sub-pixel, along the second direction Y, the first connection electrode L1 is located between the first power connection line VDDL and the scanning signal line Gate, the second connection electrode L2 and the third connection electrode L3 are located between the scanning signal line Gate and the second power connection line VSSL, and the fourth connection electrode L4 is located between the first reset control line Reset1 and the first initial signal line Vinit1.

[0414] In the example embodiment, the first power connection line VDDL can be connected to the first area AT51 of the active layer AT5 of the fifth transistor T5 in the row of sub-pixels through the eighth via V8 in the row of sub-pixels, and connected to the first plate C21 of the second capacitor C2 in the row of sub-pixels through the thirteenth via V13 in the row of sub-pixels. In the example embodiment, the first power connection line VDDL can be set as the first electrode of the fifth transistor T5 to provide the first power voltage to the plurality of fifth transistors T5 and the first plate C21 of the second capacitor C2 in the same sub-pixel. In the same sub-pixel, the first area AT51 of the active layer AT5 of the fifth transistor T5 and the second plate C22 of the second capacitor C2 can be electrically connected through the first power connection line VDDL, so that the first area AT51 of the active layer AT5 of the fifth transistor T5 and the first plate C21 of the second capacitor C2 in the same sub-pixel have the same potential.

[0415] In an example embodiment, the scan signal line Gate can be connected with the top gate T4gt of the fourth transistor T4 in a row of sub-pixels through the nineteenth via V19 in the row of sub-pixels, and connected with the bottom gate T4gb of the fourth transistor T4 in the row of sub-pixels through the eleventh via V11 in the row of sub-pixels, and be configured to provide the scan signal to the top gate T4gt and the bottom gate T4gb of the plurality of fourth transistors T4 in the row of sub-pixels. In the same sub-pixel, the top gate T4gt and the bottom gate T4gb of the fourth transistor T4 can be electrically connected through the scan signal line Gate, so that the top gate T4gt and the bottom gate T4gb of the fourth transistor T4 in the same sub-pixel have the same potential.

[0416] In an example embodiment, the second power supply connection line VSSL can be connected with a plurality of second power supply lines formed subsequently, at least part of the second power supply connection line VSSL is electrically connected with the plurality of second power supply lines, at least part of the second power supply lines is electrically connected with the plurality of second power supply connection lines VSSL, at least part of the second power supply connection lines VSSL and at least part of the second power supply lines are connected to form a grid structure, which can reduce the voltage drop of the second power supply lines and improve the display uniformity of the display substrate.

[0417] In an example embodiment, the first reset control line Reset1 can be connected with the top gate T1gt of the first transistor T1 in a row of sub-pixels through the sixteenth via V16 in the row of sub-pixels, and connected with the bottom gate T1gb of the first transistor T1 in the row of sub-pixels through the ninth via V9 in the row of sub-pixels, and be configured to provide the first reset control signal to the top gate T1gt and the bottom gate T1gb of the plurality of first transistors T1 in the row of sub-pixels. In the same sub-pixel, the top gate T1gt and the bottom gate T1gb of the first transistor T1 can be electrically connected through the second reset control line Reset2, so that the top gate T1gt and the bottom gate T1gb of the first transistor T1 in the same sub-pixel have the same potential.

[0418] In an example embodiment, the first initial signal line Vinit1 can be connected with the first region AT11 of the active layer AT1 of the first transistor T1 in a row of sub-pixels through the first via V1 in the row of sub-pixels, and be configured to provide the first initial signal to the first transistor T1 in the row of sub-pixels. In an example embodiment, the first initial signal line Vinit1 can serve as the first electrode of the first transistor T1.

[0419] In the example embodiment, the second reset control line Reset2 can be connected with the top gate T2gt of the second transistor T2 in a row of sub-pixels through the seventeenth via V17 in the row of sub-pixels, and with the bottom gate T2gb of the second transistor T2 in the row of sub-pixels through the tenth via V10 in the row of sub-pixels, and be configured to provide the second reset control signal to the top gate T2gt and the bottom gate T2gb of the second transistor T2 in the row of sub-pixels. In the same sub-pixel, the top gate T2gt and the bottom gate T2gb of the second transistor T2 can be electrically connected through the second reset control line Reset2, so that the top gate T2gt and the bottom gate T2gb of the second transistor T2 in the same sub-pixel have the same electric potential.

[0420] In the example embodiment, the second initial signal line Vinit2 can be connected with the first region AT21 of the active layer AT2 of the second transistor T2 in a row of sub-pixels through the third via V3 in the row of sub-pixels, and be configured to provide the second initial signal to the second transistor T2 in the row of sub-pixels. In the example embodiment, the second initial signal line Vinit2 can be configured as the first pole of the second transistor T2.

[0421] In the example embodiment, the first connection electrode L1 is connected with the first region AT41 of the active layer AT4 of the fourth transistor T4 through the sixth via V6. In the example embodiment, the first connection electrode L1 can be configured as the first pole of the fourth transistor T4, and be connected with the data signal line formed subsequently.

[0422] In the example embodiment, the second connection electrode L2 has a shape of approximately "L" character, and is connected with the second region AT12 of the active layer AT1 of the first transistor T1 through the second via V2, with the first plate C11 of the first capacitor C1 through the twelfth via V12, with the second region AT42 of the active layer AT4 of the fourth transistor T4 through the seventh via V7, and with the top gate T3gt of the third transistor T3 through the eighteenth via V18. The second region AT12 of the active layer AT1 of the first transistor T1, the first plate C11 of the first capacitor C1, the second region AT42 of the active layer AT4 of the fourth transistor T4, and the top gate T3gt of the third transistor T3 can be electrically connected through the second connection electrode L2, so that the second pole of the first transistor T1, the first plate C11 of the first capacitor C1, the second pole of the fourth transistor T4, and the top gate T4gt of the third transistor T3 in the same sub-pixel have the same electric potential. In the example embodiment, the second connection electrode L2 can be configured as the second pole of the first transistor T1 and the second pole of the fourth transistor T4.

[0423] In the exemplary embodiment, the third connection electrode L3 is substantially in the shape of an "L" character, the third connection electrode L3 is connected with the second region AT32 of the active layer AT3 of the third transistor T3 (also the first region AT61 of the active layer AT6 of the sixth transistor T6) through the fifth via V5, connected with the second plate C22 of the second capacitor C2 through the fourteenth via V14, connected with the second plate C12 of the first capacitor C1 through the fifteenth via V15, the second region AT32 of the active layer AT3 of the third transistor T3 (also the first region AT61 of the active layer AT6 of the sixth transistor T6), the second plate C12 of the first capacitor C1, and the second plate C22 of the second capacitor C2 can be connected through the third connection electrode L3, so that the second region AT32 of the active layer AT3 of the third transistor T3 (also the first region AT61 of the active layer AT6 of the sixth transistor T6), the second plate C12 of the first capacitor C1, and the second plate C22 of the second capacitor C2 in the same sub-pixel have the same potential. In the exemplary embodiment, the third connection electrode L3 can serve as the second electrode of the third transistor T3 and the first electrode of the sixth transistor T6.

[0424] In the exemplary embodiment, the fourth connection electrode L4 is connected with the second region AT62 of the active layer AT6 of the sixth transistor T6 (also the second region AT22 of the active layer AT2 of the second transistor T2) through the fourth via V4. In the exemplary embodiment, the fourth connection electrode L4 can serve as the second electrode of the sixth transistor T6 and the second electrode of the second transistor T2, and the fourth connection electrode L4 is configured to be connected with the anode connection electrode of the light-emitting element formed subsequently.

[0425] (208) Forming the fifth insulating layer and the first planar layer pattern. In the exemplary embodiment, forming the fifth insulating layer and the first planar layer pattern can include: on the substrate on which the aforementioned patterns are formed, first depositing a fifth insulating thin film, then coating a first planar thin film, patterning the first planar thin film and the fifth insulating thin film by using a patterning process, forming the fifth insulating layer covering the fourth conductive layer pattern and the first planar layer disposed on the fifth insulating layer, and the fifth insulating layer and the first planar layer are provided with a plurality of vias, as shown in FIG. 39, which is a planar structure diagram of three sub-pixels after the first planar layer is formed.

[0426] In the exemplary embodiment, the plurality of vias in each sub-pixel can at least include: the twentieth via V20, the twenty-first via V21, the twenty-second via V22, the twenty-third via V23, the twenty-fourth via V24, and the twenty-fifth via V25.

[0427] In an exemplary embodiment, the second twenty via V20 is located within the range of the orthogonal projection of the fourth connection electrode L4 on the substrate, the first planar layer and the fifth insulating layer within the second twenty via V20 are etched away, exposing the surface of the fourth connection electrode L4. The second twenty via V20 is configured to allow the anode connection electrode of the light emitting element formed subsequently to be electrically connected to the fourth connection electrode L4 through the via.

[0428] In an exemplary embodiment, the twenty first via V21 is located within the range of the orthogonal projection of the first power supply connection line VDDL on the substrate, the first planar layer and the fifth insulating layer within the twenty first via V21 are etched away, exposing the surface of the first power supply connection line VDDL. The twenty first via V21 is configured to allow the first power supply line formed subsequently to be connected to the first power supply connection line VDDL through the via. In an exemplary embodiment, at least part of the first power supply line and at least part of the first power supply connection line VDDL are connected to each other to form a mesh structure, reducing the voltage drop of the first power supply connection line VDDL and improving display uniformity.

[0429] In an exemplary embodiment, the twenty second via V22 is located within the range of the orthogonal projection of the first connection electrode L1 on the substrate, the first planar layer and the fifth insulating layer within the twenty second via V22 are etched away, exposing the surface of the first connection electrode L1. The twenty second via V22 is configured to allow the data signal line formed subsequently to be electrically connected to the first connection electrode L1 through the via.

[0430] In an exemplary embodiment, the twenty third via V23 is located within the range of the orthogonal projection of the first initial signal line Vinit1 on the substrate, the first planar layer and the fifth insulating layer within the twenty third via V23 are etched away, exposing the surface of the first initial signal line Vinit1. The twenty third via V23 is configured to allow the first initial signal connection line formed subsequently to be connected to the first initial signal line Vinit1 through the via.

[0431] In an exemplary embodiment, the twenty fourth via V24 is located within the range of the orthogonal projection of the second initial signal line Vinit2 on the substrate, the first planar layer and the fifth insulating layer within the twenty fourth via V24 are etched away, exposing the surface of the second initial signal line Vinit2. The twenty fourth via V24 is configured to allow the second initial signal connection line formed subsequently to be electrically connected to the second initial signal line Vinit2 through the via.

[0432] In the exemplary embodiment, the orthogonal projection of the twenty-fifth via V25 on the substrate is within the range of the orthogonal projection of the second power connection line VSSL on the substrate, the first planar layer and the fifth insulating layer in the twenty-fifth via V25 are etched away, and the surface of the second power connection line VSSL is exposed. The twenty-fifth via V25 is configured to enable the second power line formed subsequently to pass through the via and be connected with the second power connection line VSSL. In the exemplary embodiment, at least part of the second power connection line VSSL and at least part of the second power line are connected with each other to form a mesh structure, thereby reducing the voltage drop of the second power connection line VSSL and improving display uniformity.

[0433] (209) Forming a fifth conductive layer pattern. In the exemplary embodiment, forming the fifth conductive layer can include: on the substrate on which the aforementioned patterns are formed, depositing a fifth conductive thin film, and patterning the fifth conductive thin film by using a patterning process to form a fifth conductive layer disposed on the first planar layer, as shown in FIGS. 40a and 40b, FIG. 40a is a plan view of three sub-pixels after the fifth conductive layer is formed, and FIG. 40b is a plan view of the fifth conductive layer in FIG. 40a. In the exemplary embodiment, the fifth conductive layer can be referred to as a second source-drain metal (SD2) layer.

[0434] In the exemplary embodiment, the fifth conductive layer at least includes: a data signal line D, a first power line VDD, a second power line VSS, a first initial signal connection line Vinit1L, an anode connection electrode ZL, and a second initial signal connection line Vinit2L.

[0435] In the exemplary embodiment, the data signal line D is a polyline extending along the second direction Y, and the data signal line D is connected with the first connection electrode L1 through the twenty-second via V22. Since the first connection electrode L1 is connected with the first area AT41 of the active layer AT4 of the fourth transistor T4 through the via, the connection between the data signal line D and the first electrode of the fourth transistor T4 is achieved, and the data signal is written into the fourth transistor T4.

[0436] In the example embodiment, the first power supply line VDD is in the shape of a broken line extending along the second direction Y, and the first power supply line VDD is connected to the first power supply connection line VDDL through the twenty-first via V21. Since the first power supply connection line VDDL is connected to the first area AT51 of the active layer AT5 of the fifth transistor T5 and the first plate C21 of the second capacitor C2 through the via, the first power supply line VDD is connected to the fifth transistor T5 and the first plate C21 of the second capacitor C2, and the power supply signal is written to the first electrode of the fifth transistor T5 and the first plate C21 of the second capacitor C2. In the example embodiment, at least part of the first power supply connection line VDDL is electrically connected to a plurality of first power supply lines VDD, at least part of the first power supply line VDD is electrically connected to a plurality of first power supply connection lines VDDL, and at least part of the first power supply line is connected to at least part of the first power supply connection line VDDL to form a grid structure, which can reduce the voltage drop of the first power supply line VDD, so that the first power supply signals received by a plurality of sub-pixels in the display substrate are substantially consistent, and the display uniformity of the display substrate is improved. For example, each first power supply connection line VDDL is electrically connected to a plurality of first power supply lines VDD in a plurality of pixel driving circuits, each first power supply line VDD is electrically connected to a plurality of first power supply connection lines VDDL, and a plurality of first power supply lines are connected to a plurality of first power supply connection lines VDDL to form a grid structure.

[0437] In the example embodiment, the shape of the anode connection electrode ZL can be an "I" shape or a strip structure, and the anode connection electrode ZL is connected to the fourth connection electrode L4 through the twentieth via V20. Since the fourth connection electrode L4 is connected to the second area AT62 of the active layer AT6 of the sixth transistor T6 (also the second area AT22 of the active layer AT2 of the second transistor T2) through the via, the anode connection electrode ZL is connected to the second electrode of the sixth transistor T6 and the second electrode of the second transistor T2.

[0438] In the example embodiment, the first initial signal connection line Vinit1L is in the shape of a broken line extending along the second direction Y, the first initial signal connection line Vinit1L is connected to the first initial signal connection line Vinit1 through the twenty-third via V23, and a plurality of first initial signal connection lines Vinit1L are connected to a plurality of first initial signal connection lines Vinit1 to form a grid structure, so that the first initial signals received by the first transistors T1 in adjacent sub-pixels are substantially consistent, which is beneficial to improve the uniformity of the panel display, avoid display defects of the display substrate, and ensure the display effect of the display substrate.

[0439] In the example embodiment, the second initial signal connection line Vinit2L is a broken line extending along the second direction Y, the second initial signal connection line Vinit2L is connected with the second initial signal line Vinit2 through the twenty-fourth via V24, the plurality of second initial signal connection lines Vinit2L and the plurality of second initial signal lines Vinit2 are connected to form a grid structure, so that the second initial signals received by adjacent second transistors T2 are substantially consistent, which is conducive to improving the uniformity of the panel display, avoiding display defects of the display substrate, and ensuring the display effect of the display substrate.

[0440] In the example embodiment, the second power line VSS is a broken line extending along the second direction, the second power line VSS can be connected with the second power connection line VSSL through the twenty-fifth via V25, at least part of the second power connection line VSSL is electrically connected with the plurality of second power lines VSS, at least part of the second power line VSS is electrically connected with the plurality of second power connection lines VSSL located in the plurality of pixel driving circuits, and at least part of the second power connection line VSSL and at least part of the second power line VSS are connected to form a grid structure, which can reduce the voltage drop of the second power line VSS and improve the display uniformity of the display substrate; for example, each second power connection line VSSL is electrically connected with the plurality of second power lines VSS, each second power line VSS is electrically connected with the plurality of second power connection lines VSSL located in the plurality of pixel driving circuits, and the plurality of second power connection lines VSSL and the plurality of second power lines VSS are connected to form a grid structure. In the example embodiment, the display substrate can include a display area and a frame area located at the periphery of the display area, the display area can be provided with a plurality of sub-pixels, and the frame area can be provided with a second power signal line, in the first direction X, the second power connection line VSSL can be electrically connected with the second power signal line of the frame area located on both sides of the display area; in the second direction Y, the second power line VSS can be electrically connected with the second power signal line of the frame area located on both sides of the display area.

[0441] In an example embodiment, in the same pixel unit, the first power supply line VDD, the first initial signal connection line Vinit1L and the second initial signal connection line Vinit2L can be arranged in the first direction X in sequence, and are respectively arranged in the three sub-pixels of the pixel unit, for example, the first power supply line VDD is located in the first sub-pixel, the first initial signal connection line Vinit1L is located in the second sub-pixel, and the second initial signal connection line Vinit2L is located in the third sub-pixel. Each sub-pixel is provided with a second power supply line VSS and a data signal line D. In the first direction X, the data signal line D and the second power supply line VSS of the first sub-pixel are located on both sides of the first power supply line VDD, the data signal line D and the second power supply line VSS of the second sub-pixel are located on both sides of the first initial signal connection line Vinit1L, and the data signal line D and the second power supply line VSS of the third sub-pixel are located on both sides of the second initial signal connection line Vinit2L. The anode connection electrode ZL in the first sub-pixel is located between the first power supply line VDD and the second power supply line VSS, the anode connection electrode ZL in the second sub-pixel is located between the first initial signal connection line Vinit1L and the second power supply line VSS, and the anode connection electrode ZL in the third sub-pixel is located between the second initial signal connection line Vinit2L and the second power supply line VSS.

[0442] So far, the driving circuit layer has been prepared on the substrate, and the driving circuit layer is provided with the pixel driving circuit of the plurality of sub-pixels. FIGS. 33 to 40b show the planar structure schematic diagram of the pixel driving circuit of the sub-pixel in the display substrate. In an example embodiment, in the direction perpendicular to the plane of the display substrate, the driving circuit layer can include a first conductive layer, a second conductive layer, a semiconductor layer, a third conductive layer, a fourth conductive layer, and a fifth conductive layer arranged in sequence on the substrate.

[0443] In an example embodiment, in the direction perpendicular to the plane of the display substrate, the driving circuit layer can include a first insulating layer, a second insulating layer, a third insulating layer, a fourth insulating layer, a fifth insulating layer, and a first planar layer. The first insulating layer is arranged between the first conductive layer and the second conductive layer, the second insulating layer is arranged between the second conductive layer and the semiconductor layer, the third insulating layer is arranged between the semiconductor layer and the third conductive layer, the fourth insulating layer is arranged between the third conductive layer and the fourth conductive layer, and the fifth insulating layer and the first planar layer are arranged between the fourth conductive layer and the fifth conductive layer.

[0444] In the example embodiment, after the driving circuit layer is prepared, the light emitting structure layer is prepared on the driving circuit layer, and the preparation process of the light emitting structure layer can include the following operations. The second planar layer pattern is formed, and the second planar layer is provided with at least an anode via hole. The anode pattern (i.e., the anode conductive layer) is formed, and the anode is connected to the anode connecting electrode through the anode via hole. The anode pixel definition layer is formed, and the pixel definition layer is provided with a pixel opening, and the pixel opening exposes the anode. The organic light emitting layer is formed by using the evaporation or inkjet printing process, and the cathode is formed on the organic light emitting layer. The encapsulation layer is formed, and the encapsulation layer can include the first encapsulation layer, the second encapsulation layer, and the third encapsulation layer which are stacked, the first encapsulation layer and the third encapsulation layer can be made of inorganic material, the second encapsulation layer can be made of organic material, and the second encapsulation layer is arranged between the first encapsulation layer and the third encapsulation layer, which can ensure that the external water vapor cannot enter the light emitting structure layer. The step of forming the anode conductive layer is as follows:

[0445] (210) The second planar layer pattern is formed. In the example embodiment, forming the second planar layer pattern can include: on the substrate on which the aforementioned patterns are formed, coating a second planar film, and patterning the second planar film by using a patterning process to form a second planar layer covering the fifth conductive layer pattern, and the second planar layer is provided with a plurality of via holes, as shown in FIG. 15, and FIG. 41 is a planar structure diagram of three sub-pixels after the second planar layer is formed.

[0446] In the example embodiment, the plurality of via holes can at least include the twenty-sixth via hole V26.

[0447] In the example embodiment, the via hole of each sub-pixel at least includes the twenty-sixth via hole V26. The orthogonal projection of the twenty-sixth via hole V26 on the substrate is within the range of the orthogonal projection of the anode connecting electrode ZL on the substrate, the second planar layer in the twenty-sixth via hole V26 is removed to expose the surface of the anode connecting electrode ZL, and the twenty-sixth via hole V26 is configured to electrically connect the subsequently formed anode and the anode connecting electrode ZL through the via hole.

[0448] (211) The anode conductive layer pattern is formed. In the example embodiment, forming the anode conductive layer pattern can include: on the substrate on which the aforementioned patterns are formed, depositing an anode conductive film, and patterning the anode conductive film by using a patterning process to form the anode conductive layer pattern arranged on the second planar layer, as shown in FIGS. 42a and 42b, FIG. 42a is a planar structure diagram of three sub-pixels after the anode conductive layer is formed, and FIG. 42b is a planar diagram of the anode conductive layer in FIG. 42a.

[0449] In an exemplary embodiment, the anode conductive layer pattern can at least include a plurality of anodes AN, which can include a first anode AN1, a second anode AN2, and a third anode AN3. The region where the first anode AN1 is located can form a red light emitting unit that emits red light. The region where the second anode AN2 is located can form a green light emitting unit that emits green light. The region where the third anode AN3 is located can form a blue light emitting unit that emits blue light.

[0450] In an exemplary embodiment, the first anode AN1, the second anode AN2, and the third anode AN3 can be connected to the anode connection electrode ZL in the corresponding sub-pixel through the twenty-sixth via V26, respectively. Since the anode connection electrode ZL in the sub-pixel is electrically connected to the second electrode of the sixth transistor T6 (also the second electrode of the second transistor T2) through the via, the first anode AN1, the second anode AN2, and the third anode AN3 can be connected to the second electrode of the sixth transistor T6 and the second electrode of the second transistor T2 through the anode connection electrode ZL, respectively, so as to realize the driving of the light emitting device by the pixel driving circuit.

[0451] In an exemplary embodiment, the anode AN can include an anode main body AN01 and an anode connection part AN02. The anode main body AN01 can have a rectangular structure. One end of the anode connection part AN02 is connected to the anode main body AN01, and the other end is electrically connected to the anode connection electrode ZL through the twenty-sixth via V26. The anode connection part AN02 can have a strip structure or a block structure extending along the first direction X or the second direction Y. The anode connection part AN02 can be arranged to compensate for the difference in parasitic capacitance between the plurality of sub-pixels due to signal wiring. By arranging the anode connection part AN02, the parasitic capacitances of the plurality of sub-pixels can be kept substantially consistent, thereby improving the display uniformity of the display substrate.

[0452] (212) Forming a pixel definition layer pattern. In an exemplary embodiment, forming a pixel definition layer pattern can include: depositing a pixel definition layer film on the substrate on which the aforementioned pattern is formed, patterning the pixel definition layer by using a patterning process, and forming a pixel definition layer pattern arranged on the anode conductive layer. As shown in FIGS. 43a and 43b, FIG. 43a is a schematic diagram of the planar structure of three sub-pixels after forming a pixel definition layer, and FIG. 43b is a schematic diagram of the planar structure of the pixel definition layer in FIG. 43a.

[0453] In an example embodiment, the pixel definition layer pattern can include a plurality of pixel openings K0, the pixel openings K0 expose the anode AN. In an example embodiment, the orthographic projection of the pixel openings K0 on the substrate is within the range of the orthographic projection of the anode AN on the substrate. In an example embodiment, the pixel openings K0 can include a pixel opening K01 of the first sub-pixel, a pixel opening K02 of the second sub-pixel, and a pixel opening K03 of the third sub-pixel, the orthographic projection of the pixel opening K01 of the first sub-pixel on the substrate has an overlapping area with the orthographic projection of the first anode AN1 on the substrate; the orthographic projection of the pixel opening K02 of the second sub-pixel on the substrate has an overlapping area with the orthographic projection of the second anode AN2 on the substrate; the orthographic projection of the pixel opening K03 of the third sub-pixel on the substrate has an overlapping area with the orthographic projection of the third anode AN3 on the substrate.

[0454] In an example embodiment, the shielding layer, the first conductive layer, the second conductive layer, the third conductive layer, the fourth conductive layer, and the fifth conductive layer can be made of a metal material, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), and molybdenum (Mo), or an alloy material of the above-mentioned metals, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb), which can be a single-layer structure or a multi-layer composite structure, such as Mo / Cu / Mo, Ti / Al / Ti, etc. The first insulating layer, the second insulating layer, the third insulating layer, the fourth insulating layer, and the fifth insulating layer can be made of any one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON), which can be a single layer, multiple layers, or a composite layer.

[0455] In an example embodiment, taking the 3 sub-pixels (1 pixel driving circuit row of sub-pixels, 3 pixel driving circuit columns of sub-pixels, and pixel driving circuit using a 6T2C structure) in the display area (AA) as an example, another preparation process of the display substrate can include the steps (201) to (212) as described above, and the difference from the steps (201) to (212) is as follows:

[0456] The first conductive layer formed in the step (202) can be as shown in FIG. 44, and the first conductive layer shown in FIG. 44 is basically the same as the first conductive layer shown in FIG. 33.

[0457] The second conductive layer formed in the step (203) can be as shown in FIGS. 45a and 45b, FIG. 45a is a planar structure diagram of the three sub-pixels after the second conductive layer is formed, and FIG. 45b is a planar schematic diagram of the second conductive layer in FIG. 45a, and the second conductive layer shown in FIG. 45b is basically the same as the second conductive layer shown in FIG. 34b.

[0458] The third conductive layer formed in the step (205) can be as shown in FIGS. 46a and 46b. FIG. 46a is a plan view of three sub-pixels after the third conductive layer is formed, and FIG. 46b is a plan view of the third conductive layer in FIG. 46a. The third conductive layer shown in FIG. 46b is different from the third conductive layer shown in FIG. 35b in that the third conductive layer shown in FIG. 46b is not provided with the top gate T1gt of the first transistor T1 and the top gate T4gt of the fourth transistor T4.

[0459] The fourth insulating layer formed in the step (206) can be as shown in FIG. 47. The fourth insulating layer pattern shown in FIG. 47 is different from the fourth insulating layer pattern shown in FIG. 37 in that the fourth insulating layer pattern shown in FIG. 47 is not provided with the sixteenth via V16 and the nineteenth via V19, thereby reducing the number of vias and reducing the occurrence of via defects.

[0460] The fourth conductive layer formed in the step (207) can be as shown in FIGS. 48a and 48b. FIG. 48a is a plan view of three sub-pixels after the fourth conductive layer is formed, and FIG. 48b is a plan view of the fourth conductive layer in FIG. 48a. The fourth conductive layer pattern shown in FIG. 48b is different from the fourth conductive layer pattern shown in FIG. 38b in that the first reset control line Reset1 is not connected to the top gate T1gt of the first transistor T1, and the scan signal line Gate is not connected to the top gate T4gt of the fourth transistor T4. The plan view of the structure after the fifth insulating layer and the first planar layer, the fifth conductive layer, the second planar layer, the anode conductive layer, and the pixel definition layer are sequentially formed on the basis of FIG. 48a is shown in FIG. 49.

[0461] In the exemplary embodiments, the row and column of sub-pixels described in the embodiments of the present disclosure can be understood as the row and column of pixel driving circuits in the sub-pixels. The anode of a sub-pixel is connected to the pixel driving circuit in the corresponding sub-pixel, but the position of the anode of the sub-pixel does not necessarily correspond to the row and column of the pixel driving circuit connected thereto. For example, the orthogonal projection of the anode AN3 of the third sub-pixel on the substrate can overlap with the orthogonal projection of the pixel driving circuit of the first sub-pixel and the pixel driving circuit of the second sub-pixel on the substrate.

[0462] The foregoing structure and its preparation process shown in the embodiments of the present disclosure are merely exemplary descriptions. In the exemplary embodiments, the corresponding structure can be changed, and the patterning process can be increased or reduced according to actual needs. The display substrate shown in the embodiments of the present disclosure can be applied to other display devices with pixel driving circuits, such as quantum dot displays, which are not limited in the present disclosure.

[0463] The display device can be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, or the like.

[0464] The display substrate and the display device provided by the embodiments of the present disclosure can avoid screen flickering or uneven brightness to some extent, thereby improving the display effect.

[0465] The drawings of the embodiments of the present disclosure only relate to the structures involved in the embodiments of the present disclosure, and other structures can be referred to the general design.

[0466] In the case of no conflict, the features in the embodiments of the present disclosure can be combined with each other to obtain new embodiments.

[0467] Although the embodiments disclosed by the embodiments of the present disclosure are as above, the content is only the implementation adopted for the purpose of facilitating the understanding of the embodiments of the present disclosure, and is not intended to limit the embodiments of the present disclosure. Any person skilled in the art of the present disclosure can make any modification and change in the form and details without departing from the spirit and scope of the embodiments disclosed by the present disclosure. The patent protection scope of the embodiments of the present disclosure shall be subject to the scope defined by the appended claims.

Claims

1. A display substrate, comprising: A substrate and a plurality of sub-pixels arranged on one side of the substrate, at least one sub-pixel comprising a pixel driving circuit, at least one pixel driving circuit comprising a plurality of transistors, the transistors comprising an active layer and at least one gate electrode; In the same transistor, the at least one gate electrode at least partially overlaps the active layer, and the at least one gate electrode comprises at least one of a top gate and a bottom gate; in a direction perpendicular to the plane in which the substrate lies, the bottom gate is located on the side of the active layer close to the substrate, and the top gate is located on the side of the active layer away from the substrate; the plurality of transistors at least comprises a driving transistor, and the gate electrode in the driving transistor comprises a top gate and a bottom gate. 2.The display substrate of claim 1, wherein, The plurality of transistors further comprises a first light-emitting control transistor and a second light-emitting control transistor, and the first light-emitting control transistor and the second light-emitting control transistor each comprise a top gate; In the same pixel driving circuit, the second electrode of the first light-emitting control transistor is connected to the first electrode of the driving transistor, and the first electrode of the second light-emitting control transistor is connected to the second electrode of the driving transistor. 3.The display substrate of claim 2, wherein, The sub-pixel further comprises an anode, and the plurality of transistors further comprises an anode reset transistor, and the gate electrode of the anode reset transistor comprises a top gate; In the same sub-pixel, the second electrode of the anode reset transistor and the second electrode of the second light-emitting control transistor are connected to the anode; in a direction perpendicular to the plane in which the substrate lies, the anode is located on the side of the pixel driving circuit away from the substrate. 4.The display substrate of claim 3, wherein, The first light-emitting control transistor, the second light-emitting control transistor, and the anode reset transistor further comprise a bottom gate. 5.The display substrate according to claim 3 or 4, wherein, The plurality of transistors further comprises a data writing transistor and a first reset transistor, and the gate electrode of the data writing transistor and the first reset transistor comprises at least one of a top gate and a bottom gate; in the same sub-pixel, the second electrode of the data writing transistor and the second electrode of the first reset transistor are connected to the top gate of the driving transistor. 6.The display substrate of claim 3, wherein, The pixel driving circuit further comprises at least one capacitor; In a direction perpendicular to the plane in which the substrate lies, the capacitor comprises: a first plate located on one side of the substrate, and a second plate located on the side of the first plate away from the substrate; the bottom gate is arranged in the same layer as the second plate, and the active layer is located on the side of the second plate away from the substrate; the transistor further comprises: a first electrode and a second electrode located on the side of the top gate away from the substrate; in the same capacitor, the orthographic projection of the first plate on the substrate At least partially overlaps the orthographic projection of the second plate on the substrate. 7.The display substrate of claim 6, wherein, The pixel driving circuits of the plurality of sub-pixels form a plurality of rows, and the plurality of rows of pixel driving circuits are arranged in sequence in a column direction, and the plurality of pixel driving circuits in the same row are arranged in sequence in a row direction; in parallel to the plane in which the substrate lies, the row direction intersects the column direction. In the same pixel driving circuit, in the column direction, the first light-emitting control transistor is located on one side of the driving transistor and the at least one capacitor, the second light-emitting control transistor is located on the other side of the driving transistor and the at least one capacitor, and the anode reset transistor is located on the side of the second light-emitting control transistor away from the driving transistor and the at least one capacitor; the orthographic projection of the driving transistor on the substrate at least partially overlaps the orthographic projection of the at least one capacitor on the substrate. 8.The display substrate of claim 7, wherein, The plurality of transistors further comprises a first reset transistor and a data writing transistor; In the same pixel driving circuit, in the row direction, the first reset transistor and the data writing transistor are located on the same side of the driving transistor, and in the column direction, the data writing transistor and the first light-emitting control transistor are located on the same side of the driving transistor, and the first light-emitting control transistor is located on the side of the data writing transistor away from the driving transistor; the first reset transistor and the second light-emitting control transistor are located on the same side of the driving transistor, and the second light-emitting control transistor is located on the side of the first reset transistor away from the driving transistor; the second electrode of the first reset transistor and the second electrode of the data writing transistor are connected with the top gate of the driving transistor. 9.The display substrate of claim 8, wherein, The at least one capacitor comprises a first capacitor and a second capacitor, and in the same pixel driving circuit, the first plate of the first capacitor and the first plate of the second capacitor are connected with each other, the second plate of the first capacitor is connected with the second electrode of the driving transistor, the second plate of the second capacitor is connected with the top gate of the driving transistor, the orthographic projection of the driving transistor on the substrate at least partially overlaps the orthographic projection of the first capacitor on the substrate, and the second plate of the first capacitor serves as the bottom gate of the driving transistor. 10.The display substrate of claim 9, wherein, The plurality of transistors further comprises a second reset transistor, and in the same pixel driving circuit, the second electrode of the second reset transistor is connected with the first plate of the first capacitor and the first plate of the second capacitor; In the same pixel driving circuit, in the column direction, the second reset transistor is located on the side of the first reset transistor away from the data writing transistor, and in the row direction, the second reset transistor and the first reset transistor are located on the same side of the driving transistor.

11. The display substrate of claim 10, further comprising a plurality of first reset control lines, a plurality of second reset control lines, a plurality of scan signal lines, and a plurality of anode reset control lines, the first reset control lines, the second reset control lines, the scan signal lines, and the anode reset control lines being disposed in the same layer as the first electrode and the second electrode; and the gate electrodes of the first reset transistor, the second reset transistor, and the data writing transistor comprising top gates. ​ The first reset control line is connected to the top gate of at least part of the first reset transistor in at least one row of pixel driving circuits, the second reset control line is connected to the top gate of at least part of the second reset transistor in at least one row of pixel driving circuits, the scan signal line is connected to the top gate of at least part of the data writing transistor in at least one row of pixel driving circuits, and the anode reset control line is connected to the top gate of at least part of the anode reset transistor in at least one row of pixel driving circuits; In the same pixel driving circuit, in the column direction, the first capacitor is located on the side of the second capacitor away from the second light-emitting control transistor, the second capacitor is located on the side of the first capacitor away from the first light-emitting control transistor, and the anode reset control line, the second reset control line, the first reset control line and the scan signal line are sequentially and spacedly arranged along the column direction. 12.The display substrate of claim 11, wherein, The first light-emitting control transistor, the second light-emitting control transistor and the anode reset transistor further comprise a bottom gate; and the anode reset control line is further connected to the bottom gate of at least part of the anode reset transistor in at least one row of pixel driving circuits. 13.The display substrate according to claim 11 or 12, wherein, The first plate of the first capacitor and the first plate of the second capacitor are in an integral structure, the first plate and the second plate of the first capacitor and the first plate and the second plate of the second capacitor are in a rectangular structure, the area of the second plate of the first capacitor is consistent with the area of the second plate of the second capacitor, the second plate of the second capacitor is provided with an opening, and the second electrode of the second reset transistor is connected to the first plate of the first capacitor and the first plate of the second capacitor through a via at the opening position. 14.The display substrate of claim 13, wherein, The pixel driving circuit further comprises a transfer connection electrode, the transfer connection electrode is arranged in the same layer as the first electrode and the second electrode; the top gate of the driving transistor comprises a first part and a second part, the first part is in a rectangular shape, and the second part is in a strip shape or a polyline shape extending along the column direction; In the same driving transistor, the first part is connected to the second part, in the column direction, the second part is located on the side of the first part away from the first light-emitting control transistor, the orthographic projection of the first part on the substrate at least partially overlaps the orthographic projection of the first capacitor on the substrate, and the orthographic projection of the second part on the substrate at least partially overlaps the orthographic projection of the first capacitor and the second capacitor on the substrate; The transfer connection electrode is electrically connected to the second plate of the second capacitor and the second part through a via.

15. The display substrate of claim 14, further comprising a plurality of second power connection lines, the second power connection lines being arranged in the same layer as the first electrode and the second electrode, main body portions of the plurality of second power connection lines extending along the row direction and being spacedly arranged along the column direction. ​ In the same pixel driving circuit, in the column direction, the second power supply connection line is located on the side of the scan signal line away from the first reset control line, the second electrode of the first reset transistor, the second electrode of the data write transistor and the second electrode of the driving transistor are located between the scan signal line and the first reset control line, the switching connection electrode and the second electrode of the second reset transistor are located between the first reset control line and the second reset control line.

16. The display substrate of claim 10, further comprising a plurality of first reset control lines, a plurality of second reset control lines, a plurality of scan signal lines, a plurality of anode reset control lines extending along the row direction, the first reset control lines, the second reset control lines, the scan signal lines and the first electrode and the second electrode are arranged in the same layer, and the anode reset control lines are arranged in the same layer with the top gate; the first reset transistor, the second reset transistor, the data write transistor, the first light emitting control transistor, the second light emitting control transistor and the anode reset transistor all comprise a top gate and a bottom gate; the first reset control line is connected with the top gate and the bottom gate of at least part of the first reset transistor in at least one row of pixel driving circuits, the second reset control line is connected with the top gate and the bottom gate of at least part of the second reset transistor in at least one row of pixel driving circuits, the scan signal line is connected with the top gate and the bottom gate of at least part of the data write transistor in at least one row of pixel driving circuits, and the anode reset control line is provided with the top gate of at least part of the anode reset transistor in at least one row of pixel driving circuits; In the same pixel driving circuit, in the column direction, the first capacitor is located on the side of the second capacitor away from the first light emitting control transistor, the second capacitor is located on the side of the first capacitor away from the second light emitting control transistor, and the anode reset control line, the second reset control line, the first reset control line and the scan signal line are sequentially and spaced arranged along the column direction. 17.The display substrate of claim 16, wherein, The first plate of the first capacitor and the first plate of the second capacitor are in an integral structure, the first plate and the second plate of the first capacitor and the first plate and the second plate of the second capacitor are in a block structure, and the area of the second plate of the second capacitor is smaller than the area of the second plate of the first capacitor; the first plate of the first capacitor is provided with a first connection part, the second plate of the first capacitor is provided with a second connection part, and the orthogonal projection of the first connection part and the second connection part on the substrate at least partially does not overlap. In the same pixel driving circuit, in the column direction, the first connection part and the second connection part are located on the side of the first capacitor away from the first light emitting control transistor, the second electrode of the second reset transistor is connected with the first connection part through a via, and the second electrode of the driving transistor is connected with the second connection part through a via.

18. The display substrate according to claim 17, further comprising a plurality of second power supply connection lines, the second power supply connection lines being disposed in the same layer as the first poles and the second poles, main body portions of the plurality of second power supply connection lines extending in the row direction and being arranged at intervals in the column direction; in the same pixel driving circuit, in the column direction, the second power supply connection line is located between the scan signal line and the first reset control line, the second pole of the first reset transistor is located between the second power supply connection line and the first reset control line, the second pole of the data write transistor is located between the scan signal line and the second power supply connection line, and the second pole of the driving transistor is located between the first reset control line and the second reset control line.

19. The display substrate according to any one of claims 16 to 18, further comprising a plurality of third shield lines, the third shield lines being disposed in the same layer as the second pole plates, the plurality of third shield lines being in the shape of a broken line or a strip with main body portions extending in the row direction and being arranged at intervals in the column direction; the third shield line is provided with a bottom gate of at least part of the anode reset transistors in at least one row of pixel driving circuits, and the third shield line and the anode reset control line at least partially overlap in orthographic projection on the substrate. 20.The display substrate of claim 19, wherein, in the same row of pixel driving circuits, the orthographic projection of the third shield line on the substrate covers the orthographic projection of the anode reset control line on the substrate. 21.The display substrate of claim 8, wherein, the at least one capacitor includes a first capacitor and a second capacitor, in the same pixel driving circuit, the second pole of the driving transistor is electrically connected to the second pole plate of the first capacitor and the second pole plate of the second capacitor, the first pole plate of the first capacitor is connected to the top gate of the driving transistor, the orthographic projection of the driving transistor on the substrate at least partially overlaps the orthographic projection of the second capacitor on the substrate, and the second pole plate of the second capacitor serves as the bottom gate of the driving transistor; in the same pixel driving circuit, in the column direction, the first capacitor is located on the side of the second capacitor away from the first light-emitting control transistor, and the second capacitor is located on the side of the first capacitor away from the second light-emitting control transistor.

22. The display substrate according to claim 21, further comprising a plurality of first reset control lines, a plurality of scan signal lines, and a plurality of anode reset control lines, the first reset control lines, the scan signal lines, and the anode reset control lines being disposed in the same layer as the first poles and the second poles, and in the same row of pixel driving circuits, the anode reset control lines, the first reset control lines, and the scan signal lines are arranged at intervals in the column direction in sequence. The first reset transistor, the data write transistor, the first light-emitting control transistor, the second light-emitting control transistor and the anode reset transistor comprise a bottom gate; the first reset control line is connected with the bottom gate of at least part of the first reset transistor in at least one row of pixel driving circuits, the scan signal line is connected with the bottom gate of at least part of the data write transistor in at least one row of pixel driving circuits, and the anode reset control line is connected with the top gate and the bottom gate of at least part of the anode reset transistor in at least one row of pixel driving circuits.

23. The display substrate of claim 22, wherein, The first reset transistor and the data write transistor further comprise a top gate; the first reset control line is further connected with the top gate of at least part of the first reset transistor in at least one row of pixel driving circuits, and the scan signal line is further connected with the top gate of at least part of the data write transistor in at least one row of pixel driving circuits.

24. The display substrate according to any one of claims 21 to 23, further comprising a plurality of second power supply connection lines, the second power supply connection lines being disposed in the same layer as the first electrode and the second electrode, main body portions of the plurality of second power supply connection lines extending in the row direction and being arranged at intervals in the column direction. In the same pixel driving circuit, in the column direction, the second power supply connection line is located between the scan signal line and the first reset control line, and the second electrode of the first reset transistor, the second electrode of the data write transistor and the second electrode of the driving transistor are located between the scan signal line and the second power supply connection line.

25. The display substrate according to any one of claims 12, 16 to 18, 22 to 23, further comprising a plurality of first light-emitting control lines and a plurality of second light-emitting control lines, the first light-emitting control lines and the second light-emitting control lines being disposed in the same layer as the top gate; the plurality of first light-emitting control lines and the plurality of second light-emitting control lines being in the shape of a broken line or a strip with main body portions extending in the row direction and being arranged at intervals in the column direction; The first light-emitting control line is electrically connected with at least part of the first light-emitting control transistor in at least one row of pixel driving circuits, and the second light-emitting control line is electrically connected with at least part of the second light-emitting control transistor in at least one row of pixel driving circuits; an area where the first light-emitting control line overlaps with the active layer of the first light-emitting control transistor serves as the top gate of the first light-emitting control transistor, and an area where the second light-emitting control line overlaps with the active layer of the second light-emitting control transistor serves as the top gate of the second light-emitting control transistor; In the same pixel driving circuit, in the column direction, the first light-emitting control line and the first light-emitting control transistor are located on the same side of the driving transistor, the second light-emitting control line and the second light-emitting control transistor are located on the same side of the driving transistor, the anode reset control line is located on the side of the second light-emitting control line away from the first light-emitting control line, and the first reset control line and the scan signal line are located between the first light-emitting control line and the second light-emitting control line. ​ 26.The display substrate of claim 25, further comprising a plurality of first shield lines and a plurality of second shield lines, the plurality of first shield lines and the plurality of second shield lines being disposed in the same layer as the second plate; the plurality of first shield lines and the plurality of second shield lines being in a shape of a fold line or a strip shape extending along the row direction and being arranged in intervals along the column direction. In the same row of pixel driving circuits, a normal projection of the first shield line and the first light emitting control line on the substrate at least partially overlaps, and a normal projection of the second shield line and the second light emitting control line on the substrate at least partially overlaps. An area where the first shield line overlaps with an active layer of the first light emitting control transistor serves as a bottom gate of the first light emitting control transistor, and an area where the second shield line overlaps with an active layer of the second light emitting control transistor serves as a bottom gate of the second light emitting control transistor.

27. The display substrate of claim 26, wherein, In the same row of pixel driving circuits, a normal projection of the first shield line on the substrate covers a normal projection of the first light emitting control line on the substrate, and a normal projection of the second shield line on the substrate covers a normal projection of the second light emitting control line on the substrate. 28.A display device comprising the display substrate of any one of claims 1 to 27.

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