Low-power-consumption feedback apparatus insensitive to clock jitter and for continuous-time delta-sigma analog-to-digital converter, and electronic device

Abstract

The present disclosure relates to a low-power-consumption feedback apparatus insensitive to clock jitter and for a continuous-time delta-sigma analog-to-digital converter, and an electronic device. In the analog-to-digital converter, a control module is used for controlling, on the basis of a received timing control signal and a quantization signal which is output by a quantizer, a feedback capacitor module to periodically execute a charging operation and a feedback operation, wherein during the charging operation, the control module controls a capacitor in the feedback capacitor module to disconnect from an integrating capacitor, and to charge the feedback capacitor module; and during the feedback operation, the control module controls the capacitor in the feedback capacitor module to connect in parallel to the integrating capacitor, and the feedback capacitor module and the integrating capacitor share charges, so as to complete the feedback operation. The embodiments of the present disclosure can reduce the power consumption of an amplifier, thereby reducing the power consumption of the analog-to-digital converter and improving the energy efficiency.

Description

Feedback device for continuous-time delta-sigma analog-to-digital converter with low power consumption and insensitive to clock jitter and electronic device TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of integrated circuits, and particularly relates to a feedback device for a continuous-time delta-sigma analog-to-digital converter with low power consumption and insensitive to clock jitter and an electronic device. BACKGROUND

[0002] Continuous-Time Delta-Sigma Analog to Digital Converter (CTΔΣADC) is easy to drive, has lower power consumption than Discrete-Time Delta-Sigma Analog to Digital Converter (DTΔΣADC), and has an anti-aliasing function, so wideband CTΔΣADC is widely used in communication systems. Because of the need for oversampling, the sampling frequency required by wideband CTΔΣADC is usually in the GHz range. At a GHz sampling frequency, the bit number of the quantizer in the CTΔΣADC is usually no more than 4. The use of a low-bit quantizer results in a signal entering the loop filter being dominated by a high-frequency, high-amplitude feedback signal; in order to ensure linearity, the first stage of the loop filter needs to be able to quickly output a large current, as shown in (a) of FIG. 1. When the feedback is a traditional resistor or current feedback, the use of a low-bit quantizer also results in high sensitivity of the entire architecture to clock jitter. At this time, in order to achieve high conversion accuracy, a low-jitter clock is required, and generating and transmitting a low-jitter clock requires high power consumption. Switched-capacitor feedback can reduce the sensitivity of the CTΔΣADC to clock jitter; however, the amplifier in the first stage of the loop filter needs to consume higher power consumption than using resistor or current feedback to linearly process the high peak current caused by using switched-capacitor feedback, as shown in (b) of FIG. 1.

[0003] Therefore, when the quantization bit number of the CTΔΣADC is low, the use of existing feedback technology will inevitably result in high power consumption due to the need for the amplifier in the first stage of the loop filter to be able to linearly process high-frequency, high-amplitude signals or the need to generate and transmit a low-jitter clock. SUMMARY

[0004] According to an aspect of the present disclosure, an analog-to-digital converter is provided, comprising an input resistor, an amplifier, an integration capacitor, a quantizer, a feedback capacitor module, and a control module, wherein a first end of the input resistor is configured to receive an input analog voltage, a second end of the input resistor is connected to an input of the amplifier, a first end of the integration capacitor, and the feedback capacitor module, an output of the amplifier is connected to an input of the quantizer, a second end of the integration capacitor, and the feedback capacitor module, an output of the quantizer is connected to the control module, the control module is further connected to the feedback capacitor module, and the control module is configured to control the feedback capacitor module to periodically perform a charging operation and a feedback operation according to a received timing control signal and a quantization signal output by the quantizer, wherein in the charging operation, the control module controls a capacitor in the feedback capacitor module to be disconnected from the integration capacitor and to be charged, and in the feedback operation, the control module controls the capacitor in the feedback capacitor module to be connected in parallel with the integration capacitor, and the feedback capacitor module and the integration capacitor perform charge sharing to complete the feedback operation.

[0005] In a possible implementation, the feedback capacitor module comprises at least one feedback capacitor array, each feedback capacitor array comprises a first connection switch, a second connection switch, and at least one capacitor component, the capacitor component comprises a feedback capacitor and a feedback control switch, and for any one capacitor component: a first end of the feedback capacitor is connected to a first end of the first connection switch and a first end of the second connection switch, a second end of the first connection switch is connected to a first end of the integration capacitor, a second end of the second connection switch is configured to receive a first preset voltage, a second end of the feedback capacitor is connected to a first end of the feedback control switch, and a second end of the feedback control switch is connected to a second end of the integration capacitor.

[0006] In a possible implementation, the control module comprises a plurality of charging switch units, each charging switch unit comprises a charging control switch and a multiplexing switch, one charging switch unit and one capacitor component form a feedback charging loop, and for any one feedback charging loop: a control end of the multiplexing switch is configured to receive a corresponding bit of the quantization signal, a first input end of the multiplexing switch is configured to receive a first reference voltage, a second input end of the multiplexing switch is configured to receive a second reference voltage, the first reference voltage and the second reference voltage are different in polarity, an output end of the multiplexing switch is connected to a first end of the charging control switch, a second end of the charging control switch is connected to a second end of the feedback capacitor in the capacitor component and a first end of the feedback control switch, and a control signal of the charging control switch is the same as a control signal of the second connection switch.

[0007] In a possible implementation, the feedback capacitor array includes a first feedback capacitor array and a second feedback capacitor array, a duty cycle of the control signal is less than 1 / 2, the control signal includes a first control signal and a second control signal, the first control signal and the second control signal are non-overlapping signals, in the first feedback capacitor array, the second connection switch is controlled by the first control signal, the first connection switch and each feedback control switch are controlled by the second control signal, and in the first feedback capacitor array, each charging control switch corresponding to the first feedback capacitor array is controlled by the first control signal; in the second feedback capacitor array, the second connection switch is controlled by the second control signal, the first connection switch and each feedback control switch are controlled by the first control signal, and in the second feedback capacitor array, each charging control switch corresponding to the second feedback capacitor array is controlled by the second control signal.

[0008] In a possible implementation, for one clock cycle of the sampling clock signal, a rising edge and a falling edge of the first control signal are between a rising edge and a falling edge of the clock cycle, a rising edge and a falling edge of the second control signal are between a falling edge and a rising edge of the clock cycle, and a duty cycle of the sampling clock signal is 1 / 2.

[0009] In a possible implementation, the analog-to-digital converter further includes a charge compensation circuit, the charge compensation circuit includes a first compensation switch, a second compensation switch, a third compensation switch, a fourth compensation switch, a first compensation capacitor, and a second compensation capacitor, a first end of the first compensation switch is connected to a second end of the input resistor, a first end of the fourth compensation switch, a negative input end of the amplifier, and a first end of the integration capacitor through the second compensation switch, a positive input end of the amplifier is configured to receive a second preset voltage, a second end of the first compensation switch is connected to a first end of the third compensation switch and a negative output end of the amplifier, a first end of the first compensation capacitor is connected to the first end of the first compensation switch, a second end of the first compensation capacitor is connected to a first end of the second compensation capacitor, a positive output end of the amplifier, and a second end of the integration capacitor, and a second end of the third compensation switch is connected to a second end of the fourth compensation switch and a second end of the second compensation capacitor, the first compensation switch and the fourth compensation switch are controlled by the first control signal, and the second compensation switch and the third compensation switch are controlled by the second control signal.

[0010] In a possible implementation, a capacitance of the first compensation capacitor and the second compensation capacitor is (2 N -1) times a unit capacitance of the feedback capacitor, where N is a precision of the quantizer.

[0011] In a possible implementation, the quantizer is a 1-bit quantizer, the analog-to-digital converter further includes an SR latch, a first D flip-flop, a second D flip-flop, and the first feedback capacitor array and the second feedback capacitor array each includes one capacitor component and one feedback charging loop, wherein the positive output terminal and the negative output terminal of the quantizer are connected to the S terminal and the R terminal of the SR latch respectively, the Q output terminal of the SR latch is connected to the D input terminal of the first D flip-flop, the clock signal input terminal of the first D flip-flop is configured to input a first clock signal, the Q output terminal of the first D flip-flop is connected to the D input terminal of the second D flip-flop, and the output signal of the Q output terminal of the first D flip-flop is further output to the control terminal of the multiplexer of the second feedback capacitor array, the clock signal input terminal of the second D flip-flop is configured to input a second clock signal, the output signal of the Q output terminal of the second D flip-flop is output to the control terminal of the multiplexer of the first feedback capacitor array, the first clock signal and the second clock signal are non-overlapping signals, the falling edge of the first clock signal is separated from the rising edge of the second control signal by a first preset time length, and the rising edge of the second clock signal is separated from the falling edge of the first control signal by the first preset time length.

[0012] In a possible implementation, the capacitance of the first compensation capacitor, the second compensation capacitor, the feedback capacitor in the first feedback capacitor array, and the feedback capacitor in the second feedback capacitor array are equal.

[0013] According to an aspect of the present disclosure, an electronic device is provided, which includes the analog-to-digital converter.

[0014] The embodiments of the present disclosure control the feedback capacitor module to periodically perform the charging operation and the charge sharing operation according to the received timing control signal and the quantization signal output by the quantizer, separate the integrals of the feedback signal and the input signal in the first stage of the loop filter, wherein the integral of the feedback signal is completed in a passive manner, and the integral of the input signal is completed by an active RC integrator, so that the amplifier in the first stage of the loop filter only needs to process the input signal with low frequency and small amplitude, and does not participate in the integral of the feedback signal with high frequency and large amplitude, which can reduce the power consumption of the amplifier, thereby reducing the power consumption of the analog-to-digital converter and improving the energy efficiency.

[0015] It should be understood that the general description above and the following detailed description are only exemplary and explanatory, but not limiting the present disclosure. Other features and aspects of the present disclosure will become apparent according to the following detailed description of exemplary embodiments with reference to the accompanying drawings. BRIEF DESCRIPTION OF DRAWINGS

[0016] The accompanying drawings, which are incorporated herein and constitute part of the specification, illustrate embodiments consistent with the present disclosure and, together with the description, further serve to explain the principles of the present disclosure.

[0017] FIG. 1 shows a schematic diagram of an implementation of an analog-to-digital converter in the related art;

[0018] FIG. 2a shows a schematic diagram of an analog-to-digital converter according to an embodiment of the present disclosure;

[0019] FIG. 2b shows a schematic diagram of an analog-to-digital converter according to an embodiment of the present disclosure;

[0020] FIG. 2c shows a schematic diagram of a second integrator according to an embodiment of the present disclosure;

[0021] FIG. 2d shows a schematic diagram of a second integrator according to an embodiment of the present disclosure;

[0022] FIG. 3 shows a schematic diagram of an analog-to-digital converter according to an embodiment of the present disclosure;

[0023] FIGS. 4a, 4b, 4c, and 4d show schematic diagrams of an analog-to-digital converter according to an embodiment of the present disclosure;

[0024] FIG. 5 shows a schematic diagram of an analog-to-digital converter employing a charge compensation circuit according to an embodiment of the present disclosure;

[0025] FIG. 6a shows a schematic diagram of an analog-to-digital converter employing a 1-bit quantizer according to an embodiment of the present disclosure;

[0026] FIG. 6b shows a timing diagram of the analog-to-digital converter of FIG. 6a. DETAILED DESCRIPTION

[0027] Various exemplary embodiments, features, and aspects of the present disclosure will be described in detail below with reference to the accompanying drawings. The same reference numbers in different drawings represent the same or similar elements. Although various aspects of embodiments are illustrated in the drawings, the drawings are not necessarily drawn to scale unless specifically noted.

[0028] In the description of the present disclosure, it needs to be understood that the terms "length", "width", "upper", "lower", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", and the like indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present disclosure and simplifying the description, and do not indicate or imply that the devices or elements referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation on the present disclosure.

[0029] In addition, the terms "first", "second", etc. are used only for descriptive purposes and do not connote or imply a relative importance or an ordering between or among the indicated elements. Thus, a feature described as "first" can imply that the feature is either the first such feature described or the first of the feature, regardless of the number of such features that can exist.

[0030] In the present disclosure, unless specifically defined otherwise, the terms "mounting", "connection", "connecting", "fixed", and the like should be construed broadly, for example, can be fixed connection, can also be detachable connection, or integral; can be mechanical connection, can also be electrical connection; can be directly connected, can also be indirectly connected through an intermediate medium, can be the internal communication of two elements or the interaction relationship between two elements. For those skilled in the art, the specific meaning of the above terms in the present disclosure can be understood according to the specific circumstances.

[0031] The term "exemplary" is used herein to mean "serving as an example, instance, or illustration." Any embodiment described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other embodiments.

[0032] The term "and / or", only describes the association relationship of the associated objects, which means that there can be three relationships, for example, A and / or B, which can represent the existence of A alone, the existence of A and B, and the existence of B alone. In addition, the term "at least one" herein means any one of the plurality or any combination of at least two of the plurality, for example, including at least one of A, B, and C, which can mean including any one or more elements selected from the set consisting of A, B, and C.

[0033] In addition, in order to better illustrate the present disclosure, a large number of specific details are given in the specific embodiments below. Those skilled in the art should understand that the present disclosure can also be implemented without some specific details. In some examples, methods, means, elements and circuits that are well known to those skilled in the art are not described in detail, in order to highlight the main idea of the present disclosure.

[0034] Please refer to FIG. 2a, which shows a schematic diagram of an analog-to-digital converter according to an embodiment of the present disclosure.

[0035] As shown in FIG. 2a, it includes an input resistor Rin, an amplifier Amp, an integration capacitor Cint, a quantizer 10, a feedback capacitor module 20, and a control module 30, wherein,

[0036] A first end of the input resistor Rin is configured to receive an input analog voltage Vin, a second end of the input resistor Rin is connected to an input end of the amplifier Amp, a first end of the integration capacitor Cint and the feedback capacitor module 20,

[0037] An output end of the amplifier Amp is connected to an input end of the quantizer 10, a second end of the integration capacitor Cint and the feedback capacitor module 20,

[0038] The quantizer 10 is, for example, an N-bit quantizer, and an output of the quantizer 10 is an N-bit digital code, wherein an output end of the quantizer 10 is connected to the control module 30, and the output end of the quantizer 10 is configured to output an output digital signal Dout[N-1:0] of an N-bit analog-to-digital converter, N is a positive integer,

[0039] The control module 30 is further connected to the feedback capacitor module 20, and the control module 30 is configured to: according to a received timing control signal and a quantization signal output by the quantizer 10, control the feedback capacitor module 20 to periodically perform a charging operation and a charge sharing operation, wherein,

[0040] In the charging operation, the control module 30 controls a capacitor in the feedback capacitor module 20 to be disconnected from the integration capacitor Cint, and charges the feedback capacitor module 20.

[0041] In the charge sharing operation, the control module 30 controls the capacitor in the feedback capacitor module 20 to be connected in parallel to the integration capacitor Cint, and the feedback capacitor module 20 and the integration capacitor Cint perform charge sharing to complete the feedback operation.

[0042] According to the embodiments of the present disclosure, the feedback capacitor module 20 is controlled to periodically perform the charging operation and the charge sharing operation according to the received timing control signal and the quantization signal output by the quantizer 10, and the integration of the feedback signal and the input signal is separated in the first stage of the loop filter, wherein the integration of the feedback signal is completed in a passive manner, and the integration of the input signal is completed by an active RC integrator, so that the amplifier Amp in the first stage of the loop filter only needs to process the input signal with low frequency and small amplitude, and does not participate in the integration of the feedback signal with high frequency and large amplitude, thereby reducing the power consumption of the amplifier Amp, reducing the power consumption of the analog-to-digital converter, improving the energy efficiency, and realizing a continuous-time Delta-Sigma analog-to-digital converter with low power consumption and insensitive to clock jitter.

[0043] Of course, the specific implementation of the amplifier Amp, the quantizer 10, the feedback capacitor module 20, and the control module 30 is not limited in the embodiments of the present disclosure, and the specific parameters of the input resistor Rin and the integration capacitor Cint are not limited, and a person skilled in the art can use related technologies to achieve or set according to actual conditions and needs, as long as the corresponding functions can be realized.

[0044] For example, the amplifier Amp can be an OTA, etc., where OTA represents an active device operational transconductance amplifier (OTA), and Gm is the transconductance of the operational transconductance amplifier Amp. The amplifier Amp can be of the type of differential input and single output (as shown in FIG. 2a), or of the full differential type (i.e., differential input and differential output). If the amplifier Amp is of the type of differential input and single output, one input end of the differential input can be connected to the second end of the input resistor Rin, and the other input end can be connected to the input common-mode voltage of the amplifier Amp. If the amplifier Amp is a full differential amplifier, such as a differential transconductance amplifier, one input end of the differential transconductance amplifier can be connected to the second end of the input resistor, and the other input end can be connected to the input common-mode voltage of the amplifier. Correspondingly, one output end of the differential transconductance amplifier can be connected to the second end of the integration capacitor Cint, and the connection needs to ensure that the two ends of the integration capacitor Cint are connected to the input and output ends of the amplifier which are opposite to each other, so as to ensure negative feedback. Of course, a person skilled in the art can set the specific connection relationship according to actual conditions and needs, which is not limited herein. Of course, both output ends of the differential transconductance amplifier are connected to the next device (such as the quantizer 10).

[0045] The specific size of the quantization bit N of the quantizer is not limited in the embodiments of the present disclosure, and a person skilled in the art can set it according to actual conditions and needs. For example, the quantizer 10 can be a low-bit number quantizer, and the quantization bit N of the quantizer can be less than or equal to 4, such as 1 bit or 3 bits. Of course, N can also be other numbers greater than 4.

[0046] For example, the feedback capacitor module 20 can include a combination of N capacitors and a plurality of switches, and each combination of switches is used to control the parallel connection or disconnection of each capacitor and the integration capacitor Cint. The ratio of the capacitance values of the N capacitors of the feedback capacitor module 20 is: 2 N-1 : 2 N-2 : …… : 2 2 : 2 1 : 2 0 .

[0047] Exemplarily, the control module 30 can include a processing component and other devices (such as a switch, an AND gate, etc.), and in one example, the processing component includes but is not limited to a single processor, or discrete components, or a combination of the processor and the discrete components. The processor can include a controller having a function of executing instructions in an electronic device, and the processor can be implemented in any appropriate manner, for example, by one or more application specific integrated circuits (ASICs), digital signal processors (DSPs), digital signal processing devices (DSPDs), programmable logic devices (PLDs), field programmable gate arrays (FPGAs), controllers, microcontrollers, microprocessors, or other electronic elements. Inside the processor, the executable instructions can be executed by hardware circuits such as logic gates, switches, application specific integrated circuits (ASICs), programmable logic controllers, and embedded microcontrollers.

[0048] Of course, the analog-to-digital converter of the embodiments of the present disclosure can also include other components, which are not limited by the embodiments of the present disclosure.

[0049] Please refer to FIG. 2b, which shows a schematic diagram of an analog-to-digital converter according to the embodiments of the present disclosure.

[0050] Exemplarily, as shown in FIG. 2b, a second integration component 50 or more integration components can be further arranged between the amplifier Amp and the quantizer 10, so as to improve the noise shaping order of the quantization noise while keeping the over sampling rate (OSR) unchanged; a high noise shaping order is beneficial to reduce the quantization noise in the signal bandwidth, thereby improving the signal-to-quantization noise ratio (SQNR) of the CTΔΣADC.

[0051] Exemplarily, as shown in FIG. 2b, taking an example of two integration components in the loop filter in total, the first integration component is the integration component using the feedback technology proposed in the embodiments of the present disclosure, and the embodiments of the present disclosure do not limit the specific implementation manner of the second integration component 50, and a person skilled in the art can implement it according to the actual situation and needs, for example, it can include an integrator and a corresponding compensation circuit.

[0052] For example, the number of integrators included in the second integration component 50 can be set according to the order of the required noise shaping. For example, if the order of the required noise shaping is 2, the second integration component can include one integrator, in which case there are two integrators in the loop filter in total; if the order of the noise shaping is 3, the second integration component can include 2 integrators, in which case there are 3 integrators in the loop filter in total.

[0053] Referring to FIG. 2c, FIG. 2c shows a schematic diagram of the second integration component according to an embodiment of the present disclosure.

[0054] For example, as shown in FIG. 2c, the second integration component 50 can include a second integrator 510, a first compensator F1, a second compensator F2, and an analog summer SUM1. The first compensator F1 is configured to perform voltage scaling on the signal output by the amplifier Amp of the first integrator, the second integrator 510 is configured to perform integration operation on the signal output by the amplifier Amp and perform voltage scaling using the second compensator F2, and the analog summer SUM1 is configured to sum the outputs of the first compensator F1 and the second compensator F2.

[0055] It should be understood that whether the second integration component 50 needs to be added depends on the order of the required noise shaping. If only first-order noise shaping is required, i.e., only one integrator is required in the loop filter, the second integration component 50 is not required. If noise shaping higher than the first order is required, the second integration component 50 or more integration components can be provided. Because the loop needs to be compensated due to the stability of the loop (when the loop filter is first-order, i.e., only one integrator is required, no compensation is required; when the total number of integrators in the loop filter is 2, the first compensator F1 and the second compensator F2 shown in FIG. 2c can be used for compensation to ensure the stability of the entire loop), one of the commonly used compensation methods is used in the embodiment of the present disclosure, i.e., feedforward compensation. However, the embodiment of the present disclosure is not limited to this, and in other embodiments, a person skilled in the art can use other compensation methods according to actual conditions and requirements.

[0056] The embodiment of the present disclosure does not limit the specific implementation of the first compensator F1 and the second compensator F2, and a person skilled in the art can use related technologies to achieve the specific implementation according to actual conditions and requirements. For example, the first compensator F1 and the second compensator F2 can be implemented by using two resistors with appropriate resistance ratios or two transconductance operational amplifiers (OTAs) with appropriate transconductance ratios, so as to achieve proportional scaling of the outputs of the first integrator and the second integrator.

[0057] The embodiment of the present disclosure does not limit the specific implementation of the second integrator 510, and a person skilled in the art can use related technologies to achieve the specific implementation according to actual conditions and requirements.

[0058] Referring to FIG. 2d, FIG. 2d shows a schematic diagram of a second integrator according to an embodiment of the present disclosure.

[0059] For example, as shown in FIG. 2d, the second integrator can be implemented by an active RC integrator or a Gm-C integrator according to an embodiment of the present disclosure.

[0060] The possible implementation of the feedback capacitance module 20 and the control module 30 is exemplarily introduced as follows.

[0061] Referring to FIG. 3, FIG. 3 shows a schematic diagram of an analog-to-digital converter according to an embodiment of the present disclosure.

[0062] In a possible implementation, as shown in FIG. 3, the feedback capacitance module 20 can include at least one feedback capacitance array, each feedback capacitance array can include a first connection switch K1, a second connection switch K2 and at least one capacitance component 210, the capacitance component 210 can include a feedback capacitance C1 and a feedback control switch K3,

[0063] For any one capacitance component 210:

[0064] The first end of the feedback capacitance C1 is connected to the first end of the first connection switch K1 and the first end of the second connection switch K2, the second end of the first connection switch K1 is connected to the first end of the integration capacitance Cint, and the second end of the second connection switch K2 is used to receive a first preset voltage (Vcm),

[0065] The second end of the feedback capacitance C1 is connected to the first end of the feedback control switch K3, and the second end of the feedback control switch K3 is connected to the second end of the integration capacitance Cint.

[0066] For example, each feedback capacitance array includes N capacitance components 210, and each feedback capacitance C1 in the N capacitance components 210 has a capacitance value of 2 N-1 C fb0 ,2 N-2 C fb0 ,2 N-3 C fb0 ,……,2C fb0 ,C fb0 .

[0067] By using the feedback capacitance array and the control method thereof according to the present disclosure, the feedback current I fb will not enter the amplifier Amp, which can reduce the power consumption of the amplifier Amp and is not sensitive to clock jitter.

[0068] The specific size of the first preset voltage (Vcm) is not limited in the embodiments of the present disclosure, and can be set according to actual conditions and needs by those skilled in the art. For example, the first preset voltage (Vcm) satisfies: Vcm=(Vref-)+((Vref+)-(Vref-)) / 2, that is, Vcm can be the intermediate level between the first reference voltage (Vref-) and the second reference voltage (Vref+).

[0069] In a possible implementation, as shown in FIG. 3, the control module 30 can include a plurality of charging switch units 310, each of which can include a charging control switch K4 and a plurality of multiplexing switches MUX (such as MUX1-MUX N), wherein one charging switch unit 310, one capacitor assembly 210, and the second connection switch K2 form a feedback charging loop,

[0070] For any feedback charging loop:

[0071] The control end of the multiplexing switch is configured to receive a corresponding bit (DOUT[0]-DOUT[N-1]) of the quantization signal,

[0072] The first input end of the multiplexing switch MUX is configured to receive a first reference voltage (Vref-), and the second input end of the multiplexing switch MUX is configured to receive a second reference voltage (Vref+), wherein the first reference voltage and the second reference voltage are different in polarity,

[0073] The output end of the multiplexing switch MUX is connected to the first end of the charging control switch K4,

[0074] The second end of the charging control switch K4 is connected to the second end of the feedback capacitor C1 in the capacitor assembly 210 and the first end of the feedback control switch K3,

[0075] The control signal of the charging control switch K4 is the same as the control signal of the second connection switch K2.

[0076] In the embodiments of the present disclosure, the integration of the feedback signal and the input analog signal is separated in the first stage of the loop filter: the integration of the feedback signal is completed in a passive manner, and the integration of the input analog signal is completed by an active RC integrator (including an input resistor Rin and an integration capacitor Cint), so that the amplifier Amp in the first stage of the loop filter only needs to process the input signal with low frequency and small amplitude, and does not participate in the integration of the feedback signal with high frequency and large amplitude.

[0077] In this embodiment of the disclosure, a first reference voltage (Vref-) and a second reference voltage (Vref+) can be set according to the magnitude of the input analog voltage Vin. Of course, the specific magnitude of these voltages is not limited in this embodiment of the disclosure. Those skilled in the art can set them according to actual conditions and needs. For example, those skilled in the art can determine the specific magnitude of the first reference voltage (Vref-) and the second reference voltage (Vref+) based on the minimum and maximum values ​​of the input analog voltage Vin.

[0078] For example, as shown in Figure 3, in this embodiment of the present disclosure, after the feedback capacitor array has finished charging, the feedback capacitor array is directly connected in parallel with the integrating capacitor Cint in the first stage active RC integrator of the loop filter to realize the injection of the feedback signal into the loop filter; the first stage active RC integrator of the loop filter only processes the input analog signal.

[0079] For example, the total capacitance in the feedback capacitor array can satisfy the following equation: (2 N -1)C fb0 =1 / (fs·R) in ), where f s R represents the sampling frequency. in Indicates the input resistance, C fb0 This represents the unit capacitance that makes up each feedback capacitor C1, and the capacitance ratio of each feedback capacitor is: 2. N-1 :2 N-2 :……:4:2:1, meaning the capacitance of the i-th feedback capacitor is 2. i-1 C fb0 Where i ≤ N and is a positive integer, N represents the quantization precision of the quantizer, that is, the number of output bits of the quantizer; correspondingly, the quantizer outputs controlling each feedback capacitor are: Dout[N-1], Dout[N-2], ..., Dout[2], Dout[1], Dout[0], where Dout[N-1] is the output bit with the largest weight in the quantizer output, Dout[N-2] is the output bit with the second largest weight in the quantizer output, and so on, Dout[2] is the output bit with the third smallest weight in the quantizer output, Dout[1] is the output bit with the second smallest weight in the quantizer output, and Dout[0] is the output bit with the smallest weight in the quantizer output.

[0080] For example, for each feedback capacitor shown in Figure 3, the i-th feedback capacitor can be composed of 2 i-1 Unit capacitance C fb0 The second feedback capacitor can be obtained by connecting them in parallel; for example, the second feedback capacitor can be composed of two unit capacitors C. fb0 The parallel connection results in a second feedback capacitor with a capacitance of 2C. fb0; the third feedback capacitor can be obtained by connecting 4 unit capacitors C fb0 in parallel, and the capacitance of the third feedback capacitor is 4C fb0 ; the Nth feedback capacitor can be obtained by connecting 2 N-1 unit capacitors C fb0 in parallel, and the capacitance of the Nth feedback capacitor is 2 N-1 C fb0 .

[0081] In the embodiments of the present disclosure, the number of capacitor components in a feedback capacitor array corresponds to the size of the quantization accuracy, and corresponds to the number of multipath selection switches MUX and charging control switches K4. By setting the total capacitance of the feedback capacitor C1 in the feedback capacitor array to satisfy the above relationship, the embodiments of the present disclosure can realize that the amplitude ratio of the feedback signal and the input signal is 1:1.

[0082] The embodiments of the present disclosure can set multiple capacitor feedback arrays, for example, two capacitor feedback arrays can be set to work in a ping-pong manner (that is, in a two-clock interleaving manner), which can ensure that the total integration capacitor Cint seen by the input signal remains unchanged, and avoid weakening the anti-aliasing advantage of the CTΔΣADC by the switching operation of the first stage of the loop filter. The number of capacitor feedback arrays set in the embodiments of the present disclosure is denoted as M, in order to realize that the amplitude ratio of the feedback signal and the input signal is 1:1, the size of each unit capacitor C fb0 in the M capacitor feedback arrays should satisfy the following equation: M × (2 N -1)C fb0 = 1 / (fs·R in ), where f s represents the sampling frequency, R in represents the input resistance, and C fb0 represents the unit capacitor that constitutes each feedback capacitor C1 in the M capacitor feedback arrays.

[0083] Please refer to FIG. 4a, FIG. 4b, FIG. 4c, and FIG. 4d, which show schematic diagrams of an analog-to-digital converter according to an embodiment of the present disclosure.

[0084] FIG. 4b shows the circuit state when the kth period quantizer 10 quantizes the loop filter output, FIG. 4c shows the circuit state when the first control signal Φ1 is high in the kth period, and FIG. 4d shows the circuit state when the second control signal Φ2 is high in the kth period.

[0085] In a possible implementation, as shown in FIG. 4a, the feedback capacitor array can include a first feedback capacitor array A and a second feedback capacitor array B, a duty cycle of the control signal is less than 1 / 2, the control signal can include a first control signal Φ1 and a second control signal Φ2, the first control signal Φ1 and the second control signal Φ2 are non-overlapping signals, which means that the two signals cannot be at a high level (or an active level) at the same time on a time axis, wherein

[0086] In the first feedback capacitor array A, the second connection switch K2 is controlled by the first control signal Φ1, the first connection switch K1 and each feedback control switch K3 are controlled by the second control signal Φ2, and each charging control switch K4 corresponding to the first feedback capacitor array A is controlled by the first control signal Φ1 (the control signal of each charging control switch K4 corresponding to the first feedback capacitor array A is the same as the control signal of the second connection switch K2).

[0087] In the second feedback capacitor array B, the second connection switch K2 is controlled by the second control signal Φ2, the first connection switch K1 and each feedback control switch K3 are controlled by the first control signal Φ1, and each charging control switch K4 corresponding to the second feedback capacitor array B is controlled by the second control signal Φ2.

[0088] The specific generation mode of the control signal is not limited in the embodiments of the present disclosure, and can be set according to actual conditions and needs by those skilled in the art.

[0089] In a possible implementation, as shown in the timing diagram in the upper right corner of FIG. 4a, for one clock cycle of the sampling clock signal, the rising edge and the falling edge of the first control signal Φ1 are between the rising edge and the falling edge of the clock cycle, the rising edge and the falling edge of the second control signal Φ2 are between the falling edge and the rising edge of the clock cycle, and the duty cycle of the sampling clock signal fs is 1 / 2.

[0090] As shown in FIG. 4a, the first feedback capacitor array A and the second feedback capacitor array B use ping-pong operation (that is, two-way clock interleaving operation) to alternately inject feedback charges into the integration capacitor Cint of the loop filter, and the ping-pong operation ensures that the anti-aliasing advantage of the CTΔ∑ADC using the technology proposed in the embodiments of the present disclosure will not be lost due to switching operation at the front end of the loop filter, that is, the ping-pong operation ensures that the anti-aliasing advantage of the CTΔ∑ADC using the technology proposed in the embodiments of the present disclosure can still be maintained.

[0091] The working process of ping-pong operation is exemplarily introduced as follows.

[0092] Exemplarily, as shown in FIG. 4b, at the moment of k·T s , the rising edge of the sampling clock signal fs in FIG. 4b, the quantizer 10 quantizes the signal output by the loop filter (the output terminal of the amplifier) and saves the quantization result D out for one clock cycle T s ; at this time, the first connection switch K1, the second connection switch K2 and the feedback control switch K3 are all in the off state, and the first feedback capacitor array A and the second feedback capacitor array B are both in the floating state.

[0093] Exemplarily, as shown in FIG. 4c, when the first control signal Φ1 is high (FIG. 4c), each capacitor in the feedback capacitor array A is charged to V ref+ or V ref- according to the value of the corresponding quantization bit in the quantization result output by the quantizer 10 in the current period, by selecting the corresponding reference voltage (for example, V ref+ for high and V ref- for low); for example, the capacitor with a capacitance value of C fb0 in the feedback capacitor array is charged according to the value of the output bit with the smallest weight Dout[0] in the quantization result output by the quantizer 10 in the current period, by selecting the corresponding level, and for another example, the capacitor with a capacitance value of 2 N-1 C fb0 in the feedback capacitor array A is charged according to the value of the output bit with the largest weight Dout[N-1] in the quantization result output by the quantizer 10 in the current period, by selecting the corresponding level. The second connection switch K2 and the corresponding charging control switch K4 of the first feedback capacitor array A are turned on (the multiplexer outputs Vref+ or Vref- to the feedback capacitor according to the value of the corresponding bit in the quantization result), the first connection switch K1 and each feedback control switch K3 of the second feedback capacitor array B are turned on, the second feedback capacitor array B is connected in parallel with the integrating capacitor C int , and 1 / 2 of the charge amount corresponding to the quantization result D out [N-1:0][k-1] output by the quantizer 10 in the k-1th period is directly dumped into the loop filter in a passive manner. At this time, the total integrating capacitor seen by the ADC input current I in is C int +(2 Ν -1)C fb0 .

[0094] As shown in FIG. 4d, after 0.5Ts (FIG. 4d), the first control signal Φ1 becomes low, while the second control signal Φ2 becomes high, the second connection switch K2 and the corresponding charging control switch K4 of the second feedback capacitor array B are turned on (the multiplexer outputs Vref+ or Vref- to the feedback capacitor according to the value of the corresponding bit of the quantization result), the first connection switch K1 and each feedback control switch K3 of the first feedback capacitor array A are turned on, and the first feedback capacitor array A and the C int In parallel, the charge corresponding to the quantization result D out [N-1:0][k] of the kth period quantizer 10 is directly dumped into the loop filter; at the same time, the second feedback capacitor array B repeats the operation of the first feedback capacitor array A in the first half of the period, i.e., according to the quantization result D ref+ [N-1:0][k] of the current period (the kth period) quantizer 10, the corresponding 1 / 2 charge is charged to V ref- ref+ or Vref-. in The total integral capacitance seen is still C int +2 Ν C fb0 At the beginning of the k+1th period, i.e., when the first control signal Φ1 changes from low to high, the 1 / 2 charge corresponding to the quantization result D out [N-1:0][k] of the kth period quantizer 10 is dumped into the loop filter, and thus the charge corresponding to the quantization result D out [N-1:0][k] of the kth period quantizer 10 is completely dumped into the loop filter.

[0095] Referring to FIG. 5, FIG. 5 shows a schematic diagram of an analog-to-digital converter employing a charge compensation circuit according to an embodiment of the present disclosure.

[0096] In a possible implementation, as shown in FIG. 5, the analog-to-digital converter further comprises a charge compensation circuit 40, the charge compensation circuit 40 comprising a first compensation switch S1, a second compensation switch S2, a third compensation switch S3, a fourth compensation switch S4, a first compensation capacitor C c,b , a second compensation capacitor C c,a , a third compensation capacitor C

[0097] The first end of the first compensation switch S1 is connected to the second end of the input resistor Rin, the first end of the fourth compensation switch S4, the negative input end of the amplifier Amp (assuming that the amplifier Amp is a differential transconductance amplifier), and the first end of the integration capacitor Cint, and the positive input end of the amplifier Amp is used to receive a second preset voltage Vcm,amp. For example, the value of Vcm,amp is the input common-mode voltage of the amplifier.

[0098] The second end of the first compensation switch S1 is connected to the first end of the third compensation switch S3 and the negative output end of the amplifier Amp,

[0099] The first end of the first compensation capacitor C c,b is connected to the first end of the first compensation switch S1, and the second end of the first compensation capacitor C c,b is connected to the first end of the second compensation capacitor C c,a , the positive output end of the amplifier Amp, and the second end of the integration capacitor Cint.

[0100] The second end of the third compensation switch S3 is connected to the second end of the fourth compensation switch S4 and the second end of the second compensation capacitor C c,a .

[0101] The first compensation switch S1 and the fourth compensation switch S4 are controlled by the first control signal Φ1, and the second compensation switch S2 and the third compensation switch S3 are controlled by the second control signal Φ2.

[0102] In a possible implementation, the capacitance of the first compensation capacitor C c,b and the second compensation capacitor C c,a is (2 fb0 -1) times the size of the unit capacitor C N that constitutes the feedback capacitor C1, that is, C c,b =C c,a =(2 N -1)C fb0 , where N is the precision of the quantizer 10, that is, the number of output bits of the quantizer 10.

[0103] In order to compensate for the charge taken away when the feedback capacitor array is disconnected from the compensation capacitor Cint, the charge compensation circuit 40 is proposed to compensate for the loss of charge by introducing auxiliary capacitors: the first compensation capacitor C c,b and the second compensation capacitor C c,a , and the output of the amplifier Amp in the first-stage integrator is used to charge the first compensation capacitor C c,bThe second compensation capacitor C c,a Differential charging is performed using a ping-pong method. When the feedback capacitor array is disconnected from the integrating capacitor Cint, the first compensation capacitor C... c,b Or the second compensation capacitor C c,a The differential sampling amplifier Amp output is connected in parallel with the integrating capacitor Cint, so that the charge carried away by the feedback capacitor array can be fully compensated.

[0104] Specifically, when the feedback capacitor array (including the capacitor itself) is disconnected from the integrating capacitor Cint, the capacitor array carries away some of the integrating charge on the integrating capacitor Cint, causing the integration of the feedback signal to become lossy integration. To compensate for the charge carried away by the feedback capacitor array, this embodiment proposes introducing two capacitors with values ​​of (2...)... Ν -1)C fb0 The first compensation capacitor C c,b The second compensation capacitor C c,a The charge compensation circuit 40 in Figure 5 is used to compensate for the charge carried away by the feedback capacitor array.

[0105] The specific compensation procedure is illustrated in Figure 5 below:

[0106] For example, as shown in Figure 5, when the first control signal Φ1 is high (the switch controlled by the first control signal Φ1 is turned on), the second compensation capacitor C c,a The first compensation capacitor C is connected in parallel with the integrating capacitor Cint. c,b The amplifier Amp differential output in the active RC integrator is charged to a voltage value (V). o1+ )-(V o1- ).

[0107] For example, as shown in Figure 5, when the first control signal Φ1 changes from high level to low level (this moment is denoted as t1), the second feedback capacitor array B and the second compensation capacitor C c,a Both are disconnected from the integrating capacitor Cint, and the charges they take away from the integrating capacitor Cint are respectively: (2 Ν -1)C fb0 ·V o1+ (t1) and C c，a ·V o1+ (t1); At the same time, at time t1, the first compensation capacitor C c,b Disconnect from the differential output terminal of amplifier Amp, first compensation capacitor C c,b The charge deposited on top is C c，b ·(V o1+ (t1)-V o1- (t1))=Cc，b • 2V o1+ (t1), because for the signal, the two voltage amplitudes of the differential output of the full differential amplifier Amp are equal, with a phase difference of 180 degrees, i.e. V o1+ (t1) = -V o1- (t1).

[0108] As an example, as shown in Fig. 5, when the second control signal Φ2 changes from low to high, the first feedback capacitor array A is connected in parallel with the integration capacitor Cint, and the first compensation capacitor C c,b is also connected in parallel with the integration capacitor Cint, and the amount of charge deposited thereon is C c，b • 2V o1+ (t1) is brought into the loop filter, and because C c，b • 2V o1+ (t1) is equal to the amount of charge taken away by the second feedback capacitor array B and the second compensation capacitor C c,a from the loop filter before the first control signal Φ1 changes from high to low. c，b • 2V o1+ (t1) = (2 Ν -1)C fb0 • V o1+ (t1) + C c，a • V o1+ (t1), the first compensation capacitor C c,b completely compensates for the amount of charge taken away by the second feedback capacitor array B and the second compensation capacitor C c,a .

[0109] Similarly, in the next half clock cycle, the second compensation capacitor C c,a will, after being charged differentially at the output of the amplifier Amp, completely compensate for the amount of charge taken away by the first feedback capacitor array A and the first compensation capacitor C c,b .

[0110] In summary, in one complete clock cycle, because the charge compensation circuit 40 introduced above is adopted, it is equivalent to no charge being taken away from the loop filter by the first feedback capacitor array A, the second feedback capacitor array B, or the first compensation capacitor C c,b , the second compensation capacitor C c,a , and the integration of the feedback signal in one complete clock cycle is equivalent to lossless integration.

[0111] When using the conventional feedback technology, the lower the bit number of the quantizer 10 in the CTΔΣADC, the higher the power consumption of the amplifier Amp in the first stage of the loop filter needs to be, on the premise of obtaining the same linearity; when using a 1-bit quantizer, the power consumption of the amplifier Amp in the first stage of the loop filter needs to be the highest. The embodiments of the present disclosure are also applicable to the CTΔΣADC using a 1-bit quantizer 10, and FIG. 6a is an embodiment of the technical solution of the present disclosure for a 1-bit CTΔΣADC (designed as a fully differential circuit implementation, and the feedback technical solution proposed in the present disclosure in FIG. 6a only shows a single-ended circuit implementation), which is exemplarily introduced as follows.

[0112] Please refer to FIG. 6a, which shows a schematic diagram of an analog-to-digital converter using a 1-bit quantizer 10 according to an embodiment of the present disclosure. Please refer to FIG. 6b, which shows a timing diagram of the analog-to-digital converter in FIG. 6a.

[0113] In a possible implementation, as shown in FIG. 6a and FIG. 6b, the quantizer 10 is a 1-bit quantizer, and the analog-to-digital converter further includes an SR latch SR1, a first D flip-flop DFF1, a second D flip-flop DFF2, the first feedback capacitor array A and the second feedback capacitor array B each including one capacitor component 210 and one feedback charging loop, wherein,

[0114] the positive output end and the negative output end of the quantizer 10 are connected to the S end and the R end of the SR latch SR1 respectively,

[0115] the Q output end of the SR latch SR1 is connected to the D input end of the first D flip-flop DFF1,

[0116] the clock signal input end of the first D flip-flop DFF1 is used to input a first clock signal (CK DF,1 ), the Q output end of the first D flip-flop DFF1 is connected to the D input end of the second D flip-flop DFF2, and the output signal of the Q output end of the first D flip-flop DFF1 is also output to the control end of the multiplexer (MUX1) of the second feedback capacitor array B,

[0117] the clock signal input end of the second D flip-flop DFF2 is used to input a second clock signal (CK DF,2 ), and the output signal of the Q output end of the second D flip-flop DFF2 is output to the control end of the multiplexer (MUX2) of the first feedback capacitor array A,

[0118] The first clock signal and the second clock signal are non-overlapping signals (see FIG. 6b), and a falling edge of the first clock signal is separated from a rising edge of the second control signal Φ2 by a first preset time length (△t inv ), and a rising edge of the second clock signal is separated from a falling edge of the first control signal Φ1 by the first preset time length.

[0119] The first preset time length (△t inv ) is not limited in size, and can be set according to actual conditions and needs by those skilled in the art, for example, the first preset time length (△t inv ) can be a delay time length of an inverter.

[0120] In a possible implementation, the first compensation capacitor Cc,b, the second compensation capacitor Cc,a, a feedback capacitor Cfb,a in the first feedback capacitor array A, and a feedback capacitor Cfb,b in the second feedback capacitor array B have equal capacitance sizes.

[0121] In the example shown in FIG. 6a, the first D flip-flop DFF1 and the second D flip-flop DFF2 are added to achieve data retention (for example, for 1.5 clock cycles) of the quantization result of the quantizer output.

[0122] Referring to FIGS. 6a and 6b, the specific operation of the analog-to-digital converter using the 1-bit quantizer 10 according to the embodiment of the present disclosure is as follows:

[0123] (1) At a rising edge of the sampling clock fs of the 1-bit quantizer 10 (that is, at time t0 in FIG. 6b), the loop filter output is sampled by the 1-bit quantizer 10 and compared, and the comparison result D0 is stored in the SR latch SR1. The stored comparison result D0 is stored in the first D flip-flop DFF1 at a rising edge of the first clock signal (CK DF,1 ), and the first D flip-flop DFF1 outputs D1.

[0124] (2) At time t1 when the first control signal Φ1 changes from low to high, the feedback capacitor C fb，b begins to be charged to the reference voltage Vref+ or Vref- determined by the quantization result, and during the period when the first control signal Φ1 is high, the second clock signal (CK DF,2 ) changes from low to high, and D1 is stored in the second D flip-flop DFF2 to output D2. At the same time, the first compensation capacitor C c,b is charged at the differential output end of the amplifier Amp of the first stage of the loop filter. At this time, the feedback capacitor C fb，a and the second compensation capacitor C c,a are connected in parallel with the integration capacitor Cint.

[0125] (3) At the moment t2 when the second control signal Φ2 changes from low level to high level, the feedback capacitor C fb，b in parallel with the integration capacitor Cint, injects 1 / 2 of the charge corresponding to the comparison result of the current cycle quantizer 10 into the loop filter; at the same time, the feedback capacitor C fb，a begins to be charged to the reference voltage Vref+ or Vref- determined by the quantization result of this cycle. The first compensation capacitor C c,b in parallel with the integration capacitor Cint, compensates for the charge taken away by the feedback capacitor C fb，a and the second compensation capacitor C c,a . During the period when the second control signal Φ2 is high, the second compensation capacitor C c,a is charged at the differential output end of the amplifier Amp of the first stage of the loop filter.

[0126] (4) At the moment t3 when the first control signal Φ1 changes from low level to high level again, the feedback capacitor C fb，a in parallel with the integration capacitor Cint, injects the remaining 1 / 2 of the charge corresponding to the comparison result of the current cycle quantizer 10 into the loop filter; at the same time, the second compensation capacitor C c,a in parallel with the integration capacitor Cint, compensates for the charge taken away by the feedback capacitor C fb，b and the first compensation capacitor C c,b . At this point, the feedback signal corresponding to the output of the loop filter at the moment t0 is completely injected into the loop filter, and the charges taken away by the feedback capacitor C fb，a , the feedback capacitor C fb，b and the first compensation capacitor C c,b , the second compensation capacitor C c,a are also completely compensated back into the loop filter, that is, the complete feedback is completed.

[0127] The feedback technology proposed in the embodiments of the present disclosure has the following three advantages in the technical field:

[0128] 1. The power consumption of the amplifier Amp in the first stage of the loop filter is greatly reduced, and the power consumption of the amplifier Amp usually accounts for the largest proportion in the total power consumption of the low quantization bit CTΔΣADC, so the total power consumption of the low quantization bit CTΔΣADC can be reduced and its energy efficiency can be improved by using the feedback technology. The amplifier Amp in the first stage of the loop filter does not need to process high-frequency and high-amplitude feedback signals caused by low quantization bits, but only needs to process relatively low-frequency and relatively small-amplitude ADC input signals, so its power consumption is greatly reduced compared with when the traditional feedback technology is used.

[0129] 2. Not sensitive to clock jitter, thus saving the high power consumption overhead needed to generate and transmit low-jitter clock when using traditional feedback techniques.

[0130] 3. Not sensitive to inter-symbol interference (ISI), thus not requiring extra area and power consumption overhead to mitigate non-linearity caused by ISI, which is especially significant in 1-bit CTΔΣADC, because ISI is (one of) the main sources of non-linearity in 1-bit CTΔΣADC.

[0131] In terms of application, the feedback technique proposed by the embodiments of the present disclosure can significantly reduce the power consumption of CTΔΣADC with low quantization bit number; and the quantization bit number is generally low in wideband CTΔΣADC with a sampling frequency generally in the order of GHz. Such wideband CTΔΣADC is usually used in portable communication devices; the advantage of the feedback technique proposed by the embodiments of the present disclosure in significantly reducing the power consumption of the wideband CTΔΣADC is conducive to prolonging the use time of the portable communication device after each charging. The embodiments of the present disclosure can achieve the same high energy efficiency as CTΔΣADC with multi-bit quantization number for 1-bit CTΔΣADC, but avoid the shortcomings of DAC linearity needing calibration, quantizer 10 offset needing calibration, and multi-bit quantizer 10 driving difficulty in multi-bit quantization CTΔΣADC.

[0132] As can be seen from the above introduction, the embodiments of the present disclosure better solve the two problems existing in the feedback technique of CTΔΣADC:

[0133] (1) The existing feedback technique needs to rely on a high-power amplifier Amp to let the feedback signal enter the loop filter,

[0134] (2) Some existing feedback techniques are highly sensitive to clock jitter.

[0135] The embodiments of the present disclosure reduce the total power consumption of low-bit CTΔΣADC and improve its energy efficiency by avoiding the use of an amplifier Amp in the process of the feedback signal entering the loop filter and using a feedback technique with low sensitivity to clock jitter.

[0136] According to an aspect of the present disclosure, an electronic device is provided, the electronic device comprising the analog-to-digital converter.

[0137] The specific type of electronic device is not limited by the embodiments of the present disclosure, and the electronic device can include a terminal device, where the terminal device can be a user equipment (UE), a mobile device, a user terminal, a terminal, a handheld device, a computing device, or a vehicle-mounted device, etc. For example, the terminal can be a mobile phone, a tablet computer, a notebook computer, a palm computer, a mobile Internet device (MID), a wearable device, a virtual reality (VR) device, an augmented reality (AR) device, a wireless terminal in industrial control, a wireless terminal in self-driving, a wireless terminal in remote medical surgery, a wireless terminal in smart grid, a wireless terminal in transportation safety, a wireless terminal in smart city, a wireless terminal in smart home, a wireless terminal in Internet of Vehicles, etc. For example, the server can be a local server or a cloud server.

[0138] The above has described the embodiments of the present disclosure, and the above description is exemplary, not exhaustive, and is not limited to the disclosed embodiments. Many modifications and changes are obvious to those skilled in the art without departing from the scope and spirit of the described embodiments. The selection of the terms used herein is intended to best explain the principles of the embodiments, practical application, or improvement of the technology in the market, or to enable other ordinary skilled persons in the art to understand the embodiments disclosed herein.

Claims

1. An analog-to-digital converter, characterized by The analog-digital converter comprises an input resistor, an amplifier, an integration capacitor, a quantizer, a feedback capacitor module and a control module, wherein, a first end of the input resistor is configured to receive an input analog voltage, and a second end of the input resistor is connected to an input end of the amplifier, a first end of the integration capacitor and the feedback capacitor module, an output end of the amplifier is connected to an input end of the quantizer, a second end of the integration capacitor and the feedback capacitor module, an output end of the quantizer is connected to the control module, the control module is further connected to the feedback capacitor module, and the control module is configured to control the feedback capacitor module to periodically perform a charging operation and a feedback operation according to a received timing control signal and a quantization signal output by the quantizer, wherein in the charging operation, the control module controls a capacitor in the feedback capacitor module to be disconnected from the integration capacitor and charges the feedback capacitor module, in the feedback operation, the control module controls the capacitor in the feedback capacitor module to be connected in parallel to the integration capacitor, and the feedback capacitor module and the integration capacitor perform charge sharing to complete the feedback operation.

2. The analog-to-digital converter of claim 1, wherein, The feedback capacitor module comprises at least one feedback capacitor array, each feedback capacitor array comprises a first connection switch, a second connection switch and at least one capacitor component, and the capacitor component comprises a feedback capacitor and a feedback control switch, for any capacitor component: a first end of the feedback capacitor is connected to a first end of the first connection switch and a first end of the second connection switch, a second end of the first connection switch is connected to a first end of the integration capacitor, and a second end of the second connection switch is configured to receive a first preset voltage, a second end of the feedback capacitor is connected to a first end of the feedback control switch, and a second end of the feedback control switch is connected to a second end of the integration capacitor.

3. The analog-to-digital converter of claim 2, wherein, The control module comprises a plurality of charging switch units, each charging switch unit comprises a charging control switch and a multiplexing switch, wherein one charging switch unit and one capacitor component form a feedback charging loop, for any feedback charging loop: a control end of the multiplexing switch is configured to receive a corresponding bit of the quantization signal, a first input end of the multiplexing switch is configured to receive a first reference voltage, and a second input end of the multiplexing switch is configured to receive a second reference voltage, the first reference voltage and the second reference voltage are different in polarity, an output end of the multiplexing switch is connected to a first end of the charging control switch, a second end of the charging control switch is connected to a second end of the feedback capacitor in the capacitor component and a first end of the feedback control switch, wherein a control signal of the charging control switch is the same as a control signal of the second connection switch.

4. The analog-to-digital converter of claim 3, wherein, The feedback capacitor array comprises a first feedback capacitor array and a second feedback capacitor array, a duty cycle of the control signal is less than 1 / 2, the control signal comprises a first control signal and a second control signal, and the first control signal and the second control signal are non-overlapping signals, wherein In the first feedback capacitor array, the second connection switch is controlled by the first control signal, the first connection switch and each feedback control switch are controlled by the second control signal, and each charging control switch corresponding to the first feedback capacitor array is controlled by the first control signal; In the second feedback capacitor array, the second connection switch is controlled by the second control signal, the first connection switch and each feedback control switch are controlled by the first control signal, and each charging control switch corresponding to the second feedback capacitor array is controlled by the second control signal.

5. The analog-to-digital converter of claim 4, wherein, For one clock cycle of the sampling clock signal, the rising edge and the falling edge of the first control signal are between the rising edge and the falling edge of the clock cycle, the rising edge and the falling edge of the second control signal are between the falling edge and the rising edge of the clock cycle, and the duty cycle of the sampling clock signal is 1 / 2.

6. The analog-to-digital converter of claim 4, wherein, The analog-to-digital converter further comprises a charge compensation circuit, the charge compensation circuit comprising a first compensation switch, a second compensation switch, a third compensation switch, a fourth compensation switch, a first compensation capacitor, and a second compensation capacitor, wherein a first end of the first compensation switch is connected to a second end of the input resistor, a first end of the fourth compensation switch, a negative input end of the amplifier, and a first end of the integration capacitor through the second compensation switch, and a positive input end of the amplifier is used to receive a second preset voltage, a second end of the first compensation switch is connected to a first end of the third compensation switch and a negative output end of the amplifier, a first end of the first compensation capacitor is connected to the first end of the first compensation switch, and a second end of the first compensation capacitor is connected to a first end of the second compensation capacitor, a positive output end of the amplifier, and a second end of the integration capacitor, a second end of the third compensation switch is connected to a second end of the fourth compensation switch and a second end of the second compensation capacitor, wherein the first compensation switch and the fourth compensation switch are controlled by the first control signal, and the second compensation switch and the third compensation switch are controlled by the second control signal.

7. The analog-to-digital converter of claim 6, wherein, Capacitance sizes of the first compensation capacitor and the second compensation capacitor are (2 N -1) times a unit capacitance size of the feedback capacitor, where N is a precision of the quantizer.

8. The analog-to-digital converter of claim 6, wherein, The quantizer is a 1-bit quantizer, and the analog-to-digital converter further comprises an SR latch, a first D flip-flop, and a second D flip-flop, and each of the first feedback capacitor array and the second feedback capacitor array comprises one capacitor component and one feedback charging loop, wherein a positive output end and a negative output end of the quantizer are connected to an S end and an R end of the SR latch, respectively, a Q output end of the SR latch is connected to a D input end of the first D flip-flop, a clock signal input end of the first D flip-flop is used to input a first clock signal, a Q output end of the first D flip-flop is connected to a D input end of the second D flip-flop, and an output signal of the Q output end of the first D flip-flop is also output to a control end of a multiplexing switch of the second feedback capacitor array, The clock signal input end of the second D flip-flop is used for inputting a second clock signal, and an output signal of a Q output end of the second D flip-flop is output to a control end of a multiplexing switch of the first feedback capacitor array, The first clock signal and the second clock signal are non-overlapping signals, a falling edge of the first clock signal and a rising edge of the second control signal are separated by a first preset time length, and a rising edge of the second clock signal and a falling edge of the first control signal are separated by the first preset time length.

9. The analog-to-digital converter of claim 6, wherein, Capacitance sizes of the first compensation capacitor, the second compensation capacitor, feedback capacitors in the first feedback capacitor array and feedback capacitors in the second feedback capacitor array are equal.

10. An electronic device, comprising: The electronic device comprises the analog-to-digital converter as claimed in any one of claims 1-9.

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