Power domain management circuit and system-on-chip

Abstract

The present disclosure relates to a power domain management circuit and a system-on-chip. The power domain management circuit comprises: an enabling unit, configured to generate an enabling signal having a first preset level upon reception of an isolated set signal, or generate an enabling signal having a second preset level upon reception of a reset indication signal; and a clamping unit, electrically connected to the enabling unit, the clamping unit being configured to, upon reception of the enabling signal having the first preset level, clamp an initial signal transmitted from a first power domain to a second power domain, so as to generate a target signal having a third preset level, or upon reception of the enabling signal having the second preset level, not clamp the initial signal, so as to generate a target signal having a level that changes with the level of the initial signal.

Description

Power domain management circuit and system on chip

[0001] Cross-reference to related applications

[0002] This application is based on and claims priority to Chinese Patent Application No. 202411380168.X, filed on September 29, 2024, the disclosure of which is incorporated herein in its entirety. TECHNICAL FIELD

[0003] The present disclosure relates to the technical field of electronic circuit, and more particularly, to a power domain management circuit and system on chip. BACKGROUND

[0004] In an integrated circuit chip, in order to reduce the running power consumption, multiple power domains can be designed according to needs, and the opening and closing of the corresponding power domains are controlled. In addition, there can be signal interaction between different power domains. In order to ensure the normal work of each power domain, it is necessary to manage the signal isolation or interaction state between the power domains. SUMMARY

[0005] One of the purposes of the present disclosure is to provide a power domain management circuit and system on chip.

[0006] According to a first aspect of the present disclosure, a power domain management circuit is provided, comprising:

[0007] an enabling unit configured to generate an enabling signal having a first preset level if a isolation set signal is received, or generate an enabling signal having a second preset level if a reset indication signal is received, wherein the second preset level is different from the first preset level; and

[0008] a clamping unit electrically connected with the enabling unit, and the clamping unit is configured to clamp an initial signal transmitted from a first power domain to a second power domain to generate a target signal having a third preset level if the enabling signal having the first preset level is received, or not clamp the initial signal to generate a target signal having a level varying with the level of the initial signal if the enabling signal having the second preset level is received, wherein the third preset level is the same as or different from the first preset level.

[0009] In some embodiments, the isolation set signal is configured to be generated before the first power domain is powered down relative to the second power domain; or

[0010] the reset indication signal is configured to be generated after the first power domain is powered on relative to the second power domain and in a power-on stable state.

[0011] In some embodiments, the reset indication signal is configured to reset at least part of circuit components in the first power domain after the first power domain is powered on relative to the second power domain.

[0012] In some embodiments, the enabling unit comprises a first register.

[0013] In some embodiments, a reset trigger end of the first register is configured to receive the reset indication signal, and an output end of the first register is configured to output the enabling signal.

[0014] In some embodiments, the clamping unit comprises a first clamping unit, and the initial signal comprises a clock signal;

[0015] a first input end of the first clamping unit is configured to receive the enabling signal, a second input end of the first clamping unit is configured to receive the clock signal, and an output end of the first clamping unit is electrically connected to a clock trigger end of the first register.

[0016] In some embodiments, the clamping unit comprises a second clamping unit, the initial signal comprises an isolation setting signal, and the target signal comprises the isolation set signal generated according to the enabling signal and the isolation setting signal;

[0017] a first input end of the second clamping unit is configured to receive the enabling signal, a second input end of the second clamping unit is configured to receive the isolation setting signal, and an output end of the second clamping unit is electrically connected to an input end of the first register to transmit the isolation set signal to the first register.

[0018] In some embodiments, the power domain management circuit further comprises:

[0019] a state control unit, the state control unit is electrically connected to the enabling unit, and the state control unit is configured to generate a state control signal for transmission to the first power domain according to the enabling signal.

[0020] In some embodiments, the state control unit comprises a first multiplexer, a selection control end of the first multiplexer is electrically connected to an output end of the enabling unit, each of a plurality of input ends of the first multiplexer is configured to receive a corresponding state control signal, and an output end of the first multiplexer is configured to output a state control signal selected according to the enabling signal.

[0021] In some embodiments, the state control unit comprises a second register, the clamp unit comprises a first clamp unit and a third clamp unit, the initial signal comprises an input control signal, and the target signal comprises a state indication signal generated according to the enable signal and the input control signal.

[0022] The reset trigger end of the second register is configured to receive the reset indication signal.

[0023] The first input end of the first clamp unit is configured to receive the enable signal, the second input end of the first clamp unit is configured to receive the clock signal, and the output end of the first clamp unit is electrically connected to the clock trigger end of the second register; or

[0024] The first input end of the third clamp unit is configured to receive the enable signal, the second input end of the third clamp unit is configured to receive the input control signal, and the output end of the third clamp unit is electrically connected to the input end of the second register to transmit the state indication signal to the second register.

[0025] In some embodiments, the second register is configured to generate a state control signal corresponding to the input control signal when the state indication signal is received, or generate a state control signal corresponding to a normal working state when the reset indication signal is received.

[0026] In some embodiments, the state control unit further comprises a delay module, the output end of the second register is electrically connected to the input end of the delay module, and the delay module is configured to delay the state indication signal.

[0027] In some embodiments, the delay module comprises a second multiplexer, the selection control end of the second multiplexer is electrically connected to the output end of the enable unit, one input end of the second multiplexer is electrically connected to the output end of the second register, and the output end of the second multiplexer is configured to output a state control signal selected according to the enable signal.

[0028] In some embodiments, the other input end of the second multiplexer is configured to receive a state control signal corresponding to a normal working state.

[0029] In some embodiments, the state control signal comprises at least one of:

[0030] a state control signal configured to maintain power supply of a memory array of a static random access memory in the first power supply domain;

[0031] a state control signal configured to maintain power supply of input and output of an input and output unit in the first power supply domain;

[0032] a state control signal configured to maintain an analog circuit component in the first power supply domain in a shutdown state or a standby state; or

[0033] a state control signal configured to enable the first power supply domain to be in a normal working state.

[0034] In some embodiments, the power supply domain management circuit further comprises:

[0035] a power-on identification unit configured to identify whether the current power-on of the first power supply domain is a first power-on or a power-on after hibernation.

[0036] In some embodiments, the power-on identification unit comprises a latch configured to receive a power-on indication signal from a power supply source and generate a power-on identification signal for identifying whether the current power-on of the first power supply domain is a first power-on or a power-on after hibernation according to the reset indication signal and the power-on indication signal.

[0037] In some embodiments, the clamping unit comprises:

[0038] a AND gate circuit, a first input end of the AND gate circuit is configured to receive the enable signal, a second input end of the AND gate circuit is configured to receive the initial signal, and an output end of the AND gate circuit is configured to output the target signal, wherein the first preset level is a low level and the second preset level is a high level; or

[0039] a OR gate circuit, a first input end of the OR gate circuit is configured to receive the enable signal, a second input end of the OR gate circuit is configured to receive the initial signal, and an output end of the OR gate circuit is configured to output the target signal, wherein the first preset level is a high level and the second preset level is a low level.

[0040] In some embodiments, the power supply domain management circuit is arranged in the second power supply domain.

[0041] According to a second aspect of the present disclosure, there is provided a system on chip having a first power supply domain and a second power supply domain, and the system on chip comprises the power supply domain management circuit as described above.

[0042] In some embodiments, the system on chip further comprises:

[0043] a power supply source configured to supply power to the first power supply domain and the second power supply domain.

[0044] Other features of the present disclosure, and its advantages will become apparent in the detailed description of exemplary embodiments of the present disclosure given below with reference to the accompanying drawings, of which: BRIEF DESCRIPTION OF DRAWINGS

[0045] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the present disclosure and, together with the description, serve to explain the principles of the present disclosure.

[0046] The present disclosure can be understood more readily by reference to the following detailed description of exemplary embodiments of the present disclosure and the attached drawings, of which:

[0047] FIG. 1 shows a block diagram of a system-on-chip according to an exemplary embodiment of the present disclosure;

[0048] FIG. 2 shows a circuit schematic diagram of a power domain management circuit according to a specific embodiment of the present disclosure;

[0049] FIG. 3 shows a timing diagram of an isolation setup signal, a power supply signal for powering a first power domain, and a reset indication signal in a process of powering down and powering up the first power domain using the power domain management circuit of FIG. 2;

[0050] FIG. 4 shows a circuit schematic diagram of a state control unit in a power domain management circuit according to a specific embodiment of the present disclosure;

[0051] FIG. 5 shows a circuit schematic diagram of a power domain management circuit according to another specific embodiment of the present disclosure;

[0052] FIG. 6 shows a circuit schematic diagram of a state control unit and an associated clamp unit in a power domain management circuit according to a specific embodiment of the present disclosure;

[0053] FIG. 7 shows a circuit schematic diagram of a state control unit and an associated clamp unit in a power domain management circuit according to another specific embodiment of the present disclosure;

[0054] FIG. 8 shows a timing diagram of a power up indication signal, a reset indication signal, and a power up identification signal in a power domain management circuit according to a specific embodiment of the present disclosure.

[0055] Note that, in the following embodiments, the same reference numerals are sometimes used across different drawings to indicate the same or similar parts or parts having the same function, and repeated description thereof is omitted. In this specification, similar reference numerals and letters are used to denote similar items, and therefore, once an item is defined in one drawing, it need not be discussed further in subsequent drawings.

[0056] For ease of understanding, the positions, sizes, ranges, and the like of the structures shown in the drawings and the like are sometimes not actual positions, sizes, ranges, and the like. Therefore, the disclosed application is not limited to the positions, sizes, ranges, and the like disclosed in the drawings and the like. Further, the drawings are not necessarily drawn to scale, and some features can be exaggerated to show details of specific components. DETAILED DESCRIPTION

[0057] Various exemplary embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. Note that the relative arrangement of the components and steps, numerical expressions, and numerical values set forth in these embodiments are not limiting of the scope of the present disclosure unless otherwise specifically stated.

[0058] The following description of at least one exemplary embodiment is merely illustrative in nature and is in no way intended to limit the scope of the disclosure or its application or uses. That is, the structures and methods herein are shown by way of example in the drawings and detailed description, to illustrate various embodiments of the structures and methods in the present disclosure. However, those skilled in the art will recognize that they are merely illustrative of exemplary ways in which the present disclosure can be implemented, rather than an exhaustive list. Further, the drawings are not necessarily drawn to scale, and some features can be exaggerated to show details of specific components.

[0059] In addition, techniques, methods, and devices known to those of ordinary skill in the relevant art can not be discussed in detail herein, but should be considered as part of the specification, where appropriate.

[0060] In all examples shown and discussed herein, any specific values should be interpreted as merely illustrative, and not as a limitation. Thus, other examples of the exemplary embodiments can have different values.

[0061] In an integrated circuit chip or a System On Chip (SOC), a plurality of power domains can be provided, wherein the turning on or off (powering up or down) of different power domains can be controlled individually, so that the corresponding power domains can be dynamically switched on or off according to specific working scenarios, thereby helping to save the energy consumption of the circuit or chip. In a kind of circuit system, power supply can be realized by power supply source. In some examples, as shown in Figure 1, power supply source 200 such as power supply chip (PMIC) can be provided independently of SOC 10. Alternatively, in other examples, the power supply source can also be provided inside the SOC.

[0062] The SOC can have at least two power domains. In the present specification, as shown in FIG. 1, the SOC 10 is taken as an example having a first power domain 11 and a second power domain 12, and the technical solutions of the present disclosure will be described in detail, however, it can be understood that the SOC can have more power domains according to needs, which are not limited herein. In the present specification, it is assumed that the first power domain 11 is a power-off domain relative to the second power domain 12, and the second power domain 12 is a power-on domain relative to the first power domain 11, in other words, in the case that the first power domain 11 is in a power-on state, the second power domain 12 is also in a power-on state, while in the case that the second power domain 12 is in a power-on state, the first power domain 11 can be in a power-on state in part of the period and in a power-off state in another part of the period. Then, in the case that the power supply states of the first power domain 11 and the second power domain 12 are inconsistent, it is usually necessary to isolate the signal interaction between the two power domains, so as to avoid, for example, the transmission of uncertain signals from the power-off domain to the power-on domain, affecting the normal work of the power-on domain; while in the case that the first power domain 11 and the second power domain 12 are both in a power-on state, it is usually necessary to remove the signal isolation between them, so that the necessary signal interaction between different power domains can be carried out, so that the SOC can normally run.

[0063] In an exemplary embodiment, the signal isolation or interaction between the power domains can be controlled by setting a power domain management circuit (PMU). For example, as shown in FIG. 1, the SOC 10 can include a power domain management circuit 100. Alternatively, in some other embodiments, the power domain management circuit can also be set independently of the SOC, which is not limited herein. In addition, in some embodiments, the power domain management circuit 100 can be set in the second power domain 12, so as to manage the signal isolation or interaction state between different power domains at any time as needed, for example, in the case that the first power domain 11 is powered off, the power domain management circuit 100 set in the second power domain 12 can still normally run. In an exemplary embodiment, as shown in FIG. 1, the power domain management circuit 100 can include an enabling unit 110 and a clamping unit 120.

[0064] The enabling unit 110 can be configured to generate an enabling signal having a first preset level in the case of receiving an isolation set signal. Alternatively, the enabling unit 110 can be configured to generate an enabling signal having a second preset level in the case of receiving a reset indication signal. Here, the second preset level is different from the first preset level, so as to distinguish different working states. For example, in the case that the first preset level is a low level (represented by 0), the second preset level can be a high level (represented by 1); while in the case that the first preset level is a high level, the second preset level can be a low level. Wherein, the isolation set signal can be used to control the setting of the enabling signal, which will be described in detail below.

[0065] The clamping unit 120 can be electrically connected with the enabling unit 110, so as to determine whether to clamp the signal transmitted from the first power domain 11 to the second power domain 12 according to the enabling signal from the enabling unit 110, to realize the signal isolation or interaction between the first power domain 11 and the second power domain 12. Specifically, the clamping unit 120 can be configured to clamp the initial signal transmitted from the first power domain 11 to the second power domain 12 to generate a target signal with a third preset level in the case of receiving an enabling signal with a first preset level, or in response to an isolation set signal. Here, the third preset level can be the same as or different from the first preset level, that is, the specific form of the third preset level is not limited, which can be a high level, a low level, or a preset combination of high and low levels (such as 101, 110, etc.), as long as it is independent of the change of the initial signal level and is known or fixed in advance, so as to realize the isolation of the signal. Alternatively, the clamping unit 120 can be configured to not clamp the initial signal to generate a target signal with a level that changes with the level of the initial signal in the case of receiving an enabling signal with a second preset level, or in response to a reset indication signal. For example, in a specific example, the target signal can be the same as the initial signal, that is, in response to the reset indication signal, the clamping unit 120 can directly transmit the initial signal as the target signal to the second power domain 12, so as to realize the signal interaction between the first power domain 11 and the second power domain 12. Alternatively, according to the specific application needs, the clamping unit 120 can also process the initial signal, for example, invert the initial signal, etc., to generate a target signal with a level that changes with the level of the initial signal but is different from the initial signal to be transmitted to the second power domain 12. It can be understood from the above description that, in response to the reset indication signal, although the target signal is not necessarily completely the same as the initial signal, the change of the level of the target signal is usually associated with the change of the level of the initial signal, which is equivalent to realizing the interaction of the signals between the first power domain 11 and the second power domain 12.

[0066] In some embodiments, the isolation set signal can be configured to be generated before the first power domain 11 is powered off relative to the second power domain 12, so that the signal isolation between the first power domain 11 and the second power domain 12 is completed before the first power domain 11 is powered off, avoiding the transmission of uncertain signals in the first power domain 11 to the second power domain 12, so as to ensure the normal operation of the SOC 10. In addition, the reset indication signal can be configured to be generated after the first power domain 11 is powered on relative to the second power domain 12, and further, the reset indication signal can be configured to be generated after the first power domain 11 is powered on and has reached a power-on stable state, so as to restore the signal interaction between the first power domain 11 and the second power domain 12, thereby ensuring the normal operation of the SOC 10.

[0067] In some embodiments, for example in the case of containing digital circuit components in the first power domain 11, the reset indication signal can also be configured to reset at least part of the circuit components (e.g. digital circuit components and / or analog circuit components that need to be reset, etc.) in the first power domain 11 after the first power domain 11 is powered on relative to the second power domain 12, so as to eliminate the adverse effects of uncertain or incorrect signal states on the SOC 10.

[0068] In some embodiments, the enable unit 110 can be implemented by using a sequential logic circuit to generate the desired enable signal according to the isolation set signal or the reset indication signal. For example, the enable unit 110 can include a register, a latch or a combination thereof, etc. On the other hand, the clamping unit 120 can be implemented by using a combinational logic circuit to generate the desired target signal according to the enable signal and the initial signal. For example, the clamping unit 120 can include an AND gate circuit, an OR gate circuit, a NOT gate circuit or a combination thereof, etc.

[0069] In a specific embodiment, as shown in FIG. 2, the enable unit 110 can include a first register 111, which can have a reset trigger end, a clock trigger end, an input end and an output end.

[0070] In addition, the clamping unit 120 can be formed by an AND gate circuit, a first input end of the AND gate circuit can be configured to receive the enable signal, a second input end of the AND gate circuit can be configured to receive the initial signal, and an output end of the AND gate circuit can be configured to output the target signal, i.e. the target signal can be the AND operation result of the enable signal and the initial signal. Accordingly, in order to effectively control the signal isolation or interaction between the power domains, the first preset level can be a low level and the second preset level can be a high level. In this way, by means of the AND gate circuit, in response to the isolation set signal, the initial signal can be clamped to a low level under the action of the enable signal, thereby realizing the signal isolation between the power domains; while in response to the reset indication signal, the initial signal can not be clamped by the enable signal in a high level state, but can be output from the output end of the AND gate circuit as is or substantially as is, thereby realizing the signal interaction between the power domains.

[0071] In addition, as needed, the power domain management circuit 100 can include one or more clamping units 120. In the specific embodiment shown in FIG. 2, the clamping units 120 of the power domain management circuit 100 can include a first clamping unit 121 and a second clamping unit 122. Among them, the initial signal input to the first clamping unit 121 can include a clock signal (clk), and the initial signal input to the second clamping unit 122 can include an isolation setting signal (set_iso).

[0072] In the specific embodiment shown in FIG. 2, the reset trigger end of the first register 111 can be configured to receive a reset indication signal (rst n), and the output end of the first register 111 can be configured to output an enable signal (iso en). The reset indication signal (rst n) can be derived from the reset pin 300. In some embodiments, the reset pin 300 can be integrated in the second power domain 12, so that even in the case of power-off of the first power domain 11, the reset indication signal can still be generated to restore the signal interaction between the power domains.

[0073] As shown in FIG. 2, the first input end of the first clamping unit 121 can be configured to receive the enable signal (iso en), the second input end of the first clamping unit 121 can be configured to receive the clock signal (clk), and the output end of the first clamping unit 121 can be electrically connected to the clock trigger end of the first register 111. In this way, when the first power domain 11 is in the power-on state, the clock signal (clk) can be transmitted from the first power domain 11 to the second power domain 12 via the first clamping unit 121, thereby providing a clock in the second power domain 12; while in the case of power-off of the first power domain 11, the clock signal (clk) will be clamped to a low level by the first clamping unit 121, at which time the second power domain 12 can be in a clockless state, which helps to reduce the power consumption of the SOC 10.

[0074] As shown in FIG. 2, the first input end of the second clamping unit 122 can be configured to receive the enable signal (iso en), the second input end of the second clamping unit 122 can be configured to receive the isolation setting signal (set iso), and the output end of the second clamping unit 122 can be electrically connected to the input end of the first register 111 to enable the transmission of the isolation set signal to the first register 111, wherein the isolation set signal as the target signal can be generated according to the enable signal (iso en) and the isolation setting signal (set iso), for example, can be the AND operation result of the enable signal and the isolation setting signal.

[0075] As shown in FIG. 2 and FIG. 3, during the powering down of the first power domain 11, the isolation setting signal (set_iso) with a high level pulse can be first generated in the first power domain 11, for example, the isolation setting signal can be generated under the control of a circuit component such as a central processing unit (CPU) provided in the first power domain 11. At this time, since both the first power domain 11 and the second power domain 12 are in the power up state, the enable signal (iso_en) can be in the high level state, accordingly, the isolation setting signal (set_iso) will not be clamped by the second clamping unit 122, but can be transmitted from the first power domain 11 to the second power domain 12 via the second clamping unit 122, so that the input end of the first register 111 can receive the high level pulse. At the same time, the clock signal (clk) will not be clamped by the first clamping unit 121, but can be transmitted from the first power domain 11 to the second power domain 12 via the first clamping unit 121, so that the clock trigger end of the first register 111 can receive the clock signal. Further, under the triggering action of the rising or falling edge of the clock signal, based on the high level pulse received by the input end of the first register 111, the enable signal (iso_en) output from the output end of the first register 111 can be converted from the high level state to the low level state. Then, the enable signal (iso_en) in the low level state can make each clamping unit 120 clamp the initial signal from the first power domain 11 to the target signal with the third preset level, that is, the signal isolation between the first power domain 11 and the second power domain 12 is realized. After the signal isolation between the power domains has been completed, the power supply 200 can stop supplying power to the first power domain 11 (i.e. the power supply signal of the first power domain from the power supply can be converted to the low level state), thereby completing the powering down of the first power domain 11. As described above, in some embodiments, no local clock or clock signal can be provided in the second power domain 12, so that during the powering down of the first power domain 11 relative to the second power domain 12, the logic associated with the clock or clock signal in the second power domain 12 will not also flip, thereby helping to reduce the power consumption of the second power domain 12 or the entire SOC 10. In addition, in order to restore the power supply to the first power domain 11 in appropriate cases, the clock or clock signal can be provided in the power supply 200 to time the powering down state of the first power domain 11, or other circuit components can also be provided to monitor the appropriate power up opportunity and generate a corresponding signal to indicate the power up of the first power domain 11.

[0076] As shown in FIG. 2 and FIG. 3, during the power-on process of the first power domain 11, the first power domain 11 can be powered first by the power supply 200, and wait until the power supply state has stabilized (i.e., the power supply signal of the power supply to the first power domain is converted to a high level state and tends to be stable). At this time, the enable signal (iso_en) can be in a low level state, so the first power domain 11 and the second power domain 12 are still in a signal isolation state. Then, for example, a reset indication signal (rst_n) with a low level pulse can be generated by the reset pin 300 to trigger the enable signal (iso_en) output from the output end of the first register 111 to reset from a low level state to a high level state. For example, the reset indication signal (rst_n) with a low level pulse can be generated by the power supply chip by first pulling down the signal of the reset pin 300 and then pulling up the signal of the reset pin 300. Then, the enable signal (iso_en) in a high level state can cause each clamping unit 120 not to clamp the corresponding initial signal from the first power domain 11, i.e., each clamping unit 120 can output a corresponding target signal with a level that changes with the level of the corresponding initial signal, i.e., the signal interaction between the first power domain 11 and the second power domain 12 is realized. In addition, as described above, the reset indication signal (rst_n) with a low level pulse can also be transmitted to at least part of the circuit components (e.g., digital circuit components and / or analog circuit components that need to be reset, etc.) in the first power domain 11 to reset these circuit components, thereby ensuring their normal operation.

[0077] It can be understood that in other embodiments, other ways can also be used to set the enable unit 110 and the clamping unit 120, and in addition, the active level or active edge of one or more of the isolation set signal, the reset indication signal, the enable signal, the clock signal, the isolation set signal, etc. described above can also be changed, which is not limited herein.

[0078] For example, in other embodiments, the clamping unit 120 can be formed by an OR gate circuit, a first input end of the OR gate circuit can be configured to receive the enable signal, a second input end of the OR gate circuit can be configured to receive the initial signal, and an output end of the OR gate circuit can be configured to output the target signal, i.e., the target signal can be the OR operation result of the enable signal and the initial signal, and accordingly, in order to effectively control the signal isolation or interaction between the power domains, the first preset level can be a high level and the second preset level can be a low level. In this way, by means of the OR gate circuit, in response to the isolation set signal, the initial signal can be clamped to a high level under the action of the enable signal, thereby realizing the isolation between the power domains; and in response to the reset indication signal, the initial signal can not be clamped by the enable signal in a low level state, but can be output from the output end of the OR gate circuit, thereby realizing the signal interaction between the power domains.

[0079] In addition, in some embodiments, the clamping unit 120 can also be formed by two or more of various types of circuits, such as AND gate circuit, OR gate circuit, NOT gate circuit, etc., as needed, without limitation. For example, the clamping unit 120 can be formed by an AND gate circuit and a NOT gate circuit connected at the output end of the AND gate circuit, so that, compared with the clamping unit 120 shown in FIG. 2, the target signal can be inverted under the action of the NOT gate circuit to meet the specific application requirements.

[0080] In addition, the enabling unit 110 can also be triggered or reset in other ways or by other forms of signals (e.g., signals with different active levels or active edges) to generate the corresponding enabling signal, without limitation.

[0081] Further, in some embodiments, considering that at least part of the circuit components in the SOC 10 are usually in different working states in the case that the first power domain 11 is in the power-on state and the power-off state, respectively, in order to control these working states, as shown in FIGS. 1, 2 and 4-7, the power domain management circuit 100 can further include a state control unit 130, which can be electrically connected with the enabling unit 110, and the state control unit 130 can be configured to generate a state control signal (state_ctl) for transmission to the first power domain 11 according to the enabling signal, so as to set the working state (e.g., normal working state, standby state or shutdown state, etc.) of the related circuit components in the first power domain 11. It can be understood that the state control unit 130 can be set in various ways as needed, without limitation.

[0082] In a specific embodiment, as shown in FIG. 2 and FIG. 4, the state control unit 130 can include a first multiplexer (MUX) 131, a selection control terminal of the first multiplexer 131 can be electrically connected to an output terminal of the enable unit 110, each of a plurality of input terminals of the first multiplexer 131 can be configured to receive a corresponding state control signal, and an output terminal of the first multiplexer 131 can be configured to output a state control signal selected according to the enable signal. For example, in the specific embodiment of FIG. 4, one input terminal of the first multiplexer 131 can be configured to receive a first state control signal (state_ctl_1) corresponding to a normal working state, and another input terminal can be configured to receive a second state control signal (state_ctl_2) corresponding to a standby state or a shutdown state. In this way, in the case that the selection control terminal of the first multiplexer 131 receives an enable signal at a first preset level, the output terminal of the first multiplexer 131 can select to output the second state control signal to instruct the corresponding circuit component in the first power domain 11 connected to the output terminal of the first multiplexer 131 to work in the standby state or the shutdown state, i.e., in the case that the first power domain 11 is in the power-off state, the circuit component is in the standby state or the shutdown state to reduce power consumption; and in the case that the selection control terminal of the first multiplexer 131 receives an enable signal at a second preset level, the output terminal of the first multiplexer 131 can select to output the first state control signal to instruct the corresponding circuit component in the first power domain 11 connected to the output terminal of the first multiplexer 131 to work in the normal working state. It can be understood that the first multiplexer 131 can also include more input terminals, thereby providing more types of state control signals to control the operating state of the related circuit component in the first power domain 11.

[0083] However, in the specific embodiment shown in FIG. 4, the corresponding state control signal is fixed corresponding to a certain enable signal, and cannot be flexibly adjusted according to the needs of the user. For example, if the second state control signal is used to indicate the shutdown state of the related circuit component corresponding to the enable signal at the first preset level, as long as the state control unit 130 receives the enable signal at the first preset level, the related circuit component can only be in the shutdown state under the action of the second state control signal, and cannot be adjusted to be in the standby state.

[0084] To solve the above problems, in another specific embodiment, as shown in FIGS. 5 to 7, the state control unit 130 can include a second register 132. In addition, the clamping unit 120 can include the first clamping unit 121 and the third clamping unit 123 as described above. It should be noted that in one specific example, the first clamping unit 121 shown in FIGS. 6 and 7 is the first clamping unit 121 shown in FIG. 5, and the third clamping unit 123 shown in FIGS. 6 and 7 is the third clamping unit 123 shown in FIG. 5. Accordingly, the initial signal can also include an input control signal (input signal) for transmission to the third clamping unit 123, and the target signal can also include a state indication signal generated according to the enable signal (iso_en) and the input control signal (input signal). Under the joint action of such a second register 132, a first clamping unit 121 and a third clamping unit 123, the configuration of the operating state or working state of the relevant circuit components can be achieved.

[0085] Specifically, in the specific embodiment shown in FIG. 6, the reset trigger end of the second register 132 can be configured to receive a reset indication signal (rst_n). In addition, the first input end of the first clamping unit 121 can be configured to receive an enable signal (iso_en), the second input end of the first clamping unit 121 can be configured to receive a clock signal (clk), and the output end of the first clamping unit 121 can be electrically connected to the clock trigger end of the second register 132. The first input end of the third clamping unit 123 can be configured to receive the enable signal (iso_en), the second input end of the third clamping unit 123 can be configured to receive an input control signal (input_signal), and the output end of the third clamping unit 123 can be electrically connected to the input end of the second register 132 to transmit the state indication signal to the second register 132. In this way, the output end of the second register 132 can be configured to output a first state control signal for indicating a normal working state to control the relevant circuit components in the first power supply domain 11 to operate in the normal working state when the reset indication signal is received at the reset trigger end of the second register 132. When the target signal clamped to the third preset level is received at the clock trigger end of the second register 132, the output end of the second register 132 can output a state control signal corresponding to the state indication signal received at its input end. In this way, the working state of the relevant circuit components in the first power supply domain 11 under the power-off condition of the first power supply domain 11 can be configured by configuring the corresponding input control signal, for example, in some cases it can be a shutdown state, and in other cases it can be a standby state. It can be understood that in order to better distinguish various state control signals or working states, the state control signal can be formed by multiple bits, for example, the state control signal can be 0001 to correspond to the standby state, 0010 to correspond to the shutdown state, etc., and accordingly, the third clamping unit 123 can clamp the corresponding bit of the input control signal to the preset level as needed to generate the corresponding state control signal, which is not limited herein.

[0086] In a specific embodiment, the second register 132 and the clamp unit 120, etc. can be configured for a static random access memory (SRAM) provided in the first power domain 11, for example, to configure the working state of the SRAM in the power-off state of the first power domain 11. Specifically, in the case of power-off of the first power domain 11, the SRAM can be in a shutdown state, i.e. the power supply of the storage array and the interface power supply of the SRAM can be disconnected, at this time the content stored in the SRAM cannot be retained; or the SRAM can also be in a retention state, i.e. the power supply of the storage array is maintained, and the interface power supply can be disconnected, at this time the content stored in the SRAM can be retained for subsequent use. In addition, in the case of power-on of the first power domain 11, the SRAM can be in a normal working state, i.e. the power supply of the storage array and the interface power supply of the SRAM exist. Then, when the working state of the SRAM is controlled by the state control unit 130 and the related clamp unit 120 shown in FIG. 6, in response to the second register 132 receiving an enable signal at the first preset level, the output end of the second register 132 can generate a state control signal corresponding to the input control signal, so that by setting different input control signals, different state control signals can be generated to control whether the SRAM works in the shutdown state or the retention state; and in response to the second register 132 receiving an enable signal at the second preset level, the output end of the second register 132 can generate a first state control signal corresponding to the normal working state to indicate that the SRAM works in the normal working state.

[0087] However, in the specific embodiment shown in FIG. 6, once the working state of the relevant circuit components in the power-off state is configured in the first power domain 11, it will generally take effect immediately, and at this time the first power domain 11 can not have entered the power-off state. But in some cases, it is necessary to control the relevant circuit components in the first power domain 11 to work in the configured working state only after the first power domain 11 enters the power-off state. For example, in the case where the state control signal is to be input to the circuit components such as central processing unit (CPU) provided in the first power domain 11, it can be necessary to impose a certain delay on the state control signal, so that these circuit components enter the configured shutdown state or standby state, etc. only after the first power domain 11 is powered off, thereby ensuring the normal operation of the SOC 10. For this purpose, as shown in FIG. 7, in another specific embodiment, the state control unit 130 can further include a delay module 133, and the output end of the second register 132 can be electrically connected to the input end of the delay module 133, which can be configured to delay the state indication signal. In the specific embodiment shown in FIG. 7, the delay module 133 can be formed by a second multiplexer (MUX), wherein the selection control end of the second multiplexer can be electrically connected to the output end of the enable unit 110, one input end of the second multiplexer can be electrically connected to the output end of the second register 132, and the output end of the second multiplexer can be configured to output the state control signal selected according to the enable signal. In this way, since the state control signal is transmitted to the relevant circuit components in the first power domain 11 through the second multiplexer, the necessary delay can be introduced to ensure the normal operation of the SOC 10.

[0088] In some specific examples, the first state control signal for indicating the normal working state can also be derived from the second register 132. Alternatively, in other specific examples, as shown in FIG. 7, another input end of the second multiplexer can be configured to receive the state control signal (first state control signal (state_ctl_1)) corresponding to the normal working state, so that the second register 132 can be used separately to set the state control signal in the power-off state of the first power domain 11.

[0089] According to the specific circuit components, corresponding state control signals can be provided. For example, the main circuit components or logic of the SOC can be provided in the first power domain 11 to minimize power consumption. Accordingly, static random access memory (SRAM), input / output (IO) units, and various analog circuit components (e.g., analog IP components, etc.) for implementing specific functions can be provided in the first power domain 11. In a specific example, the state control signals can include a state control signal configured to maintain power supply of a memory array of the SRAM in the first power domain 11, such that in the case of power down of the first power domain 11, the information stored in the SRAM is still retained, while other power supply of the SRAM can be cut off, thereby saving power consumption. In another specific example, the state control signals can include a state control signal configured to maintain power supply of input / output of the IO units in the first power domain 11, such that in the case of power down of the first power domain 11, necessary input / output or signal interaction can still be implemented, while other power supply of the IO units can be cut off, thereby saving power consumption. In yet another specific example, the state control signals can also include a state control signal configured to maintain the analog circuit components in the first power domain 11 in a shutdown state or standby state, to save power consumption. In addition, the state control signals can also include a state control signal configured to cause the first power domain 11 to be in a normal working state, such that in the case of power up of the first power domain 11, the circuit components therein resume to the normal working state. It can be understood that other types of state control signals can also be provided according to specific needs, which are not limited herein.

[0090] In some embodiments, as shown in FIG. 1, the power domain management circuit 100 can further include a power-on identification unit 140, which can be configured to identify whether the current power-on of the first power domain 11 is a first power-on or a post-sleep power-on, so as to generate a corresponding signal to control the operation of the SOC 10. Here, the first power-on can refer to the simultaneous power-on of the first power domain 11 and the second power domain 12, or the first power-on of the first power domain 11 after the power-on of the second power domain 12; and the post-sleep power-on can refer to the non-first power-on of the first power domain 11 after the power-on of the second power domain 12. In a specific embodiment, the power-on identification unit 140 can include a latch, which can be configured to receive a power-on indication signal from the power supply 200, and generate a power-on identification signal for identifying whether the current power-on of the first power domain 11 is a first power-on or a post-sleep power-on according to the reset indication signal and the power-on indication signal. In a specific example, as shown in FIG. 8, when the reset indication signal is active at a high level, if the power-on indication signal is at a low level, it indicates a first power-on, and if the power-on indication signal is at a high level, it indicates a post-sleep power-on. At this time, the latch can latch the power-on indication signal at a high level, i.e., the power-on identification signal is converted from a low level to a high level, to distinguish between a first power-on and a post-sleep power-on. In the SOC 10, other register and circuit components can control the corresponding working state based on whether it is a first power-on according to the power-on identification signal in the latch, and avoid the interference caused by the subsequent changes of the reset indication signal. In addition, after the power-on reset, the level of the power-on indication signal from the power supply can be changed at will, i.e., it can be used to realize the input function. It should be noted that in other embodiments, other types of timing logic circuits such as registers can also be used to implement the power-on identification unit, which is not limited here.

[0091] In the technical solution of the present disclosure, a power domain management circuit is proposed, which can release the signal isolation between power domains based on a reset indication signal. In addition, the power domain management circuit can also set the isolation between power domains based on an isolation set signal. In some embodiments, the power domain management circuit can be a clockless design, so that in the case of power domain isolation, there is no clock and the flip caused by the clock in the power domain management circuit and the system on chip, thereby helping to reduce the circuit complexity and power consumption of the power domain management circuit and the system on chip containing it. In addition, in some embodiments, at least part of the circuit components in the power-down domain can also be controlled to work in a power-down state according to specific needs. In addition, by setting a power-on identification unit, it can be determined whether the current power-on of the power-down domain is a first power-on or a post-sleep power-on, so as to control the work of the corresponding register and circuit components according to specific needs, further improving the flexibility and richness of power domain management.

[0092] The words "left," "right," "front," "back," "top," "bottom," "over," "under," "upper," "lower," and the like in the description and the claims, if any, are used for description and not necessarily for limiting relative positions. It will be appreciated with understanding that the words so used are interchangeable with respect to the illustrated embodiments and can be used in other orientations. For example, if the device in the drawings were inverted, then a feature which is described as above other features would then be resolved as being below other features. The device can be oriented in other ways (rotated at 90 degrees or at other orientations) and the relative spatial relationships would then be interpreted accordingly.

[0093] In the description and claims, when an element is referred to as being "on," "attached," "connected" or "coupled" to another element, it can be directly on, attached to, connected to or coupled to the other element or one or more intervening elements can be present. In contrast, when an element is referred to as being "directly on," "directly attached" "directly connected" or "directly coupled" to another element, there are no intervening elements present. In the description and claims, an element is arranged "adjacent" to another element can mean that the element has a portion that overlaps the adjacent element or a portion that is above or below the adjacent element.

[0094] As used herein, the word "exemplary" means "serving as an example, instance, or illustration," and not "preferred" or "advantageous over other implementations." Furthermore, the disclosure is not to be limited to any expressed or implied theory of operation by examples described herein.

[0095] As used herein, the word "substantially" means including any small variations caused by design or manufacturing tolerances, environmental impacts, and / or other factors. The word "substantially" also allows for differences due to parasitics, noise, and other practical considerations in an actual implementation.

[0096] Also, the terms "first", "second", and other such numerical terms, can be used herein, simply for purposes of reference and are not intended to limit, unless otherwise specifically indicated. For example, the words "first", "second", and other such numerical terms referring to structures or elements do not imply a sequence or order unless clearly indicated by the context.

[0097] It will be further understood that the terms "comprises" and / or "comprising", when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0098] In addition, as used in the present disclosure, the words "herein", "above", "below", "hereunder", "the preceding", "hereinbefore" or similar expressions are intended to include the entire disclosure herein, rather than any specific part of the disclosure. Furthermore, conditional language, such as "can", "could", "might", "may", "e.g.", "for example", "such as", etc., unless specifically stated otherwise, is understood as enabling the inclusion of the features, elements, and / or states recited therein, but not the exclusion of any of the same, whether expressly stated or otherwise. Thus, such conditional language is not generally intended to imply that features, elements and / or states are in any way required, or that any particular embodiment includes, or is intended to include, any of the same, or that any particular embodiment is in any way required to operate in accordance with any of the same.

[0099] In the present disclosure, the term "provide" is used in a broad sense to encompass all means of obtaining an object, and thus "providing an object" includes, but is not limited to, "buying", "preparing / manufacturing", "arranging / setting", "installing / fitting", and / or "ordering" the object, etc. In addition, in the present disclosure, the terms "circuit", "unit", and "module" can be used interchangeably.

[0100] As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.

[0101] Those skilled in the art will realize that the boundaries between the above described operations merely illustrative. The multiple operations can be combined into a single operation, a single operation can be distributed in additional operations and operations can be executed at least partially overlapping in time. Moreover, alternative embodiments can include multiple instances of a particular operation and the order of operations can be altered in other various embodiments. However, other modifications, variations, and alternatives are also possible using the teachings of this disclosure. All of the disclosed embodiments of the present application can be combined in any way possible, and all of the aspects and elements of the disclosed embodiments can be combined in any way possible, to provide additional embodiments of the present application. Accordingly, the description and drawings are to be regarded as illustrative in nature and not as restrictive. Indeed, novel devices, methods and systems described herein can be embodied in a variety of other forms; furthermore, various omissions, substitutions and changes in the form of the methods and systems described herein can be made without departing from the spirit of the disclosure. For example, while the blocks are presented in a given arrangement, alternative embodiments can perform similar functions with different components and / or circuit topologies, and can delete, move, add, split, combine, and / or modify some blocks. Each of these blocks can be implemented in a variety of different ways.

[0102] Various embodiments of the present disclosure can be described in a progression of form, each embodiment being provided for the enabling comparison of some more specific form with some other more general form. It is to be understood that not all of the described embodiments or features are necessary to practice the present disclosure. It is also to be understood that well known methods and components have not been described in detail in order to avoid obscuring the present disclosure. It is also to be understood that one or more of the described embodiments can be implemented in a variety of ways.

[0103] While specific embodiments of the disclosure have been described above, it is understood that they have been presented by way of example only, and not limitation. Various embodiments of the present disclosure can be combined in any way possible, without departing from the spirit and scope of the present disclosure. It is also to be understood that the above description is intended to be illustrative, and not restrictive. Many other modifications, variations, and alternatives to the embodiments of the disclosure described and illustrated herein will be apparent to those of ordinary skill in the art having the benefit of this disclosure. The scope of the disclosure should be determined from the following claims.

Claims

1. A power domain management circuit, comprising: an enabling unit configured to generate an enabling signal having a first preset level upon receiving an isolation set signal, or generate an enabling signal having a second preset level upon receiving a reset indication signal, wherein the second preset level is different from the first preset level; and a clamping unit electrically connected with the enabling unit, and the clamping unit is configured to clamp an initial signal transmitted from a first power domain to a second power domain to generate a target signal having a third preset level upon receiving the enabling signal having the first preset level, or not clamp the initial signal to generate a target signal having a level varying with a level of the initial signal upon receiving the enabling signal having the second preset level, wherein the third preset level is the same as or different from the first preset level.

2. The power domain management circuit of claim 1, wherein, the isolation set signal is configured to be generated before the first power domain powers down relative to the second power domain; or the reset indication signal is configured to be generated after the first power domain powers up relative to the second power domain and in a power up stable state.

3. The power domain management circuit of claim 1, wherein, the reset indication signal is configured to reset at least part of circuit components in the first power domain after the first power domain powers up relative to the second power domain.

4. The power domain management circuit of claim 1, wherein, the enabling unit comprises a first register.

5. The power domain management circuit of claim 4, wherein, a reset trigger end of the first register is configured to receive the reset indication signal, and an output end of the first register is configured to output the enabling signal.

6. The power domain management circuit of claim 4, wherein, the clamping unit comprises a first clamping unit, and the initial signal comprises a clock signal; a first input end of the first clamping unit is configured to receive the enabling signal, a second input end of the first clamping unit is configured to receive the clock signal, and an output end of the first clamping unit is electrically connected to a clock trigger end of the first register.

7. The power domain management circuit of claim 4, wherein, the clamping unit comprises a second clamping unit, the initial signal comprises an isolation set signal, and the target signal comprises the isolation set signal generated according to the enabling signal and the isolation set signal; a first input end of the second clamping unit is configured to receive the enabling signal, a second input end of the second clamping unit is configured to receive the isolation set signal, and an output end of the second clamping unit is electrically connected to an input end of the first register to transmit the isolation set signal to the first register.

8. The power domain management circuit of claim 1, further comprising: a state control unit electrically connected with the enabling unit, and the state control unit is configured to generate a state control signal for transmission to the first power domain according to the enabling signal.

9. The power domain management circuit of claim 8, wherein, The state control unit comprises a first multiplexer, a selection control end of the first multiplexer is electrically connected to an output end of the enable unit, each of a plurality of input ends of the first multiplexer is configured to receive a corresponding state control signal, and an output end of the first multiplexer is configured to output a state control signal selected according to the enable signal.

10. The power domain management circuit of claim 8, wherein, The state control unit comprises a second register, the clamping unit comprises a first clamping unit and a third clamping unit, the initial signal comprises an input control signal, and the target signal comprises a state indication signal generated according to the enable signal and the input control signal. A reset trigger end of the second register is configured to receive the reset indication signal. A first input end of the first clamping unit is configured to receive the enable signal, a second input end of the first clamping unit is configured to receive the clock signal, and an output end of the first clamping unit is electrically connected to a clock trigger end of the second register. Or A first input end of the third clamping unit is configured to receive the enable signal, a second input end of the third clamping unit is configured to receive the input control signal, and an output end of the third clamping unit is electrically connected to an input end of the second register to transmit the state indication signal to the second register.

11. The power domain management circuit of claim 10, wherein, The second register is configured to generate a state control signal corresponding to the input control signal when the state indication signal is received, or generate a state control signal corresponding to a normal working state when the reset indication signal is received.

12. The power domain management circuit of claim 10, wherein, The state control unit further comprises a delay module, an output end of the second register is electrically connected to an input end of the delay module, and the delay module is configured to delay the state indication signal.

13. The power domain management circuit of claim 12, wherein, The delay module comprises a second multiplexer, a selection control end of the second multiplexer is electrically connected to an output end of the enable unit, one input end of the second multiplexer is electrically connected to an output end of the second register, and an output end of the second multiplexer is configured to output a state control signal selected according to the enable signal.

14. The power domain management circuit of claim 13, wherein, Another input end of the second multiplexer is configured to receive a state control signal corresponding to a normal working state.

15. The power domain management circuit of claim 8, wherein, The state control signal comprises at least one of: a state control signal configured to maintain power supply of a memory array of a static random access memory in the first power supply domain; a state control signal configured to maintain power supply of input and output of an input and output unit in the first power supply domain; a state control signal configured to maintain an analog circuit component in the first power supply domain in a shutdown state or a standby state; or a state control signal configured to enable the first power supply domain to be in a normal working state.

16. The power supply domain management circuit of claim 1, further comprising: a power-on identification unit configured to identify whether current power-on of the first power supply domain is initial power-on or power-on after hibernation. ​ 17. The power domain management circuit of claim 16, wherein, The power-on identification unit includes a latch configured to receive a power-on indication signal from a power supply, and generate a power-on identification signal for identifying whether a current power-on of the first power domain is a first power-on or a power-on after hibernation according to the reset indication signal and the power-on indication signal.

18. The power domain management circuit of claim 1, wherein, The clamping unit includes: an AND gate circuit, a first input end of the AND gate circuit is configured to receive the enable signal, a second input end of the AND gate circuit is configured to receive the initial signal, and an output end of the AND gate circuit is configured to output the target signal, wherein the first preset level is a low level, and the second preset level is a high level; or an OR gate circuit, a first input end of the OR gate circuit is configured to receive the enable signal, a second input end of the OR gate circuit is configured to receive the initial signal, and an output end of the OR gate circuit is configured to output the target signal, wherein the first preset level is a high level, and the second preset level is a low level.

19. The power domain management circuit of claim 1, wherein, The power domain management circuit is arranged in the second power domain.

20. A system on chip, having a first power domain and a second power domain, and comprising the power domain management circuit according to any one of claims 1 to 19.

21. The system on chip according to claim 20, further comprising: a power supply configured to supply power to the first power domain and the second power domain.

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