Synchronization method, apparatus, and device

Abstract

Embodiments of the present application relate to the technical field of interface communications, and provide a synchronization method, an apparatus, and a device, used for achieving time synchronization between apparatuses by means of one transmission, thereby shortening the synchronization time. The method comprises: generating a burst, wherein the burst comprises a synchronization sequence, an alignment sequence, a timestamp sequence and a burst end sequence, the synchronization sequence is used for physical layer synchronization between a first apparatus and a second apparatus, the alignment sequence is located after the synchronization sequence, the timestamp sequence is located after the alignment sequence, the burst end sequence is located after the timestamp sequence, the timestamp sequence comprises a K-code sequence and a timestamp value, the K-code sequence is used for marking the timestamp sequence, the timestamp value is used for indicating a moment at which a target bit in the burst is sent to a physical layer of the first apparatus, and the target bit is located in the synchronization sequence or the alignment sequence; and sending the burst to the second apparatus, wherein the first apparatus and the second apparatus perform timing on the basis of clocks having a same frequency and phase.

Description

Synchronization method, apparatus and device

[0001] The present application claims priority from the Chinese patent application No. 202411357717.1 filed on September 26, 2024, and entitled "Synchronization method, apparatus and device", the whole content of which is incorporated herein by reference. TECHNICAL FIELD

[0002] The present application relates to the technical field of interface communication, in particular to a synchronization method, apparatus and device. BACKGROUND

[0003] In an electronic device, there is usually a communication scenario between a master device and a slave device. The master device can be a system on chip (SoC), and the slave device can be a memory, a display or a sensor, etc. When the master device and the slave device do not need to perform data transmission, the master device and the slave device can enter a low-power sleep state. When the master device and the slave device need to perform data transmission, the master device and the slave device can wake up from the sleep state.

[0004] At present, in order to avoid conflicts between the master device and the slave device when waking up, the master device and the slave device need to initiate wake-up within a specified time window based on the same time. How to ensure that the time on both sides of the master device and the slave device is consistent is a technical problem to be solved. SUMMARY

[0005] The present application provides a synchronization method, apparatus and device for realizing time synchronization between devices through one transmission and shortening synchronization time.

[0006] To achieve the above-mentioned purpose, the embodiments of the present application adopt the following technical solutions:

[0007] In a first aspect, a method for synchronizing an inter-device interface is provided, and is applied to a first device, which can be one of a master device or a slave device. The method comprises: generating a burst, which comprises a synchronization sequence, an alignment sequence, a timestamp sequence, and a burst end sequence. The synchronization sequence is used for physical layer synchronization between the first device and a second device. The alignment sequence is located after the synchronization sequence. The timestamp sequence is located after the alignment sequence. The burst end sequence is located after the timestamp sequence. The timestamp sequence comprises a K code sequence and a timestamp value. The K code sequence is used to mark the timestamp sequence. The timestamp value is used to indicate a time point at which a target bit in the burst is sent to a physical layer of the first device. The target bit is located in the synchronization sequence or the alignment sequence. The method further comprises: sending the burst to the second device, i.e., sending the burst to the second device by a physical layer of the first device. The first device and the second device are clocked based on a same frequency and phase.

[0008] In the above technical solution, the first device and the second device are clocked based on a same frequency and phase, so that the timestamp values of the first device and the second device can increase at the same frequency. In addition, the first device sends the burst to the second device. The timestamp sequence in the burst comprises a K code sequence and a timestamp value. The K code sequence is used to mark the timestamp sequence. The timestamp value is used to indicate a time point at which a target bit in the burst is sent to a physical layer of the first device. The target bit is located in the synchronization sequence or the alignment sequence in the burst. In this way, the second device can achieve time synchronization between the second device and the first device according to the received timestamp value in the burst and a corresponding delay. That is, time synchronization between the first device and the second device can be achieved through one transmission, and multiple handshakes are not required, so that the synchronization time is greatly shortened, and power consumption is reduced.

[0009] In a possible implementation manner of the first aspect, the target bit is a first bit of the alignment sequence. In this way, the second device can simply and quickly detect the target bit. Alternatively, the target bit is a last bit of the alignment sequence, or a first bit or a last bit of the synchronization sequence. In this way, flexibility of setting the target bit can be improved.

[0010] In a possible implementation manner of the first aspect, the same frequency and phase clock is a same clock shared by the first device and the second device. In the above possible implementation manner, the first device and the second device share the same clock, so that the first device and the second device can reduce costs and design complexity while ensuring that the timestamp values of the first device and the second device can increase at the same frequency.

[0011] In a possible implementation of the first aspect, the burst further includes service data, and the service data is located between the alignment sequence and the timestamp sequence. In the possible implementation, the time synchronization between the first device and the second device can be achieved through one transmission, so that the synchronization time is greatly shortened, and the power consumption is reduced.

[0012] In a possible implementation of the first aspect, the timestamp sequence further includes a check code, and the check code is used to check the timestamp value. Optionally, the check code is a CRC check code. In the possible implementation, the timestamp sequence sent by the first device to the second device further includes the check code, so that the second device can check the timestamp value in the timestamp sequence according to the received check code, thereby avoiding the problem that the second device performs incorrect time synchronization in the case that the timestamp value has an error code.

[0013] In a second aspect, a synchronization method of an inter-device interface is provided, and the method is applied to a second device. The method includes the following steps: receiving a burst from a first device, the burst including a synchronization sequence, an alignment sequence, a timestamp sequence, and a burst end sequence, the synchronization sequence being used for physical layer synchronization between the first device and the second device, the alignment sequence being located after the synchronization sequence, the timestamp sequence being located after the alignment sequence, the burst end sequence being located after the timestamp sequence, the timestamp sequence including a K code sequence and a timestamp value, the K code sequence being used to mark the timestamp sequence, and the timestamp value being used to indicate a time point at which a target bit in the burst is sent to a physical layer of the first device, the target bit being located in the synchronization sequence or the alignment sequence; performing time synchronization between the second device and the first device according to the timestamp value, a first receiving time of the target bit by the second device, and a second receiving time of the timestamp sequence by the second device; and wherein the first device and the second device are based on a same frequency and phase clock.

[0014] In a possible implementation of the second aspect, the target bit is a first bit of the alignment sequence. Optionally, the target bit is a last bit of the alignment sequence, or a first bit or a last bit of the synchronization sequence.

[0015] In a possible implementation of the second aspect, the same frequency and phase clock is a same clock shared by the first device and the second device, that is, the first device and the second device share the same clock.

[0016] In a possible implementation of the second aspect, the burst further includes service data, and the service data is located between the alignment sequence and the timestamp sequence.

[0017] In a possible implementation of the second aspect, the timestamp sequence further comprises a check code, and the check code is used to check the timestamp value. Optionally, the check code can be a CRC check code.

[0018] In a possible implementation of the second aspect, the time synchronization between the second device and the first device is performed according to the timestamp value, the first receiving moment of the target bit by the second device, and the second receiving moment of the timestamp sequence by the second device, and the time synchronization comprises: performing the time synchronization between the second device and the first device according to the timestamp value, the first receiving moment, the second receiving moment, a physical layer sending delay of the first device, and a physical layer receiving delay of the second device.

[0019] In a possible implementation of the second aspect, the time synchronization between the second device and the first device comprises: obtaining a local timestamp value T0 of the second device receiving the timestamp sequence, and the T0 is equal to a sum of the timestamp value, a difference between the first receiving moment and the second receiving moment, the physical layer sending delay of the first device, and the physical layer receiving delay of the second device.

[0020] In a third aspect, a synchronization device is provided, which functions as the first device and can implement the functions performed by the first device in the above method. The functions can be implemented by hardware or by hardware executing corresponding software. The hardware or software comprises one or more modules corresponding to the above functions.

[0021] In a possible implementation of the third aspect, the device comprises a processing unit and a sending unit; the processing unit is configured to support the device to perform the corresponding functions in the above method; and the sending unit is used to support the device to communicate with the second device.

[0022] In another possible implementation of the third aspect, the device comprises a processing circuit and a transmitter; the processing circuit is configured to support the device to perform the corresponding functions in the above method; and the transmitter is used to support the device to communicate with the second device.

[0023] In a fourth aspect, a synchronization device is provided, which functions as the second device and can implement the functions performed by the second device in the above method. The functions can be implemented by hardware or by hardware executing corresponding software. The hardware or software comprises one or more modules corresponding to the above functions.

[0024] In a possible implementation of the fourth aspect, the device comprises a receiving unit and a processing unit; the processing unit is configured to support the device to perform the corresponding functions in the above method; and the receiving unit is used to support the device to communicate with the first device.

[0025] In a further possible implementation form of the fourth aspect, the apparatus comprises a processing circuitry and a receiver; the processing circuitry is configured to support the apparatus to perform the corresponding functions in the above-described method; and the receiver is configured to support the apparatus to communicate with the first apparatus.

[0026] In a further aspect of the present application, an electronic device is provided, comprising a first apparatus and a second apparatus; wherein the first apparatus is the synchronization apparatus provided in the third aspect or in any possible implementation form of the third aspect, and is configured to perform the method provided in the first aspect or in any possible implementation form of the first aspect; and the second apparatus is the synchronization apparatus provided in the fourth aspect or in any possible implementation form of the fourth aspect, and is configured to perform the method provided in the second aspect or in any possible implementation form of the second aspect.

[0027] In a further aspect of the present application, a readable storage medium is provided, in which a computer program or instructions are stored, and when a device executes the computer program or instructions, the device is caused to perform the method provided in the first aspect or in any possible implementation form of the first aspect.

[0028] In a further aspect of the present application, a readable storage medium is provided, in which a computer program or instructions are stored, and when a device executes the computer program or instructions, the device is caused to perform the method provided in the second aspect or in any possible implementation form of the second aspect.

[0029] In a further aspect of the present application, a computer program product is provided, comprising: a computer program (also referred to as code or instructions), when the computer program is executed by a device, the device is caused to perform the method provided in the first aspect or in any possible implementation form of the first aspect.

[0030] In a further aspect of the present application, a computer program product is provided, comprising: a computer program (also referred to as code or instructions), when the computer program is executed by a device, the device is caused to perform the method provided in the second aspect or in any possible implementation form of the second aspect.

[0031] It can be understood that the beneficial effects of other aspects in addition to the first aspect and any possible implementation form of the first aspect can be correspondingly referred to the beneficial effects of the above-mentioned first aspect and any possible implementation form of the first aspect, which will not be described here. BRIEF DESCRIPTION OF DRAWINGS

[0032] FIG. 1 is a structural schematic diagram of an electronic device provided by an embodiment of the present application;

[0033] FIG. 2 is a schematic diagram of a method for synchronizing two devices using non-identical clocks according to an embodiment of the present application;

[0034] FIG. 3 is a schematic diagram of a method for calibrating a count step and calculating a delay according to an embodiment of the present application;

[0035] FIG. 4 is a schematic diagram of a method for synchronizing an interface between devices according to an embodiment of the present application;

[0036] FIG. 5 is a schematic diagram of a structure of a first device and a second device according to an embodiment of the present application;

[0037] FIG. 6 is a schematic diagram of a plurality of sequences in a burst according to an embodiment of the present application;

[0038] FIG. 7 is a schematic diagram of a time stamp sequence according to an embodiment of the present application;

[0039] FIG. 8 is a schematic diagram of a structure of a first device according to an embodiment of the present application;

[0040] FIG. 9 is a schematic diagram of another structure of a first device according to an embodiment of the present application;

[0041] FIG. 10 is a schematic diagram of a structure of a second device according to an embodiment of the present application;

[0042] FIG. 11 is a schematic diagram of another structure of a second device according to an embodiment of the present application. DETAILED DESCRIPTION

[0043] In this embodiment, each circuit, software or other component can be described as or referred to as being "configured to" perform a certain operation or task. In this case, the circuit / software / component can be understood as being configured to perform the task by virtue of including the structure (e.g. circuitry) that performs the task during operation. Thus, the task can be performed by the circuit / software / component even when the circuit / software / component is not currently operational (e.g. not powered up). In other words, the task can be performed by the circuit / software / component when the circuit / software / component is in an unpowered state.

[0044] The technical solutions in the embodiments of the present application will be described below with reference to the drawings in the embodiments of the present application. In the present application, "at least one" means one or more, and "multiple" means two or two or more. The "and / or" describes the association relationship between the associated objects, which means that there can be three kinds of relationships, for example, A and / or B, which can represent the following three cases: A exists alone, A and B exist together, and B exists alone, where A and B can be singular or plural. The character " / " generally represents an "or" relationship between the associated objects before and after it. "At least one of the following" or similar expressions means any combination of these items, including any combination of single or multiple items. For example, at least one of a, b or c can represent: a, b, c, a and b, a and c, b and c, a, b and c; where a, b and c can be single or multiple.

[0045] The embodiments of the present application use "first" and "second" and the like to distinguish between objects or functions or roles similar in name or function. Those skilled in the art can understand that "first" and "second" and the like do not limit the quantity and execution order. The word "coupled" is used to represent electrical connection, including direct connection through a wire or connection end or indirect connection through other devices. Therefore, "coupled" should be regarded as a broad sense of electronic communication connection.

[0046] It should be noted that in the present application, the words "exemplary" or "for example" are used to indicate an example, illustration or description. Any embodiment or design scheme described as "exemplary" or "for example" in the present application should not be interpreted as more preferred or more advantageous than other embodiments or design schemes. Rather, the use of "exemplary" or "for example" is intended to present the relevant concept in a specific manner.

[0047] The technical solutions provided by the present application can be applied to electronic devices including multiple communication devices, which are also referred to as devices. Optionally, the device can be a device, a chip applied to the device, or an interface device or module in the chip, etc., and two different devices can be connected to each other. In the present application, the multiple devices can transmit signals through the interface device.

[0048] Optionally, when the apparatus is a chip, the chip can further comprise an interface module, i.e., the present application can be applied in an interface module for interconnection between chips. The interface module can be understood as an intellectual property (IP) module integrated in a chip. Alternatively, the interface module can also be sold as an IP module independently. For example, the chip can be a system on chip (SoC), a central processing unit (CPU), or a graphics processing unit (GPU), etc., and the interface module can be an interface module in the SoC, the CPU, or the GPU, etc. Optionally, the chip can also be a small chip such as a die, and the interface module can be a sending circuit and / or a receiving circuit in the die.

[0049] The structure of the electronic device is exemplarily described below by taking an example that the electronic device comprises two apparatuses.

[0050] FIG. 1 is a structural schematic diagram of an electronic device provided by an embodiment of the present application. The electronic device comprises a first apparatus 101 and a second apparatus 102 connected through an interface. Exemplarily, the first apparatus 101 comprises an interface A, and the second apparatus 102 comprises an interface B. The interface A and the interface B are connected through a cable. The first apparatus 101 can output a signal to the second apparatus 102 through the interface A, and the second apparatus 102 can receive a signal from the first apparatus 101 through the interface B.

[0051] In a possible embodiment, the electronic device can comprise a master device and a slave device. The master device can also be referred to as a host or a master state machine, and the slave device can also be referred to as a slave or a slave state machine. In actual application, the first apparatus 101 can be the master device, and the second apparatus 102 can be the slave device; or the first apparatus 101 can be the slave device, and the second apparatus 102 can be the master device.

[0052] Optionally, the master device can be a processor or a SoC including a processor, etc. Illustratively, the processor can include a central processing unit (CPU), a neural-network processing unit (NPU), a graphics processing unit (GPU), an application processor, an application specific integrated circuit (ASIC), a complex programmable logic device (CPLD), a field-programmable gate array (FPGA), etc. Optionally, the slave device can include a camera, a display, a memory, a sensor, or an audio device, etc. Illustratively, the memory can include a random access memory (RAM), a read-only memory (ROM), a flash, a disk, etc. Illustratively, the audio device can include a sound box, a microphone, a speaker, etc.

[0053] Optionally, the interface A and the interface B can include, but are not limited to, a peripheral component interconnect express (PCIe) interface, a small computer system interface (SCSI), a serial attached SCSI (SAS) interface, a universal serial bus (USB) interface, a Mobile Industry Processor Interface (MIPI), a high definition multimedia interface (HDMI), a mini HDMI, a micro HDMI, a display port (DP), a unified multimedia interconnection (UMMI) interface, a unified media interconnection (UMI) interface, a type-A interface, a type-B interface, a type-C interface, or a private interface, etc.

[0054] It can be understood that the above-mentioned interfaces with different interface specifications are only exemplary, and in actual application, the interface specifications can also include other or any future interface specifications, and the embodiments of the present application do not make specific limitations thereto.

[0055] In the present application, the electronic device can include, but is not limited to, a mobile phone, a tablet computer, a notebook computer, a palm computer, a mobile internet device (MID), a camera, a wearable device (for example, a smart watch, a smart bracelet, a pedometer, etc.), a sound equipment, an audio and video player, a set-top box, a game machine, a printer, a mouse, a keyboard, a vehicle-mounted device (for example, a device on a vehicle such as a car, a bicycle, an electric vehicle, an airplane, a ship, a train, and a high-speed rail), a virtual reality (VR) device, an augmented reality (AR) device, a wireless terminal in industrial control, a smart home device (for example, a refrigerator, a television, an air conditioner, an electric meter, etc.), a smart robot, a plant device, a wireless terminal in self-driving, a wireless terminal in remote medical surgery, a wireless terminal in a smart grid, a wireless terminal in transportation safety, a wireless terminal in a smart city, or a wireless terminal in a smart home, a flight device (for example, a smart robot, a hot air balloon, a drone, an airplane), and the like.

[0056] In the above electronic device, there is usually a scenario of communication between two devices. When data transmission is not required between the two devices, the two devices can enter a low-power sleep state; when data transmission is required between the two devices, the two devices can be awakened from the sleep state. In order to avoid conflicts when the two devices are awakened, both devices need to initiate awakening within a specified time window based on the same time, and how to ensure that the time on both sides of the two devices is consistent is a technical problem to be solved.

[0057] In a possible embodiment, for two devices using non-identical clocks, a multiple calibration and multiple handshake method is usually used to calibrate the count step and calculate the transmission delay in sequence to realize time synchronization of the two devices. For example, FIG. 2 shows a flowchart for realizing time synchronization of a first device and a second device using non-identical clocks, and the specific process of the time synchronization can include three stages.

[0058] The first device sends a timestamp value every fixed time, which is about 1-2 ms, and the second device adjusts the count step of the local timestamp counter according to the received timestamp value each time, so that the timestamp counters of the first device and the second device increase at the same frequency. In FIG. 2, T1-T3 represent the time when the first device sends a timestamp value, and T1'-T3' represent the time when the second device receives a timestamp value.

[0059] For example, as shown in (a) of FIG. 3, in the synchronization process, it is assumed that the timestamp value of the first device changes from 0 to 11 according to a fixed count step, and the first device sends the timestamp values 1, 4, 7 and 10 to the second device every fixed time. When the second device receives the timestamp values 1, 4, 7 and 10 from the first device in turn, it adjusts the local timestamp value (i.e. the timestamp value of the second device) to 1, 5, 7 and 10 in turn, and adjusts the count step of the local timestamp counter each time a timestamp value is received, so that the count steps of the first device and the second device are the same.

[0060] In the second stage, the first device and the second device calculate the delay experienced by the timestamp value of the first device from sending to receiving through multiple handshakes, so that the second device takes the delay into account in the time synchronization process. The number of times of the multiple handshakes is usually at least 4. For example, for each handshake, the first device sends a specific sequence, and the second device returns a response to the first device as soon as the specific sequence is received, so that the first device can divide the time between the time when the specific sequence is sent and the time when the response is received by 2 to obtain the delay of one handshake; the first device can inform the second device of the delay of the timestamp value of the first device by taking the average of the multiple delays corresponding to the multiple handshakes. In FIG. 2, T4" represents the time when the first device sends a specific sequence, T4' represents the time when the second device returns a response, and T4 represents the time when the first device receives the response.

[0061] For example, as shown in (b) of FIG. 3, in the process of calculating the delay, it is assumed that the first device sends a specific sequence to the second device when the timestamp value is 13; the second device receives the specific sequence when the local timestamp value is 12 and returns a response; the first device receives the response when the timestamp value is 19, and determines that the delay ΔT corresponding to this handshake is (19-13) / 2=3; the first device and the second device can perform multiple handshakes according to the above steps, and then the first device can inform the second device of the average of the multiple delays corresponding to the multiple handshakes.

[0062] The third stage: the first device sends the timestamp value again every fixed time, which can be extended to 10-20 ms, and the second device obtains the calibrated timestamp value according to the sum of the received timestamp value and the delay received in the second stage, and calibrates the counting step of the local timestamp counter to realize the time synchronization between the second device and the first device. In FIG. 2, the first device sends the corresponding timestamp value at T5 and T6, and the second device receives the corresponding timestamp value at T5' and T6' as an example.

[0063] In the above time synchronization scheme, the first device and the second device need to perform multiple calibrations and multiple handshakes, thereby having the problem of long synchronization time. In addition, the first device and the second device use non-identical clocks, which causes the first device and the second device to perform the above time synchronization process every certain time.

[0064] Therefore, embodiments of the present application provide a synchronization method for an interface between devices, in which the first device and the second device are based on clocks with the same frequency and phase. The first device can send a burst to the second device, the timestamp sequence in the burst includes a K code sequence and a timestamp value, the K code sequence is used to mark the timestamp sequence, that is, to indicate that the corresponding sequence in the burst is a timestamp sequence rather than other sequence types, and the timestamp value is used to indicate the time when the target bit in the synchronous sequence or the align sequence in the burst is sent to the physical layer of the first device. In this way, the second device can realize the time synchronization between the second device and the first device according to the timestamp value. In the method, the first device and the second device can realize the time synchronization between devices through the transmission of a burst, and do not need to perform multiple handshakes, thereby greatly shortening the synchronization time and reducing the power consumption.

[0065] FIG. 4 is a flowchart of a synchronization method for an interface between devices provided by an embodiment of the present application. The method can be applied to an electronic device including a first device and a second device, the first device and the second device are based on clocks with the same frequency and phase, and the method includes the following steps.

[0066] S201: The first device generates a burst, the burst includes a synchronous sequence, an align sequence, a timestamp sequence, and a burst end sequence, the timestamp sequence includes a K code sequence and a timestamp value, the K code sequence is used to mark the timestamp sequence, and the timestamp value is used to indicate the time when the target bit in the synchronous sequence or the align sequence is sent to the physical layer of the first device.

[0067] The first device and the second device are clocked based on a same frequency and phase, or in other words, the first device and the second device are clocked using a common clock. In this way, the count step (or in other words, the clocking step) of the first device is the same as the count step of the second device, thereby ensuring that the timestamp values of the first device and the second device can increase at the same frequency. For example, the same frequency and phase clock can be a same clock shared between the first device and the second device.

[0068] In addition, the first device can be one of a master device or a slave device in the electronic device, and the second device can be the other of the master device or the slave device. For example, the first device can be a SoC, and the second device can be a sensor chip. Alternatively, the first device can be a sensor chip, and the second device can be a SoC.

[0069] Further, as shown in FIG. 5, the first device and the second device can each include a link layer and a physical layer. In this application, the link layer can be used to generate or process the burst, such as generating or processing the synchronization sequence, the alignment sequence, the timestamp sequence, and the end of burst (EOB) sequence in the burst, etc. In FIG. 5, the first device and the second device share a same clock, and the clock is located in the first device. Alternatively, the clock can be located in the second device or as a separate device outside the first device and the second device.

[0070] In one possible example, as shown in FIG. 6, the positions of the sequences in the burst can be as follows: the synchronization sequence is located at the head of the burst, the alignment sequence is located after the synchronization sequence, the timestamp sequence is located after the alignment sequence, and the EOB sequence is located after the timestamp sequence. Optionally, as shown in FIG. 6, the burst can further include data, which is located between the alignment sequence and the timestamp sequence. Optionally, the length of the alignment sequence and the length of the timestamp sequence can be fixed, the length of the synchronization sequence and the length of the EOB sequence can be variable, and the length of the data can also be variable.

[0071] The synchronization sequence is used for physical layer synchronization between the first device and the second device, and can be used for the second device to correctly receive the sequence after the synchronization sequence. The synchronization sequence can include frequent bit transitions, and the second device can recover the clock signal of the first device sending the burst through the frequent bit transitions, and capture the sequence after the synchronization sequence, such as the alignment sequence, the timestamp sequence and the service data, according to the clock signal, that is, the second device can realize clock and data recovery (CDR) according to the synchronization sequence. The service data involved in the embodiment can include image data, sensor data, or audio data, etc.

[0072] The alignment sequence can be used to mark the start of the sequence after the synchronization sequence, or to mark the start of the useful sequence after the synchronization sequence. The useful sequence can be other sequence except the alignment sequence and the end of burst sequence, and the useful sequence is located after the alignment sequence and before the end of burst sequence. For example, when the burst includes the synchronization sequence, the alignment sequence, the timestamp sequence and the end of burst sequence, the alignment sequence is used to indicate the start of the timestamp sequence; when the burst includes the synchronization sequence, the alignment sequence, the service data, the timestamp sequence and the end of burst sequence, the alignment sequence is used to indicate the start of the service data.

[0073] In a possible implementation, if the target bit is located in the alignment sequence, the target bit can be the first bit of the alignment sequence or the last bit of the alignment sequence, that is, the timestamp value in the timestamp sequence records the time when the first bit or the last bit of the alignment sequence is sent to the physical layer of the first device; if the target bit is located in the synchronization sequence, the target bit can be the first bit of the synchronization sequence or the last bit of the synchronization sequence, that is, the timestamp value in the timestamp sequence records the time when the first bit or the last bit of the synchronization sequence is sent to the physical layer of the first device. In actual application, the target bit can also be other bit in the alignment sequence or the synchronization sequence except the first bit and the last bit, that is, the target bit is a reference bit for positioning time, and the position of the target bit can be adjusted as needed and preset in the electronic device, which is not limited in the embodiment of the application.

[0074] Optionally, the timestamp sequence can further include a check code, which can be used to check the timestamp value. For example, the check code can be a cyclic redundancy check (CRC) code. In a possible embodiment, as shown in FIG. 7, the timestamp sequence includes a K code sequence, a timestamp value, and a check code, the timestamp value is located after the K code sequence, and the check code is located after the timestamp value. For example, the length of the timestamp sequence can be 16 bytes, the length of the K code sequence can be 6 bytes, the length of the timestamp value can be 8 bytes, and the length of the check code can be 2 bytes.

[0075] It can be understood that the generation manner of the check code can refer to the manner in the related art, for example, the check code can be generated by using a polynomial manner, and the present embodiment does not limit the generation manner of the check code or the specific form of the polynomial used to generate the check code. In addition, the timestamp sequence can also be referred to as a timestamp packet, and the K code sequence can be a packet header. The K code sequence is used to indicate the type of the timestamp sequence, that is, to indicate that the timestamp value is carried in the timestamp sequence.

[0076] In a possible implementation manner, the K code sequence can include a plurality of K codes, which can be K codes used in the 8b / 10b encoding specification. Optionally, the K code sequence can include a plurality of same K codes, which can be alternately arranged. For example, as shown in FIG. 7, the K code sequence can include six K codes, which can be K29.7, K28.6, K29.7, K28.6, K29.7, and K28.6 in sequence.

[0077] It can be understood that the above description of the K code sequence is only exemplary, and in actual application, the K code sequence can also include a different number of K codes or different K codes from the above description, and the above examples do not limit the present embodiment.

[0078] S202a: The first device sends the burst to the second device. S202b: The second device receives the burst.

[0079] In a possible embodiment, the connection layer of the first device can generate the burst and transmit the burst to the physical layer of the first device according to the arrangement order of the sequences in the burst, and the physical layer of the first device can send the received burst to the second device; after receiving the burst, the second device can process the burst and perform time synchronization between the second device and the first device in the process of processing the burst. Optionally, the physical layer of the second device can receive the burst and transmit the burst to the connection layer of the second device.

[0080] S203: The second device processes the burst to achieve time synchronization between the second device and the first device in the process of processing the burst.

[0081] In a possible embodiment, when the second device detects the synchronization sequence in the burst, the second device can recover the clock signal of the first device sending the burst according to the synchronization sequence to achieve physical layer synchronization between the first device and the second device; then, the second device can determine the alignment sequence after the synchronization sequence according to the clock signal, and determine the position of the timestamp sequence according to the alignment sequence, or determine the position of the timestamp sequence according to the alignment sequence and the length of the service data; then, the second device determines the timestamp value in the timestamp sequence after the K code sequence in the timestamp sequence according to the K code sequence in the timestamp sequence, and in the case that the timestamp sequence further includes the check code, the second device can further verify the timestamp value according to the check code; after the timestamp value is verified successfully, the second device performs time synchronization between the second device and the first device according to the timestamp value, the first receiving time of the second device to the target bit, and the second receiving time of the second device to the timestamp sequence.

[0082] The first receiving time can be the time when the connection layer of the second device receives the target bit; the second receiving time can be the time when the connection layer of the second device receives the timestamp sequence. Optionally, the target bit can be the first bit of the alignment sequence. In the case that the burst does not include service data, the difference between the first receiving time and the second receiving time can be the delay of the connection layer of the first device transmitting the alignment sequence to the physical layer of the first device; in the case that the burst includes the alignment sequence and the service data, the difference between the first receiving time and the second receiving time can be the delay of the connection layer of the first device transmitting the alignment sequence and the service data to the physical layer of the first device. The first receiving time and the second receiving time can be obtained by the connection layer of the second device. For example, in the case that the timestamp sequence includes the K code sequence and the timestamp value, the second receiving time can be the time when the connection layer of the second device receives the last K code of the K code sequence, and assuming that the K code sequence includes 6 K codes, the second receiving time can be the time when the connection layer of the second device receives the 6th K code.

[0083] In addition, the physical layer transmission delay of the first device can be a delay of the physical layer of the first device in transmitting a single bit, and the physical layer reception delay of the second device can be a delay of the physical layer of the second device in receiving a single bit. In actual application, the physical layer transmission delay of the first device and the physical layer reception delay of the second device can be defined within a fixed error range, can be obtained by actual measurement, and are configured in the electronic device in advance to facilitate use in the process of performing time synchronization between the second device and the first device. For example, the physical layer transmission delay of the first device and the physical layer reception delay of the second device are configured in a register of the electronic device in advance. In FIG. 5, the physical layer transmission delay of the first device is denoted as TX_DLY, and the physical layer reception delay of the second device is denoted as RX_DLY.

[0084] Further, the second device can perform time synchronization between the second device and the first device according to the timestamp value, the first reception time, the second reception time, the physical layer transmission delay of the first device, and the physical layer reception delay of the second device, that is, refresh or adjust the time of the second device to be synchronized with the time of the first device.

[0085] For example, the time synchronization between the second device and the first device can be performed as follows: the second device obtains a local timestamp value of the second device in receiving the timestamp sequence, and the local timestamp value is equal to a sum of the timestamp value, a difference between the first reception time and the second reception time, the physical layer transmission delay of the first device, and the physical layer reception delay of the second device. Here, the local timestamp value of the second device in receiving the timestamp sequence can refer to a value that needs to be refreshed when the second device performs a synchronization operation after receiving the timestamp sequence.

[0086] wherein, if a local timestamp value that needs to be refreshed when the second device performs a synchronization operation after receiving the timestamp sequence is denoted as RX_TimeStamp_Counter, the timestamp value is denoted as TimeStamp_value, the difference between the first reception time and the second reception time is denoted as Receive_delay, the physical layer transmission delay of the first device is denoted as TX_DLY, and the physical layer reception delay of the second device is denoted as RX_DLY, the local timestamp value RX_TimeStamp_Counter satisfies the following formula (1). RX_TimeStamp_Counter=TimeStamp_value+Receive_delay+TX_DLY+RX_DLY (1)

[0087] It can be understood that the local timestamp value of the timestamp sequence received by the second device described above, the order of the difference between the first receiving time and the second receiving time, the physical layer transmission delay of the first device, and the physical layer receiving delay of the second device in the formula are only exemplary and do not limit the embodiments of the present application. In addition, the difference between the first receiving time and the second receiving time, the physical layer transmission delay of the first device, and the physical layer receiving delay of the second device can be used to calculate the delay of the transmission path of the burst, which can be referred to as a path delay. The sum of the above three is used as an example in the above example.

[0088] In the process of performing time synchronization between the second device and the first device described above, not only the difference between the first receiving time and the second receiving time is considered, but also the physical layer transmission delay of the first device and the physical layer receiving delay of the second device are considered, thereby further improving the accuracy of time synchronization.

[0089] In the embodiments of the present application, the first device and the second device are based on the same frequency and phase clock timing, the first device sends a burst to the second device, the timestamp sequence in the burst includes a K code sequence and a timestamp value, the K code sequence is used to mark the timestamp sequence, and the timestamp value is used to indicate the time when the target bit in the burst is sent to the physical layer of the first device. The target bit is located in the synchronization sequence or the alignment sequence in the burst, so that the second device can realize time synchronization between the second device and the first device according to the received timestamp value in the burst and the path delay, and the path delay is the delay of the burst in the transmission path. That is, the time synchronization between the devices can be realized by transmitting a burst once between the first device and the second device, and multiple handshakes are not required, thereby greatly shortening the synchronization time and reducing the power consumption.

[0090] The above mainly introduces the scheme provided by the embodiments of the present application from the perspective of the interaction between the first device and the second device. It can be understood that the first device and the second device include the corresponding hardware structure and / or software module for executing each function in order to realize the above functions. Those skilled in the art should easily realize that the units and algorithm steps of each example described in combination with the embodiments disclosed in the present application can be realized in the form of hardware or a combination of hardware and computer software. Whether a certain function is executed in hardware or computer software driven hardware depends on the specific application and design constraints of the technical solution. Professional technicians can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of the present application.

[0091] The embodiments of the present application can divide the functional modules of the first device and the second device according to the above method examples. For example, each functional module can be divided according to each function, or two or more functions can be integrated in one module. The integrated module can be implemented in the form of hardware or in the form of a software functional module. It should be noted that the division of the modules in the embodiments of the present application is illustrative, and is only a logical function division. In actual implementation, another division mode can be used. The following will be described by taking the division of each functional module according to each function as an example.

[0092] In the case of using an integrated unit, FIG. 8 shows a structural schematic diagram of a first device involved in the above embodiments. The first device can be a device or a chip applied to the device or a module inside the device, and the device includes a processing unit 301 and a sending unit 302. In a possible embodiment, the processing unit 301 is configured to support the device to perform S201 in the above method embodiments; and the sending unit 302 is configured to support the device to perform S202a in the above method embodiments. The sending unit 302 can be an interface module. All related contents of each step involved in the above method embodiments can be referred to the function description of the corresponding functional module, which will not be described herein again.

[0093] On the basis of using hardware implementation, the processing unit 301 in the embodiments of the present application can be a processing circuit of the device, and the sending unit 302 can be a transmitter of the device. The transmitter can be integrated with a receiver to serve as a transceiver. The specific transceiver can also be referred to as a communication interface or an interface circuit.

[0094] FIG. 9 is a structural schematic diagram of another first device provided by the embodiments of the present application. The device can be a device or a chip applied to the device, and the device includes a processing circuit 311 and a transmitter 312. In a possible embodiment, the processing circuit 311 is configured to support the device to perform S201 in the above method embodiments and / or other technical processes described herein; and the transmitter 312 is configured to support the device to communicate, for example, to support the device to communicate with a second device. The transmitter 312 can be an interface element.

[0095] In the embodiments of the present application, the processing circuit 311 can be a processor, which can include a central processing unit, a general processor, a digital signal processor, an application specific integrated circuit, a field programmable gate array or other programmable logic device, a transistor logic device, a hardware component or any combination thereof. It can implement or execute various exemplary logic blocks, modules and circuits described in combination with the disclosure of the present application. The processor can also be a combination of computing functions, such as one or more microprocessor combinations, combinations of digital signal processors and microprocessors, etc.

[0096] In the case of employing an integrated unit, FIG. 10 shows a structural diagram of a second device involved in the above-described embodiments. The device can be a device or a chip applied to a device, and the device includes a receiving unit 401 and a processing unit 402. In a possible embodiment, the receiving unit 401 is configured to support the device to perform S202b in the above-described method embodiments, and the receiving unit 401 can be an interface module; the processing unit 402 is configured to support the device to perform S203 in the above-described method embodiments, and / or other technical processes described herein. All related contents of the steps involved in the above-described method embodiments can be cited to the function description of the corresponding functional modules, and the embodiments of the present application will not be described here again.

[0097] On the basis of employing hardware, the processing unit 402 in the embodiments of the present application can be a processing circuit of the device, and the receiving unit 401 can be a receiver of the device. The receiver can be integrated with a transmitter to serve as a transceiver, and the specific transceiver can also be referred to as a communication interface or an interface circuit.

[0098] FIG. 11 is a structural diagram of another second device provided by the embodiments of the present application. The device can be a device or a chip applied to a device, and the device includes a receiver 411 and a processing circuit 412. In a possible embodiment, the processing circuit 412 is configured to support the device to perform S203 in the above-described method embodiments, and / or other technical processes described herein; the receiver 411 is configured to support the device to communicate, such as supporting the device to communicate with a first device, and the receiver 411 can be an interface element.

[0099] In the embodiments of the present application, the processing circuit 412 can be a processor, which can include a central processing unit, a general-purpose processor, a digital signal processor, an application-specific integrated circuit, a field programmable gate array, or other programmable logic device, a transistor logic device, a hardware component, or any combination thereof. It can implement or execute various exemplary logical blocks, modules and circuits described in combination with the disclosure of the present application. The processor can also be a combination of computing functions, such as one or more microprocessor combinations, combinations of digital signal processors and microprocessors, and the like.

[0100] In another embodiment of the present application, an electronic device is provided, which includes a first device and a second device connected through an interface; wherein the first device can be or include the device provided in FIG. 8 or FIG. 9, and is configured to perform the steps of the first device in the above-provided method embodiments; the second device can be or include the device provided in FIG. 10 or FIG. 11, and is configured to perform the steps of the second device in the above-provided method embodiments.

[0101] It can be understood that all related contents of the steps involved in the above method embodiments can be cited into the embodiments of the first device and the second device, and the embodiments of the electronic device, which will not be described herein again.

[0102] In several embodiments provided in the present application, it should be understood that the disclosed method and device can be implemented in other manners. For example, the described device embodiments are merely schematic, and the division of the modules or units is merely a logical function division, and there can be another division manner in actual implementation. For example, a plurality of units or components can be combined or integrated into another device, or some features can be ignored or not executed.

[0103] The integrated unit, if realized in the form of a software function unit and sold or used as an independent product, can be stored in a readable storage medium, which can include a U disk, a mobile hard disk, a read-only memory, a random access memory, a magnetic disk or an optical disk, and various storage medium that can store program codes. Based on such understanding, the technical solutions of the embodiments of the present application can be embodied in the form of a software product, essentially or say the part of the prior art that makes a contribution or the whole or part of the technical solutions.

[0104] In another embodiment of the present application, a readable storage medium is also provided, which stores a computer program or instructions, and when a device runs the computer program or instructions, the device executes the steps of the first device in the above method embodiments.

[0105] In another embodiment of the present application, a readable storage medium is also provided, which stores a computer program or instructions, and when a device runs the computer program or instructions, the device executes the steps of the second device in the above method embodiments.

[0106] In still another embodiment of the present application, a computer program product is also provided, which includes a computer program, and when the computer program is executed by a device, the device executes the steps of the first device in the above method embodiments.

[0107] In still another embodiment of the present application, a computer program product is also provided, which includes a computer program, and when the computer program is executed by a device, the device executes the steps of the second device in the above method embodiments.

[0108] Finally, it should be noted that the above only describes specific embodiments of the present application, but the protection scope of the present application is not limited thereto, and any changes or replacements within the technical scope disclosed by the present application should be covered in the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. A method of synchronizing an inter-device interface, the method comprising: The method comprises: generating a burst, the burst comprising a synchronization sequence, an alignment sequence, a timestamp sequence and a burst end sequence, the synchronization sequence being used for physical layer synchronization between the first device and the second device, the alignment sequence being located after the synchronization sequence, the timestamp sequence being located after the alignment sequence, the burst end sequence being located after the timestamp sequence, the timestamp sequence comprising a K code sequence and a timestamp value, the K code sequence being used for marking the timestamp sequence, the timestamp value being used for indicating a time instant when a target bit in the burst is sent to a physical layer of the first device, the target bit being located in the synchronization sequence or the alignment sequence; sending the burst to the second device; wherein the first device and the second device are clocked based on a same frequency and phase clock.

2. The method of claim 1, wherein, The target bit is a first bit of the alignment sequence.

3. The method according to claim 1 or 2, characterized in that, The same frequency and phase clock is a same clock shared between the first device and the second device.

4. The method according to any one of claims 1 to 3, characterized in that, The burst further comprises service data, the service data being located between the alignment sequence and the timestamp sequence.

5. The method according to any one of claims 1 to 4, characterized in that, The timestamp sequence further comprises a check code, the check code being used for checking the timestamp value.

6. A method of synchronizing an inter-device interface, the method comprising: The method comprises: receiving a burst from a first device, the burst comprising a synchronization sequence, an alignment sequence, a timestamp sequence and a burst end sequence, the synchronization sequence being used for physical layer synchronization between the first device and the second device, the alignment sequence being located after the synchronization sequence, the timestamp sequence being located after the alignment sequence, the burst end sequence being located after the timestamp sequence, the timestamp sequence comprising a K code sequence and a timestamp value, the K code sequence being used for marking the timestamp sequence, the timestamp value being used for indicating a time instant when a target bit in the burst is sent to a physical layer of the first device, the target bit being located in the synchronization sequence or the alignment sequence; performing time synchronization between the second device and the first device according to the timestamp value, a first receiving time instant of the target bit by the second device and a second receiving time instant of the timestamp sequence by the second device; wherein the first device and the second device are clocked based on a same frequency and phase clock.

7. The method of claim 6, wherein, The target bit is a first bit of the alignment sequence.

8. The method according to claim 6 or 7, characterized in that, The same frequency and phase clock is a same clock shared between the first device and the second device.

9. The method according to any one of claims 6-8, characterized in that, The burst further comprises service data, the service data being located between the alignment sequence and the timestamp sequence.

10. The method according to any one of claims 6-9, characterized in that, The timestamp sequence further comprises a check code, the check code being used for checking the timestamp value.

11. The method according to any one of claims 6-10, characterized in that, The performing time synchronization between the second device and the first device according to the timestamp value, a first receiving time instant of the target bit by the second device and a second receiving time instant of the timestamp sequence by the second device comprises: According to the timestamp value, the first receiving time, the second receiving time, a physical layer sending delay of the first device and a physical layer receiving delay of the second device, time synchronization between the second device and the first device is performed.

12. The method of claim 11, wherein, The time synchronization between the second device and the first device comprises: A local timestamp value T0 of the second device receiving the timestamp sequence is obtained, wherein the T0 is equal to a sum of the timestamp value, a difference between the first receiving time and the second receiving time, the physical layer sending delay of the first device and the physical layer receiving delay of the second device.

13. A synchronization apparatus, characterized by comprising: The device is used as the first device, and the method comprises: A processing unit is configured to generate a burst, wherein the burst comprises a synchronization sequence, an alignment sequence, a timestamp sequence and a burst end sequence, the synchronization sequence is used for physical layer synchronization between the first device and the second device, the alignment sequence is located after the synchronization sequence, the timestamp sequence is located after the alignment sequence, the burst end sequence is located after the timestamp sequence, the timestamp sequence comprises a K code sequence and a timestamp value, the K code sequence is used for marking the timestamp sequence, and the timestamp value is used for indicating a time when a target bit in the burst is sent to a physical layer of the first device, and the target bit is located in the synchronization sequence or the alignment sequence; A sending unit is configured to send the burst to the second device; The first device and the second device are clocked based on a same frequency and phase clock.

14. The synchronization apparatus of claim 13, wherein, The target bit is a first bit of the alignment sequence.

15. The synchronization apparatus according to claim 13 or 14, characterized by The same frequency and phase clock is a same clock shared between the first device and the second device.

16. The synchronization apparatus of any of claims 13-15, wherein, The burst further comprises service data, and the service data is located between the alignment sequence and the timestamp sequence.

17. The synchronization apparatus of any of claims 13-16, wherein, The timestamp sequence further comprises a check code, and the check code is used for checking the timestamp value.

18. A synchronization apparatus, comprising: The device is used as the second device, and the method comprises: A receiving unit is configured to receive a burst from a first device, wherein the burst comprises a synchronization sequence, an alignment sequence, a timestamp sequence and a burst end sequence, the synchronization sequence is used for physical layer synchronization between the first device and the second device, the alignment sequence is located after the synchronization sequence, the timestamp sequence is located after the alignment sequence, the burst end sequence is located after the timestamp sequence, the timestamp sequence comprises a K code sequence and a timestamp value, the K code sequence is used for marking the timestamp sequence, and the timestamp value is used for indicating a time when a target bit in the burst is sent to a physical layer of the first device, and the target bit is located in the synchronization sequence or the alignment sequence; A processing unit is configured to perform time synchronization between the second device and the first device according to the timestamp value, a first receiving time of the second device to the target bit and a second receiving time of the second device to the timestamp sequence; The first device and the second device are clocked based on a same frequency and phase clock.

19. The synchronization apparatus of claim 18, wherein, The target bit is a first bit of the alignment sequence.

20. The synchronization apparatus of claim 18 or 19, wherein, The clock of the same frequency and phase is a same clock shared between the first device and the second device.

21. The synchronization apparatus of any of claims 18-20, wherein, The burst further includes service data, the service data being located between the alignment sequence and the timestamp sequence.

22. The synchronization apparatus of any of claims 18-21, wherein, The timestamp sequence further includes a check code, the check code being used to check the timestamp value.

23. The synchronization apparatus of any of claims 18-22, wherein, The processing unit is further configured to: perform time synchronization between the second device and the first device according to the timestamp value, the first receiving time, the second receiving time, a physical layer transmission delay of the first device, and a physical layer reception delay of the second device.

24. The synchronization apparatus of claim 23, wherein, The processing unit is further configured to: obtain a local timestamp value T0 of the second device receiving the timestamp sequence, the T0 being equal to a sum of the timestamp value, a difference between the first receiving time and the second receiving time, the physical layer transmission delay of the first device, and the physical layer reception delay of the second device.

25. A synchronization apparatus, comprising: The synchronization device includes a processing circuit and a transmitter, the processing circuit and the transmitter being configured to support the device to perform the method according to any one of claims 1-5.

26. A synchronization apparatus, comprising: The device includes a processing circuit and a receiver, the processing circuit and the receiver being configured to support the device to perform the method according to any one of claims 6-12.

27. An electronic device, comprising: The electronic device includes a first device and a second device connected through an interface, the first device including the device according to any one of claims 13-17 or the device according to claim 25, and the second device including the device according to any one of claims 18-24 or the device according to claim 26.

28. A readable storage medium, characterized by The readable storage medium stores instructions, when a device executes the instructions, causing the device to perform the method according to any one of claims 1-12.

29. A computer program product, characterised in that, The computer program product includes a computer program, when the computer program is executed by a device, causing the device to perform the method according to any one of claims 1-12.

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