Bit interleaving method, electronic device, and computer-readable storage medium

Abstract

Embodiments of the present disclosure provide a bit interleaving method, an electronic apparatus, and a computer-readable storage medium. The method comprises: dividing a bit sequence to be interleaved into two parts; performing bit interleaving on a first part by using a first interleaving mode; and performing bit interleaving or not performing bit interleaving on a second part by using a second interleaving mode. The first interleaving mode is different from the second interleaving mode.

Description

Bit interleaving method, electronic device and computer readable storage medium

[0001] Cross-reference to related applications

[0002] The present disclosure is based on Chinese Patent Application No. CN202411348960.7 entitled “Bit interleaving method, electronic device and computer readable storage medium” filed on September 25, 2024, and claims priority to the same, the disclosure of which is incorporated herein by reference in its entirety. TECHNICAL FIELD

[0003] Embodiments of the present disclosure relate to the field of communication, in particular, to a bit interleaving method, an electronic device and a computer readable storage medium. BACKGROUND

[0004] ITU-T G.9804.2 HSP (Higher speed passive optical network) can optionally use bit interleaving function in the downlink direction to deal with bit concentration errors, and the interleaving method is that bit interleaving is performed on every 4 FEC code blocks, wherein each Forward Error Correction (FEC) code block is 17280 bits, and the interleaving method is shown in FIG. 1.

[0005] FIG. 1 is a schematic diagram of G.9804.2 bit interleaving. As shown in FIG. 1, the bit interleaving process is the formation process from four code blocks to one interleaved block in the sending process. For every 4 FEC code blocks, one bit is taken from the front of the first code block and sent, one bit is taken from the front of the second code block and sent, one bit is taken from the front of the third code block and sent, one bit is taken from the front of the fourth code block and sent in order, then the second bit is taken from the first, second, third and fourth code blocks in order, and so on, until all the bits of the four code blocks are sent, forming one interleaved block with a total of 17280*4=69120 bits. In the receiving process, the formation process from one interleaved block to 4 code blocks. For every 4 interleaved blocks of 17280 bits, the first bit is taken as the first bit of the first code block, the second bit is taken as the first bit of the second code block, the third and fourth bits are taken as the first bits of the third and fourth code blocks, the fifth, sixth, seventh and eighth bits are taken as the second bits of the first, second, third and fourth code blocks, respectively, and so on, until the 4*17280 bit interleaved block forms 4 FEC code blocks.

[0006] ITU-T G.9804.2 HSP, when the downstream rate is 49.7664 Gbps, the length of 125 microseconds of a superframe is 777600 bytes, that is, 6220800 bits, which is 360 times of 17280 bits, and can be divided into 90 code block groups, each code block group is 4 FEC code blocks, the length of a downstream superframe is an integer multiple of 4 FEC code blocks, and complete 4 FEC code block bit interleaving can be used. At present, the standard organization discusses that different FEC code types need to be introduced according to the link loss of the downstream, potential FEC code type options are LDPC (15872, 14592), LDPC (17664-S, 14592-S), wherein S = CS * 256, CS is a value between 19 and 35, or other more general LDPC (C, P), wherein C is a code block length, P is a payload length, C-P is a check length, wherein LDPC is Low Density Parity Check, the FEC code block lengths are 15872 bits, 17664-S bits and C bits respectively, when these FEC code type options are used, the length of a downstream superframe can no longer be an integer multiple of 4 FEC code blocks, therefore, how to implement bit interleaving of a non-specified interleaving block integer multiple is a problem to be studied. SUMMARY

[0007] Embodiments of the present disclosure provide a bit interleaving method, an electronic device and a computer readable storage medium to at least solve the problem of bit interleaving of a non-specified interleaving block integer multiple in the related art.

[0008] According to an embodiment of the present disclosure, a bit interleaving method is provided, which includes: dividing a bit sequence to be interleaved into two parts, performing bit interleaving on a first part by using a first interleaving manner, and performing bit interleaving or not performing bit interleaving on a second part by using a second interleaving manner, wherein the first interleaving manner is different from the second interleaving manner.

[0009] According to another embodiment of the present disclosure, a computer readable storage medium is also provided, and the computer readable storage medium stores a computer program, wherein the computer program is set to execute the steps in any of the method embodiments when running.

[0010] According to another embodiment of the present disclosure, an electronic device is also provided, which includes a memory and a processor, the memory stores a computer program, and the processor is set to run the computer program to execute the steps in any of the method embodiments.

[0011] According to still another embodiment of the present disclosure, a computer program product is also provided, comprising a computer program which, when executed by a processor, implements the steps of any of the method embodiments described above. BRIEF DESCRIPTION OF DRAWINGS

[0012] FIG. 1 is a schematic diagram of a bit interleaving process according to the related art;

[0013] FIG. 2 is a schematic diagram of a system architecture operated by a bit interleaving method according to an embodiment of the present disclosure;

[0014] FIG. 3 is a flowchart of a bit interleaving method according to an embodiment of the present disclosure;

[0015] FIG. 4 is a schematic diagram of a basic interleaving mode according to an embodiment of the present disclosure;

[0016] FIG. 5 is a schematic diagram of an uplink bandwidth according to an embodiment of the present disclosure;

[0017] FIG. 6 is a schematic diagram of a bandwidth tail interleaving mode according to an embodiment of the present disclosure;

[0018] FIG. 7 is a schematic diagram of the structure of an electronic device according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0019] Embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings and in conjunction with embodiments.

[0020] It should be noted that the terms "first", "second", etc. in the specification and claims of the present disclosure and the above-described drawings are used to distinguish similar objects, and do not necessarily have to describe a specific order or sequence.

[0021] As described above, when the ITU-T G.9804.2 HSP downlink adopts the FEC code type option, the downlink superframe length can no longer be an integer multiple of 4 FEC code blocks. Therefore, how to implement bit interleaving for a non-specified interleaving block integer multiple of the region to be interleaved is a problem that needs to be studied. In addition, the ITU-T G.9804.2 HSP uplink direction also has a bit concentration error, so there is a need for bit interleaving function in the uplink. The uplink direction is allocated by the OLT (Optical Line Terminal) to the ONU (Optical Network Unit), and the uplink bit interleaving is generally implemented within a burst sent by a single ONU. The uplink service of the ONU is dynamically changing, and the obtained uplink bandwidth is also dynamically changing. Within a certain specific burst, assuming that the FEC code type is LDPC (C, P), the region to be interleaved can not be an integer multiple of 4 FEC code blocks. For the part less than 4 FEC code blocks, the bit interleaving method shown in FIG. 1 can not be used.

[0022] In view of the above, how to implement bit interleaving of a to-be-interleaved region that is not an integer multiple of a specified interleaving block is a problem to be studied. Embodiments of the present disclosure provide a bit interleaving method and an electronic device, a computer readable storage medium, and a computer program product.

[0023] The method embodiments provided in the embodiments of the present application can be executed in a mobile terminal, a computer terminal, or a similar computing device. Taking a computer terminal as an example, FIG. 2 is a hardware structure block diagram of a computer terminal on which the method embodiments of the present disclosure are executed. As shown in FIG. 2, the computer terminal can include one or more (only one is shown in FIG. 2) processors 102 (the processor 102 can include, but is not limited to, a processing device such as a microprocessor MCU or a programmable logic device FPGA) and a memory 104 for storing data, wherein the computer terminal can further include a transmission device 106 for communication function and an input and output device 108. Those skilled in the art can understand that the structure shown in FIG. 2 is only schematic, and does not limit the structure of the computer terminal. For example, the computer terminal can include more or fewer components than those shown in FIG. 2, or have a different configuration from that shown in FIG. 2.

[0024] The memory 104 can be used to store computer programs, for example, software programs of application software and modules, such as a computer program corresponding to the bit interleaving method in the embodiments of the present disclosure. The processor 102 executes various function applications and data processing by running the computer programs stored in the memory 104, that is, implements the above method. The memory 104 can include a high-speed random access memory, and can further include a non-volatile memory, such as one or more magnetic storage devices, a flash memory, or other non-volatile solid-state memories. In some examples, the memory 104 can further include a memory remotely arranged with respect to the processor 102, and the remote memory can be connected to the computer terminal through a network. Examples of the network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and a combination thereof.

[0025] The transmission device 106 is used to receive or send data via a network. Specific examples of the network can include a wireless network provided by a communication provider of the computer terminal. In one example, the transmission device 106 includes a network adapter (Network Interface Controller, NIC), which can be connected to other network devices through a base station so as to communicate with the Internet. In one example, the transmission device 106 can be a radio frequency (Radio Frequency, RF) module, which is used to communicate with the Internet in a wireless manner.

[0026] A bit interleaving method executable on the computer terminal is provided in the embodiment, and FIG. 3 is a flowchart of the bit interleaving method according to the embodiment of the present disclosure. As shown in FIG. 3, the flowchart comprises the following steps:

[0027] In step S302, the bit sequence to be interleaved is divided into two parts, wherein the first part is a part satisfying a specified length, and the second part is a part not satisfying the specified length.

[0028] The bit interleaving method provided in the embodiment can be applied to bit interleaving in a case where a flexible FEC code type is used in downlink or a case where a flexible uplink bandwidth allocation and a flexible FEC code type are used in uplink. Therefore, the bit sequence to be interleaved can be, for example, a downlink superframe or an uplink burst frame.

[0029] In the embodiment, the first part refers to a part satisfying a specified interleaving block integer multiple, and the second part refers to a part not satisfying the specified interleaving block integer multiple after the first part is removed. For example, when a G.9804.2 HSP downlink direction uses an LDPC (15872, 14592) FEC code type, the code block length is 15872 bits, the payload length is 14592 bits, the check length is 15872-14592=1280 bits, the downlink superframe length is 6220800 bits, which is 391 code blocks and a remaining 14848 bits, and 4-code block bit interleaving is used, 388 code blocks are the first part satisfying the specified interleaving block integer multiple, and the remaining 3 code blocks and 14848 bits are the second part not satisfying the specified interleaving block integer multiple.

[0030] In step S304, a first interleaving manner is used to perform bit interleaving on the first part, and a second interleaving manner is used to perform bit interleaving or not perform bit interleaving on the second part.

[0031] In the embodiment, different interleaving manners can be used to perform bit interleaving on the first part and the second part. For example, the number of interleaving blocks of the first interleaving manner is different from the number of interleaving blocks of the second interleaving manner, or the interleaving block length of the first interleaving manner is different from the interleaving block length of the second interleaving manner.

[0032] The first interleaving manner can use a specified number of interleaving blocks and a specified interleaving block length. For example, 4-code block bit interleaving is used, and each code block length is 15872 bits. One bit from the front of the first bit block is transmitted first, one bit from the front of the second bit block is transmitted second, one bit from the front of the third bit block and one bit from the front of the fourth bit block are transmitted in sequence third and fourth, respectively, and then the second bits from the first, second, third, and fourth bit blocks are transmitted in sequence, and so on, until all the 4 bit blocks are transmitted, to form an interleaving block of a total of 4*15872 bits.

[0033] For the second interleaving mode, the number of interleaving blocks of the second interleaving mode can be indicated by configuration information.

[0034] For example, for the first part and the second part divided by the step S302, the first part includes 388 FEC codes, and the first part can be interleaved according to the 4-code block bit interleaving mode. The second part includes 3 code blocks and 14848 bits, that is, 62464 bits, and the second part is interleaved according to the second interleaving mode. That is, the second part is divided into 4 bit blocks, each bit block has 15616 bits, and 1280 bits in each bit block are check bits and 14336 bits are payload bits. When calculating the check, the payload is padded with 0 in front or behind to 14592 bits, and then the check bits are calculated according to LDPC (15872, 14592). The interleaving mode can still be interleaved according to the interleaving mode described in the foregoing, that is, the first bit of each bit is sent in turn until all 4 bit blocks are sent. The number of bit blocks n = 4, and the bit block length X = 15616. The length of the interleaving block of the second interleaving mode is different from the length of the interleaving block of the first interleaving mode.

[0035] According to the steps S302 and S304, since the bit sequence to be interleaved is divided into two parts, the first interleaving mode is used for bit interleaving for the part satisfying the specified interleaving block integer multiple, and the second interleaving mode is used for bit interleaving for the part not satisfying the specified interleaving block integer multiple, and thus the bit interleaving problem of the interleaving area being a non-specified interleaving block integer multiple can be solved.

[0036] In some embodiments, the above steps are mainly described from the interleaving end. Similarly, at the deinterleaving end, the deinterleaving mode corresponding to the interleaving method described above can be used for deinterleaving, so as to obtain the original bit sequence. For example, at the deinterleaving end, for each n*X bit interleaving block, the first bit of the interleaving block is taken as the first bit of the first bit block, the second bit of the interleaving block is taken as the first bit of the second bit block, the third,..., n bits of the interleaving block are taken as the first bits of the third,..., n bit blocks, respectively, the n+1, n+2,..., 2n bits of the interleaving block are taken as the second bits of the first, second,..., n bit blocks, respectively, and so on, until n*X bits form n bit blocks.

[0037] In order to facilitate the understanding of the technical solutions provided by the present disclosure, the following will be described in combination with the embodiments of the specific implementation scenarios.

[0038] Before describing the embodiments of the specific implementation scenarios of the present disclosure, the basic interleaving mode involved in the embodiments of the present disclosure will be introduced first.

[0039] The basic interleaving mode involved in the embodiments of the present disclosure is shown in FIG. 4. n X-bit bit blocks are interleaved into n*X-bit interleaving blocks, and the n*X-bit interleaving blocks are deinterleaved into n X-bit bit blocks.

[0040] In the sending process, for every n bit blocks, one bit from the first bit block is sent first, one bit from the second bit block is sent next, one bit from the third bit block is sent next, and so on, until all n bit blocks are sent, forming an interleaving block of n*X bits.

[0041] In the receiving process, for every n*X-bit interleaving block, the first bit of the interleaving block is taken as the first bit of the first bit block, the second bit of the interleaving block is taken as the first bit of the second bit block, the third bit of the interleaving block is taken as the first bit of the third bit block, and so on, until n*X bits form n bit blocks.

[0042] Taking the FEC code type LDPC (17280, 14592) in the existing standard and the 4 FEC code block interleaving mode as an example, the interleaving and deinterleaving are performed in the manner of FIG. 4, the bit block number n = 4, and the bit block length X = 17280. For shorter bit blocks, which are less than 4*17280 bits, they can be represented as n*X', and the bit block length X' < 17280. When X' ≤ the check length (here, 17280-14592 = 2688), these bit blocks do not send service data, because X' bits are insufficient to send the payload, and therefore only the padding value is sent. Of course, in order to consider the bandwidth utilization, this part can adopt a new interleaving mode, for example, a smaller bit block number n' is adopted to obtain a larger bit block, or even a single FEC code block is sent without interleaving, so that these parts can send the payload in addition to the check. This function is realized by configuration. When X' > the check length, X' can send the payload in addition to the check, and a flexible bit interleaving mode can be adopted to continue to perform interleaving in the manner of FIG. 4, and the bit block number n = 4 remains unchanged, and the bit block length X = X' can be used.

[0043] The interleaving mode of the tail (i.e., the second part in the foregoing embodiment) (i.e., the second interleaving mode in the foregoing embodiment) can be set by, for example, two bits of RR in the 6th byte of a Burst_Profile message, as shown in Table 1 below. For example, when RR=00, it indicates that the tail part is not interleaved, when RR=01, it indicates that the tail uses 2-code block interleaving, when RR=10, it indicates that the tail uses 3-code block interleaving, and when RR=11, it indicates that the tail uses 4-code block interleaving. RR is valid for both uplink and downlink.

[0044] Table 1

[0045] Embodiment One

[0046] In this embodiment one, the interleaving of LDPC (15872, 14592) FEC code type in the downlink direction of G.9804.2 HSP is taken as an example for description.

[0047] When the LDPC (15872, 14592) FEC code type is used in the downlink direction of G.9804.2 HSP, the code block length is 15872 bits, the payload length is 14592 bits, and the check length is 15872-14592=1280 bits. The bit interleaving mode is as follows:

[0048] The downlink superframe length is 6220800 bits, which is 391 code blocks and a remaining 14848 bits. Assuming that 4-code block bit interleaving is used, 388 code blocks can be interleaved into 97 interleaving blocks, and the remaining 3 code blocks and 14848 bits cannot be interleaved completely using 4-code block bit interleaving. Therefore, a tail bit interleaving method (i.e., the second interleaving mode of the second part in the foregoing embodiment) is used.

[0049] The tail bit interleaving method of this embodiment one is that 62464 bits of 3 code blocks and 14848 bits are divided into 4 bit blocks, each bit block is 15616 bits, and in each bit block, 1280 bits are check bits and 14336 bits are payload bits. When calculating the check, the payload needs to be padded with 0 in front or behind to 14592 bits and then calculate the check bits according to LDPC (15872, 14592). Then, the tail bit interleaving method is used, that is, the interleaving method shown in FIG. 4 is still used, where the number of bit blocks n=4 and the bit block length X=15616. The specific interleaving process is not repeated here.

[0050] Embodiment Two

[0051] In this embodiment two, the LDPC (17664-CS*256, 14592-CS*256) FEC code type in the downlink direction of G.9804.2 HSP is taken as an example for description.

[0052] When G.9804.2 HSP downlink direction adopts LDPC (17664-CS*256, 14592-CS*256) FEC code type (where CS is 19 to 35), the code block length is 17664-CS*256 bits, the payload length is 14592-CS*256 bits, and the check length is (17664-CS*256)-(14592-CS*256)=3072 bits, and the bit interleaving mode is as follows:

[0053] When CS=19, it is LDPC (12800, 9728), the code block length is 12800 bits, the payload length is 9728 bits, the downlink superframe length is 6220800 bits, which is 486 code blocks, assuming that 4 code block bit interleaving is adopted, then 484 code blocks can be interleaved into 121 interleaving blocks by 4 code block bit interleaving, the remaining 2 code blocks are 19456 bits, which are divided into 4 bit blocks, each bit block is 4864 bits, of which 3072 bits are check bits and 1792 bits are payload bits. When calculating the check, the payload needs to be padded with 0 in front or behind to 9728 bits, and then the check bits are calculated according to LDPC (12800, 9728) to form a code block of 12800 bits long, and then tail bit interleaving method is adopted, that is, still according to the interleaving method shown in Figure 4, the bit block number n=4, and the bit block length X=4864.

[0054] When CS=35, it is LDPC (8704, 5632), the code block length is 8704 bits, the payload length is 5632 bits, the downlink superframe length is 6220800 bits, which is 712 code blocks and remaining 23552 bits, assuming that 4 code block bit interleaving is adopted, then 712 code blocks can be interleaved into 178 interleaving blocks by 4 code block bit interleaving, the remaining 23552 bits are divided into 4 bit blocks, each bit block is 5888 bits, of which 3072 bits are check bits and 2816 bits are payload bits. When calculating the check, the payload needs to be padded with 0 in front or behind to 5632 bits, and then the check bits are calculated according to LDPC (8704, 5632) to form a code block of 8704 bits long, and then tail bit interleaving method is adopted, that is, still according to the interleaving method shown in Figure 4, the bit block number n=4, and the bit block length X=5888.

[0055] Other CS values, as shown in Table 2 (taking 4-bit block interleaving as an example), when CS = 24, the number of downlink code blocks is exactly an integer multiple of 4, and bit interleaving can be performed according to the bit block number n = 4 and the bit block length X = 11520; when CS = 22, the number of downlink code blocks is 129 4-bit blocks, and bit interleaving is performed according to the bit block number n = 4 and the bit block length X = 12032, and 4*3072 bits are left, each bit block is equal to the check length, and cannot carry the payload, so a padding value is sent, and CS = 26 is similar; CS = 23, 25, 28, and 32 respectively include 132, 138, 148, and 164 4-bit blocks, and bit interleaving is performed according to the bit block number n = 4, the bit block length X = 11776, 11264, 10496, and 9472, respectively, and the number of remaining bits is less than 4*3072, and the length of each bit block is less than 3072 bits, so a padding value is sent; other CS values are interleaved in the CS = 19 and 35 modes.

[0056] For CS = 22, 26, 23, 25, 28, and 32, in order to consider the bandwidth utilization, the tail part can adopt a new interleaving mode, for example, a smaller bit block number n' is used to obtain a larger bit block, or even no interleaving is performed and only one FEC code block is sent, so that these tail parts can send the payload in addition to sending the check.

[0057] Table 2 Interleaving reference under different CS conditions

[0058] Embodiment Three

[0059] This embodiment three is described taking uplink bit interleaving as an example.

[0060] G.9804.2 HSP uplink direction FEC adopts LDPC, and there are three code types, taking LDPC (17280, 14592) as an example, and taking 4 LDPC code block interleaving as an example.

[0061] The data transmission of the ONU uplink direction is arranged by the OLT allocated uplink bandwidth, as shown in FIG. 5, the OLT allocated uplink bandwidth includes the uplink bandwidth allocated to the T-CONT, such as GrantSize A (GrantSize A) and GrantSize B (GrantSize B) in FIG. 5, Allocation A (Allocation A) and Allocation B (Allocation B), and other implicitly allocated uplink bandwidth, including the bandwidth for FS header (FS header), FS trailer (FS trailer) and the like in FIG. 5, and the bandwidth for adding FEC check to the FS burst (Framing Sublayer burst, Framing Sublayer burst) FEC-protected data (FEC-protected data).

[0062] In the process of bandwidth allocation from the OLT to the ONU, in order to realize tail bit interleaving, 4 check blocks corresponding bandwidths are reserved for the payload of the FS burst tail. Of course, the OLT can also adjust the bandwidth allocation according to specific requirements. If in order to realize uniform bit interleaving in the upstream direction, the OLT can ensure that the FS burst length is an integer multiple of 4 FEC payloads when allocating upstream bandwidth; if in order to realize upstream bandwidth utilization, the payload of the FS burst tail can realize less bit block interleaving, or even no interleaving, so that the OLT can reserve less upstream bandwidth corresponding to the FEC check block.

[0063] The upstream bit interleaving starts from the first bit after the PSBu. The ONU completes the upstream FS burst framing according to the upstream bandwidth allocated by the OLT, and divides the FS burst frame into 4 FEC code block payloads, i.e. divides the FS burst frame into 4 segments of 14592 bits, adds a check to each segment to form a bit block of 17280 bits, and for a complete 4-bit block of 17280 bits, interleaves according to Figure 4, with a bit block length X = 17280 and a bit block number n = 4.

[0064] For a segment less than 4 segments of 14592 bits, divide it into 4 segments of length X' (<14592) on average, add a check block of 2688 bits to each segment to form a bit block of X'+2688, and then interleave according to Figure 4, where the bit block length X = X'+2688 and the bit block number n = 4.

[0065] The OLT calculates the length of the burst sent by the ONU according to the locally saved BWmap (Bandwidth map) and the upstream bit interleaving option, the burst starts from the first bit after the PSBu, and is divided into 4-bit blocks of 17280 bits, each interleaving block is de-interleaved according to the manner of Figure 4, where the bit block length X = 17280 and the bit block number n = 4. For an interleaving block less than 4*17280 bits, de-interleave according to the 4*X' manner and the inverse operation of the interleaving manner of Figure 4, where the bit block length X = X' and the bit block number n = 4.

[0066] For other tail interleaving manners, they are not described here.

[0067] Embodiment Four

[0068] This embodiment four also takes the upstream bit interleaving as an example for description.

[0069] G.9804.2HSP upstream FEC adopts LDPC, there are three code types, taking LDPC(17280,14592) as an example, and taking 4 LDPC code block interleaving as an example.

[0070] The ONU acquires the uplink bandwidth allocated by the OLT, completes uplink FS burst framing, and divides the FS burst frame according to a 4 FEC code block payload, that is, divides the FS burst frame according to 4 14592 bits.

[0071] For a complete 4 14592 bit segment, interleaving is performed according to FIG. 4, X = 14592, n = 4, the bit sequence after interleaving is re-divided into 4 14594 bit blocks, 2688 bit checks are calculated for each bit block, then the original payload block and the 4 checks are sent together, the 4 check blocks can be re-interleaved (according to FIG. 4, X = 2688, n = 4), and then each 2688 bit is sequentially placed after each 14592 bit block.

[0072] FIG. 6 is a schematic diagram of a bandwidth tail interleaving manner according to an embodiment of the present disclosure. As shown in FIG. 6, in the present embodiment, for a segment of less than 4 14592 bits in the tail, if the length is less than or equal to 4 2688 bits, the part is sent with a fill value, for example, all 0, otherwise, the length of the 4 2688 bit check blocks is subtracted, the remaining bandwidth is used to send service data to form an original payload block, the 4 14592 bit payload blocks are filled, then interleaving is performed according to FIG. 4, X = 14592, n = 4, the bit sequence after interleaving is re-divided into 4 14594 bit blocks, 2688 bit checks are calculated for each bit block, then the original payload block and the 4 checks are sent together, and the 4 check blocks can be re-interleaved (according to FIG. 4, X = 2688, n = 4). The detailed interleaving process of less than 4 FEC code blocks can be referred to FIG. 6.

[0073] In the embodiment of the present disclosure, bit interleaving is completed when the FEC check is added, and then scrambling is performed.

[0074] The uplink bit de-interleaving process of the embodiment of the present disclosure is described as follows.

[0075] The OLT calculates the length of the burst sent by the ONU according to the locally saved BWmap, de-scrambles the uplink burst, and then divides the burst according to 4 FEC code blocks, that is, divides the burst according to 4 17280 bits.

[0076] For a complete 4 17280 bit segment, de-interleaving is performed according to the inverse operation of the interleaving manner of FIG. 4, X = 17280, n = 4, after the FEC check is completed, 4*14592 is left, and then de-interleaving is performed according to the manner of FIG. 4, X = 14592, n = 4.

[0077] For the segment with tail less than 414592 bits, if the length is less than 4 2688 bits, the part is discarded, otherwise, 4 2688 bit check blocks are taken out, the remaining part forms the original payload block, fills up to 4 14592 bit payload blocks, each bit check block is inserted into the corresponding 14592 bit payload block, then deinterleaving is performed, X=17280, n=4, after the FEC check is completed, the 4 14592 bit payload blocks are deinterleaved again, X=14592, n=4, then the padding is removed, thereby obtaining the bit sequence before interleaving.

[0078] Through the description of the above embodiments, those skilled in the art can clearly understand that the method according to the above embodiments can be realized by means of software on a general hardware platform as necessary, and of course can also be realized by hardware, but in many cases the former is a better embodiment. Based on such understanding, the technical solutions of the disclosure can be embodied in the form of a software product in essence or in the form of a part of the prior art that makes a contribution. The computer software product is stored in a storage medium (such as a ROM / RAM, a magnetic disk, or an optical disk), and includes a plurality of instructions for causing a terminal device (which can be a mobile phone, a computer, a server, or a network device) to execute the method described in each embodiment of the disclosure.

[0079] The embodiments of the disclosure further provide a computer readable storage medium, which stores a computer program. The computer program is configured to execute the steps in any of the above method embodiments when running.

[0080] In an example embodiment, the above computer readable storage medium can include, but is not limited to, a U disk, a read-only memory (ROM), a random access memory (RAM), a mobile hard disk, a magnetic disk or an optical disk, and various media that can store computer programs.

[0081] The embodiments of the disclosure further provide a computer program product, which includes a computer program. The computer program is executed by a processor to implement the steps in any of the above method embodiments.

[0082] As shown in FIG. 7, the embodiments of the disclosure further provide an electronic device 400, which includes a processor 401 and a memory 402. The memory 402 stores a computer program, and the processor 401 is configured to run the computer program to execute the steps in any of the above method embodiments.

[0083] In one example embodiment, the electronic device 400 can further include a transmission device connected to the processor and an input / output device connected to the processor.

[0084] The specific examples in the present embodiment can refer to the examples described in the above embodiments and exemplary implementations, which will not be repeated here.

[0085] Obviously, those skilled in the art should understand that the modules or steps of the present disclosure described above can be realized by general computing devices, which can be concentrated on a single computing device or distributed on a network composed of multiple computing devices, which can be realized by program codes executable by the computing devices, so that they can be stored in storage devices and executed by the computing devices, and in some cases, the steps shown or described can be executed in different order, or they can be made into individual integrated circuit modules, or multiple modules or steps can be made into a single integrated circuit module. Thus, the present disclosure is not limited to any specific combination of hardware and software.

[0086] The above only describes the preferred embodiments of the present disclosure and is not intended to limit the present disclosure. Those skilled in the art can make various modifications and changes to the present disclosure. Any modification, equivalent replacement, improvement, etc. within the principles of the present disclosure shall be included in the protection scope of the present disclosure

Claims

1. A bit interleaving method, comprising: dividing a bit sequence to be interleaved into two parts, interleaving a first part using a first interleaving manner, and interleaving or not interleaving a second part using a second interleaving manner, wherein the first interleaving manner is different from the second interleaving manner.

2. The method of claim 1, wherein, the first interleaving manner is different from the second interleaving manner includes: a number of interleaving blocks of the first interleaving manner is different from a number of interleaving blocks of the second interleaving manner, or a length of interleaving blocks of the first interleaving manner is different from a length of interleaving blocks of the second interleaving manner.

3. The method of claim 1, wherein, the first interleaving manner includes a specified length of interleaving blocks and a number of interleaving blocks.

4. The method of claim 3, wherein, the first part is a part satisfying a specified length, and the second part is a part not satisfying the specified length, wherein the specified length is an integer multiple of a product of the number of interleaving blocks and the length of interleaving blocks specified by the first interleaving manner.

5. The method of claim 1, wherein, further comprising: indicating the second interleaving manner through configuration information in a first message, wherein the configuration information includes whether to perform bit interleaving on the second part, or a number of interleaving blocks of the second interleaving manner.

6. The method of claim 3, wherein, interleaving the first part using the first interleaving manner includes: interleaving the first part based on a number of interleaving blocks and a length of interleaving blocks specified by the first interleaving manner.

7. The method of claim 2, wherein, in a case where a length of the second part is less than or equal to a product of the number of interleaving blocks of the second interleaving manner and a check length, not performing bit interleaving on the second part; in a case where the length of the second part is greater than the product of the number of interleaving blocks of the second interleaving manner and the check length, interleaving the second part using the second interleaving manner.

8. The method of claim 7, wherein, interleaving the second part using the second interleaving manner includes: dividing the length of the second part by the number of interleaving blocks of the second interleaving manner to obtain a length of interleaving blocks of the second interleaving manner; interleaving the second part based on the number of interleaving blocks and the length of interleaving blocks of the second interleaving manner.

9. The method of claim 1, wherein, the bit sequence to be interleaved is a downlink frame or an uplink frame.

10. The method of claim 1, wherein, the length of interleaving blocks specified by the first interleaving manner is a length of a forward error correction (FEC) code block.

11. A computer-readable storage medium having stored therein a computer program, wherein, the computer program, when executed by a processor, implements steps of the method recited in any one of claims 1 to 10. 12.An electronic device comprising a memory, a processor, and a computer program stored on the memory and executable on the processor, wherein the processor, when executing the computer program, implements steps of the method recited in any one of claims 1 to 10. 13.A computer program product comprising a computer program, wherein the computer program, when executed by a processor, implements steps of the method recited in any one of claims 1 to 10.

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