Memory circuit and control method therefor, memory, and electronic device

Abstract

The present application relates to the technical field of storage, and provides a memory circuit and a control method therefor, a memory, and an electronic device, used for allowing a ferroelectric capacitor to be fully switched. The memory circuit comprises a first ferroelectric memory cell, a first current mirror, a first voltage generation circuit, a comparison circuit, and a first voltage end. The first current mirror comprises a first branch and a second branch, one end of the first branch and one end of the second branch are electrically connected to the first voltage end, and currents of the first branch and the second branch are identical. An output end of the first ferroelectric memory cell is electrically connected to the other end of the first branch at a first node, the other end of the second branch is electrically connected to an output end of the first voltage generation circuit and an input end of the comparison circuit at a second node, and an output end of the comparison circuit is electrically connected to an output end of the memory circuit.

Description

Storage circuit, control method thereof, memory and electronic device

[0001] The present application claims priority to the Chinese patent application No. 202411398212.X, filed on September 30, 2024, and entitled "Storage circuit, control method thereof, memory and electronic device", the content of which is incorporated herein by reference in its entirety. TECHNICAL FIELD

[0002] The present application relates to the technical field of storage, and in particular to a storage circuit, a control method thereof, a memory and an electronic device. BACKGROUND

[0003] With the rapid development of the chip industry, the performance and storage density of the memory gradually become important factors that limit the performance of the chip. As a new storage, the ferroelectric random access memory (FeRAM) based on hafnium-based material has reliability and speed close to the dynamic random access memory (DRAM), and the ferroelectric storage array in the FeRAM can be stacked in the back-end process and has non-volatile storage characteristics. These advantages make the FeRAM have wide potential application value in customized DRAM and embedded non-volatile memory (NVM) and other scenarios. The storage unit of the ferroelectric storage array includes a transistor and a ferroelectric capacitor (FeCap).

[0004] In the prior art, when reading a digital signal 1, the ferroelectric capacitor is polarized and the digital signal is read through a bit line (BL), which makes the potential on the bit line rise and accumulate over time, thereby reducing the potential difference between the plate line and the bit line connected to both ends of the ferroelectric capacitor, reducing the effective flipping voltage of the ferroelectric capacitor for controlling the flipping of the ferroelectric capacitor, and the flipping of the ferroelectric capacitor becomes slower and less sufficient. This phenomenon is the self-inhibition phenomenon of the FeRAM when reading the digital signal 1, which will affect the uniformity and reliability of the FeRAM, and also reduce the memory window (MW) of the FeRAM. SUMMARY

[0005] To solve the above technical problems, the application provides a storage circuit, a control method thereof, a memory and an electronic device, so that the potential on the first node is always kept at the initial voltage, to ensure that the potential difference between the plate line and the bit line is not reduced due to reading data, resulting in insufficient flipping of the ferroelectric capacitor. In order to normally read data by using the storage circuit, a second node can also be added, the potential on the second node is closely related to the charge output by the first ferroelectric storage unit when reading data, so that the potential on the second node can be used to determine whether the digital signal read by the storage circuit is 0 or 1.

[0006] In a first aspect, the application provides a storage circuit, which includes a first ferroelectric storage unit, a first current mirror, a first voltage generating circuit, a comparison circuit, and a first voltage terminal. The first current mirror includes a first branch and a second branch, one end of the first branch and one end of the second branch are electrically connected to the first voltage terminal, and the currents of the first branch and the second branch are the same. The output end of the first ferroelectric storage unit and the other end of the first branch are electrically connected to a first node, the other end of the second branch and the output end of the first voltage generating circuit and the input end of the comparison circuit are electrically connected to a second node, and the output end of the comparison circuit is electrically connected to the output end of the storage circuit.

[0007] In the reading stage, the first ferroelectric storage unit inputs a voltage to the first node (first bit line). If the voltage input by the first ferroelectric storage unit to the first node is a positive voltage, the first branch of the first current mirror can be used to extract charge from the first node, so that the voltage of the first node is kept at the initial voltage in the pre-charging stage (before the reading stage). If the voltage input by the first ferroelectric storage unit to the first node is a negative voltage, the first node can extract charge from the first branch of the first current mirror, so that the voltage of the first node is kept at the initial voltage in the pre-charging stage (before the reading stage).

[0008] The potential on the first node (first bit line) is kept at the initial voltage, on the one hand, the potential difference between the plate line and the first bit line located at both ends of the first ferroelectric storage unit is stabilized at a fixed value, which does not affect the polarization flipping of the ferroelectric capacitor; on the other hand, the potential difference between the plate line and the first bit line is always at a large value, so that the polarization flipping of the ferroelectric capacitor will not become slower and slower due to the reduction of the potential difference between the plate line and the first bit line, or even insufficient, thereby the self-inhibition phenomenon occurs, the uniformity and reliability of the storage circuit are improved, and the storage window of the ferroelectric circuit is also improved.

[0009] In order to satisfy the working principle of the first current mirror, the current of the first branch is equal to the current of the second branch, in the case that the first branch extracts the charge from the first node, since the first branch and the second branch are both electrically connected to the first voltage terminal, the second branch extracts the charge from the second node which is electrically connected to the second branch. In the case that the first node extracts the charge from the first branch, since the first branch and the second branch are both electrically connected to the first voltage terminal, the second node extracts the charge from the second branch which is electrically connected to the second node.

[0010] In the reading stage, when the ferroelectric capacitor in the first ferroelectric memory cell occurs polarization flip, the first ferroelectric memory cell outputs polarization current; when the ferroelectric capacitor does not occur polarization flip, the first ferroelectric memory cell outputs dielectric current. The amount of charge output when the ferroelectric capacitor occurs polarization flip is greater than the amount of charge output when the ferroelectric capacitor does not occur polarization flip, thus, if the first branch extracts the charge from the first node, the amount of charge extracted from the first node by the first branch when the ferroelectric capacitor occurs polarization flip is greater than the amount of charge extracted from the first node by the first branch when the ferroelectric capacitor does not occur polarization flip, and further, the amount of charge extracted from the second node by the second branch when the ferroelectric capacitor occurs polarization flip is greater than the amount of charge extracted from the second node by the second branch when the ferroelectric capacitor does not occur polarization flip. If the first node extracts the charge from the first branch, the amount of charge extracted from the first branch by the first node when the ferroelectric capacitor occurs polarization flip is greater than the amount of charge extracted from the first branch by the first node when the ferroelectric capacitor does not occur polarization flip, and further, the amount of charge extracted from the second branch by the second node when the ferroelectric capacitor occurs polarization flip is greater than the amount of charge extracted from the second branch by the second node when the ferroelectric capacitor does not occur polarization flip. That is, whether the ferroelectric capacitor occurs polarization flip or not, the voltage remaining in the second node is different.

[0011] In this way, the second node inputs the voltage remaining to the comparison circuit, and the comparison circuit can determine whether the data read out by the first ferroelectric memory cell is digital signal 0 or digital signal 1 according to the received voltage.

[0012] In some possible implementation manners, the first branch includes a first transistor, and the second branch includes a second transistor, and the first transistor is the same as the second transistor. The first electrode of the first transistor is electrically connected to the first node, the gate of the first transistor is electrically connected to the gate of the second transistor, the second electrode of the first transistor and the second electrode of the second transistor are both electrically connected to the first voltage terminal, and the first electrode of the second transistor is electrically connected to the second node. In the reading stage, the first voltage terminal is configured to input the first voltage to the second electrode of the first transistor and the second electrode of the second transistor.

[0013] The connection mode of the first transistor and the second transistor and the same structure parameters of the first transistor and the second transistor can realize the same function of the first current mirror input current and output current, so that when reading the digital signal 0 and the digital signal 1, the first branch sends the received current (polarization current or dielectric current) to the second branch, and according to the different currents, the second branch extracts different amounts of charges from the second node, or the second node extracts different amounts of charges from the second branch.

[0014] In some possible implementations, in the first current mirror, since the current input to the first branch is always the same as the current output by the second branch, in order to ensure that the first branch copies the same polarization current or dielectric current to the second branch when the first current mirror works, the initial current flowing through the first branch should be the same as the initial current flowing through the second branch before the polarization current or dielectric current flows to the first branch. However, the current of the first branch is easily affected by the first node, and the current of the second branch is easily affected by the second node, which may cause the initial current of the first branch to be different from the initial current flowing through the second branch.

[0015] Therefore, the storage chip further includes a third transistor and a fourth transistor, the third transistor is connected in series between the first node and the first transistor, and the fourth transistor is connected in series between the second node and the second transistor. In the reading stage, the third transistor is configured to input a clamping voltage to the first electrode of the first transistor, and the fourth transistor is configured to input a clamping voltage to the first electrode of the second transistor.

[0016] In the reading stage, the third transistor and the fourth transistor are both turned on, the second electrode of the third transistor inputs the clamping voltage to the first electrode of the first transistor, and the second electrode of the fourth transistor inputs the clamping voltage to the first electrode of the second transistor, so that the potential of the connection node of the third transistor and the first transistor is the same as the potential of the connection node of the fourth transistor and the second transistor, so as to realize the same initial current flowing through the first branch and the initial current flowing through the second branch in the case that the first transistor and the second transistor are the same (the resistance of the first transistor and the second transistor is the same).

[0017] In some possible implementations, the first voltage generating circuit includes a second voltage terminal and an electric storage capacitor, and the electric storage capacitor is electrically connected between the second node and the second voltage terminal. In the reading stage, the second voltage terminal is configured to input a second voltage to the second node through the electric storage capacitor.

[0018] If the first voltage generating circuit includes a second voltage terminal, in the reading stage, the second voltage terminal is used to input a second voltage to the second node. However, due to the existence of the parasitic capacitance, the voltage value received by the second node will not reach the voltage value output by the second voltage terminal. Therefore, the first voltage generating circuit can further include a storage capacitor. In this way, the first voltage generating circuit can first input the second voltage to the first electrode of the storage capacitor, and the first electrode of the storage capacitor couples the second voltage to the second electrode of the storage capacitor and the second node, so as to improve the problem that the voltage output by the second voltage terminal is largely taken away by the parasitic capacitance, resulting in that the voltage value received by the second node cannot reach the voltage value output by the second voltage terminal.

[0019] In some possible implementations, the first voltage generating circuit further includes an inverter, and the inverter is electrically connected between the second voltage terminal and the storage capacitor. Since there is usually a loss problem in the transmission of a signal, electrically connecting the inverter between the second voltage terminal and the storage capacitor can use the inverter to enhance the signal.

[0020] In some possible implementations, the storage circuit further includes a third voltage terminal and a pre-charge circuit, and the pre-charge circuit is electrically connected between the third voltage terminal and the first node.

[0021] The storage circuit further includes a plate line and a first bit line (i.e., the bit line in the claim), the first ferroelectric storage unit is electrically connected between the first bit line and the plate line, and the first bit line, the output terminal of the first ferroelectric storage unit, and one end of the first branch are electrically connected to the first node. In the pre-charge stage, the third voltage terminal is used to charge the initial voltage to the first bit line through the pre-charge circuit, to prepare for the reading stage. Further, in the reading stage, the potential difference between the plate line and the first bit line can be controlled by controlling the voltage on the plate line, so as to control the first ferroelectric storage unit to read data.

[0022] In some possible implementations, the pre-charge circuit includes a first switch and a second switch, the first switch is electrically connected between the input terminal of the first branch and the output terminal of the second branch, and the second switch is electrically connected between the third voltage terminal and the second node. In the pre-charge stage, the first switch and the second switch are both turned on, and the third voltage terminal inputs the initial voltage to the first bit line through the second switch and the first switch.

[0023] In some possible implementations, in addition to pre-charging the first bit line, the third voltage terminal can also pre-charge the second node through the second switch in the pre-charge stage. In this case, the second switch is turned on, and the third voltage terminal pre-charges the second node to a charging voltage through the second switch. At the same time, the first switch is turned off, so that the charging voltage of the third voltage terminal does not affect the potential on the first bit line.

[0024] In the pre-charge phase, the third voltage terminal inputs a charging voltage to the second node; in the read phase, the second voltage terminal inputs a second voltage to the second node. In this way, the voltage on the second node is the sum of the charging voltage and the second voltage before the second node is extracted by the second branch. Embodiments of the present application input the voltage to the second node multiple times to ensure that the voltage on the second node is large enough, thereby increasing the third voltage of the second node when reading the digital signal 1, and the difference between the third voltage of the second node when reading the digital signal 0, and increasing the MW of the storage circuit.

[0025] In addition, in the read phase, the first switch and the second switch are both open. In this way, the second node is isolated (the second node is isolated from the first node through the first switch, and the second node is isolated from the third voltage terminal through the second switch), so that the second node is not disturbed by the parasitic capacitance on the first bit line, and the parasitic capacitance on the second node is very small, which has little effect on the MW of the storage circuit.

[0026] In some possible implementations, in the read phase: the ferroelectric storage unit is configured to input charge to the first node. The first branch is configured to copy the first current of the first branch to the second branch, and keep the potential of the first node at the initial voltage according to the first voltage and the initial voltage. The second branch is configured to change the potential of the second node from the second voltage to the third voltage according to the first current, the first voltage and the second voltage. The comparison circuit is configured to receive the third voltage input by the second node, and determine whether the data read by the first ferroelectric storage unit is a digital signal 0 or 1 according to the third voltage.

[0027] Specifically, in some possible implementations, the first transistor and the second transistor are both N-type transistors, the initial voltage and the second voltage are both greater than the first voltage, and the initial voltage is a low voltage. The first branch is configured to extract charge from the first node according to the first voltage and the initial voltage, so that the potential of the first node is kept at the initial voltage. The second branch is configured to extract charge from the second node according to the first current, the first voltage and the second voltage, so that the potential of the second node is reduced from the second voltage to the third voltage. In the case that the first transistor and the second transistor are both N-type transistors, and the first voltage input by the first voltage terminal to the first transistor and the second transistor is less than the initial voltage, the charge of the first node can be moved to the first branch.

[0028] In the case that the initial voltage and the second voltage are both greater than the first voltage, and the initial voltage is a low level, when the first ferroelectric memory cell reads data, the first ferroelectric memory cell inputs charges to the first node, and because the initial voltage is greater than the first voltage, there is a potential difference between the first node and the first branch, and the first branch extracts charges from the first node. In this way, the first node receives the charges input by the first ferroelectric memory cell, and at the same time, the first node is also extracted by the first branch, so the first node remains at the initial voltage. That is, the charges input by the first ferroelectric memory cell to the first node are not accumulated in the first node.

[0029] Further, according to the working principle of the first current mirror, the first branch copies the first current flowing through the first branch to the second branch, and then the second branch changes the potential of the second node from the second voltage to the third voltage according to the first current, the first voltage input to the first current mirror, and the second voltage of the second node.

[0030] It should be understood that in the case that the current flowing through the first branch and the second branch is the first current, the first voltage terminal simultaneously inputs the first voltage to the first branch and the second branch, and the second voltage of the second node is greater than the first voltage, if the first branch extracts charges from the first node, the second branch will also extract charges from the second node, so that the potential of the second node decreases from the second voltage to the third voltage.

[0031] In the read stage, when the ferroelectric capacitor in the first ferroelectric memory cell undergoes polarization reversal, the first ferroelectric memory cell outputs a polarization current; when the ferroelectric capacitor does not undergo polarization reversal, the first ferroelectric memory cell outputs a dielectric current. The amount of charge input to the first node when the ferroelectric capacitor undergoes polarization reversal is greater than the amount of charge input to the first node when the ferroelectric capacitor does not undergo polarization reversal, so the amount of charge extracted by the first branch from the first node when the ferroelectric capacitor undergoes polarization reversal is greater than the amount of charge extracted by the first branch from the first node when the ferroelectric capacitor does not undergo polarization reversal.

[0032] It is known that the amount of charge extracted by the first branch from the first node when the ferroelectric capacitor undergoes polarization reversal is greater than the amount of charge extracted by the first branch from the first node when the ferroelectric capacitor does not undergo polarization reversal, so the amount of charge extracted by the second branch from the second node when the ferroelectric capacitor undergoes polarization reversal is also greater than the amount of charge extracted by the second branch from the second node when the ferroelectric capacitor does not undergo polarization reversal. That is, whether the ferroelectric capacitor undergoes polarization reversal or not, the third voltage remaining after the second node is extracted by the charge is not the same.

[0033] In this way, the second node inputs the remaining third voltage to the comparison circuit, and the comparison circuit can determine whether the data read by the first ferroelectric memory cell is a digital signal 0 or a digital signal 1 according to the third voltage.

[0034] In the present application, due to whether the ferroelectric capacitor occurs polarization reversal, the data (digital signal 1 or digital signal 0) read by the first ferroelectric memory cell is different, the amount of charge input to the first node is different, the first current flowing through the first branch and the second branch is also different, the amount of charge extracted from the first node by the first branch is different, and the potential difference between the second node and the second branch is different. Therefore, when the first ferroelectric memory cell reads different data, the second branch can extract charge from the second node according to the first current, the first voltage, and the second voltage, so that the potential of the second node decreases from the second voltage to the third voltage. It can be seen that the residual potential on the second node, the third voltage, is related to the data (digital signal 1 or digital signal 0) read by the first ferroelectric memory cell. Therefore, the third voltage can be input to the comparison circuit by using the second node, so that the comparison circuit determines whether the data read by the first ferroelectric memory cell is digital signal 0 or digital signal 1 according to the third voltage.

[0035] At the same time, whether reading digital signal 1 or digital signal 0, the charge on the first bit line (the first node) electrically connected to the first ferroelectric memory cell is extracted by the first branch, so that the potential on the first bit line is kept at the initial voltage. On the one hand, the potential difference between the plate line and the first bit line is stabilized at a fixed value, which does not affect the polarization reversal of the ferroelectric capacitor. On the other hand, the potential difference between the plate line and the first bit line is always at a large value, so that the polarization reversal of the ferroelectric capacitor does not become slower and slower or even insufficient due to the decrease of the potential difference between the plate line and the first bit line, thereby improving the uniformity and reliability of the storage circuit and the storage window of the ferroelectric circuit.

[0036] Further, in some possible implementation manners, if the first ferroelectric memory cell reads digital signal 1 and the ferroelectric capacitor in the first ferroelectric memory cell occurs polarization reversal, then when the first ferroelectric memory cell reads digital signal 1, the first ferroelectric memory cell will output a polarization current, the polarization current flows to the first branch through the first node, the first branch copies a polarization current of the same size to the second branch, and the second branch extracts a first amount of charge from the second node under the influence of the polarization current, the first voltage, and the second voltage. The potential of the second node will decrease significantly. When the first ferroelectric memory cell reads digital signal 0, the first ferroelectric memory cell will output a small amount of dielectric current, the dielectric current flows to the first branch through the first node, the first branch copies a dielectric current of the same size to the second branch, and the second branch extracts a second amount of charge from the second node under the influence of the dielectric current, the first voltage, and the second voltage. The potential of the second node will decrease slightly. Wherein, the first amount of charge is greater than the second amount of charge.

[0037] In this case, the third voltage when the first ferroelectric memory cell reads digital signal 1 is less than the third voltage when the first ferroelectric memory cell reads digital signal 0.

[0038] If the first ferroelectric memory cell reads a digital signal 0, the ferroelectric capacitor in the first ferroelectric memory cell undergoes a polarization flip, and the first ferroelectric memory cell outputs a polarization current when reading a digital signal 0. The polarization current flows to the first branch through the first node, and the first branch copies a polarization current of the same size to the second branch. Influenced by the polarization current, the first voltage and the second voltage, the second branch extracts a first charge amount from the second node, and the potential of the second node is greatly reduced. When the first ferroelectric memory cell reads a digital signal 1, the first ferroelectric memory cell outputs a small amount of dielectric current, and the dielectric current flows to the first branch through the first node. The first branch copies a dielectric current of the same size to the second branch. Influenced by the dielectric current, the first voltage and the second voltage, the second branch extracts a second charge amount from the second node, and the potential of the second node is slightly reduced. The first charge amount is greater than the second charge amount.

[0039] In this case, the third voltage when the first ferroelectric memory cell reads a digital signal 1 is greater than the third voltage when the first ferroelectric memory cell reads a digital signal 0.

[0040] In some possible implementation manners, the first transistor and the second transistor are P-type transistors, the initial voltage and the second voltage are both less than the first voltage, and the initial voltage is a high level. The first node is configured to extract a charge from the first branch according to the first voltage and the initial voltage, so that the potential of the first node is maintained at the initial voltage. The second node is configured to extract a charge from the second branch according to the first current, the first voltage and the second voltage, so that the potential of the second node is increased from the second voltage to the third voltage. When the first voltage input to the first transistor and the second transistor by the first voltage terminal is greater than the initial voltage, the first transistor and the second transistor are P-type transistors, and the charge of the first branch can be moved to the first node.

[0041] In the case where the initial voltage and the second voltage are both less than the first voltage, and the initial voltage is a high level, when the first ferroelectric memory cell reads data, the first ferroelectric memory cell inputs a charge to the first node. Since the initial voltage is less than the first voltage, there is a potential difference between the first node and the first branch, and the first node extracts a charge from the first branch. In this way, the first node receives the charge input by the first ferroelectric memory cell while extracting a charge from the first branch, and therefore the first node is maintained at the initial voltage. That is, the charge input by the first ferroelectric memory cell to the first node is not accumulated in the first node.

[0042] Further, according to the working principle of the first current mirror, the first branch copies the first current flowing through the first branch to the second branch, and then the second branch changes the potential of the second node from the second voltage to the third voltage according to the first current, the first voltage input to the first current mirror, and the second voltage of the second node.

[0043] It should be understood that the current flowing through the first branch and the second branch is the first current, the first voltage terminal simultaneously inputs the first voltage to the first branch and the second branch, and the second voltage of the second node is less than the first voltage. If the first node extracts charges from the first branch, the second node will also extract charges from the second branch, so that the potential of the second node increases from the second voltage to the third voltage.

[0044] In the read stage, when the ferroelectric capacitor in the first ferroelectric memory cell occurs polarization flip, the first ferroelectric memory cell outputs polarization current, and when the ferroelectric capacitor does not occur polarization flip, the first ferroelectric memory cell outputs dielectric current. The amount of charge input to the first node when the ferroelectric capacitor occurs polarization flip is greater than the amount of charge input to the first node when the ferroelectric capacitor does not occur polarization flip. Therefore, the amount of charge extracted from the first branch by the first node when the ferroelectric capacitor occurs polarization flip is greater than the amount of charge extracted from the first branch by the first node when the ferroelectric capacitor does not occur polarization flip.

[0045] It is known that the amount of charge extracted from the first branch by the first node when the ferroelectric capacitor occurs polarization flip is greater than the amount of charge extracted from the first branch by the first node when the ferroelectric capacitor does not occur polarization flip. Therefore, the amount of charge extracted from the second branch by the second node when the ferroelectric capacitor occurs polarization flip is also greater than the amount of charge extracted from the second branch by the second node when the ferroelectric capacitor does not occur polarization flip. That is, whether the ferroelectric capacitor occurs polarization flip or not, the third voltage after the second node extracts charges is not the same.

[0046] In this way, the second node inputs the third voltage to the comparison circuit, and the comparison circuit can determine whether the data read out by the first ferroelectric memory cell is digital signal 0 or digital signal 1 according to the third voltage.

[0047] In the present application, the data (digital signal 1 or digital signal 0) read by the first ferroelectric memory cell is different due to whether the polarization of the ferroelectric capacitor flips or not, the amount of charge input to the first node is different, the first current flowing through the first branch and the second branch is also different, the amount of charge extracted from the first branch by the first node is different, and the potential difference between the second node and the second branch is different. Therefore, when the first ferroelectric memory cell reads different data, the second node can extract charge from the second branch according to the first current, the first voltage, and the second voltage, so that the potential of the second node increases from the second voltage to the third voltage. It can be seen that the third voltage on the second node is related to the data (digital signal 1 or digital signal 0) read by the first ferroelectric memory cell, and therefore the third voltage can be input to the comparison circuit by using the second node, so that the comparison circuit determines whether the data read by the first ferroelectric memory cell is digital signal 0 or digital signal 1 according to the third voltage.

[0048] At the same time, whether reading digital signal 1 or digital signal 0, the first bit line (the first node) electrically connected to the first ferroelectric memory cell extracts charge from the first branch, so that the potential on the first bit line remains at the initial voltage. On the one hand, the potential difference between the plate line and the first bit line is stabilized at a fixed value, which does not affect the polarization flip of the ferroelectric capacitor. On the other hand, the potential difference between the plate line and the first bit line is always at a large value, so that the polarization flip of the ferroelectric capacitor does not become slower and slower due to the decrease of the potential difference between the plate line and the first bit line, and even does not become insufficient, thereby improving the uniformity and reliability of the storage circuit, and also improving the storage window of the ferroelectric circuit.

[0049] Further, in some possible implementation manners, if the polarization of the ferroelectric capacitor in the first ferroelectric memory cell flips when the first ferroelectric memory cell reads digital signal 1, then when the first ferroelectric memory cell reads digital signal 1, the first ferroelectric memory cell will output a polarization current, the polarization current flows to the first branch through the first node, the first branch copies a polarization current of the same size to the second branch, and the second node will extract a first amount of charge from the second branch under the influence of the polarization current, the first voltage, and the second voltage, and the potential of the second node will increase greatly. When the first ferroelectric memory cell reads digital signal 0, the first ferroelectric memory cell will output a small amount of dielectric current, the dielectric current flows to the first branch through the first node, the first branch copies a dielectric current of the same size to the second branch, and the second node will extract a second amount of charge from the second branch under the influence of the dielectric current, the first voltage, and the second voltage, and the potential of the second node will increase slightly. Wherein, the first amount of charge is greater than the second amount of charge.

[0050] In this case, the third voltage when the first ferroelectric memory cell reads digital signal 1 is greater than the third voltage when the first ferroelectric memory cell reads digital signal 0.

[0051] If the first ferroelectric memory cell reads a digital signal 0, the ferroelectric capacitor in the first ferroelectric memory cell undergoes a polarization flip, then when the first ferroelectric memory cell reads a digital signal 0, the first ferroelectric memory cell will output a polarization current, the polarization current flows through the first node to the first branch, the first branch copies a polarization current of the same size to the second branch, under the influence of the polarization current, the first voltage and the second voltage, the second node will extract a first charge amount from the second branch, and the potential of the second node will be greatly increased. When the first ferroelectric memory cell reads a digital signal 1, the first ferroelectric memory cell will output a small amount of dielectric current, the dielectric current flows through the first node to the first branch, the first branch copies a dielectric current of the same size to the second branch, under the influence of the dielectric current, the first voltage and the second voltage, the second node will extract a second charge amount from the second branch, and the potential of the second node will be slightly increased. Wherein, the first charge amount is greater than the second charge amount.

[0052] In this case, the third voltage when the first ferroelectric memory cell reads a digital signal 1 is less than the third voltage when the first ferroelectric memory cell reads a digital signal 0.

[0053] In some possible implementations, the storage circuit further includes a reference voltage terminal. In the reading stage: the reference voltage terminal is configured to input a reference voltage to the comparison circuit, the reference voltage has a voltage value between the third voltage when the first ferroelectric memory cell reads a digital signal 0 and the third voltage when the first ferroelectric memory cell reads a digital signal 1; and the comparison circuit is configured to determine whether the data read by the first ferroelectric memory cell is a digital signal 0 or a digital signal 1 according to the third voltage and the reference voltage. Details of how the comparison circuit determines whether the data read by the first ferroelectric memory cell is a digital signal 0 or a digital signal 1 according to the reference voltage and the third voltage will be described below in combination with the circuit connection relationship of the comparison circuit.

[0054] The comparison circuit includes a fourth voltage terminal, a first P-type transistor, a second P-type transistor, a first N-type transistor, a second N-type transistor, and a ground terminal; and the storage circuit further includes an output terminal. In the reading stage, the fourth voltage terminal is at a high level, and the ground terminal is at a low level.

[0055] The gate of the first P-type transistor and the gate of the first N-type transistor are electrically connected to the second electrode of the second P-type transistor, the first electrode of the second N-type transistor, and the reference voltage terminal; the first electrode of the first P-type transistor is electrically connected to the fourth voltage terminal; the second electrode of the first P-type transistor is electrically connected to the first electrode of the first N-type transistor and the output terminal; and the second electrode of the first N-type transistor is electrically connected to the ground terminal. The gate of the second P-type transistor and the gate of the second N-type transistor are electrically connected to the second node; the first electrode of the second P-type transistor is electrically connected to the fourth voltage terminal; and the second electrode of the second N-type transistor is electrically connected to the ground terminal.

[0056] For example, assume that the first ferroelectric memory cell is set to flip the polarization of the ferroelectric capacitor when reading a digital signal of 1. In this case, the third voltage when reading a digital signal of 1 is less than the third voltage when reading a digital signal of 0.

[0057] When reading a digital signal of 1, the third voltage at the second node is low, and the second P-type transistor is turned on. The reference voltage at the reference voltage terminal is greater than the third voltage when the first ferroelectric memory cell reads a digital signal of 1, and less than the third voltage when the first ferroelectric memory cell reads a digital signal of 0. Thus, even though the reference voltage terminal is electrically connected to the gate of the first P-type transistor and the gate of the first N-type transistor, the first P-type transistor and the first N-type transistor are less likely to be turned on than the second P-type transistor. The second P-type transistor can be charged more quickly, and the high voltage at the fourth voltage terminal is transmitted to the gate of the first N-type transistor and the reference voltage terminal, and the reference voltage terminal is pulled high. Further, the first N-type transistor is turned on, and the ground terminal transmits a low voltage to the output terminal through the first N-type transistor, and the output terminal outputs a low voltage, confirming that the data read by the first ferroelectric memory cell is a digital signal of 1.

[0058] When reading a digital signal of 0, the third voltage at the second node B is high, and the second N-type transistor is turned on. The reference voltage at the reference voltage terminal is greater than the third voltage when the first ferroelectric memory cell reads a digital signal of 1, and less than the third voltage when the first ferroelectric memory cell reads a digital signal of 0. Thus, even though the reference voltage terminal is electrically connected to the gate of the first P-type transistor and the gate of the first N-type transistor, the first P-type transistor and the first N-type transistor are less likely to be turned on than the second N-type transistor. The second N-type transistor can be charged more quickly, and the low voltage at the ground terminal is transmitted to the gate of the first P-type transistor and the reference voltage terminal, and the reference voltage terminal is pulled low. Further, the first P-type transistor is turned on, and the fourth voltage terminal transmits a high voltage to the output terminal through the first P-type transistor, and the output terminal outputs a high voltage, confirming that the data read by the first ferroelectric memory cell is a digital signal of 0.

[0059] For example, assume that the first ferroelectric memory cell is set to flip the polarization of the ferroelectric capacitor when reading a digital signal of 0. In this case, the third voltage when reading a digital signal of 0 is less than the third voltage when reading a digital signal of 1.

[0060] When reading digital signal 0, the third voltage of the second node is low, and the second P-type transistor is turned on. The reference voltage of the reference voltage terminal is greater than the third voltage when the first ferroelectric storage unit reads digital signal 0, and is less than the third voltage when the first ferroelectric storage unit reads digital signal 1. Therefore, even if the reference voltage terminal is electrically connected to the gate of the first P-type transistor and the gate of the first N-type transistor, the turn-on degree of the first P-type transistor and the first N-type transistor is less than the turn-on degree of the second P-type transistor, the second P-type transistor can be charged more quickly, and the high level of the fourth voltage terminal is transmitted to the gate of the first N-type transistor and the reference voltage terminal, and the reference voltage terminal is pulled high. Further, the first N-type transistor is turned on, the ground terminal transmits the low level to the output terminal through the first N-type transistor, the output terminal outputs the low level, and it is confirmed that the data read by the first ferroelectric storage unit is digital signal 0.

[0061] When reading digital signal 1, the third voltage of the second node is high, and the second N-type transistor is turned on. The reference voltage of the reference voltage terminal Vref is greater than the third voltage when the first ferroelectric storage unit reads digital signal 0, and is less than the third voltage when the first ferroelectric storage unit reads digital signal 1. Therefore, even if the reference voltage terminal is electrically connected to the gate of the first P-type transistor and the gate of the first N-type transistor, the turn-on degree of the first P-type transistor and the first N-type transistor is less than the turn-on degree of the second N-type transistor, the second N-type transistor can be charged more quickly, and the low level of the ground terminal is transmitted to the gate of the first P-type transistor and the reference voltage terminal, and the reference voltage terminal is pulled low. Further, the first P-type transistor is turned on, the fourth voltage terminal transmits the high level to the output terminal through the first P-type transistor, the output terminal outputs the high level, and it is confirmed that the data read by the first ferroelectric storage unit is digital signal 1.

[0062] In some possible implementation manners, the storage circuit further includes a reference voltage generation circuit, the reference voltage generation circuit including a second ferroelectric storage unit, a third ferroelectric storage unit, a second current mirror, a second voltage generation circuit, and a third node; the circuit structure of the second ferroelectric storage unit and the third ferroelectric storage unit is the same as that of the first ferroelectric storage unit; and the second current mirror includes a third branch and a fourth branch.

[0063] In the reading stage: the second voltage generating circuit is configured to input a fourth voltage to the third node, the fourth voltage being the same as the second voltage. The second ferroelectric storage unit is configured to input a second current to the third branch, the second current representing the second ferroelectric storage unit reading a digital signal 1. The third ferroelectric storage unit is configured to input a third current to the fourth branch, the third current representing the third ferroelectric storage unit reading a digital signal 0. The third branch is configured to receive the second current and the third current and copy an average of the second current and the third current to the fourth branch. The third node is configured to transmit charges to the fourth branch according to the average of the second current and the third current, so that the potential of the third node decreases from the second voltage to a fifth voltage, and the fifth voltage is input to the reference voltage terminal; wherein the fifth voltage is half of the fourth voltage.

[0064] Since the circuit structures of the second ferroelectric storage unit and the third ferroelectric storage unit are the same as that of the first ferroelectric storage unit, the fourth voltage on the third node is the same as the second voltage on the second node, and the current of the fourth branch is the average of the second current when the second ferroelectric storage unit reads the digital signal 1 and the third current when the third ferroelectric storage unit reads the digital signal 0, the fourth branch extracts an average charge amount between the digital signal 0 and the digital signal 1 from the third node, and the fifth voltage remaining on the third node is also between the third voltage when the first ferroelectric storage unit reads the digital signal 1 and the third voltage when the first ferroelectric storage unit reads the digital signal 0, so that the fifth voltage can be used as the reference voltage to determine whether the third voltage input to the comparison circuit by the second node corresponds to the digital signal 0 or the digital signal 1.

[0065] In addition, since the circuit structures of the second ferroelectric storage unit and the third ferroelectric storage unit are the same as that of the first ferroelectric storage unit, when the performance of the first ferroelectric storage unit changes due to external changes (such as temperature, voltage, etc.), the performance of the second ferroelectric storage unit and the third ferroelectric storage unit also changes accordingly, so that the reference voltage generating circuit can also be used to realize automatic adjustment in different environments.

[0066] In addition, in order to realize that when the performance of the first ferroelectric storage unit changes due to external changes (such as temperature, voltage, etc.), the performance of the second ferroelectric storage unit and the third ferroelectric storage unit also changes accordingly, the circuit structure of the second voltage generating circuit can be the same as that of the first voltage generating circuit, the second ferroelectric storage unit is also electrically connected to the second bit line, the third ferroelectric storage unit is also electrically connected to the third bit line, and the parasitic capacitance on the second bit line and the parasitic capacitance on the third bit line are the same as the parasitic capacitance on the first bit line.

[0067] In some possible implementation manners, the third branch includes a fifth transistor and a sixth transistor, and the fourth branch includes a seventh transistor; channel widths of the fifth transistor, the sixth transistor and the seventh transistor are the same; a gate of the fifth transistor, a gate of the sixth transistor, a first electrode of the fifth transistor, a first electrode of the sixth transistor and a gate of the seventh transistor are electrically connected to the output terminals of the second ferroelectric storage unit and the third ferroelectric storage unit; a second electrode of the fifth transistor, a second electrode of the sixth transistor and a second electrode of the seventh transistor are electrically connected to the fifth voltage terminal, and a first electrode of the seventh transistor is electrically connected to the third node.

[0068] According to the current formula of the transistor, in the third branch, the fifth transistor and the sixth transistor are connected in parallel, and the channel width of the fifth transistor is the same as that of the sixth transistor, so that the total current flowing through the third branch is the sum of the second current flowing through the fifth transistor and the third current flowing through the sixth transistor. Further, because the channel widths of the fifth transistor, the sixth transistor and the seventh transistor are the same, the ratio of the total channel width of the third branch to the channel width of the fourth branch is 2:1, and the third branch can copy the average of the second current and the third current to the fourth branch.

[0069] Alternatively, the third branch includes a fifth transistor, and the fourth branch includes a sixth transistor, a channel width of the fifth transistor is twice that of the sixth transistor; a gate of the fifth transistor, a gate of the sixth transistor and a first electrode of the fifth transistor are electrically connected to the output terminals of the second ferroelectric storage unit and the third ferroelectric storage unit; a second electrode of the fifth transistor and a second electrode of the sixth transistor are electrically connected to the fifth voltage terminal; and a first electrode of the sixth transistor is electrically connected to the third node.

[0070] According to the current formula of the transistor, the channel width of the fifth transistor is twice that of the sixth transistor, so that the current flowing through the sixth transistor is twice the current flowing through the fifth transistor. The current on the third branch composed of the fifth transistor is the sum of the second current and the third current, so that the third branch can copy the average of the second current and the third current to the fourth branch.

[0071] In some possible implementation manners, the storage circuit further includes a third switch electrically connected between the reference voltage terminal and the first node. In the reading stage, the third switch is turned off to prevent the signal of the reference voltage terminal from being input to the first node through the third switch. In the anti-writing stage, the third switch is turned on to input the writing signal of the reference voltage terminal to the first ferroelectric storage unit through the first node.

[0072] In a second aspect, the present application provides a control method of a storage circuit. The storage unit comprises a first ferroelectric storage unit, a first current mirror, a first voltage generating circuit, a comparison circuit, and a first voltage terminal. The first ferroelectric storage unit and a first branch of the first current mirror are electrically connected to a first node. A second branch of the first current mirror, the first voltage generating circuit, and the comparison circuit are electrically connected to a second node.

[0073] The control method of the storage circuit comprises: in a pre-charging phase, pre-charging the first node so that the potential of the first node is an initial voltage. In a reading phase: inputting a first voltage to the first current mirror through the first voltage terminal. Inputting charges to the first node by the first ferroelectric storage unit. Inputting a second voltage to the second node by the first voltage generating circuit; the initial voltage and the second voltage are both greater than the first voltage, and the initial voltage is a low level; or, the initial voltage and the second voltage are both less than the first voltage, and the initial voltage is a high level. According to the first voltage and the initial voltage, the first branch keeps the potential of the first node at the initial voltage and copies the first current of the first branch to the second branch. According to the first current, the first voltage, and the second voltage, the second branch changes the potential of the second node from the second voltage to a third voltage. The comparison circuit receives the third voltage and determines whether the data read by the first ferroelectric storage unit is digital signal 0 or 1 according to the third voltage.

[0074] In some possible implementation manners, the first transistor and the second transistor are both N-type transistors, and the initial voltage and the second voltage are both greater than the first voltage. According to the first voltage and the initial voltage, the first branch extracts charges from the first node so that the potential of the first node is kept at the initial voltage. According to the first current, the first voltage, and the second voltage, the second branch extracts charges from the second node so that the potential of the second node is reduced from the second voltage to the third voltage.

[0075] In some possible implementation manners, if the ferroelectric capacitor in the first ferroelectric storage unit is polarized to flip when the first ferroelectric storage unit reads digital signal 1, the third voltage when the first ferroelectric storage unit reads digital signal 1 is less than the third voltage when the first ferroelectric storage unit reads digital signal 0. If the ferroelectric capacitor in the first ferroelectric storage unit is polarized to flip when the first ferroelectric storage unit reads digital signal 0, the third voltage when the first ferroelectric storage unit reads digital signal 1 is greater than the third voltage when the first ferroelectric storage unit reads digital signal 0.

[0076] In some possible implementation manners, the first transistor and the second transistor are both N-type transistors, and the initial voltage and the second voltage are both less than the first voltage. The first node is used to draw charges from the first branch according to the first voltage and the initial voltage, so that the potential of the first node is kept at the initial voltage. The second node is used to draw charges from the second branch according to the first current, the first voltage and the second voltage, so that the potential of the second node is increased from the second voltage to the third voltage.

[0077] In some possible implementation manners, if the ferroelectric capacitor in the first ferroelectric memory cell is polarized to flip when the first ferroelectric memory cell reads a digital signal 1, the third voltage when the first ferroelectric memory cell reads the digital signal 1 is greater than the third voltage when the first ferroelectric memory cell reads a digital signal 0. If the ferroelectric capacitor in the first ferroelectric memory cell is polarized to flip when the first ferroelectric memory cell reads a digital signal 0, the third voltage when the first ferroelectric memory cell reads the digital signal 0 is greater than the third voltage when the first ferroelectric memory cell reads the digital signal 1.

[0078] In some possible implementation manners, after the first node is precharged in the precharge phase, the control method of the storage circuit further includes: precharging the second node in the precharge phase.

[0079] In some possible implementation manners, the storage circuit further includes a reference voltage terminal. In the read phase, a reference voltage is input to the comparison circuit through the reference voltage terminal, and the voltage value of the reference voltage is between the third voltage when the first ferroelectric memory cell reads a digital signal 0 and the third voltage when the first ferroelectric memory cell reads a digital signal 1. The comparison circuit is used to determine whether the data read out by the first ferroelectric memory cell is a digital signal 0 or a digital signal 1 according to the third voltage and the reference voltage.

[0080] In some possible implementation manners, the storage circuit further includes a third switch electrically connected between the reference voltage terminal and the first node. In the read phase, the third switch is turned off. In the write-back phase, the third switch is turned on, and the write signal of the reference voltage terminal is input to the first ferroelectric memory cell through the first node by the third switch.

[0081] The second aspect and any one of the implementation manners of the second aspect correspond to the first aspect and any one of the implementation manners of the first aspect respectively. For details, refer to the technical effects of the first aspect and any one of the implementation manners of the first aspect, which are not described herein again.

[0082] In a third aspect, the present application provides a storage circuit, which comprises a ferroelectric storage unit, a clamping circuit, a voltage generating circuit and a comparison circuit. An output terminal of the ferroelectric storage unit is electrically connected to a first node at one end of the clamping circuit; the other end of the clamping circuit, the voltage generating circuit and an input terminal of the comparison circuit are electrically connected to a second node, and an output terminal of the comparison circuit is electrically connected to an output terminal of the storage circuit.

[0083] In the present application, when reading data, the ferroelectric storage unit inputs a voltage to the first node, and since the voltage at the first node is higher than that at the second node, the ferroelectric storage unit inputs the second voltage to the second node through the first node. Whether the ferroelectric capacitor occurs polarization reversal or not, the data (digital signal 1 or digital signal 0) read by the ferroelectric storage unit is different, and the voltage input by the ferroelectric storage unit to the second node is different. Therefore, after receiving the voltage input by the second node, the comparison circuit can determine whether the data read by the ferroelectric storage unit is digital signal 1 or digital signal 0 according to the received voltage.

[0084] Meanwhile, whether reading digital signal 1 or digital signal 0, the voltage on the bit line (first node) is clamped to the initial voltage 0V by the clamping circuit, on the one hand, the potential difference between the plate line and the bit line is stabilized at a fixed value, which does not affect the polarization reversal of the ferroelectric capacitor; on the other hand, the potential difference between the plate line and the bit line is always at a large value, so that the polarization reversal of the ferroelectric capacitor will not become slower and slower, or even insufficient, thus the self-inhibition phenomenon occurs, which improves the uniformity and reliability of the storage circuit, and also improves the storage window of the ferroelectric circuit.

[0085] In addition, as mentioned above, in the prior art, the comparison circuit reads digital signal 1 or digital signal 0 by obtaining the charge on the bit line, and the bit line is usually connected with multiple ferroelectric storage units, and its length is relatively long. In the storage chip, the bit line inevitably forms a parasitic capacitor with multiple conductive structures, and the parasitic capacitor has a negative impact on the MW of the storage circuit.

[0086] However, in the present application, the voltage on the bit line (first node) is clamped to the initial voltage by the clamping circuit, and the parasitic capacitor cannot be transmitted to the second node through the bit line, and the comparison circuit of the present application confirms the data as digital signal 0 or digital signal 1 according to the voltage transmitted by the second node, so the parasitic capacitor will not have a negative impact on the MW of the storage circuit.

[0087] In some possible implementation manners, the voltage generation circuit comprises a first voltage terminal, and a storage capacitor electrically connected between the second node and the first voltage terminal. In the pre-charge phase, the first voltage terminal is configured to input the first voltage to the second node through the storage capacitor. In the read phase, the ferroelectric storage unit is configured to input the second voltage to the second node through the first node and the clamping circuit. In the read phase, the first voltage terminal is configured to input a third voltage to the second node through the storage capacitor.

[0088] If the voltage generation circuit comprises the first voltage terminal, in the read phase, the first voltage terminal is configured to input the third voltage to the second node. However, due to the parasitic capacitor, the voltage value received by the second node cannot reach the voltage value output by the first voltage terminal. Therefore, the voltage generation circuit can further comprise the storage capacitor electrically connected between the second node and the first voltage terminal, wherein the first voltage terminal is electrically connected to a first electrode of the storage capacitor, and the second node is electrically connected to a second electrode of the storage capacitor. In this way, the voltage generation circuit can first input the third voltage to the first electrode, and the first electrode couples the third voltage to the second electrode and the second node, so as to improve the problem that the voltage output by the first voltage terminal is largely taken away by the parasitic capacitor, resulting in that the voltage value received by the second node cannot reach the voltage value output by the first voltage terminal.

[0089] In some possible implementation manners, during the transmission of the signal, there is usually a loss problem. Therefore, the voltage generation circuit further comprises an inverter electrically connected between the first voltage terminal and the storage capacitor, so as to enhance the signal.

[0090] In some possible implementation manners, the clamping circuit comprises a first transistor and a second transistor, the first transistor is an N-type transistor, and the second transistor is a P-type transistor. The first transistor is electrically connected between the first node and the second transistor. When the ferroelectric storage unit inputs the second voltage to the second node through the first node and the clamping circuit, the first transistor and the second transistor are turned on. Since the second transistor is a P-type transistor, the node connected between the second transistor and the first transistor can be clamped. The potential of the node connected between the second transistor and the first transistor is the same as the potential of the first node, and the second transistor is configured to clamp the potential of the first node to 0 V through the first transistor.

[0091] When the voltage generation circuit inputs the third voltage to the second node, the first transistor is turned off, so as to prevent the potential of the second node from being raised and affecting the potential of the first node through the second transistor and the first transistor, thereby causing the potential of the first node to increase.

[0092] In some possible implementations, the storage circuit further includes a third transistor and a second voltage terminal. In the pre-charge phase, the second voltage terminal is configured to pre-charge the first node to 0 V through the third transistor, to prepare for the read phase. In the read phase, the first voltage is less than 0 V, the second voltage is greater than 0 V, and the voltage of the first node is greater than the sum of the first voltage and the second voltage.

[0093] In some possible implementations, the third transistor is electrically connected between the second node and the second voltage terminal, and the second voltage terminal is configured to pre-charge the first node to 0 V through the third transistor, the second node, the second transistor and the first transistor. Alternatively, the third transistor is electrically connected between the third node and the second voltage terminal, and the third node is a connection node of the first transistor and the second transistor, and the second voltage terminal is configured to pre-charge the first node to 0 V through the third transistor, the third node and the first transistor.

[0094] In some possible implementations, in the read phase, the second node is configured to input a fourth voltage to the comparison circuit, and the fourth voltage is the sum of the first voltage, the second voltage and the third voltage. The comparison circuit is configured to receive the fourth voltage input by the second node, and determine, according to the fourth voltage, whether the data read by the ferroelectric storage unit is a digital signal 0 or a digital signal 1, wherein the fourth voltage is within the working voltage range of the comparison voltage.

[0095] In the present application, when reading data, the second voltage of the ferroelectric storage unit is first input to the first node. Since the potential of the first node is higher than that of the second node, the ferroelectric storage unit inputs the second voltage to the second node through the first node. Whether the ferroelectric capacitor is polarized or not, the data (digital signal 1 or digital signal 0) read by the ferroelectric storage unit is different, and the second voltage input to the second node by the ferroelectric storage unit is different. In addition to the second voltage, the first voltage when the ferroelectric storage unit reads the digital signal 1 is the same as the first voltage when the ferroelectric storage unit reads the digital signal 0, and the third voltage when the ferroelectric storage unit reads the digital signal 1 is the same as the third voltage when the ferroelectric storage unit reads the digital signal 0. Therefore, after the comparison circuit receives the fourth voltage input by the second node, the comparison circuit can determine, according to the fourth voltage, whether the data read by the ferroelectric storage unit is a digital signal 1 or a digital signal 0.

[0096] Meanwhile, whether reading a digital signal 1 or a digital signal 0, the voltage on the bit line (first node) is clamped by the clamping circuit to the initial voltage. On the one hand, the potential difference between the plate line and the bit line is stabilized at a fixed value, which does not affect the polarization of the ferroelectric capacitor. On the other hand, the potential difference between the plate line and the bit line is always at a large value, so that the polarization of the ferroelectric capacitor does not become slower and slower, or even insufficient, thereby improving the uniformity and reliability of the storage circuit, and also improving the storage window of the ferroelectric circuit.

[0097] And, as mentioned above, the prior art comparison circuit reads digital signal 1 or digital signal 0 by obtaining the charge on the bit line, and the bit line is usually connected with a plurality of ferroelectric storage units, and the length is relatively long, and in the storage chip, the bit line inevitably forms a parasitic capacitance with a plurality of conductive structures, which has a negative impact on the MW of the storage circuit.

[0098] And the voltage on the bit line (first node) of the present application is clamped by the clamping circuit to the initial voltage, and the parasitic capacitance cannot be transmitted to the second node through the bit line, and the comparison circuit of the present application confirms the data as digital signal 0 or digital signal 1 according to the fourth voltage transmitted by the second node, so the parasitic capacitance will not have a negative impact on the MW of the storage circuit.

[0099] In some possible implementations, the third voltage is the absolute value of the first voltage, and the fourth voltage is equal to the second voltage. For example, first use the voltage generating circuit to pull down the second node by 5V (the first voltage is -5V), and then use the voltage generating circuit to pull up the second node by 5V (the third voltage is 5V) after receiving the second voltage at the second node. The fourth voltage obtained is the second voltage input to the second node by the ferroelectric storage unit.

[0100] In some possible implementations, the storage circuit further includes a third voltage terminal and a fourth transistor, and the fourth transistor is an N-type transistor. The gate of the fourth transistor is electrically connected with the second node, the first pole of the fourth transistor is electrically connected with the third voltage terminal, and the second pole of the fourth transistor is electrically connected with the input terminal of the comparison circuit.

[0101] As mentioned above, the fourth voltage is positive no matter whether digital signal 1 or digital signal 0 is read, but the fourth voltage when reading digital signal 1 is different from the fourth voltage when reading digital signal 0.

[0102] Suppose that the first ferroelectric storage unit is polarized and flipped when reading digital signal 1, and the first ferroelectric storage unit does not polarize and flip when reading digital signal 0, then the fourth voltage when reading digital signal 1 is greater than the fourth voltage when reading digital signal 0, the conduction degree of the fourth transistor when reading digital signal 1 is greater than the conduction degree of the fourth transistor when reading digital signal 0, the current flowing through the fourth transistor when reading digital signal 1 is more, and then the charge accumulated at the input terminal of the comparison circuit in a certain time is more, and the voltage received by the comparison circuit is more. The comparison circuit determines whether the data read by the ferroelectric storage unit is digital signal 0 or digital signal 1 according to the size of the received voltage.

[0103] When the first ferroelectric memory unit reads a digital signal 0, the ferroelectric capacitor is polarized and flipped; when the first ferroelectric memory unit reads a digital signal 1, the ferroelectric capacitor is not polarized and flipped. Therefore, the fourth voltage when reading a digital signal 0 is greater than the fourth voltage when reading a digital signal 1. The fourth transistor is turned on to a greater extent when reading a digital signal 0 than when reading a digital signal 1. More current flows through the fourth transistor when reading a digital signal 0 than when reading a digital signal 1. In a certain period of time, more charge is accumulated at the input end of the comparison circuit, and the comparison circuit receives more voltage. The comparison circuit determines whether the data read by the ferroelectric memory unit is a digital signal 0 or a digital signal 1 according to the received voltage.

[0104] In this case, the gate of the fourth transistor is electrically connected to the second node, and the fourth voltage controls the on-off degree of the fourth transistor and the current flowing through the fourth transistor. Therefore, the comparison circuit indirectly determines whether the data read by the ferroelectric memory unit is a digital signal 0 or a digital signal 1 according to the fourth voltage. Further, the fourth voltage can be amplified by charge accumulation to improve the reading quality and resolution of the storage circuit.

[0105] In a fourth aspect, the application provides a control method of a storage circuit. The storage circuit includes a ferroelectric memory unit, a clamping circuit, a voltage generation circuit, and a comparison circuit. The ferroelectric memory unit and the clamping circuit are electrically connected to a first node. The clamping circuit, the voltage generation circuit, and the comparison circuit are electrically connected to a second node.

[0106] In the pre-charging phase, the first node is pre-charged to 0V, and the voltage generation circuit is used to pre-charge the second node to a first voltage, which is less than 0V. In the reading phase, the ferroelectric memory unit inputs a second voltage to the second node through the first node and the clamping circuit, and the second voltage is greater than 0V. The clamping circuit clamps the potential of the first node to an initial voltage. The voltage generation circuit inputs a third voltage to the second node, and the potential of the second node is a fourth voltage. The comparison circuit receives the fourth voltage input by the second node and determines whether the data read by the ferroelectric memory unit is a digital signal 0 or 1 according to the fourth voltage. The fourth voltage is within the working voltage range of the comparison voltage.

[0107] In some possible implementations, the third voltage is the absolute value of the first voltage, and the fourth voltage is equal to the second voltage.

[0108] In some possible implementations, the storage circuit further includes a third transistor and a second voltage terminal. In the pre-charging phase, the first node is pre-charged to 0V, including: in the pre-charging phase, the third transistor is turned on, and the second voltage terminal pre-charges the first node to 0V through the third transistor.

[0109] The fourth aspect and any kind of implementation manner of the fourth aspect correspond to the first aspect and any kind of implementation manner of the first aspect respectively. The technical effects corresponding to the fourth aspect and any kind of implementation manner of the fourth aspect can be referred to the technical effects corresponding to the first aspect and any kind of implementation manner of the first aspect, which will not be repeated here.

[0110] In the fifth aspect, the application provides a memory, comprising a controller and the memory circuit according to the first aspect or the third aspect, wherein the controller is configured to control the memory circuit to read and write data.

[0111] The fifth aspect and any kind of implementation manner of the fifth aspect correspond to the first aspect and the third aspect and any kind of implementation manner of the first aspect and the third aspect respectively. The technical effects corresponding to the fifth aspect and any kind of implementation manner of the fifth aspect can be referred to the technical effects corresponding to the first aspect and the third aspect and any kind of implementation manner of the first aspect and the third aspect, which will not be repeated here.

[0112] In the sixth aspect, the application provides an electronic device, comprising a circuit board and the memory according to the fifth aspect, wherein the memory is arranged on the circuit board.

[0113] The sixth aspect and any kind of implementation manner of the sixth aspect correspond to the first aspect and the third aspect and any kind of implementation manner of the first aspect and the third aspect respectively. The technical effects corresponding to the sixth aspect and any kind of implementation manner of the sixth aspect can be referred to the technical effects corresponding to the first aspect and the third aspect and any kind of implementation manner of the first aspect and the third aspect, which will not be repeated here. BRIEF DESCRIPTION OF DRAWINGS

[0114] FIG. 1a is a relationship diagram of the memory and other modules in the electronic device according to the embodiments of the application;

[0115] FIG. 1b is an interaction diagram of the modules in the memory according to the embodiments of the application;

[0116] FIG. 2 is a circuit diagram of the ferroelectric memory array according to the embodiments of the application;

[0117] FIG. 3 is a timing diagram when the ferroelectric memory cell reads data according to the related art;

[0118] FIG. 4a is a circuit diagram of the memory circuit according to the embodiments of the application;

[0119] FIG. 4b is a working timing diagram of the circuit diagram shown in FIG. 4a;

[0120] FIG. 5a is a circuit diagram of the memory circuit according to the embodiments of the application;

[0121] Fig. 5b is a working timing diagram of the circuit diagram shown in Fig. 5a;

[0122] Fig. 6 is a circuit diagram of a storage circuit provided by an embodiment of the present application;

[0123] Fig. 7a is a circuit diagram of a storage circuit provided by an embodiment of the present application;

[0124] Fig. 7b is a circuit diagram of a storage circuit provided by an embodiment of the present application;

[0125] Fig. 8 is a circuit diagram of a storage circuit provided by an embodiment of the present application;

[0126] Fig. 9a is a circuit diagram of a storage circuit provided by an embodiment of the present application;

[0127] Fig. 9b is a working timing diagram of the circuit diagram shown in Fig. 9a;

[0128] Fig. 10 is a circuit diagram of a storage circuit provided by an embodiment of the present application;

[0129] Fig. 11 is a circuit diagram of a storage circuit provided by an embodiment of the present application;

[0130] Fig. 12 is a circuit diagram of a storage circuit provided by an embodiment of the present application. DETAILED DESCRIPTION

[0131] The technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are some of the embodiments of the present application, but not all the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative work fall within the scope of the present application.

[0132] The term “and / or” in the present application is only used to describe the association relationship of the associated objects, and means that there can be three relationships, for example, A and / or B can mean that A exists alone, A and B exist together, and B exists alone.

[0133] The terms “first” and “second” and the like in the specification and claims of the embodiments of the present application are used to distinguish different objects, and are not used to describe the specific order of the objects. For example, the first target object and the second target object are used to distinguish different target objects, and are not used to describe the specific order of the target objects.

[0134] In the embodiments of the present application, the word "exemplary" or "for example" is used to mean serving as an example, instance, or illustration. Any embodiment or design presented as "exemplary" or "for example" in the embodiments of the present application is not necessarily to be construed as preferred or advantageous over other embodiments or designs. Rather, use of the word "exemplary" or "for example" is intended to present concepts in a concrete manner.

[0135] In the description of the embodiments of the present application, the meaning of "a plurality of" is two or more, unless otherwise specified. For example, a plurality of processing units means two or more processing units; a plurality of systems means two or more systems.

[0136] The embodiments of the present application provide an electronic device, which can be a consumer electronic product, a home electronic product, a vehicle-mounted electronic product, a financial terminal product, a communication electronic product, and the like, including a memory.

[0137] The consumer electronic product is, for example, a mobile phone, a tablet computer, a notebook computer, a personal computer (PC), a personal digital assistant (PDA), a smart wearable product (for example, a smart watch, a smart bracelet, and the like), a virtual reality (VR) terminal device, an augmented reality (AR) terminal device, a drone, and the like. The home electronic product is, for example, a smart door lock, a television, a smart sound box, a refrigerator, a sweeping robot, and the like. The vehicle-mounted electronic product is, for example, a vehicle-mounted navigator, a vehicle-mounted display, and the like. The financial terminal product is, for example, an automated teller machine (ATM) machine, a self-service terminal, and the like. The communication electronic product is, for example, a server, a memory, a radar, a base station, and the like.

[0138] FIG. 1a is a structural schematic diagram of a memory in an electronic device provided by the present application. The electronic device includes a memory and other chips or independent devices, which can include a processor. As shown in FIG. 1b, the memory includes a storage array, a controller, a row decoder, a column decoder, and the like. The processor can send an address of a selected storage unit to the row decoder and the column decoder through the controller. The row decoder and the column decoder determine a storage unit in the storage array as the selected storage unit after decoding the received address, and then perform a read / write operation on the selected storage unit.

[0139] In some embodiments, the memory of the present application can be ferroelectric memory, which includes ferroelectric random access memory (FeRAM or FRAM) and ferroelectric field-effect transistor (FeFET) memory. As a new type of memory, ferroelectric memory has greater performance than traditional DRAM in terms of non-volatility, capacity density, etc. The storage unit in the ferroelectric memory includes a transistor and a ferroelectric capacitor, and the ferroelectric capacitor stores information based on the ferroelectric effect. The ferroelectric capacitor includes two electrodes and a ferroelectric material, such as a ferroelectric thin film, disposed between the two electrodes. Due to the nonlinear characteristics of the ferroelectric material, the dielectric constant of the ferroelectric material can not only be adjusted, but also become very large near the phase transition temperature. Therefore, compared with the traditional capacitor, the ferroelectric capacitor can have a larger dielectric constant and a smaller volume. In the embodiments of the present application, the number of transistors and ferroelectric capacitors in the storage unit is not limited, and the storage unit includes at least one transistor and at least one ferroelectric capacitor.

[0140] The working principle of the ferroelectric memory is as follows: when an electric field is applied to the ferroelectric capacitor of the storage unit, the central atoms stay in a low-energy state along the electric field; on the contrary, when the electric field is reversed and applied to the ferroelectric capacitor, the central atoms move in the crystal along the direction of the electric field and stay in another low-energy state. A large number of central atoms move in the crystal cell to form a ferroelectric domain, and the ferroelectric domain forms a polarization charge under the action of the electric field. The polarization charge formed by the ferroelectric domain under the electric field is high, and the polarization charge formed by the ferroelectric domain without reversal under the electric field is low. The binary stable state of such ferroelectric material makes the ferroelectric material can be used as a memory. The ferroelectric thin film can use common ferroelectric materials, such as Hf 0.5 Zr 0.5 O2, or antiferromagnetic materials such as PbZrO3, NH4H2PO4, etc.

[0141] FIG. 2 shows a circuit diagram of a storage array including a plurality of storage units, each of which includes a transistor and a ferroelectric capacitor connected to the transistor. For each storage unit, the gate of the transistor is connected to a word line WL, the first pole of the transistor is connected to a bit line BL, and the second pole is connected to a plate line PL through the ferroelectric capacitor.

[0142] In the process of reading and writing data in the ferroelectric memory cell using the ferroelectric memory, a voltage is applied to the ferroelectric capacitor by the plate line PL and the bit line BL. The existing reading method will affect the reliability of the ferroelectric memory. As shown in FIG. 3, before reading data, the bit line BL is pre-charged to 0 V, and then is in a floating state. Then, in the reading stage, a voltage is applied to the transistor by the word line WL to turn on the transistor, and a positive voltage is applied to the plate line PL. If the ferroelectric capacitor is polarized to flip, the potential on the bit line BL rises to a higher potential; if the ferroelectric capacitor does not polarize to flip, the potential on the bit line BL rises to a lower potential. Then, the potential on the BL is compared with the reference voltage Vref by using a comparison circuit to read the storage information 0 / 1 of the ferroelectric memory cell.

[0143] However, as mentioned in the background, assuming that the read information is a digital signal 1, the ferroelectric capacitor is polarized to flip, and the digital signal is read through the bit line BL, which makes the potential on the bit line BL rise and accumulate over time, thereby reducing the potential difference between the plate line PL and the bit line BL electrically connected to both ends of the ferroelectric capacitor, reducing the ferroelectric effective flipping voltage for controlling the ferroelectric capacitor to flip, and making the ferroelectric capacitor flip slower and insufficient. This phenomenon is the self-inhibition phenomenon of FeRAM reading a digital signal 1, which will affect the uniformity and reliability of the ferroelectric memory, and also reduce the storage window of the ferroelectric memory.

[0144] Based on this, the embodiment of the present application provides a storage circuit. In the reading stage, the first current mirror is used to make the potential on the first bit line BL1 always remain at the initial voltage, so as to ensure that the potential difference between the plate line PL and the first bit line BL1 is not reduced due to reading data, thereby causing the ferroelectric capacitor to flip insufficiently. In order to normally read data by using the storage circuit, another node can also be added. The potential on the node is closely related to the charge output by the first ferroelectric memory cell when reading data and the voltage on the first current mirror, so that the digital signal read by the storage circuit can be determined by the potential on the node as 0 / 1.

[0145] As shown in FIGS. 4a-4b and 5a-5b, in the case that the initial voltage pre-charged to the first bit line BL1 in the pre-charging stage is different potential (high level or low level), in the reading stage, the potential change trend of the first bit line BL1 is different when the ferroelectric capacitor FE-Cap is polarized to flip. Therefore, the working principle of the storage circuit is described respectively when the initial voltage of the first bit line BL1 is low level and high level.

[0146] It should be understood that in the reading stage, if the initial voltage of the first bit line BL1 is low level, the voltage on the plate line PL is high level; if the initial voltage of the first bit line BL1 is high level, the voltage on the plate line PL is low level.

[0147] As shown in FIG. 4a, the storage circuit includes a first ferroelectric storage unit 11, a first current mirror 12, a first voltage generating circuit 13, a comparison circuit 14, and a first voltage terminal Vss1. The first current mirror includes a first branch and a second branch, one end of the first branch and one end of the second branch are electrically connected to the first voltage terminal, and the current of the first branch is the same as that of the second branch. The output end of the first ferroelectric storage unit 11 is electrically connected to the other end of the first branch at a first node A, the other end of the second branch is electrically connected to the input end of the first voltage generating circuit 13 and the comparison circuit 14 at a second node B, and the output end of the comparison circuit 14 is electrically connected to the output end of the storage circuit.

[0148] The first current mirror 12 can include a first transistor T1 and a second transistor T2, and the first transistor T1 and the second transistor T2 are the same, that is, the parameters of each film layer in the first transistor T1 are the same as the parameters of each film layer in the second transistor T2. The first transistor T1 and the second transistor T2 can be N-type transistors, or the first transistor T1 and the second transistor T2 can also be P-type transistors. If the initial voltage of the first bit line BL1 is low, the first transistor T1 and the second transistor T2 are both N-type transistors; if the initial voltage of the first bit line BL1 is high, the first transistor T1 and the second transistor T2 are both P-type transistors.

[0149] The working principle of the storage circuit will be described in detail below in combination with FIG. 4a and FIG. 4b.

[0150] FIG. 4a and FIG. 4b respectively show the circuit diagram and the timing diagram of the storage circuit when the first transistor T1 and the second transistor T2 are both N-type transistors, and FIG. 4b shows the timing diagram when other transistors in the storage circuit are all N-type transistors, and the ferroelectric capacitor FE-Cap flips when reading the digital signal 1. The first voltage generating circuit 13 includes an inverter as an example, and the timing diagram corresponds to the potential of the gate of each transistor.

[0151] In the precharge phase, the potential of the first node A (the first bit line BL1) is the initial voltage, which is low, for example, the initial voltage can be 0V.

[0152] In the read phase, the working process of each module in the storage circuit is as follows:

[0153] The first voltage terminal Vss1 is used to input the first voltage to the first current mirror 12, and the first voltage generating circuit 13 is used to input the second voltage to the second node B. Here, the first voltage terminal Vss1 is a ground terminal, and the first voltage input to the first current mirror 12 is low; the second voltage is high, and the second voltage is greater than the first voltage; and the initial voltage is greater than the first voltage.

[0154] When the first ferroelectric memory cell 11 reads data, the first ferroelectric memory cell 11 inputs charges (positive charges) to the first node A (the first bit line BL1), and because the initial voltage is greater than the first voltage, there is a potential difference between the first node A and the first branch, and the first branch extracts charges from the first node A (as those skilled in the art should know, charges move from a high potential to a low potential). In this way, the first node A receives the charges input by the first ferroelectric memory cell 11 while also being extracted by the first branch, and therefore the first node A remains at the initial voltage. That is, the charges input by the first ferroelectric memory cell 11 to the first node A are not accumulated at the first node A.

[0155] Further, according to the working principle of the first current mirror 12, the first branch copies the first current flowing through the first branch to the second branch, and then the second branch changes the potential of the second node B from the second voltage to the third voltage according to the first current, the first voltage input to the first current mirror, and the second voltage of the second node B.

[0156] It should be understood that, in the case where the first transistor T1 and the second transistor T2 are the same, the current flowing through the first transistor T1 and the second transistor T2 is the first current, the first voltage terminal Vss1 simultaneously inputs a low level to the first transistor T1 and the second transistor T2, and the second voltage of the second node B is greater than the first voltage, if the first branch extracts charges from the first node A, the second branch will also extract charges from the second node B, so that the potential of the second node B decreases from the second voltage to the third voltage.

[0157] As those skilled in the art should know, in the read stage, when the ferroelectric capacitor FE-Cap in the first ferroelectric memory cell 11 undergoes a polarization flip, the first ferroelectric memory cell 11 outputs a polarization current; when the ferroelectric capacitor FE-Cap does not undergo a polarization flip, the first ferroelectric memory cell 11 outputs a dielectric current. The amount of charges input to the first node A when the ferroelectric capacitor FE-Cap undergoes a polarization flip is greater than the amount of charges input to the first node A when the ferroelectric capacitor FE-Cap does not undergo a polarization flip, and therefore the amount of charges extracted by the first branch from the first node A when the ferroelectric capacitor FE-Cap undergoes a polarization flip is greater than the amount of charges extracted by the first branch from the first node A when the ferroelectric capacitor FE-Cap does not undergo a polarization flip.

[0158] It is known that the amount of charge extracted from the first node A by the first branch when the ferroelectric capacitor FE-Cap undergoes a polarization reversal is greater than the amount of charge extracted from the first node A by the first branch when the ferroelectric capacitor FE-Cap does not undergo a polarization reversal. Therefore, the amount of charge extracted from the second node B by the second branch when the ferroelectric capacitor FE-Cap undergoes a polarization reversal is also greater than the amount of charge extracted from the second node B by the second branch when the ferroelectric capacitor FE-Cap does not undergo a polarization reversal. That is, whether the ferroelectric capacitor FE-Cap undergoes a polarization reversal or not, the third voltage remaining on the second node B after the charge is extracted is not the same.

[0159] Further, the second node B inputs the remaining third voltage to the comparison circuit 14, and the comparison circuit 14 can determine whether the data read by the first ferroelectric memory cell 11 is a digital signal 0 or a digital signal 1 according to the third voltage.

[0160] In the present application, because the data (digital signal 1 or digital signal 0) read by the first ferroelectric memory cell 11 is different when the ferroelectric capacitor FE-Cap undergoes a polarization reversal or not, the amount of charge input to the first node A is different, the first current flowing through the first branch and the second branch is different, the amount of charge extracted from the first node A by the first branch is different, and the potential difference between the second node B and the second branch is different. Therefore, when the first ferroelectric memory cell 11 reads different data, the second branch can extract charge from the second node B according to the first current, the first voltage, and the second voltage, so that the potential of the second node B decreases from the second voltage to the third voltage. It can be seen that the remaining potential third voltage on the second node B is related to the data (digital signal 1 or digital signal 0) read by the first ferroelectric memory cell 11. Therefore, the third voltage can be input to the comparison circuit 14 by using the second node B, so that the comparison circuit 14 can determine whether the data read by the first ferroelectric memory cell 11 is a digital signal 0 or a digital signal 1 according to the third voltage.

[0161] Meanwhile, whether the digital signal 1 is read or the digital signal 0 is read, the charge on the first bit line BL1 is extracted by the first branch, so that the potential on the first bit line BL1 is kept at 0V (or close to 0V). On the one hand, the potential difference between the plate line PL and the first bit line BL1 is stabilized at a fixed value, which does not affect the polarization reversal of the ferroelectric capacitor FE-Cap. On the other hand, the potential difference between the plate line PL and the first bit line BL1 is always at a large value, so that the polarization reversal of the ferroelectric capacitor FE-Cap does not become slower and slower or even insufficient due to the decrease of the potential difference between the plate line PL and the first bit line BL1, thereby avoiding the self-inhibition phenomenon, improving the uniformity and reliability of the storage circuit, and also improving the storage window of the ferroelectric circuit.

[0162] In some possible implementations, the third voltage read by the first ferroelectric memory cell 11 is different in size depending on the data (digital signal 1 or digital signal 0) read when the polarization of the ferroelectric capacitor FE-Cap is flipped.

[0163] For example, it is assumed that the polarization of the ferroelectric capacitor FE-Cap is flipped when the first ferroelectric memory cell 11 reads a digital signal 1, and the polarization of the ferroelectric capacitor FE-Cap is not flipped when the first ferroelectric memory cell 11 reads a digital signal 0. In this case, when the first ferroelectric memory cell 11 reads a digital signal 1, the first ferroelectric memory cell 11 outputs a polarization current, the polarization current flows to the first branch through the first node A, the first branch copies a polarization current of the same size to the second branch, and the second branch extracts a first charge amount from the second node B under the influence of the polarization current, the first voltage, and the second voltage, and the potential of the second node B is greatly reduced. When the first ferroelectric memory cell 11 reads a digital signal 0, the first ferroelectric memory cell 11 outputs a small amount of dielectric current, the dielectric current flows to the first branch through the first node A, the first branch copies a dielectric current of the same size to the second branch, and the second branch extracts a second charge amount from the second node B under the influence of the dielectric current, the first voltage, and the second voltage, and the potential of the second node B is slightly reduced. The first charge amount is greater than the second charge amount.

[0164] In this case, the third voltage when the first ferroelectric memory cell 11 reads a digital signal 1 is smaller than the third voltage when the first ferroelectric memory cell 11 reads a digital signal 0.

[0165] For example, it is assumed that the polarization of the ferroelectric capacitor FE-Cap is flipped when the first ferroelectric memory cell 11 reads a digital signal 0, and the polarization of the ferroelectric capacitor FE-Cap is not flipped when the first ferroelectric memory cell 11 reads a digital signal 1. In this case, when the first ferroelectric memory cell 11 reads a digital signal 0, the first ferroelectric memory cell 11 outputs a polarization current, the polarization current flows to the first branch through the first node A, the first branch copies a polarization current of the same size to the second branch, and the second branch extracts a first charge amount from the second node B under the influence of the polarization current, the first voltage, and the second voltage, and the potential of the second node B is greatly reduced. When the first ferroelectric memory cell 11 reads a digital signal 1, the first ferroelectric memory cell 11 outputs a small amount of dielectric current, the dielectric current flows to the first branch through the first node A, the first branch copies a dielectric current of the same size to the second branch, and the second branch extracts a second charge amount from the second node B under the influence of the dielectric current, the first voltage, and the second voltage, and the potential of the second node B is slightly reduced. The first charge amount is greater than the second charge amount.

[0166] In this case, the third voltage when the first ferroelectric memory cell 11 reads the digital signal 1 is greater than the third voltage when the first ferroelectric memory cell 11 reads the digital signal 0.

[0167] In some embodiments, in the first current mirror 12, since the current input to the first branch is always the same as the current output by the second branch, in order to ensure that the first branch copies the same polarization current or dielectric current to the second branch when the first current mirror 12 is working, the initial current flowing through the first branch should be the same as the initial current flowing through the second branch before the polarization current or dielectric current flows to the first branch. However, the current of the first branch is easily affected by the first node A, and the current of the second branch is easily affected by the second node B, which may cause the initial current of the first branch to be different from the initial current flowing through the second branch.

[0168] Based on this, the storage circuit of the embodiments of the present application further comprises a third transistor T3 and a fourth transistor T4, the third transistor T3 is connected in series between the first node A and the first transistor T1 (the first pole of the third transistor T3 is electrically connected with the first node A, and the second pole of the third transistor T3 is electrically connected with the first pole of the first transistor T1), and the fourth transistor T4 is connected in series between the second node B and the second transistor T2 (the first pole of the fourth transistor T4 is electrically connected with the second node B, and the second pole of the fourth transistor T4 is electrically connected with the first pole of the second transistor T2). Moreover, the third transistor T3 and the fourth transistor T4 are also N-type transistors.

[0169] In the reading stage, the third transistor T3 and the fourth transistor T4 are both turned on, the second pole of the third transistor T3 inputs the clamping voltage to the first pole of the first transistor T1, and the second pole of the fourth transistor T4 inputs the clamping voltage to the first pole of the second transistor T2, so that the potential of the connection node C of the third transistor T3 and the first transistor T1 and the potential of the connection node D of the fourth transistor T4 and the second transistor T2 are the same, so as to realize that the initial current flowing through the first branch is the same as the initial current flowing through the second branch in the case that the first transistor T1 and the second transistor T2 are the same (the resistances of the first transistor T1 and the second transistor T2 are the same).

[0170] In addition, due to the existence of the clamping voltage, after the first current mirror 12 reaches a certain voltage value, the voltage no longer rises. In this way, if the first branch extracts charges from the first node A, the voltage value of the first current mirror 12 is saturated, and at this time, the first branch no longer extracts charges from the first node A, and there are still residual charges on the first bit line BL1, so that the potential on the first bit line BL1 is greater than 0V, and the potential difference between the plate line PL and the first bit line BL1 is reduced. Based on this, the storage circuit can also not contain the third transistor T3 and the fourth transistor T4.

[0171] Of course, it should be understood that even if the storage circuit includes the third transistor T3 and the fourth transistor T4, the first branch can still extract charges from the first node A, and thus, compared with the prior art, the potential difference between the plate line PL and the first bit line BL1 can still be increased, thereby improving the self-inhibition phenomenon.

[0172] In some embodiments, the first voltage generating circuit 13 includes a second voltage terminal V_boost, which is used to input a second voltage to the second node B during the reading stage. However, due to the parasitic capacitance, the voltage value received by the second node B cannot reach the voltage value output by the second voltage terminal V_boost. Therefore, the first voltage generating circuit 13 can further include a tank capacitor TC, which is electrically connected between the second node B and the second voltage terminal V_boost, wherein the second voltage terminal V_boost is electrically connected to a first electrode of the tank capacitor TC, and the second node B is electrically connected to a second electrode of the tank capacitor TC. In this way, the first voltage generating circuit 13 can first input the second voltage to the first electrode, and the first electrode can couple the second voltage to the second electrode and the second node B, so as to improve the problem that the voltage output by the second voltage terminal V_boost is largely taken away by the parasitic capacitance, resulting in that the voltage value received by the second node B cannot reach the voltage value output by the second voltage terminal V_boost.

[0173] In addition, since the first electrode and the second electrode of the tank capacitor TC are isolated by the insulating material therebetween, after the first electrode couples the second voltage to the second electrode and the second node B, the potential of the second electrode and the second node B is no longer affected by the second voltage terminal V_boost and the first electrode even if the second voltage terminal V_boost still provides the second voltage to the first electrode. Therefore, after the second node B is extracted by the second branch, the potential on the second node B decreases, rather than being maintained at 0V (or approaching 0V) as the first node A even if the first node A is extracted by the first branch.

[0174] In some possible implementation manners, as shown in FIG. 6, there is usually a loss problem in the transmission process of the signal. Based on this, the first voltage generating circuit 13 can further include an inverter 131 electrically connected between the second voltage terminal V_boost and the tank capacitor TC, so as to enhance the signal.

[0175] Here, it should be noted that the second voltage required by the second node B is a high level. If the first voltage generating circuit 13 does not include the inverter 131, the voltage output by the second voltage terminal V_boost is also a high level. If the first voltage generating circuit 13 includes the inverter 131, the voltage output by the second voltage terminal V_boost is a low level.

[0176] In some embodiments, as shown in Fig. 6, the storage circuit further comprises a third voltage terminal V3 and a pre-charge circuit 15 electrically connected between the third voltage terminal V3 and the first node A. In a pre-charge phase before the read phase, the third voltage terminal V3 is used to input an initial voltage of 0V to the first bit line BL1 through the pre-charge circuit 15, in preparation for the read phase. Further, in the read phase, the potential difference between the control plate line PL and the first bit line BL1 can be controlled by controlling the voltage on the control plate line PL, so as to control the first ferroelectric storage unit 11 to read data.

[0177] Optionally, the pre-charge circuit 15 comprises a first switch ISO and a second switch PCH, the first switch ISO being electrically connected between the input end of the first branch and the output end of the second branch, and the second switch PCH being electrically connected between the third voltage terminal V3 and the second node B. In the pre-charge phase, both the first switch ISO and the second switch PCH are turned on, and the third voltage terminal V3 inputs an initial voltage of 0V to the first bit line BL1 through the second switch PCH and the first switch ISO.

[0178] In some possible implementations, after pre-charging the first bit line BL1 with the third voltage terminal V3 in the pre-charge phase, the second node B can also be pre-charged with the third voltage terminal V3, in which case the second switch PCH is turned on, and the third voltage terminal V3 pre-charges the second node B to a charging voltage through the second switch PCH, the charging voltage being greater than 0V. At the same time, the first switch ISO is turned off, so the charging voltage of the third voltage terminal V3 does not affect the potential on the first bit line BL1.

[0179] In the pre-charge phase, the third voltage terminal V3 inputs a charging voltage to the second node B; in the read phase, the second voltage terminal V_boost inputs a second voltage to the second node B. In this way, before the second node B is extracted of electric charges by the second branch, the voltage on the second node B is the sum of the charging voltage and the second voltage. The embodiments of the present application input voltages to the second node B multiple times to ensure that the voltage on the second node B is large enough, thereby increasing the MW of the storage circuit by increasing the difference between the third voltage of the second node B when reading the digital signal 1 and the third voltage of the second node B when reading the digital signal 0.

[0180] In other embodiments, as mentioned above, the comparison circuit 14 in the prior art reads the digital signal 1 or the digital signal 0 by obtaining electric charges on the first bit line BL1, and the first bit line BL1 is usually connected with multiple ferroelectric storage units and has a relatively long length, so the first bit line BL1 inevitably forms a parasitic capacitance Cbl1 with multiple conductive structures in the storage chip, and the parasitic capacitance Cbl1 has a negative impact on the MW of the storage circuit.

[0181] According to the formula charge quantity (Q) = voltage (U) * capacitance (C), the greater the parasitic capacitance Cbl1 on the first bit line BL1, the smaller the voltage U on the first bit line BL1, the greater the potential difference between the plate line PL and the first bit line BL1, and the greater the effective flipping voltage of the ferroelectric capacitor FE-Cap, and the more sufficient the flipping of the ferroelectric capacitor FE-Cap.

[0182] It can be seen that the existence of the parasitic capacitance Cbl1 leads to a trade-off between the MW of the storage circuit and the effective flipping voltage of the ferroelectric capacitor FE-Cap, and therefore is limited in design.

[0183] In the scheme of the present application, the comparison circuit 14 no longer reads the digital signal 1 or the digital signal 0 by obtaining the voltage on the first bit line BL1, but reads the digital signal 1 or the digital signal 0 by obtaining the voltage on the second node B. In this way, even if there is a large parasitic capacitance Cbl1 on the first bit line BL1, it will not have a negative impact on the MW of the storage circuit, and according to the formula charge quantity (Q) = voltage (U) * capacitance (C), the parasitic capacitance Cbl1 of the first bit line BL1 can also increase the effective flipping voltage, so that the ferroelectric capacitor FE-Cap flips more fully.

[0184] On this basis, in the reading stage, the first switch ISO and the second switch PCH can be disconnected, so that the second node B is isolated (the second node B is isolated from the first node A by the first switch ISO, and the second node B is isolated from the third voltage terminal V3 by the second switch PCH), and therefore the parasitic capacitance of the second node B is very small, and the impact on the MW of the storage circuit is also very small.

[0185] In some embodiments, as shown in FIG. 6, the storage circuit further includes a reference voltage terminal Vref. In the reading stage, the reference voltage terminal Vref can input a reference voltage to the comparison circuit 14, and the comparison circuit 14 determines whether the data read by the first ferroelectric storage unit 11 is a digital signal 0 or a digital signal 1 according to the received third voltage and the reference voltage.

[0186] In contrast to the prior art, if it is set that the ferroelectric capacitor FE-Cap of the first ferroelectric storage unit 11 flips when reading the digital signal 1, the third voltage of the prior art when reading the digital signal 1 is greater than the third voltage when reading the digital signal 0; and the third voltage of the present application when reading the digital signal 1 is less than the third voltage when reading the digital signal 0. If it is set that the ferroelectric capacitor FE-Cap of the first ferroelectric storage unit 11 flips when reading the digital signal 0, the third voltage of the prior art when reading the digital signal 0 is greater than the third voltage when reading the digital signal 1; and the third voltage of the present application when reading the digital signal 0 is less than the third voltage when reading the digital signal 1.

[0187] Based on this, the comparison circuit 14 of the present application should combine the data read when the ferroelectric capacitor FE-Cap occurs polarization reversal according to the set, to determine the data read by the first ferroelectric memory cell 11 as digital signal 0 or digital signal 1 according to the received fourth voltage and the reference voltage.

[0188] The working principle of the comparison circuit 14 of the present application reading data will be described in detail below in combination with the circuit structure of the comparison circuit 14.

[0189] As shown in FIG. 6, the comparison circuit 14 includes a fourth voltage terminal V4, a first P-type transistor P1, a second P-type transistor P2, a first N-type transistor N1, a second N-type transistor N2, a ground terminal Vss2, and a storage circuit further including an output terminal OUT. In the reading stage, the fourth voltage terminal V4 is high, and the ground terminal Vss2 is low.

[0190] The gate of the first P-type transistor P1 and the gate of the first N-type transistor N1 are electrically connected with the second pole of the second P-type transistor, the first pole of the second N-type transistor, and the reference voltage terminal Vref, the first pole of the first P-type transistor P1 is electrically connected with the fourth voltage terminal V4, the second pole of the first P-type transistor P1 is electrically connected with the first pole of the first N-type transistor N1 and the output terminal OUT, and the second pole of the first N-type transistor N1 is electrically connected with the ground terminal Vss2. The gate of the second P-type transistor P2 and the gate of the second N-type transistor N2 are electrically connected with the second node B, the first pole of the second P-type transistor P2 is electrically connected with the fourth voltage terminal V4, the second pole of the second N-type transistor N2 is electrically connected with the ground terminal Vss2. The output terminal OUT is electrically connected between the second node B and the second pole of the first P-type transistor P1 and the first pole of the first N-type transistor N1.

[0191] For example, taking the first ferroelectric memory cell 11 as an example, when reading digital signal 1, the ferroelectric capacitor FE-Cap occurs polarization reversal, the third voltage when reading digital signal 1 is less than the third voltage when reading digital signal 0.

[0192] When reading the digital signal 1, the third voltage of the second node B is low, and the second P-type transistor P2 is turned on. The reference voltage of the reference voltage terminal Vref is greater than the third voltage when the first ferroelectric storage unit 11 reads the digital signal 1, and is less than the third voltage when the first ferroelectric storage unit 11 reads the digital signal 0. Therefore, even if the reference voltage terminal Vref is electrically connected to the gate of the first P-type transistor P1 and the gate of the first N-type transistor N1, the turn-on degree of the first P-type transistor P1 and the first N-type transistor N1 is less than the turn-on degree of the second P-type transistor P2. The second P-type transistor P2 can be charged more quickly, and the high level of the fourth voltage terminal V4 is transmitted to the gate of the first N-type transistor N1 and the reference voltage terminal Vref. The reference voltage terminal Vref is pulled high. Further, the first N-type transistor N1 is turned on, the ground terminal Vss2 transmits the low level to the output terminal OUT through the first N-type transistor N1, the output terminal OUT outputs the low level, and it is confirmed that the data read by the first ferroelectric storage unit 11 is the digital signal 1.

[0193] When reading the digital signal 0, the third voltage of the second node B is high, and the second N-type transistor N2 is turned on. The reference voltage of the reference voltage terminal Vref is greater than the third voltage when the first ferroelectric storage unit 11 reads the digital signal 1, and is less than the third voltage when the first ferroelectric storage unit 11 reads the digital signal 0. Therefore, even if the reference voltage terminal Vref is electrically connected to the gate of the first P-type transistor P1 and the gate of the first N-type transistor N1, the turn-on degree of the first P-type transistor P1 and the first N-type transistor N1 is less than the turn-on degree of the second N-type transistor N2. The second N-type transistor N2 can be charged more quickly, and the low level of the ground terminal Vss2 is transmitted to the gate of the first P-type transistor P1 and the reference voltage terminal Vref. The reference voltage terminal Vref is pulled low. Further, the first P-type transistor P1 is turned on, the fourth voltage terminal V4 transmits the high level to the output terminal OUT through the first P-type transistor P1, the output terminal OUT outputs the high level, and it is confirmed that the data read by the first ferroelectric storage unit 11 is the digital signal 0.

[0194] For example, when the first ferroelectric storage unit 11 is set to read the digital signal 0, the ferroelectric capacitor FE-Cap is polarized to flip. The third voltage when reading the digital signal 0 is less than the third voltage when reading the digital signal 1.

[0195] When reading digital signal 0, the third voltage of the second node B is low, and the second P-type transistor P2 is turned on. The reference voltage of the reference voltage terminal Vref is greater than the third voltage when the first ferroelectric storage unit 11 reads digital signal 0, and is less than the third voltage when the first ferroelectric storage unit 11 reads digital signal 1. Therefore, even if the reference voltage terminal Vref is electrically connected to the gate of the first P-type transistor P1 and the gate of the first N-type transistor N1, the on degree of the first P-type transistor P1 and the first N-type transistor N1 is less than the on degree of the second P-type transistor P2, the second P-type transistor P2 can be charged more quickly, and the high level of the fourth voltage terminal V4 is transmitted to the gate of the first N-type transistor N1 and the reference voltage terminal Vref, and the reference voltage terminal Vref is pulled high. Further, the first N-type transistor N1 is turned on, the ground terminal Vss2 transmits low level to the output terminal OUT through the first N-type transistor N1, the output terminal OUT outputs low level, and it is confirmed that the data read by the first ferroelectric storage unit 11 is digital signal 0.

[0196] When reading digital signal 1, the third voltage of the second node B is high, and the second N-type transistor N2 is turned on. The reference voltage of the reference voltage terminal Vref is greater than the third voltage when the first ferroelectric storage unit 11 reads digital signal 0, and is less than the third voltage when the first ferroelectric storage unit 11 reads digital signal 1. Therefore, even if the reference voltage terminal Vref is electrically connected to the gate of the first P-type transistor P1 and the gate of the first N-type transistor N1, the on degree of the first P-type transistor P1 and the first N-type transistor N1 is less than the on degree of the second N-type transistor N2, the second N-type transistor N2 can be charged more quickly, and the low level of the ground terminal Vss2 is transmitted to the gate of the first P-type transistor P1 and the reference voltage terminal Vref, and the reference voltage terminal Vref is pulled low. Further, the first P-type transistor P1 is turned on, the fourth voltage terminal V4 transmits high level to the output terminal OUT through the first P-type transistor P1, the output terminal OUT outputs high level, and it is confirmed that the data read by the first ferroelectric storage unit 11 is digital signal 1.

[0197] In some embodiments, as shown in FIG. 7a and FIG. 7b, the storage circuit further comprises a reference voltage generating circuit 16 and a fifth voltage terminal Vss3, the reference voltage generating circuit 16 is used to provide a reference voltage for the comparison circuit 14. The reference voltage generating circuit 16 comprises a second ferroelectric storage unit 161, a third ferroelectric storage unit 162, a second current mirror 163, a second voltage generating circuit 164, and a third node E. The circuit structure of the second ferroelectric storage unit 161 and the third ferroelectric storage unit 162 is the same as that of the first ferroelectric storage unit 11, and the second current mirror 163 comprises a third branch and a fourth branch.

[0198] The circuit structure of the second ferroelectric memory unit 161 and the third ferroelectric memory unit 162 is the same as that of the first ferroelectric memory unit 11, which means that the number of transistors and the number of ferroelectric capacitors included in the second ferroelectric memory unit 161 and the third ferroelectric memory unit 162 are the same as those included in the first ferroelectric memory unit 11, and the parameters of each film layer of the transistors in the second ferroelectric memory unit 161 and the third ferroelectric memory unit 162 are the same as those of the transistors in the first ferroelectric memory unit 11; the parameters of each film layer of the ferroelectric capacitors in the second ferroelectric memory unit 161 and the third ferroelectric memory unit 162 are the same as those of the ferroelectric capacitors in the first ferroelectric memory unit 11.

[0199] In the read stage:

[0200] The second voltage generating circuit 164 is configured to input a fourth voltage to the third node E, and the fourth voltage is the same as the second voltage. The fifth voltage terminal Vss3 is configured to input a low level to the second current mirror 163.

[0201] The second ferroelectric memory unit 161 is configured to input a second current to the third branch, and the second current represents that the second ferroelectric memory unit 161 reads the digital signal 1. The third ferroelectric memory unit 162 is configured to input a third current to the fourth branch, and the third current represents that the third ferroelectric memory unit 162 reads the digital signal 0. The third branch receives the second current and the third current, and copies the average of the second current and the third current to the fourth branch.

[0202] The fourth branch is configured to extract charges from the third node E according to the average of the second current and the third current, the fourth voltage, and the low level on the fourth branch, so that the potential of the third node E decreases from the fourth voltage to a fifth voltage, and the fifth voltage is input to the reference voltage terminal Vref. The fifth voltage is half of the fourth voltage.

[0203] Since the circuit structure of the second ferroelectric memory unit 161 and the third ferroelectric memory unit 162 is the same as that of the first ferroelectric memory unit 11, the fourth voltage on the third node E is the same as the second voltage on the second node B, and the current of the fourth branch is the average of the second current when the second ferroelectric memory unit 161 reads the digital signal 1 and the third current when the third ferroelectric memory unit 162 reads the digital signal 0, the fourth branch extracts an average charge amount between the digital signal 0 and the digital signal 1 from the third node E, and the fifth voltage remaining on the third node E is also between the third voltage when the first ferroelectric memory unit 11 reads the digital signal 1 and the third voltage when the first ferroelectric memory unit 11 reads the digital signal 0, so the fifth voltage can be used as a reference voltage to determine whether the third voltage input by the second node B to the comparison circuit 14 corresponds to the digital signal 0 or the digital signal 1.

[0204] And, since the circuit structure of the second ferroelectric memory unit 161 and the third ferroelectric memory unit 162 is the same as that of the first ferroelectric memory unit 11, when the performance of the first ferroelectric memory unit 11 changes due to external changes (such as temperature, voltage, etc.), the performance of the second ferroelectric memory unit 161 and the third ferroelectric memory unit 162 also changes accordingly, so the reference voltage generating circuit 16 can also be used to achieve automatic adjustment under different environments.

[0205] In addition, in order to achieve the same change in the performance of the second ferroelectric memory unit 161 and the third ferroelectric memory unit 162 when the performance of the first ferroelectric memory unit 11 changes due to external changes (such as temperature, voltage, etc.), the circuit structure of the second voltage generating circuit 164 can be the same as that of the first voltage generating circuit 13, the second ferroelectric memory unit 161 is also electrically connected to the second bit line BL2, the third ferroelectric memory unit 162 is also electrically connected to the third bit line BL3, and the parasitic capacitance Cbl2 on the second bit line BL2 and the parasitic capacitance Cbl3 on the third bit line BL3 are the same as the parasitic capacitance on the first bit line BL1.

[0206] However, those skilled in the art should know that although the circuit structure of the second ferroelectric memory unit 161 and the third ferroelectric memory unit 162 is the same as that of the first ferroelectric memory unit 11, the digital signal 1 and the digital signal 0 output by the second ferroelectric memory unit 161 and the third ferroelectric memory unit 162 are not counted as the data read out by the storage circuit.

[0207] In some possible implementations, the third branch can copy the average of the second current and the third current to the fourth branch in the following two ways.

[0208] The first way is shown in FIG. 7a. The third branch includes a fifth transistor T5 and a sixth transistor T6, and the fourth branch includes a seventh transistor T7. The channel width of the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 is the same. The gate of the fifth transistor T5, the gate of the sixth transistor T6, the first electrode of the fifth transistor T5, the first electrode of the sixth transistor T6, and the gate of the seventh transistor T7 are electrically connected to the output terminals of the second ferroelectric memory unit 161 and the third ferroelectric memory unit 162. The second electrode of the fifth transistor T5, the second electrode of the sixth transistor T6, and the second electrode of the seventh transistor T7 are electrically connected to the fifth voltage terminal Vss3, and the first electrode of the seventh transistor T7 is electrically connected to the third node E.

[0209] According to the current formula of the transistor, in the third branch, the fifth transistor T5 and the sixth transistor T6 are connected in parallel, and the channel width of the fifth transistor T5 is the same as that of the sixth transistor T6. Therefore, the total current flowing through the third branch is the sum of the second current flowing through the fifth transistor T5 and the third current flowing through the sixth transistor T6. Further, because the channel widths of the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 are the same, the ratio of the total channel width of the third branch to the channel width of the fourth branch is 2:1, and the third branch can copy the average of the second current and the third current to the fourth branch.

[0210] The second mode, as shown in FIG. 7b, the third branch includes the fifth transistor T5, the fourth branch includes the sixth transistor T6, and the channel width of the fifth transistor T5 is twice that of the sixth transistor T6. The gate of the fifth transistor T5, the gate of the sixth transistor T6, and the first pole of the fifth transistor T5 are electrically connected to the output terminals of the second ferroelectric storage unit 161 and the third ferroelectric storage unit 162. The second pole of the fifth transistor T5 and the second pole of the sixth transistor T6 are electrically connected to the fifth voltage terminal Vss3, and the first pole of the sixth transistor T6 is electrically connected to the third node E.

[0211] According to the current formula of the transistor, the channel width of the fifth transistor T5 is twice that of the sixth transistor T6. Therefore, the current flowing through the sixth transistor T6 is twice the current flowing through the fifth transistor T5. The current on the third branch composed of the fifth transistor T5 is the sum of the second current and the third current. Therefore, the third branch can copy the average of the second current and the third current to the fourth branch.

[0212] In some embodiments, after the reading stage, the first ferroelectric storage unit can also be subjected to a reverse writing operation. The storage circuit further includes a third switch WR electrically connected between the reference voltage terminal and the first node. In the reading stage, the third switch WR is open; in the reverse writing stage, the third switch WR is turned on to input the writing signal of the reference voltage terminal Vref to the first ferroelectric storage unit 11 through the first node A.

[0213] Taking the case that the first ferroelectric storage unit 11 is set to read the digital signal 1 and the ferroelectric capacitor is polarized to flip as an example, when reading the digital signal 1, the reference voltage terminal Vref is at a high level; in the reverse writing stage, the reference voltage terminal Vref inputs the high level to the first ferroelectric storage unit 11 through the third switch WR, completing the reverse writing of the digital signal 1. When reading the digital signal 0, the reference voltage terminal Vref is at a low level; in the reverse writing stage, the reference voltage terminal Vref inputs the low level to the first ferroelectric storage unit 11 through the third switch WR, completing the reverse writing of the digital signal 0.

[0214] For example, when the first ferroelectric memory cell 11 reads a digital signal 0, the reference voltage terminal Vref is high. In the write-back stage, the reference voltage terminal Vref inputs high to the first ferroelectric memory cell 11 through the third switch WR, and the write-back of the digital signal 0 is completed. When the first ferroelectric memory cell 11 reads a digital signal 1, the reference voltage terminal Vref is low. In the write-back stage, the reference voltage terminal Vref inputs low to the first ferroelectric memory cell 11 through the third switch WR, and the write-back of the digital signal 1 is completed.

[0215] In addition, if the first ferroelectric memory cell 11 reads a digital signal 1 in the read stage, and a digital signal 0 needs to be written to the first ferroelectric memory cell 11 in the write stage, the first ferroelectric memory cell 11 can be rewritten instead of write-back. Alternatively, if the first ferroelectric memory cell 11 reads a digital signal 0 in the read stage, and a digital signal 1 needs to be written to the first ferroelectric memory cell 11 in the write stage, the first ferroelectric memory cell 11 can be rewritten instead of write-back.

[0216] In this case, the first ferroelectric memory cell 11 is no longer write-back by the reference voltage terminal Vref, but the output terminal OUT of the storage circuit is multiplexed as the input terminal of the storage circuit (or the comparison circuit), and the first ferroelectric memory cell 11 is rewritten by the input terminal of the storage circuit.

[0217] The foregoing describes the working principle of the storage circuit when the initial voltage of the first node A (the first bit line BL1) is low, and the first transistor T1 and the second transistor T2 are both N-type transistors. In the following, the working principle of the storage circuit when the initial voltage of the first node A (the first bit line BL1) is low, and the first transistor T1 and the second transistor T2 are both P-type transistors will be described with reference to the accompanying drawings. Different from when the first transistor T1 and the second transistor T2 are both N-type transistors, when the first transistor T1 and the second transistor T2 are both P-type transistors, the first node A (the first bit line BL1) is high in the pre-charge stage and the read stage, and the plate line PL connected to the other end of the first ferroelectric memory cell 11 is low (for example, 0V). In the read stage, the first ferroelectric memory cell 11 inputs a read signal to the first node A (the first bit line BL1), so that the voltage of the first node A (the first bit line BL1) decreases instead of increasing, thereby causing the potential difference between the first bit line BL1 and the plate line PL to decrease, the effective flipping voltage for controlling the flipping of the ferroelectric capacitor FE-Cap to decrease, and the flipping of the ferroelectric capacitor FE-Cap to become slower and insufficient. This phenomenon is the self-inhibition phenomenon of the FeRAM when reading a digital signal 1, which will affect the uniformity and reliability of the ferroelectric circuit, and also reduce the storage window of the ferroelectric circuit.

[0218] FIG. 5a and FIG. 5b respectively show a circuit diagram and a timing diagram of the storage circuit when the first transistor T1 and the second transistor T2 are both P-type transistors, and FIG. 5b shows the timing diagram when the other transistors in the storage circuit are all N-type transistors and the ferroelectric capacitor FE-Cap flips to read the digital signal 1, and the first voltage generating circuit 13 includes an inverter as an example, and the timing diagram corresponds to the potential of the gate of each transistor.

[0219] As shown in FIG. 5a, the storage circuit includes the first ferroelectric storage unit 11, the first current mirror 12, the first voltage generating circuit 13, the comparison circuit 14, and the first voltage terminal Vdd. The first ferroelectric storage unit 11 and the first branch of the first current mirror 12 are electrically connected to the first node A, and the second branch of the first current mirror 12 and the first voltage generating circuit 13 and the comparison circuit 14 are electrically connected to the second node B.

[0220] In the pre-charge phase, the potential of the first node A is an initial voltage, which is high.

[0221] In the read phase, the working process of each module in the storage circuit is as follows:

[0222] The first voltage terminal Vdd is used to input a first voltage to the first current mirror 12, and the first voltage generating circuit 13 is used to input a second voltage to the second node B. Here, the first voltage input by the first voltage terminal Vdd to the first current mirror 12 is high, the second voltage is low, the second voltage is less than the first voltage, and the initial voltage is less than the first voltage.

[0223] When the first ferroelectric storage unit 11 reads data, the first ferroelectric storage unit 11 inputs charges (negative charges) to the first node A (the first bit line BL1), and because the initial voltage is less than the first voltage, the first node A has a potential difference with the first branch, and the first node A extracts charges from the first branch. In this way, the first node A receives the charges input by the first ferroelectric storage unit 11 while also extracting charges from the first branch, so the first node A remains at the initial voltage. That is, the charges input by the first ferroelectric storage unit 11 to the first node A are not accumulated in the first node A.

[0224] Further, according to the working principle of the first current mirror 12, the first branch copies the first current flowing through the first branch to the second branch, and then the second branch changes the potential of the second node B from the second voltage to a third voltage according to the first current, the first voltage input to the first current mirror, and the second voltage of the second node B.

[0225] It should be understood that, in the case that the first transistor T1 is the same as the second transistor T2, the current flowing through the first transistor T1 and the second transistor T2 is the first current, the first voltage terminal Vdd simultaneously inputs a high level to the first transistor T1 and the second transistor T2, and the second voltage of the second node B is less than the first voltage, if the first node A extracts charges from the first branch, the second node B will also extract charges from the second branch, so that the potential of the second node B increases from the second voltage to the third voltage.

[0226] In the reading stage, when the ferroelectric capacitor FE-Cap in the first ferroelectric memory cell 11 occurs polarization flip, the first ferroelectric memory cell 11 outputs a polarization current, and when the ferroelectric capacitor FE-Cap does not occur polarization flip, the first ferroelectric memory cell 11 outputs a dielectric current. The amount of charges input to the first node A when the ferroelectric capacitor FE-Cap occurs polarization flip is greater than the amount of charges input to the first node A when the ferroelectric capacitor FE-Cap does not occur polarization flip, therefore, the amount of charges extracted from the first branch by the first node A when the ferroelectric capacitor FE-Cap occurs polarization flip is greater than the amount of charges extracted from the first branch by the first node A when the ferroelectric capacitor FE-Cap does not occur polarization flip.

[0227] It is known that the amount of charges extracted from the first branch by the first node A when the ferroelectric capacitor FE-Cap occurs polarization flip is greater than the amount of charges extracted from the first branch by the first node A when the ferroelectric capacitor FE-Cap does not occur polarization flip, then, the amount of charges extracted from the second branch by the second node B when the ferroelectric capacitor FE-Cap occurs polarization flip is also greater than the amount of charges extracted from the second branch by the second node B when the ferroelectric capacitor FE-Cap does not occur polarization flip. That is, whether the ferroelectric capacitor FE-Cap occurs polarization flip or not, the third voltage after the second node B extracts charges is not the same.

[0228] Further, the second node B inputs the third voltage to the comparison circuit 14, and the comparison circuit 14 can determine whether the data read out by the first ferroelectric memory cell 11 is a digital signal 0 or a digital signal 1 according to the third voltage.

[0229] In the present application, the data (digital signal 1 or digital signal 0) read by the first ferroelectric memory cell 11 is different due to whether the ferroelectric capacitor FE-Cap undergoes polarization reversal, the amount of charge input to the first node A is different, the first current flowing through the first branch and the second branch is also different, the amount of charge extracted by the first node A from the first branch is different, and the potential difference between the second node B and the second branch is different. Therefore, when the first ferroelectric memory cell 11 reads different data, the second node B can extract charge from the second branch according to the first current, the first voltage, and the second voltage, so that the potential of the second node B increases from the second voltage to the third voltage. It can be seen that the potential of the third voltage on the second node B is related to the data (digital signal 1 or digital signal 0) read by the first ferroelectric memory cell 11. Therefore, the third voltage can be input to the comparison circuit 14 by using the second node B, so that the comparison circuit 14 determines the data read by the first ferroelectric memory cell 11 as digital signal 0 or digital signal 1 according to the third voltage.

[0230] At the same time, whether reading digital signal 1 or digital signal 0, the first bit line BL1 extracts charge from the first branch, so that the potential on the first bit line BL1 remains at the initial voltage. On the one hand, the potential difference between the plate line PL and the first bit line BL1 is stabilized at a fixed value, which does not affect the polarization reversal of the ferroelectric capacitor FE-Cap. On the other hand, the potential difference between the plate line PL and the first bit line BL1 is always at a large value, so that the polarization reversal of the ferroelectric capacitor FE-Cap does not become slower and slower or even insufficient due to the decrease of the potential difference between the plate line PL and the first bit line BL1, thereby avoiding the self-inhibition phenomenon, improving the uniformity and reliability of the storage circuit, and also improving the storage window of the ferroelectric circuit.

[0231] In some possible implementations, the data (digital signal 1 or digital signal 0) read by the first ferroelectric memory cell 11 is different, and the size of the third voltage is related to the data read when the ferroelectric capacitor FE-Cap undergoes polarization reversal.

[0232] For example, assume that the first ferroelectric memory cell 11 is configured to undergo a polarization switching of the ferroelectric capacitor FE-Cap when reading a digital signal of 1, and not to undergo a polarization switching of the ferroelectric capacitor FE-Cap when reading a digital signal of 0. Then, when reading a digital signal of 1, the first ferroelectric memory cell 11 outputs a polarization current, the polarization current flows through the first node A to the first branch, the first branch copies a polarization current of the same size to the second branch, and the second node B extracts a first charge amount from the second branch due to the polarization current, the first voltage, and the second voltage, and the potential of the second node B is greatly increased. When reading a digital signal of 0, the first ferroelectric memory cell 11 outputs a small dielectric current, the dielectric current flows through the first node A to the first branch, the first branch copies a dielectric current of the same size to the second branch, and the second node B extracts a second charge amount from the second branch due to the dielectric current, the first voltage, and the second voltage, and the potential of the second node B is slightly increased. Here, the first charge amount is greater than the second charge amount.

[0233] In this case, the third voltage when the first ferroelectric memory cell 11 reads a digital signal of 1 is greater than the third voltage when the first ferroelectric memory cell 11 reads a digital signal of 0.

[0234] For example, assume that the first ferroelectric memory cell 11 is configured to undergo a polarization switching of the ferroelectric capacitor FE-Cap when reading a digital signal of 0, and not to undergo a polarization switching of the ferroelectric capacitor FE-Cap when reading a digital signal of 1. Then, when reading a digital signal of 0, the first ferroelectric memory cell 11 outputs a polarization current, the polarization current flows through the first node A to the first branch, the first branch copies a polarization current of the same size to the second branch, and the second node B extracts a first charge amount from the second branch due to the polarization current, the first voltage, and the second voltage, and the potential of the second node B is greatly increased. When reading a digital signal of 1, the first ferroelectric memory cell 11 outputs a small dielectric current, the dielectric current flows through the first node A to the first branch, the first branch copies a dielectric current of the same size to the second branch, and the second node B extracts a second charge amount from the second branch due to the dielectric current, the first voltage, and the second voltage, and the potential of the second node B is slightly increased. Here, the first charge amount is greater than the second charge amount.

[0235] In this case, the third voltage when the first ferroelectric memory cell 11 reads a digital signal of 1 is less than the third voltage when the first ferroelectric memory cell 11 reads a digital signal of 0.

[0236] In some embodiments, in the first current mirror 12, since the current input to the first branch is always the same as the current output by the second branch, in order to ensure that the first branch copies the same polarization current or dielectric current to the second branch when the first current mirror 12 is working, the initial current flowing through the first branch should be the same as the initial current flowing through the second branch before the polarization current or dielectric current flows to the first branch. However, the current of the first branch is easily affected by the first node A, and the current of the second branch is easily affected by the second node B, which may cause the initial current of the first branch to be different from the initial current flowing through the second branch.

[0237] Based on this, the storage circuit of the embodiments of the present application further includes a third transistor T3 and a fourth transistor T4, the third transistor T3 is connected in series between the first node A and the first transistor T1 (the first pole of the third transistor T3 is electrically connected with the first node A, and the second pole of the third transistor T3 is electrically connected with the first pole of the first transistor T1), and the fourth transistor T4 is connected in series between the second node B and the second transistor T2 (the first pole of the fourth transistor T4 is electrically connected with the second node B, and the second pole of the fourth transistor T4 is electrically connected with the first pole of the second transistor T2). Moreover, the third transistor T3 and the fourth transistor T4 are also P-type transistors.

[0238] In the reading stage, the third transistor T3 and the fourth transistor T4 are both turned on, the second pole of the third transistor T3 inputs the clamping voltage to the first pole of the first transistor T1, and the second pole of the fourth transistor T4 inputs the clamping voltage to the first pole of the second transistor T2, so that the potential of the connection node C of the third transistor T3 and the first transistor T1, and the potential of the connection node D of the fourth transistor T4 and the second transistor T2 are the same, so as to achieve the same initial current flowing through the first branch and the initial current flowing through the second branch in the case that the first transistor T1 and the second transistor T2 are the same (the resistances of the first transistor T1 and the second transistor T2 are the same).

[0239] In addition, due to the existence of the clamping voltage, after the first current mirror 12 reaches a certain voltage value, the voltage no longer rises. In this way, if the first node A extracts charges from the first branch, the voltage value of the first current mirror 12 is saturated, and at this time, the first node A no longer extracts charges from the first branch, and the first bit line BL1 is still reduced by a small amount, so that the potential on the first bit line BL1 is less than the initial voltage, and the potential difference between the plate line PL and the first bit line BL1 is reduced. Based on this, the storage circuit can also not include the third transistor T3 and the fourth transistor T4.

[0240] Of course, it should be understood that even if the storage circuit includes the third transistor T3 and the fourth transistor T4, the first node A can still draw charges from the first branch, and thus, compared with the prior art, the potential difference between the plate line PL and the first bit line BL1 can still be increased, and the self-inhibition phenomenon can be improved.

[0241] In some embodiments, the first voltage generating circuit 13 includes a second voltage terminal V_boost, which is used to input a voltage to the second node B during the reading stage. However, due to the parasitic capacitance, the voltage value received by the second node B cannot reach the voltage value output by the second voltage terminal V_boost. Therefore, the first voltage generating circuit 13 can further include a tank capacitor TC, which is electrically connected between the second node B and the second voltage terminal V_boost, wherein the second voltage terminal V_boost is electrically connected to a first electrode of the tank capacitor TC, and the second node B is electrically connected to a second electrode of the tank capacitor TC. In this way, the first voltage generating circuit 13 can first input the second voltage to the first electrode, and the first electrode can couple the second voltage to the second electrode and the second node B, so as to improve the problem that the voltage output by the second voltage terminal V_boost is largely taken away by the parasitic capacitance, resulting in that the voltage value received by the second node B cannot reach the voltage value output by the second voltage terminal V_boost.

[0242] In addition, since the first electrode and the second electrode of the tank capacitor TC are isolated by the insulating material therebetween, after the first electrode couples the second voltage to the second electrode and the second node B, even if the second voltage terminal V_boost still provides the second voltage to the first electrode, the potentials of the second electrode and the second node B are no longer affected by the second voltage terminal V_boost and the first electrode. Therefore, after the second node B draws charges from the second branch, the potential on the second node B rises, rather than, like the first node A, remaining at the initial voltage even if charges are drawn from the first branch.

[0243] In some possible implementation manners, as shown in FIG. 8, there is usually a loss problem in the transmission process of the signal. Based on this, the first voltage generating circuit 13 can further include an inverter 131 electrically connected between the second voltage terminal V_boost and the tank capacitor TC, so as to enhance the signal.

[0244] Here, it should be noted that the second voltage required by the second node B is a high level. If the first voltage generating circuit 13 does not include the inverter 131, the voltage output by the second voltage terminal V_boost is also a low level. If the first voltage generating circuit 13 includes the inverter 131, the voltage output by the second voltage terminal V_boost is a high level.

[0245] In some embodiments, as shown in Fig. 8, the storage circuit further comprises a third voltage terminal V3 and a pre-charge circuit 15 electrically connected between the third voltage terminal V3 and the first node A. In a pre-charge phase before the read phase, the third voltage terminal V3 is used to input an initial voltage to the first bit line BL1 through the pre-charge circuit 15, to prepare for the read phase. Further, in the read phase, the potential difference between the control plate line PL and the first bit line BL1 can be controlled by controlling the voltage on the control plate line PL, to control the first ferroelectric storage unit 11 to read data.

[0246] Optionally, the pre-charge circuit 15 comprises a first switch ISO electrically connected between the input end of the first branch and the output end of the second branch, and a second switch PCH electrically connected between the third voltage terminal V3 and the second node B. In the pre-charge phase, the first switch ISO and the second switch PCH are both turned on, and the third voltage terminal V3 inputs the initial voltage to the first bit line BL1 through the second switch PCH and the first switch ISO.

[0247] In some possible implementations, in the pre-charge phase, after pre-charging the first bit line BL1 with the third voltage terminal V3, the second node B can also be pre-charged with the third voltage terminal V3, in which case the second switch PCH is turned on, and the third voltage terminal V3 pre-charges the second node B to a charging voltage through the second switch PCH, the charging voltage being a low level. At the same time, the first switch ISO is turned off, so the charging voltage of the third voltage terminal V3 does not affect the potential on the first bit line BL1.

[0248] In the pre-charge phase, the third voltage terminal V3 inputs the charging voltage to the second node B; in the read phase, the second voltage terminal V_boost inputs the second voltage to the second node B. In this way, before the second node B is extracted by the second branch, the voltage on the second node B is the sum of the charging voltage and the second voltage. The embodiments of the present application input the voltage to the second node B multiple times to ensure that the voltage on the second node B is small enough, thereby increasing the difference between the third voltage of the second node B when reading the digital signal 1 and the third voltage of the second node B when reading the digital signal 0, and increasing the MW of the storage circuit.

[0249] In other embodiments, as mentioned above, the comparison circuit 14 in the prior art reads the digital signal 1 or the digital signal 0 by obtaining the charge on the first bit line BL1, and the first bit line BL1 is usually connected with multiple ferroelectric storage units and has a relatively long length, so the first bit line BL1 inevitably forms a parasitic capacitance Cbl1 with multiple conductive structures in the storage chip, and the parasitic capacitance Cbl1 has a negative impact on the MW of the storage circuit.

[0250] According to the formula charge quantity (Q) = voltage (U) * capacitance (C), the greater the parasitic capacitance Cbl1 on the first bit line BL1, the smaller the voltage U on the first bit line BL1, the greater the potential difference between the plate line PL and the first bit line BL1, and the greater the effective flipping voltage of the ferroelectric capacitor FE-Cap, and the more sufficient the flipping of the ferroelectric capacitor FE-Cap.

[0251] It can be seen that the existence of the parasitic capacitance Cbl1 leads to a trade-off between the MW of the storage circuit and the effective flipping voltage of the ferroelectric capacitor FE-Cap, and therefore is limited in design.

[0252] In the scheme of the present application, the comparison circuit 14 no longer reads the digital signal 1 or the digital signal 0 by obtaining the voltage on the first bit line BL1, but reads the digital signal 1 or the digital signal 0 by obtaining the voltage on the second node B. In this way, even if there is a large parasitic capacitance Cbl1 on the first bit line BL1, it will not have a negative impact on the MW of the storage circuit, and according to the formula charge quantity (Q) = voltage (U) * capacitance (C), the parasitic capacitance Cbl1 on the first bit line BL1 can also increase the effective flipping voltage, so that the ferroelectric capacitor FE-Cap flips more fully.

[0253] On this basis, in the reading stage, the present application embodiment can also disconnect the first switch ISO and the second switch PCH, so that the second node B is isolated (the second node B is isolated from the first node A through the first switch ISO, and the second node B is isolated from the third voltage terminal V3 through the second switch PCH), and therefore the parasitic capacitance of the second node B is very small, and the impact on the MW of the storage circuit is also very small.

[0254] In some embodiments, as shown in FIG. 6, the storage circuit further includes a reference voltage terminal Vref. In the reading stage, the reference voltage terminal Vref can input a reference voltage to the comparison circuit 14, and the comparison circuit 14 determines whether the data read by the first ferroelectric storage unit 11 is a digital signal 0 or a digital signal 1 according to the received third voltage and the reference voltage.

[0255] The comparison circuit 14 of the present application should combine the data read when the polarization flipping of the set ferroelectric capacitor FE-Cap occurs to determine whether the data read by the first ferroelectric storage unit 11 is a digital signal 0 or a digital signal 1 according to the received third voltage and the reference voltage.

[0256] The working principle of the comparison circuit 14 of the present application for reading data will be described in detail below in combination with the circuit structure of the comparison circuit 14.

[0257] As shown in Fig. 6, the comparison circuit 14 comprises a fourth voltage terminal V4, a first P-type transistor P1, a second P-type transistor P2, a first N-type transistor N1, a second N-type transistor N2, a ground terminal Vss1, and an output terminal OUT. In the reading stage, the fourth voltage terminal V4 is high, and the ground terminal Vss1 is low.

[0258] The gate of the first P-type transistor P1 and the gate of the first N-type transistor N1 are electrically connected to the second pole of the second P-type transistor, the first pole of the second N-type transistor, and the reference voltage terminal Vref. The first pole of the first P-type transistor P1 is electrically connected to the fourth voltage terminal V4. The second pole of the first P-type transistor P1 is electrically connected to the first pole of the first N-type transistor N1 and the output terminal OUT. The second pole of the first N-type transistor N1 is electrically connected to the ground terminal Vss1. The gate of the second P-type transistor P2 and the gate of the second N-type transistor N2 are electrically connected to the second node B. The first pole of the second P-type transistor P2 is electrically connected to the fourth voltage terminal V4. The second pole of the second N-type transistor N2 is electrically connected to the ground terminal Vss1. The output terminal OUT is electrically connected between the second node B and the second pole of the first P-type transistor P1 and the first pole of the first N-type transistor N1.

[0259] For example, when the first ferroelectric storage unit 11 is set to read the digital signal 1, the ferroelectric capacitor FE-Cap is polarized to flip. The third voltage when reading the digital signal 1 is greater than the third voltage when reading the digital signal 0.

[0260] In the reading of the digital signal 0, the third voltage of the second node B is low, and the second P-type transistor P2 is turned on. The reference voltage of the reference voltage terminal Vref is greater than the third voltage when the first ferroelectric storage unit 11 reads the digital signal 1, and less than the third voltage when the first ferroelectric storage unit 11 reads the digital signal 0. Therefore, even if the reference voltage terminal Vref is electrically connected to the gate of the first P-type transistor P1 and the gate of the first N-type transistor N1, the degree of conduction of the first P-type transistor P1 and the first N-type transistor N1 is less than the degree of conduction of the second P-type transistor P2. The second P-type transistor P2 can be charged more quickly, and the high level of the fourth voltage terminal V4 is transmitted to the gate of the first N-type transistor N1 and the reference voltage terminal Vref. The reference voltage terminal Vref is pulled high. Further, the first N-type transistor N1 is turned on, the ground terminal Vss1 transmits the low level to the output terminal OUT through the first N-type transistor N1, the output terminal OUT outputs the low level, and it is confirmed that the data read by the first ferroelectric storage unit 11 is the digital signal 0.

[0261] In reading the digital signal 1, the third voltage of the second node B is high, and the second N-type transistor N2 is turned on. The reference voltage of the reference voltage terminal Vref is greater than the third voltage when the first ferroelectric storage unit 11 reads the digital signal 1, and is less than the third voltage when the first ferroelectric storage unit 11 reads the digital signal 0. Therefore, even if the reference voltage terminal Vref is electrically connected to the gate of the first P-type transistor P1 and the gate of the first N-type transistor N1, the turn-on degree of the first P-type transistor P1 and the first N-type transistor N1 is less than the turn-on degree of the second N-type transistor N2. The second N-type transistor N2 can be charged more quickly, and the low level of the ground terminal Vss1 is transmitted to the gate of the first P-type transistor P1 and the reference voltage terminal Vref. The reference voltage terminal Vref is pulled low. Further, the first P-type transistor P1 is turned on, the fourth voltage terminal V4 transmits the high level to the output terminal OUT through the first P-type transistor P1, and the output terminal OUT outputs the high level, confirming that the data read by the first ferroelectric storage unit 11 is the digital signal 1.

[0262] For another example, in setting the first ferroelectric storage unit 11 to polarize and flip the ferroelectric capacitor FE-Cap when reading the digital signal 0, the third voltage when reading the digital signal 0 is greater than the third voltage when reading the digital signal 1.

[0263] In reading the digital signal 1, the third voltage of the second node B is low, and the second P-type transistor P2 is turned on. The reference voltage of the reference voltage terminal Vref is greater than the third voltage when the first ferroelectric storage unit 11 reads the digital signal 0, and is less than the third voltage when the first ferroelectric storage unit 11 reads the digital signal 1. Therefore, even if the reference voltage terminal Vref is electrically connected to the gate of the first P-type transistor P1 and the gate of the first N-type transistor N1, the turn-on degree of the first P-type transistor P1 and the first N-type transistor N1 is less than the turn-on degree of the second P-type transistor P2. The second P-type transistor P2 can be charged more quickly, and the high level of the fourth voltage terminal V4 is transmitted to the gate of the first N-type transistor N1 and the reference voltage terminal Vref. The reference voltage terminal Vref is pulled high. Further, the first N-type transistor N1 is turned on, the ground terminal Vss1 transmits the low level to the output terminal OUT through the first N-type transistor N1, and the output terminal OUT outputs the low level, confirming that the data read by the first ferroelectric storage unit 11 is the digital signal 1.

[0264] When reading the digital signal 0, the third voltage of the second node B is high, and the second N-type transistor N2 is turned on. The reference voltage of the reference voltage terminal Vref is greater than the third voltage when the first ferroelectric storage unit 11 reads the digital signal 0, and is less than the third voltage when the first ferroelectric storage unit 11 reads the digital signal 1. Therefore, even if the reference voltage terminal Vref is electrically connected with the gate of the first P-type transistor P1 and the gate of the first N-type transistor N1, the turning-on degree of the first P-type transistor P1 and the first N-type transistor N1 is less than the turning-on degree of the second N-type transistor N2, the second N-type transistor N2 can be charged more quickly, and the low level of the ground terminal Vss1 is transmitted to the gate of the first P-type transistor P1 and the reference voltage terminal Vref, and the reference voltage terminal Vref is pulled low. Further, the first P-type transistor P1 is turned on, the fourth voltage terminal V4 transmits the high level to the output terminal OUT through the first P-type transistor P1, and the output terminal OUT outputs the high level, confirming that the data read by the first ferroelectric storage unit 11 is the digital signal 0.

[0265] In some embodiments, after the reading stage, the first ferroelectric storage unit can also be subjected to a reverse writing operation, and the storage circuit further comprises a third switch WR electrically connected between the reference voltage terminal and the first node. In the reading stage, the third switch WR is open; in the reverse writing stage, the third switch WR is turned on, for inputting the writing signal of the reference voltage terminal Vref to the first ferroelectric storage unit 11 through the first node A.

[0266] Taking the case of setting the first ferroelectric storage unit 11 to read the digital signal 1, and the ferroelectric capacitor is polarized to flip as an example, when reading the digital signal 1, the reference voltage terminal Vref is low; in the reverse writing stage, the reference voltage terminal Vref inputs the low level to the first bit line BL1 through the third switch WR, and then inputs the high level to the plate line PL, so that the first bit line BL1 and the plate line PL form a potential difference at both ends of the first ferroelectric storage unit 11, and the reverse writing of the digital signal 1 is completed. When reading the digital signal 0, the reference voltage terminal Vref is high; in the reverse writing stage, the reference voltage terminal Vref inputs the high level to the first bit line BL1 through the third switch WR, and then inputs the low level to the plate line PL, so that the first bit line BL1 and the plate line PL form a potential difference at both ends of the first ferroelectric storage unit 11, and the reverse writing of the digital signal 0 is completed.

[0267] For example, in the case of reading a digital signal 0 from the first ferroelectric memory cell 11, the reference voltage terminal Vref is at a low level. In the write-back stage, the reference voltage terminal Vref inputs a low level to the first bit line BL1 through the third switch WR, and inputs a high level to the plate line PL. A potential difference is formed between the first bit line BL1 and the plate line PL at both ends of the first ferroelectric memory cell 11, and the write-back of the digital signal 0 is completed. In the case of reading a digital signal 1 from the first ferroelectric memory cell 11, the reference voltage terminal Vref is at a high level. In the write-back stage, the reference voltage terminal Vref inputs a high level to the first bit line BL1 through the third switch WR, and inputs a low level to the plate line PL. A potential difference is formed between the first bit line BL1 and the plate line PL at both ends of the first ferroelectric memory cell 11, and the write-back of the digital signal 1 is completed.

[0268] In addition, in the case where the first transistor T1 and the second transistor T2 are both P-type transistors, the storage chip can also include a reference voltage generating circuit 16 for providing a reference voltage to the comparison circuit 14. The circuit connection and working principle of the reference voltage generating circuit 16 are the same as those in the previous embodiment where the first transistor T1 and the second transistor T2 are both N-type transistors, and will not be described here again.

[0269] In other embodiments, if the first ferroelectric memory cell 11 reads a digital signal 1 in the read stage, and a digital signal 0 needs to be written into the first ferroelectric memory cell 11 in the write stage, the first ferroelectric memory cell 11 can be rewritten instead of write-back. Alternatively, if the first ferroelectric memory cell 11 reads a digital signal 0 in the read stage, and a digital signal 1 needs to be written into the first ferroelectric memory cell 11 in the write stage, the first ferroelectric memory cell 11 can be rewritten instead of write-back.

[0270] In this case, the signal is no longer write-back to the first ferroelectric memory cell 11 through the reference voltage terminal Vref, but the output terminal OUT of the storage circuit is multiplexed as the input terminal of the storage circuit (or the comparison circuit), and the signal is rewritten to the first ferroelectric memory cell 11 through the input terminal of the storage circuit.

[0271] In another embodiment, the present application also provides a control method of a storage circuit, as shown in FIGS. 4a-4b, 6, 7a-7b. The circuit structure of the storage circuit is the same as that in the previous embodiment, and will not be described here again. In this embodiment, the first transistor T1 and the second transistor T2 are both N-type transistors.

[0272] In the pre-charge phase, the second switch PCH and the first switch ISO are turned on, and the third voltage terminal V3 inputs an initial voltage of 0V to the first bit line BL1 through the second switch PCH and the first switch ISO, so as to prepare for the read phase. The initial voltage is a low level, for example, the initial voltage is 0V. Then, the second switch PCH is turned on, and the first switch ISO is turned off. The third voltage terminal V3 can also be used to pre-charge the second node B.

[0273] In the read phase, the first transistor T1 of the first branch and the second transistor T2 of the second branch in the first current mirror 12 are both turned on, and the third transistor T3 and the fourth transistor T4 are also turned on in the case that the storage circuit includes the third transistor T3 and the fourth transistor T4.

[0274] In addition, the first voltage terminal Vss1 inputs a first voltage to the first current mirror 12, and the first voltage generating circuit 13 inputs a second voltage to the second node B. Here, the first voltage terminal Vss1 is a ground terminal, and the first voltage input to the first current mirror 12 is a low level; the second voltage is a high level, and the second voltage is greater than the first voltage.

[0275] When the first ferroelectric storage unit 11 reads data, the first ferroelectric storage unit 11 inputs charges (positive charges) to the first node A (the first bit line BL1), and since the initial voltage is greater than the first voltage, a potential difference is generated between the first node A and the first branch, and the first branch extracts charges from the first node A. In this way, the first node A receives the charges input by the first ferroelectric storage unit 11, and at the same time, the first node A is also extracted by the first branch, so that the first node A is kept at the initial voltage. That is, the charges input by the first ferroelectric storage unit 11 to the first node A are not accumulated in the first node A.

[0276] Here, in the read phase, when the ferroelectric capacitor FE-Cap in the first ferroelectric storage unit 11 undergoes a polarization flip, the first ferroelectric storage unit 11 outputs a polarization current, and when the ferroelectric capacitor FE-Cap does not undergo a polarization flip, the first ferroelectric storage unit 11 outputs a dielectric current. The amount of charges input to the first node A when the ferroelectric capacitor FE-Cap undergoes a polarization flip is greater than the amount of charges input to the first node A when the ferroelectric capacitor FE-Cap does not undergo a polarization flip, so that the amount of charges extracted from the first node A by the first branch when the ferroelectric capacitor FE-Cap undergoes a polarization flip is greater than the amount of charges extracted from the first node A by the first branch when the ferroelectric capacitor FE-Cap does not undergo a polarization flip.

[0277] Further, according to the working principle of the first current mirror 12, the first branch copies the first current flowing through the first branch to the second branch, and then the second branch changes the potential of the second node B from the second voltage to the third voltage according to the first current, the first voltage input to the first current mirror, and the second voltage of the second node B.

[0278] It should be understood that, in the case that the first transistor T1 is the same as the second transistor T2, the current flowing through the first transistor T1 and the second transistor T2 is the first current, the first voltage terminal Vss1 simultaneously inputs a low level to the first transistor T1 and the second transistor T2, and the second voltage of the second node B is greater than the first voltage, if the first branch extracts charges from the first node A, the second branch will also extract charges from the second node B, so that the potential of the second node B decreases from the second voltage to the third voltage.

[0279] It is known that, when the ferroelectric capacitor FE-Cap occurs polarization reversal, the amount of charges extracted from the first node A by the first branch is greater than the amount of charges extracted from the first node A by the first branch when the ferroelectric capacitor FE-Cap does not occur polarization reversal, and then the amount of charges extracted from the second node B by the second branch when the ferroelectric capacitor FE-Cap occurs polarization reversal is also greater than the amount of charges extracted from the second node B by the second branch when the ferroelectric capacitor FE-Cap does not occur polarization reversal. That is, whether the ferroelectric capacitor FE-Cap occurs polarization reversal or not, the third voltage remaining after the second node B is extracted by charges is not the same.

[0280] Further, the second node B inputs the remaining third voltage to the comparison circuit 14, and the comparison circuit 14 can determine whether the data read by the first ferroelectric memory cell 11 is a digital signal 0 or a digital signal 1 according to the third voltage.

[0281] In this application, because the data (digital signal 1 or digital signal 0) read by the first ferroelectric memory cell 11 is different when the ferroelectric capacitor FE-Cap occurs polarization reversal or not, the amount of charges input to the first node A is different, the first current flowing through the first branch and the second branch is different, the amount of charges extracted from the first node A by the first branch is different, and the potential difference between the second node B and the second branch is different. Therefore, when the first ferroelectric memory cell 11 reads different data, the second branch can extract charges from the second node B according to the first current, the first voltage, and the second voltage, so that the potential of the second node B decreases from the second voltage to the third voltage. It can be seen that the remaining potential third voltage on the second node B is related to the data (digital signal 1 or digital signal 0) read by the first ferroelectric memory cell 11, and therefore the third voltage can be input to the comparison circuit 14 by using the second node B, so that the comparison circuit 14 can determine whether the data read by the first ferroelectric memory cell 11 is a digital signal 0 or a digital signal 1 according to the third voltage.

[0282] Meanwhile, no matter reading digital signal 1 or digital signal 0, the charge on the first bit line BL1 is extracted by the first branch, so that the potential on the first bit line BL1 is kept at 0V (or close to 0V), on the one hand, the potential difference between the plate line PL and the first bit line BL1 is stabilized at a fixed value, which does not affect the polarization reversal of the ferroelectric capacitor FE-Cap; on the other hand, the potential difference between the plate line PL and the first bit line BL1 is always at a large value, and then the polarization reversal of the ferroelectric capacitor FE-Cap will not become slower and slower, or even insufficient, resulting in self-inhibition phenomenon, which improves the uniformity and reliability of the storage circuit, and also improves the storage window of the ferroelectric circuit.

[0283] In some possible implementations, the third voltage read by the first ferroelectric storage unit 11 is different when reading digital signal 1 or digital signal 0, and the size of the third voltage is related to the data read when the polarization reversal of the ferroelectric capacitor FE-Cap occurs.

[0284] For example, it is set that the polarization reversal of the ferroelectric capacitor FE-Cap occurs when the first ferroelectric storage unit 11 reads digital signal 1, and the polarization reversal of the ferroelectric capacitor does not occur when the first ferroelectric storage unit 11 reads digital signal 0. Then, when the first ferroelectric storage unit 11 reads digital signal 1, the first ferroelectric storage unit 11 will output a polarization current, and the polarization current flows to the first branch through the first node A, the first branch copies a polarization current with the same size to the second branch, and the second branch extracts a first charge amount from the second node B under the influence of the polarization current, the first voltage and the second voltage, and the potential of the second node B will be greatly reduced. When the first ferroelectric storage unit 11 reads digital signal 0, the first ferroelectric storage unit 11 will output a small amount of dielectric current, and the dielectric current flows to the first branch through the first node A, the first branch copies a dielectric current with the same size to the second branch, and the second branch extracts a second charge amount from the second node B under the influence of the dielectric current, the first voltage and the second voltage, and the potential of the second node B will be slightly reduced. Wherein, the first charge amount is greater than the second charge amount.

[0285] In this case, the third voltage when the first ferroelectric storage unit 11 reads digital signal 1 is less than the third voltage when the first ferroelectric storage unit 11 reads digital signal 0.

[0286] For example, if the first ferroelectric memory cell 11 is configured to read a digital signal 0, the ferroelectric capacitor FE-Cap is configured to flip; if the first ferroelectric memory cell 11 is configured to read a digital signal 1, the ferroelectric capacitor FE-Cap is not configured to flip. When the first ferroelectric memory cell 11 reads a digital signal 0, the first ferroelectric memory cell 11 outputs a polarization current, the polarization current flows through the first node A to the first branch, the first branch copies a polarization current of the same size to the second branch, and the second branch extracts a first charge from the second node B under the influence of the polarization current, the first voltage and the second voltage, and the potential of the second node B is greatly reduced. When the first ferroelectric memory cell 11 reads a digital signal 1, the first ferroelectric memory cell 11 outputs a small amount of dielectric current, the dielectric current flows through the first node A to the first branch, the first branch copies a dielectric current of the same size to the second branch, and the second branch extracts a second charge from the second node B under the influence of the dielectric current, the first voltage and the second voltage, and the potential of the second node B is slightly reduced. The first charge is greater than the second charge.

[0287] In this case, the third voltage when the first ferroelectric memory cell 11 reads a digital signal 1 is greater than the third voltage when the first ferroelectric memory cell 11 reads a digital signal 0.

[0288] Then, in the reading stage, the reference voltage terminal Vref can input a reference voltage to the comparison circuit 14, and the comparison circuit 14 determines whether the data read by the first ferroelectric memory cell 11 is a digital signal 0 or a digital signal 1 according to the received third voltage and the reference voltage.

[0289] In contrast to the prior art, if the first ferroelectric memory cell 11 is configured to read a digital signal 1, the ferroelectric capacitor FE-Cap is configured to flip, the third voltage when the prior art reads a digital signal 1 is greater than the third voltage when the prior art reads a digital signal 0; and the third voltage when the present application reads a digital signal 1 is less than the third voltage when the present application reads a digital signal 0. If the first ferroelectric memory cell 11 is configured to read a digital signal 0, the ferroelectric capacitor FE-Cap is configured to flip, the third voltage when the prior art reads a digital signal 0 is greater than the third voltage when the prior art reads a digital signal 1; and the third voltage when the present application reads a digital signal 0 is less than the third voltage when the present application reads a digital signal 1.

[0290] Therefore, the comparison circuit 14 of the present application should determine whether the data read by the first ferroelectric memory cell 11 is a digital signal 0 or a digital signal 1 according to the received third voltage and the reference voltage in combination with the data read when the ferroelectric capacitor FE-Cap is configured to flip.

[0291] The working principle of the comparison circuit 14 of the present application for reading data will be described in detail below in combination with the circuit structure of the comparison circuit 14.

[0292] As shown in Fig. 6, the comparison circuit 14 comprises a fourth voltage terminal V4, a first P-type transistor P1, a second P-type transistor P2, a first N-type transistor N1, a second N-type transistor N2, a ground terminal Vss2, and an output terminal OUT. In the reading stage, the fourth voltage terminal V4 is high, and the ground terminal Vss2 is low.

[0293] The gate of the first P-type transistor P1 and the gate of the first N-type transistor N1 are electrically connected to the second pole of the second P-type transistor, the first pole of the second N-type transistor, and the reference voltage terminal Vref. The first pole of the first P-type transistor P1 is electrically connected to the fourth voltage terminal V4. The second pole of the first P-type transistor P1 is electrically connected to the first pole of the first N-type transistor N1 and the output terminal OUT. The second pole of the first N-type transistor N1 is electrically connected to the ground terminal Vss2. The gate of the second P-type transistor P2 and the gate of the second N-type transistor N2 are electrically connected to the second node B. The first pole of the second P-type transistor P2 is electrically connected to the fourth voltage terminal V4. The second pole of the second N-type transistor N2 is electrically connected to the ground terminal Vss2. The output terminal OUT is electrically connected between the second node B and the second pole of the first P-type transistor P1 and the first pole of the first N-type transistor N1.

[0294] For example, when the first ferroelectric memory cell 11 is set to read the digital signal 1, the ferroelectric capacitor FE-Cap is polarized to flip. The third voltage when reading the digital signal 1 is less than the third voltage when reading the digital signal 0.

[0295] In the reading of the digital signal 1, the third voltage of the second node B is low, and the second P-type transistor P2 is turned on. The reference voltage of the reference voltage terminal Vref is greater than the third voltage when the first ferroelectric memory cell 11 reads the digital signal 1, and less than the third voltage when the first ferroelectric memory cell 11 reads the digital signal 0. Therefore, even if the reference voltage terminal Vref is electrically connected to the gate of the first P-type transistor P1 and the gate of the first N-type transistor N1, the degree of conduction of the first P-type transistor P1 and the first N-type transistor N1 is less than that of the second P-type transistor P2. The second P-type transistor P2 can be charged more quickly, and the high level of the fourth voltage terminal V4 is transmitted to the gate of the first N-type transistor N1 and the reference voltage terminal Vref, and the reference voltage terminal Vref is pulled high. Further, the first N-type transistor N1 is turned on, the ground terminal Vss2 transmits the low level to the output terminal OUT through the first N-type transistor N1, the output terminal OUT outputs the low level, and it is confirmed that the data read by the first ferroelectric memory cell 11 is the digital signal 1.

[0296] When reading the digital signal 0, the third voltage of the second node B is high, and the second N-type transistor N2 is turned on. The reference voltage of the reference voltage terminal Vref is greater than the third voltage when the first ferroelectric storage unit 11 reads the digital signal 1, and is less than the third voltage when the first ferroelectric storage unit 11 reads the digital signal 0. Therefore, even if the reference voltage terminal Vref is electrically connected to the gate of the first P-type transistor P1 and the gate of the first N-type transistor N1, the turn-on degree of the first P-type transistor P1 and the first N-type transistor N1 is less than the turn-on degree of the second N-type transistor N2. The second N-type transistor N2 can be charged more quickly, and the low level of the ground terminal Vss2 is transmitted to the gate of the first P-type transistor P1 and the reference voltage terminal Vref. The reference voltage terminal Vref is pulled low. Further, the first P-type transistor P1 is turned on, the fourth voltage terminal V4 transmits the high level to the output terminal OUT through the first P-type transistor P1, and the output terminal OUT outputs the high level, confirming that the data read by the first ferroelectric storage unit 11 is the digital signal 0.

[0297] For another example, when the first ferroelectric storage unit 11 is set to read the digital signal 0, the ferroelectric capacitor FE-Cap is polarized to flip. The third voltage when reading the digital signal 0 is less than the third voltage when reading the digital signal 1.

[0298] When reading the digital signal 0, the third voltage of the second node B is low, and the second P-type transistor P2 is turned on. The reference voltage of the reference voltage terminal Vref is greater than the third voltage when the first ferroelectric storage unit 11 reads the digital signal 0, and is less than the third voltage when the first ferroelectric storage unit 11 reads the digital signal 1. Therefore, even if the reference voltage terminal Vref is electrically connected to the gate of the first P-type transistor P1 and the gate of the first N-type transistor N1, the turn-on degree of the first P-type transistor P1 and the first N-type transistor N1 is less than the turn-on degree of the second P-type transistor P2. The second P-type transistor P2 can be charged more quickly, and the high level of the fourth voltage terminal V4 is transmitted to the gate of the first N-type transistor N1 and the reference voltage terminal Vref. The reference voltage terminal Vref is pulled high. Further, the first N-type transistor N1 is turned on, the ground terminal Vss2 transmits the low level to the output terminal OUT through the first N-type transistor N1, and the output terminal OUT outputs the low level, confirming that the data read by the first ferroelectric storage unit 11 is the digital signal 0.

[0299] When reading the digital signal 1, the third voltage of the second node B is high, and the second N-type transistor N2 is turned on. The reference voltage of the reference voltage terminal Vref is greater than the third voltage when the first ferroelectric storage unit 11 reads the digital signal 0, and is less than the third voltage when the first ferroelectric storage unit 11 reads the digital signal 1. Therefore, even if the reference voltage terminal Vref is electrically connected with the gate of the first P-type transistor P1 and the gate of the first N-type transistor N1, the turning-on degree of the first P-type transistor P1 and the first N-type transistor N1 is less than the turning-on degree of the second N-type transistor N2, the second N-type transistor N2 can be charged more quickly, and the low level of the ground terminal Vss2 is transmitted to the gate of the first P-type transistor P1 and the reference voltage terminal Vref, and the reference voltage terminal Vref is pulled low. Further, the first P-type transistor P1 is turned on, the fourth voltage terminal V4 transmits the high level to the output terminal OUT through the first P-type transistor P1, and the output terminal OUT outputs the high level, confirming that the data read by the first ferroelectric storage unit 11 is the digital signal 1.

[0300] In the anti-writing phase, the third switch WR is turned on, and the writing signal of the reference voltage terminal Vref is input to the first ferroelectric storage unit 11 through the first node A.

[0301] Taking the case that the first ferroelectric storage unit 11 is set to read the digital signal 1 and the ferroelectric capacitor is polarized to flip as an example, when reading the digital signal 1, the reference voltage terminal Vref is high; in the anti-writing phase, the reference voltage terminal Vref inputs the high level to the first ferroelectric storage unit 11 through the third switch WR, and the anti-writing of the digital signal 1 is completed. When reading the digital signal 0, the reference voltage terminal Vref is low; in the anti-writing phase, the reference voltage terminal Vref inputs the low level to the first ferroelectric storage unit 11 through the third switch WR, and the anti-writing of the digital signal 0 is completed.

[0302] Taking the case that the first ferroelectric storage unit 11 is set to read the digital signal 0 and the ferroelectric capacitor is polarized to flip as an example, when reading the digital signal 0, the reference voltage terminal Vref is high; in the anti-writing phase, the reference voltage terminal Vref inputs the high level to the first ferroelectric storage unit 11 through the third switch WR, and the anti-writing of the digital signal 0 is completed. When reading the digital signal 1, the reference voltage terminal Vref is low; in the anti-writing phase, the reference voltage terminal Vref inputs the low level to the first ferroelectric storage unit 11 through the third switch WR, and the anti-writing of the digital signal 1 is completed.

[0303] In addition, other explanations and benefits of the embodiments of the present application are the same as the explanations and benefits of the initial voltage being low in the previous embodiment, and will not be repeated here.

[0304] In other embodiments, if the first ferroelectric memory cell 11 reads a digital signal 1 in the reading stage, and a digital signal 0 needs to be written into the first ferroelectric memory cell 11 in the writing stage, the first ferroelectric memory cell 11 can be rewritten instead of being inverted. Or, if the first ferroelectric memory cell 11 reads a digital signal 0 in the reading stage, and a digital signal 1 needs to be written into the first ferroelectric memory cell 11 in the writing stage, the first ferroelectric memory cell 11 can be rewritten instead of being inverted.

[0305] In this case, instead of inverting the signal of the first ferroelectric memory cell 11 by the reference voltage terminal Vref, the output terminal OUT of the storage circuit is multiplexed as the input terminal of the storage circuit (or the comparison circuit), and the input terminal of the storage circuit is used to rewrite the signal of the first ferroelectric memory cell 11.

[0306] The foregoing describes the working principle of the storage circuit when the initial voltage of the first node A (the first bit line BL1) is low, and the first transistor T1 and the second transistor T2 are both N-type transistors. In the following, the working principle of the storage circuit when the initial voltage of the first node A (the first bit line BL1) is low, and the first transistor T1 and the second transistor T2 are both P-type transistors will be described with reference to the accompanying drawings. Different from when the first transistor T1 and the second transistor T2 are both N-type transistors, when the first transistor T1 and the second transistor T2 are both P-type transistors, the first node A (the first bit line BL1) is high in the pre-charging stage and the reading stage, and the plate line PL connected to the other end of the first ferroelectric memory cell 11 is low (for example, 0V). In the reading stage, the first ferroelectric memory cell 11 inputs a reading signal to the first node A (the first bit line BL1), so that the voltage of the first node A (the first bit line BL1) decreases instead of increasing, thereby causing the potential difference between the first bit line BL1 and the plate line PL to decrease, the effective flipping voltage for controlling the ferroelectric capacitor FE-Cap to flip to decrease, and the ferroelectric capacitor FE-Cap to flip more and more slowly and insufficiently. This phenomenon is the self-inhibition phenomenon of the FeRAM reading a digital signal 1, which will affect the uniformity and reliability of the ferroelectric circuit, and also reduce the storage window of the ferroelectric circuit.

[0307] As shown in FIGS. 5a-5b and 8, the circuit structure of the storage circuit is the same as that of the storage circuit in the previous embodiment, which will not be described again. Among them, the first transistor T1 and the second transistor T2 are both P-type transistors.

[0308] In the pre-charge phase, the second switch PCH and the first switch ISO are turned on, and the third voltage terminal V3 inputs an initial voltage to the first bit line BL1 through the second switch PCH and the first switch ISO, so as to prepare for the read phase. Then, the second switch PCH is turned on, and the first switch ISO is turned off. The third voltage terminal V3 can also be used to pre-charge the second node B.

[0309] In the read phase, the first transistor T1 of the first branch and the second transistor T2 of the second branch in the first current mirror 12 are both turned on. In the case where the storage circuit includes the third transistor T3 and the fourth transistor T4, the third transistor T3 and the fourth transistor T4 are also turned on.

[0310] Further, the first voltage terminal Vdd inputs a first voltage to the first current mirror 12, and the first voltage generating circuit 13 is used to input a second voltage to the second node B. Here, the first voltage input by the first voltage terminal Vdd to the first current mirror 12 is a high level; the second voltage is a low level, and the second voltage is smaller than the first voltage.

[0311] When the first ferroelectric storage unit 11 reads data, the first ferroelectric storage unit 11 inputs charges (negative charges) to the first node A (the first bit line BL1). Since the initial voltage is smaller than the first voltage, there is a potential difference between the first node A and the first branch, and the first node A extracts charges from the first branch. In this way, the first node A receives the charges input by the first ferroelectric storage unit 11, and also extracts charges from the first branch, so the first node A is maintained at the initial voltage. That is, the charges input by the first ferroelectric storage unit 11 to the first node A are not accumulated in the first node A.

[0312] Here, in the read phase, when the ferroelectric capacitor FE-Cap in the first ferroelectric storage unit 11 undergoes a polarization reversal, the first ferroelectric storage unit 11 outputs a polarization current, and when the ferroelectric capacitor FE-Cap does not undergo a polarization reversal, the first ferroelectric storage unit 11 outputs a dielectric current. The amount of charges input to the first node A when the ferroelectric capacitor FE-Cap undergoes a polarization reversal is greater than the amount of charges input to the first node A when the ferroelectric capacitor FE-Cap does not undergo a polarization reversal. Therefore, the amount of charges extracted from the first branch by the first node A when the ferroelectric capacitor FE-Cap undergoes a polarization reversal is greater than the amount of charges extracted from the first branch by the first node A when the ferroelectric capacitor FE-Cap does not undergo a polarization reversal.

[0313] Further, according to the working principle of the first current mirror 12, the first branch copies the first current flowing through the first branch to the second branch. Then, the second branch changes the potential of the second node B from the second voltage to the third voltage according to the first current, the first voltage input to the first current mirror, and the second voltage of the second node B.

[0314] It should be understood that, in the case that the first transistor T1 is the same as the second transistor T2, the current flowing through the first transistor T1 and the second transistor T2 is the first current, the first voltage terminal Vdd simultaneously inputs a high level to the first transistor T1 and the second transistor T2, and the second voltage of the second node B is less than the first voltage, if the first node A extracts charges from the first branch, the second node B will also extract charges from the second branch, so that the potential of the second node B increases from the second voltage to the third voltage.

[0315] It is known that the amount of charges extracted from the first branch by the first node A when the ferroelectric capacitor FE-Cap occurs polarization reversal is greater than the amount of charges extracted from the first branch by the first node A when the ferroelectric capacitor FE-Cap does not occur polarization reversal, and then the amount of charges extracted from the second branch by the second node B when the ferroelectric capacitor FE-Cap occurs polarization reversal is also greater than the amount of charges extracted from the second branch by the second node B when the ferroelectric capacitor FE-Cap does not occur polarization reversal. That is, whether the ferroelectric capacitor FE-Cap occurs polarization reversal or not, the third voltage after the second node B extracts charges is not the same.

[0316] Further, the second node B inputs the third voltage to the comparison circuit 14, and the comparison circuit 14 can determine that the data read by the first ferroelectric memory cell 11 is the digital signal 0 or the digital signal 1 according to the third voltage.

[0317] In the present application, because the data (the digital signal 1 or the digital signal 0) read by the first ferroelectric memory cell 11 is different when the ferroelectric capacitor FE-Cap occurs polarization reversal or not, the amount of charges input to the first node A is different, the first current flowing through the first branch and the second branch is also different, the amount of charges extracted from the first branch by the first node A is different, and the potential difference between the second node B and the second branch is different. Therefore, when the first ferroelectric memory cell 11 reads different data, the second node B can extract charges from the second branch according to the first current, the first voltage and the second voltage, so that the potential of the second node B increases from the second voltage to the third voltage. It can be seen that the potential of the second node B, i.e. the third voltage, is related to the data (the digital signal 1 or the digital signal 0) read by the first ferroelectric memory cell 11, and therefore, the third voltage can be input to the comparison circuit 14 by using the second node B, so that the comparison circuit 14 can determine that the data read by the first ferroelectric memory cell 11 is the digital signal 0 or the digital signal 1 according to the third voltage.

[0318] Meanwhile, no matter reading digital signal 1 or digital signal 0, the first bit line BL1 extracts charges from the first branch, so that the potential on the first bit line BL1 is kept at the initial voltage. On the one hand, the potential difference between the plate line PL and the first bit line BL1 is stabilized at a fixed value, which does not affect the polarization reversal of the ferroelectric capacitor FE-Cap; on the other hand, the potential difference between the plate line PL and the first bit line BL1 is always at a large value, so that the polarization reversal of the ferroelectric capacitor FE-Cap does not become slower and slower, or even insufficient, thus the self-inhibition phenomenon occurs, the uniformity and reliability of the storage circuit are improved, and the storage window of the ferroelectric circuit is also improved.

[0319] In some possible implementations, the third voltage read by the first ferroelectric storage unit 11 is different when reading digital signal 1 or digital signal 0, and the size of the third voltage is related to the data read when the polarization reversal of the ferroelectric capacitor FE-Cap occurs.

[0320] For example, it is set that the polarization reversal of the ferroelectric capacitor FE-Cap occurs when the first ferroelectric storage unit 11 reads digital signal 1, and the polarization reversal of the ferroelectric capacitor FE-Cap does not occur when the first ferroelectric storage unit 11 reads digital signal 0. Then, when the first ferroelectric storage unit 11 reads digital signal 1, the first ferroelectric storage unit 11 will output a polarization current, and the polarization current flows to the first branch through the first node A, and the first branch copies a polarization current with the same size to the second branch. Influenced by the polarization current, the first voltage and the second voltage, the second node B extracts a first charge amount from the second branch, and the potential of the second node B is greatly increased. When the first ferroelectric storage unit 11 reads digital signal 0, the first ferroelectric storage unit 11 will output a small amount of dielectric current, and the dielectric current flows to the first branch through the first node A, and the first branch copies a dielectric current with the same size to the second branch. Influenced by the dielectric current, the first voltage and the second voltage, the second node B extracts a second charge amount from the second branch, and the potential of the second node B is slightly increased. Wherein, the first charge amount is greater than the second charge amount.

[0321] In this case, the third voltage when the first ferroelectric storage unit 11 reads digital signal 1 is greater than the third voltage when the first ferroelectric storage unit 11 reads digital signal 0.

[0322] For example, the first ferroelectric memory cell 11 is set to read a digital signal 0, and the ferroelectric capacitor FE-Cap is polarized to flip. The first ferroelectric memory cell 11 is set to read a digital signal 1, and the ferroelectric capacitor FE-Cap is not polarized to flip. When the first ferroelectric memory cell 11 reads a digital signal 0, the first ferroelectric memory cell 11 outputs a polarization current, which flows through the first node A to the first branch. The first branch copies a polarization current of the same size to the second branch. The second node B extracts a first charge quantity from the second branch under the influence of the polarization current, the first voltage and the second voltage. The potential of the second node B is greatly increased. When the first ferroelectric memory cell 11 reads a digital signal 1, the first ferroelectric memory cell 11 outputs a small amount of dielectric current, which flows through the first node A to the first branch. The first branch copies a dielectric current of the same size to the second branch. The second node B extracts a second charge quantity from the second branch under the influence of the dielectric current, the first voltage and the second voltage. The potential of the second node B is slightly increased. The first charge quantity is greater than the second charge quantity.

[0323] In this case, the third voltage when the first ferroelectric memory cell 11 reads a digital signal 1 is less than the third voltage when the first ferroelectric memory cell 11 reads a digital signal 0.

[0324] Then, in the read stage, the reference voltage terminal Vref can input a reference voltage to the comparison circuit 14. The comparison circuit 14 determines whether the data read by the first ferroelectric memory cell 11 is a digital signal 0 or a digital signal 1 according to the received third voltage and the reference voltage.

[0325] The comparison circuit 14 of the present application should be combined with the data read when the ferroelectric capacitor FE-Cap is set to flip polarization. The comparison circuit 14 determines whether the data read by the first ferroelectric memory cell 11 is a digital signal 0 or a digital signal 1 according to the received third voltage and the reference voltage.

[0326] The working principle of the comparison circuit 14 of the present application for reading data will be described in detail below in combination with the circuit structure of the comparison circuit 14.

[0327] As shown in FIG. 6, the comparison circuit 14 includes a fourth voltage terminal V4, a first P-type transistor P1, a second P-type transistor P2, a first N-type transistor N1, a second N-type transistor N2, a ground terminal Vss1, and an output terminal OUT. In the read stage, the fourth voltage terminal V4 is high, and the ground terminal Vss1 is low.

[0328] The gate of the first P-type transistor P1 and the gate of the first N-type transistor N1 are electrically connected with the second pole of the second P-type transistor, the first pole of the second N-type transistor, and the reference voltage terminal Vref. The first pole of the first P-type transistor P1 is electrically connected with the fourth voltage terminal V4. The second pole of the first P-type transistor P1 is electrically connected with the first pole of the first N-type transistor N1 and the output terminal OUT. The second pole of the first N-type transistor N1 is electrically connected with the ground terminal Vss1. The gate of the second P-type transistor P2 and the gate of the second N-type transistor N2 are electrically connected with the second node B. The first pole of the second P-type transistor P2 is electrically connected with the fourth voltage terminal V4. The second pole of the second N-type transistor N2 is electrically connected with the ground terminal Vss1. The output terminal OUT is electrically connected between the second node B and the second pole of the first P-type transistor P1 and the first pole of the first N-type transistor N1.

[0329] For example, when the first ferroelectric storage unit 11 is set to read the digital signal 1, the ferroelectric capacitor FE-Cap is polarized to flip, and the third voltage when reading the digital signal 1 is greater than the third voltage when reading the digital signal 0.

[0330] When reading the digital signal 0, the third voltage of the second node B is low, and the second P-type transistor P2 is turned on. The reference voltage of the reference voltage terminal Vref is greater than the third voltage when the first ferroelectric storage unit 11 reads the digital signal 1, and less than the third voltage when the first ferroelectric storage unit 11 reads the digital signal 0. Therefore, even if the reference voltage terminal Vref is electrically connected with the gate of the first P-type transistor P1 and the gate of the first N-type transistor N1, the degree of conduction of the first P-type transistor P1 and the first N-type transistor N1 is less than the degree of conduction of the second P-type transistor P2. The second P-type transistor P2 can be charged more quickly, and the high level of the fourth voltage terminal V4 is transmitted to the gate of the first N-type transistor N1 and the reference voltage terminal Vref, and the reference voltage terminal Vref is pulled high. Further, the first N-type transistor N1 is turned on, the ground terminal Vss1 transmits the low level to the output terminal OUT through the first N-type transistor N1, the output terminal OUT outputs the low level, and it is confirmed that the data read by the first ferroelectric storage unit 11 is the digital signal 0.

[0331] In reading the digital signal 1, the third voltage of the second node B is high, and the second N-type transistor N2 is turned on. The reference voltage of the reference voltage terminal Vref is greater than the third voltage when the first ferroelectric storage unit 11 reads the digital signal 1, and is less than the third voltage when the first ferroelectric storage unit 11 reads the digital signal 0. Therefore, even if the reference voltage terminal Vref is electrically connected to the gate of the first P-type transistor P1 and the gate of the first N-type transistor N1, the turn-on degree of the first P-type transistor P1 and the first N-type transistor N1 is less than the turn-on degree of the second N-type transistor N2. The second N-type transistor N2 can be charged more quickly, and the low level of the ground terminal Vss1 is transmitted to the gate of the first P-type transistor P1 and the reference voltage terminal Vref. The reference voltage terminal Vref is pulled low. Further, the first P-type transistor P1 is turned on, the fourth voltage terminal V4 transmits the high level to the output terminal OUT through the first P-type transistor P1, and the output terminal OUT outputs the high level, confirming that the data read by the first ferroelectric storage unit 11 is the digital signal 1.

[0332] For example, when the first ferroelectric storage unit 11 is set to read the digital signal 0, the ferroelectric capacitor FE-Cap is polarized to flip. The third voltage when the digital signal 0 is read is greater than the third voltage when the digital signal 1 is read.

[0333] In reading the digital signal 1, the third voltage of the second node B is low, and the second P-type transistor P2 is turned on. The reference voltage of the reference voltage terminal Vref is greater than the third voltage when the first ferroelectric storage unit 11 reads the digital signal 0, and is less than the third voltage when the first ferroelectric storage unit 11 reads the digital signal 1. Therefore, even if the reference voltage terminal Vref is electrically connected to the gate of the first P-type transistor P1 and the gate of the first N-type transistor N1, the turn-on degree of the first P-type transistor P1 and the first N-type transistor N1 is less than the turn-on degree of the second P-type transistor P2. The second P-type transistor P2 can be charged more quickly, and the high level of the fourth voltage terminal V4 is transmitted to the gate of the first N-type transistor N1 and the reference voltage terminal Vref. The reference voltage terminal Vref is pulled high. Further, the first N-type transistor N1 is turned on, the ground terminal Vss1 transmits the low level to the output terminal OUT through the first N-type transistor N1, and the output terminal OUT outputs the low level, confirming that the data read by the first ferroelectric storage unit 11 is the digital signal 1.

[0334] When reading digital signal 0, the third voltage of the second node B is high, and the second N-type transistor N2 is turned on. The reference voltage of the reference voltage terminal Vref is greater than the third voltage when the first ferroelectric storage unit 11 reads digital signal 0, and is less than the third voltage when the first ferroelectric storage unit 11 reads digital signal 1. Therefore, even if the reference voltage terminal Vref is electrically connected with the gate of the first P-type transistor P1 and the gate of the first N-type transistor N1, the turn-on degree of the first P-type transistor P1 and the first N-type transistor N1 is less than the turn-on degree of the second N-type transistor N2, the second N-type transistor N2 can be charged more quickly, and the low level of the ground terminal Vss1 is transmitted to the gate of the first P-type transistor P1 and the reference voltage terminal Vref, and the reference voltage terminal Vref is pulled low. Further, the first P-type transistor P1 is turned on, the fourth voltage terminal V4 transmits the high level to the output terminal OUT through the first P-type transistor P1, and the output terminal OUT outputs the high level, confirming that the data read by the first ferroelectric storage unit 11 is digital signal 0.

[0335] In the anti-writing phase, the third switch WR is turned on, and the write signal of the reference voltage terminal Vref is input to the first ferroelectric storage unit 11 through the first node A.

[0336] Taking the case that the first ferroelectric storage unit 11 is set to read digital signal 1 and the ferroelectric capacitor is polarized to flip as an example, when reading digital signal 1, the reference voltage terminal Vref is low; in the anti-writing phase, the reference voltage terminal Vref inputs low to the first bit line BL1 through the third switch WR, and then inputs high to the plate line PL, so that the first bit line BL1 and the plate line PL form a potential difference at both ends of the first ferroelectric storage unit 11, completing the anti-writing of digital signal 1. When reading digital signal 0, the reference voltage terminal Vref is high; in the anti-writing phase, the reference voltage terminal Vref inputs high to the first bit line BL1 through the third switch WR, and then inputs low to the plate line PL, so that the first bit line BL1 and the plate line PL form a potential difference at both ends of the first ferroelectric storage unit 11, completing the anti-writing of digital signal 0.

[0337] For example, when reading digital signal 0, the first ferroelectric memory cell 11 is set to read digital signal 0, and the ferroelectric capacitor is polarized to flip. When reading digital signal 0, the reference voltage terminal Vref is at low level. In the write-back stage, the reference voltage terminal Vref inputs low level to the first bit line BL1 through the third switch WR, and then inputs high level to the plate line PL. The first bit line BL1 and the plate line PL form a potential difference at both ends of the first ferroelectric memory cell 11, and the write-back of digital signal 0 is completed. When reading digital signal 1, the reference voltage terminal Vref is at high level. In the write-back stage, the reference voltage terminal Vref inputs high level to the first bit line BL1 through the third switch WR, and then inputs low level to the plate line PL. The first bit line BL1 and the plate line PL form a potential difference at both ends of the first ferroelectric memory cell 11, and the write-back of digital signal 1 is completed.

[0338] In addition, other explanations and benefits of the embodiments of the present application are the same as the explanations and benefits of the initial voltage being high level in the previous embodiment, and will not be repeated here.

[0339] In other embodiments, if the first ferroelectric memory cell 11 reads digital signal 1 in the read stage, and digital signal 0 needs to be written to the first ferroelectric memory cell 11 in the write stage, the first ferroelectric memory cell 11 can be rewritten instead of write-back. Alternatively, if the first ferroelectric memory cell 11 reads digital signal 0 in the read stage, and digital signal 1 needs to be written to the first ferroelectric memory cell 11 in the write stage, the first ferroelectric memory cell 11 can be rewritten instead of write-back.

[0340] In this case, instead of write-back signal to the first ferroelectric memory cell 11 through the reference voltage terminal Vref, the output terminal OUT of the storage circuit is multiplexed as the input terminal of the storage circuit (or comparison circuit), and the input terminal of the storage circuit is used to rewrite the signal to the first ferroelectric memory cell 11.

[0341] In yet another embodiment, the present application also provides a storage circuit, as shown in FIGS. 9a and 9b, which includes a ferroelectric memory cell 11, a clamping circuit 12, a voltage generating circuit 13, and a comparison circuit 14. The output terminal of the ferroelectric memory cell 11 and one end of the clamping circuit 12 are electrically connected to a first node A, the other end of the clamping circuit 12, the voltage generating circuit 13, and the output terminal of the comparison circuit 14 are electrically connected to a second node B, and the output terminal of the comparison circuit 14 is electrically connected to the output terminal OUT of the storage circuit.

[0342] The working process of the storage circuit includes:

[0343] In the pre-charge stage, the voltage of the first node is charged to 0V, and the voltage generating circuit 13 is used to provide a first voltage to the second node B, and the first voltage is less than 0V. That is, the potential of the first node A is higher than the potential of the second node B.

[0344] During the reading phase:

[0345] Ferroelectric storage cell 11 is used to input a second voltage to the first node A. Since the potential of the first node A is higher than that of the second node B, the ferroelectric storage cell 11 is used to input a second voltage to the second node B through the first node A and the clamping circuit 12. The second voltage is greater than 0V. Although the ferroelectric storage cell 11 inputs a second voltage to the first node A, the clamping circuit 12 clamps the potential of the first node A at the initial voltage. Therefore, the second voltage output by the ferroelectric storage cell 11 passes through the first node A but does not accumulate at the first node A, and the voltage of the first node A remains the initial voltage.

[0346] During the reading phase, when the polarization of the ferroelectric capacitor FE-Cap in the ferroelectric storage cell 11 reverses, the first ferroelectric storage cell 11 outputs a polarization current; when the polarization of the ferroelectric capacitor FE-Cap does not reverse, the ferroelectric storage cell 11 outputs a dielectric current. The second voltage output when the polarization of the ferroelectric capacitor FE-Cap reverses is greater than the second voltage output when the polarization of the ferroelectric capacitor FE-Cap does not reverse. Therefore, when the polarization of the ferroelectric capacitor FE-Cap reverses, the ferroelectric storage cell 11 inputs a second voltage to the second node B through the first node A and the clamping circuit 12, which is greater than the second voltage input to the second node B through the first node A and the clamping circuit 12 when the polarization of the ferroelectric capacitor FE-Cap does not reverse.

[0347] Regardless of whether the polarization of the ferroelectric capacitor FE-Cap reverses, the voltage at the second node B increases, from the original first voltage to the sum of the first and second voltages.

[0348] The voltage generating circuit 13 is also used to input a third voltage to the second node B, changing the potential of the second node B to a fourth voltage. The voltage generating circuit 13 is also used to input the fourth voltage to the comparator circuit 14. The fourth voltage is the sum of the first, second, and third voltages.

[0349] The comparator circuit 14 receives the fourth voltage input from the second node B and determines whether the data read from the ferroelectric storage cell 11 is digital signal 0 or digital signal 1 based on the fourth voltage. The fourth voltage is within the operating voltage range of the comparator voltage 14.

[0350] It should be understood that the fourth voltage when reading the digital signal 1 is different from the fourth voltage when reading the digital signal 0, and only when the fourth voltage when reading the digital signal 1 and the fourth voltage when reading the digital signal 0 are both within the working voltage range of the comparison circuit 14, the comparison circuit 14 can compare the fourth voltage to determine whether the data indicated by the fourth voltage received by the comparison circuit 14 is the digital signal 1 or the digital signal 0.

[0351] Optionally, the working voltage of the comparison circuit 14 is usually positive, and the range can be 0V-3.3V, or 0V-2.5V, etc. After the ferroelectric storage unit 11 inputs the second voltage to the first node A, although the potential of the second node B becomes the sum of the first voltage and the second voltage, at this time, the potential of the second node B can still be negative, or in the case of polarization flip of the ferroelectric capacitor FE-Cap, the potential of the second node B (the sum of the first voltage and the second voltage) is positive; in the case of no polarization flip of the ferroelectric capacitor FE-Cap, the potential of the second node B (the sum of the first voltage and the second voltage) is still negative. Therefore, the voltage generating circuit 13 can also input a third voltage to the second node B, and the third voltage is positive, at this time, the voltage of the second node B is the fourth voltage (the sum of the first voltage, the second voltage and the third voltage). The specific value of the third voltage is not limited in the embodiment of the application, and the third voltage can be adjusted according to the sum of the first voltage and the second voltage and the working voltage of the comparison circuit 14.

[0352] In some possible implementations, the third voltage can be the absolute value of the first voltage, for example, first use the voltage generating circuit 13 to pull down the second node B by 5V (the first voltage is -5V), and then use the voltage generating circuit 13 to pull up the second node B by 5V (the third voltage is 5V) after the second node B receives the second voltage, so that the fourth voltage obtained is the second voltage input to the second node B by the ferroelectric storage unit 11.

[0353] Of course, in another possible implementation, if the potential of the second node B becomes the sum of the first voltage and the second voltage after the ferroelectric storage unit 11 inputs the second voltage to the first node A, and the potential is already positive and within the working voltage range of the comparison circuit 14, the third voltage can also be 0V, and the voltage generating circuit 13 can no longer provide the third voltage to the second node B. Or, if the potential of the second node B becomes the sum of the first voltage and the second voltage after the ferroelectric storage unit 11 inputs the second voltage to the first node A, and the potential is already positive and the fourth voltage is greater than the upper limit of the working voltage of the comparison circuit 14 (for example, 3.3V or 2.5V), the third voltage can also be negative. Hereinafter, unless otherwise stated, the third voltage is taken as an example for description.

[0354] In the present application, when reading data, the second voltage of the ferroelectric storage unit 11 is first input to the first node A. Since the potential of the first node A is higher than that of the second node B, the ferroelectric storage unit 11 inputs the second voltage to the second node B through the first node A. Whether the ferroelectric capacitor FE-Cap undergoes polarization reversal or not, the data (digital signal 1 or digital signal 0) read by the ferroelectric storage unit 11 is different, and the second voltage input to the second node B by the ferroelectric storage unit 11 is different. Except for the second voltage, the first voltage when the ferroelectric storage unit 11 reads digital signal 1 is the same as the first voltage when it reads digital signal 0, and the third voltage when the ferroelectric storage unit 11 reads digital signal 1 is the same as the third voltage when it reads digital signal 0. Therefore, after receiving the fourth voltage input by the second node B, the comparison circuit 14 can determine whether the data read by the ferroelectric storage unit 11 is digital signal 1 or digital signal 0 according to the fourth voltage.

[0355] At the same time, whether reading digital signal 1 or digital signal 0, the voltage on the bit line BL (first node A) is clamped by the clamping circuit 12 to the initial voltage. On the one hand, the potential difference between the plate line PL and the bit line BL is stabilized at a fixed value, which does not affect the polarization reversal of the ferroelectric capacitor FE-Cap. On the other hand, the potential difference between the plate line PL and the bit line BL is always at a large value, so that the polarization reversal of the ferroelectric capacitor FE-Cap does not become slower and slower or even insufficient due to the decrease of the potential difference between the plate line PL and the bit line BL, thereby preventing the self-inhibition phenomenon, improving the uniformity and reliability of the storage circuit, and also improving the storage window of the ferroelectric circuit.

[0356] In addition, as mentioned above, the comparison circuit 14 in the prior art reads digital signal 1 or digital signal 0 by obtaining the charge on the bit line BL. The bit line BL is usually connected with multiple ferroelectric storage units and has a relatively long length. In a storage chip, the bit line BL inevitably forms a parasitic capacitance Cbl1 with multiple conductive structures. The parasitic capacitance Cbl has a negative impact on the MW of the storage circuit.

[0357] In the present application, the voltage on the bit line BL (first node A) is clamped by the clamping circuit 12 to the initial voltage. The parasitic capacitance Cbl cannot be transmitted to the second node B through the bit line BL. The comparison circuit 14 in the present application confirms whether the data is digital signal 0 or digital signal 1 according to the fourth voltage transmitted by the second node B. Therefore, the parasitic capacitance Cbl does not have a negative impact on the MW of the storage circuit.

[0358] In some embodiments, as shown in FIG. 9a, the clamping circuit 12 includes a first transistor T1 and a second transistor T2. The first transistor T1 is an N-type transistor, and the second transistor T2 is a P-type transistor. The first transistor T1 is electrically connected between the first node A and the second transistor T2.

[0359] When the ferroelectric memory cell 11 inputs the second voltage to the second node B through the first node A and the clamping circuit 12, the first transistor T1 and the second transistor T2 are turned on, and the second transistor T2 is a P-type transistor, so that the node connected with the first transistor T1 can be clamped by the second transistor T2, and the potential of the node connected with the first transistor T1 is the same as the potential of the first node A, so that the potential of the first node A can be clamped at 0V by the second transistor T2 through the first transistor T1.

[0360] When the voltage generating circuit 13 inputs the third voltage to the second node B, the first transistor T1 is turned off to prevent the potential of the first node A from increasing when the potential of the second node B is raised through the second transistor T2 and the first transistor T1.

[0361] Similarly, in some possible implementation manners, the storage circuit can further include a P-type transistor P1 electrically connected between the second node B and the comparison circuit 14, and the P-type transistor P1 is turned off when the voltage generating circuit 13 inputs the third voltage to the second node B to prevent the potential of the comparison circuit 14 from being affected through the second transistor T2 and the first transistor T1 when the potential of the second node B is raised. Then, the P-type transistor P1 is turned on, and the second node B inputs the fourth voltage to the comparison circuit 14 through the P-type transistor P1.

[0362] In some embodiments, as shown in FIG. 9a, the voltage generating circuit includes a first voltage terminal V_boost, and the first voltage terminal V_boost is used to input the third voltage to the second node B in the reading stage. However, due to the existence of the parasitic capacitance, the voltage value received by the second node B cannot reach the voltage value output by the first voltage terminal V_boost, so the voltage generating circuit 13 can further include a storage capacitor TC electrically connected between the second node B and the first voltage terminal V_boost, wherein the first voltage terminal V_boost is electrically connected with a first electrode of the storage capacitor TC, and the second node B is electrically connected with a second electrode of the storage capacitor TC. In this way, the voltage generating circuit 13 can first input the third voltage to the first electrode, and the first electrode couples the third voltage to the second electrode and the second node B to improve the problem that the voltage output by the first voltage terminal V_boost is largely taken away by the parasitic capacitance, resulting in that the voltage value received by the second node B cannot reach the voltage value output by the first voltage terminal V_boost.

[0363] In some possible implementation manners, as shown in FIG. 10, there is usually a loss problem in the transmission process of the signal, and based on this, the voltage generation circuit 13 can further include an inverter 131 electrically connected between the first voltage terminal V_boost and the storage capacitor TC to enhance the signal.

[0364] Here, it should be noted that if the third voltage required by the second node B is high, in the case where the first voltage generation circuit 13 does not include the inverter 131, the voltage output by the first voltage terminal V_boost is also high; and in the case where the third voltage generation circuit 13 includes the inverter 131, the voltage output by the first voltage terminal V_boost is low.

[0365] In some embodiments, the storage circuit further includes a third transistor T3 and a second voltage terminal V2, in the pre-charging phase, the third transistor T3 is turned on, and the second voltage terminal V2 is pre-charged to 0V to the first node A through the third transistor T3 to prepare for the reading phase.

[0366] Optionally, as shown in FIG. 10, the third transistor T3 is electrically connected between the second node B and the second voltage terminal V2, and the second voltage terminal V2 is pre-charged to 0V to the first node A through the third transistor T3, the second node B, the second transistor T2 and the first transistor T1.

[0367] Optionally, as shown in FIG. 11, the third transistor T3 is electrically connected between the third node C and the second voltage terminal V2, and the third node C is a connection node of the first transistor T1 and the second transistor T2, and the second voltage terminal V2 is pre-charged to 0V to the first node A through the third transistor T3, the third node C and the first transistor T1.

[0368] In some possible implementation manners, as shown in FIG. 9b, in the pre-charging phase, the voltage generation circuit 13 provides the first voltage less than 0V for the second node B, which can be implemented in the following way:

[0369] The first voltage terminal V_boost is low, and after passing through the inverter 131, a high level is input to the first electrode of the storage capacitor TC; the third transistor T3 is turned on, and the second voltage terminal V2 provides a voltage of 0V for the second node B and the second electrode of the storage capacitor TC. Then, the first voltage terminal V_boost is high, and after passing through the inverter 131, a voltage of 0V is input to the first electrode of the storage capacitor TC, the voltage on the first electrode decreases, and the voltage on the second electrode also decreases under the coupling of the first electrode, and the voltage on the second electrode changes from 0V to a negative number.

[0370] In some embodiments, as shown in FIG. 12, the storage circuit further comprises a third voltage terminal V3 and a fourth transistor T4, the fourth transistor T4 being an N-type transistor, the gate of the fourth transistor T4 being electrically connected with the second node B, the first pole of the fourth transistor T4 being electrically connected with the third voltage terminal V3, and the second pole of the fourth transistor T4 being electrically connected with the input terminal of the comparison circuit 14. On this basis, the storage circuit can further comprise a fifth transistor T5, the fifth transistor T5 being a P-type transistor, and the fifth transistor T5 being electrically connected between the fourth transistor T4 and the third voltage terminal V3.

[0371] As mentioned above, the fourth voltage is positive no matter whether the digital signal 1 or the digital signal 0 is read, but the fourth voltage when the digital signal 1 is read is different from the fourth voltage when the digital signal 0 is read.

[0372] As shown in FIG. 9b, it is assumed that the first ferroelectric storage unit 11 is set to have the ferroelectric capacitor FE-Cap polarized and flipped when the digital signal 1 is read, and the first ferroelectric storage unit 11 is set to have the ferroelectric capacitor not polarized and flipped when the digital signal 0 is read. Then, the fourth voltage when the digital signal 1 is read is greater than the fourth voltage when the digital signal 0 is read, the fourth transistor T4 is turned on to a greater extent when the digital signal 1 is read than when the digital signal 0 is read, the current flowing through the fourth transistor T4 is greater when the digital signal 1 is read than when the digital signal 0 is read, and thus more electric charges are accumulated at the input terminal of the comparison circuit 14 within a certain time, the voltage received by the comparison circuit 14 is greater, and the comparison circuit 14 determines the data read by the first ferroelectric storage unit 11 to be the digital signal 0 or the digital signal 1 according to the size of the received voltage.

[0373] It is assumed that the first ferroelectric storage unit 11 is set to have the ferroelectric capacitor FE-Cap polarized and flipped when the digital signal 0 is read, and the first ferroelectric storage unit 11 is set to have the ferroelectric capacitor not polarized and flipped when the digital signal 1 is read. Then, the fourth voltage when the digital signal 0 is read is greater than the fourth voltage when the digital signal 1 is read, the fourth transistor T4 is turned on to a greater extent when the digital signal 0 is read than when the digital signal 1 is read, the current flowing through the fourth transistor T4 is greater when the digital signal 0 is read than when the digital signal 1 is read, and thus more electric charges are accumulated at the input terminal of the comparison circuit 14 within a certain time, the voltage received by the comparison circuit 14 is greater, and the comparison circuit 14 determines the data read by the first ferroelectric storage unit 11 to be the digital signal 0 or the digital signal 1 according to the size of the received voltage.

[0374] In this case, since the gate of the fourth transistor T4 is electrically connected with the second node B, the fourth voltage controls the on-off degree of the fourth transistor T4 and the current flowing through the fourth transistor T4, and thus the comparison circuit 14 indirectly determines the data read by the ferroelectric memory cell 11 as the digital signal 0 or the digital signal 1 according to the fourth voltage. Further, the fourth voltage can be amplified by means of charge accumulation, so as to improve the reading quality and resolution of the storage circuit.

[0375] In some embodiments, after the reading stage, the ferroelectric memory cell 11 can also be subjected to a write-back. In the write-back stage, the P-type transistor P1, the second transistor T2 and the first transistor T1 are all turned on, and the comparison circuit 14 inputs the write signal to the ferroelectric memory cell 11 through the P-type transistor P1, the second transistor T2 and the first transistor T1.

[0376] In another embodiment, if the first ferroelectric memory cell 11 reads the digital signal 1 in the reading stage, and the digital signal 0 needs to be written into the first ferroelectric memory cell 11 in the writing stage, the first ferroelectric memory cell 11 can be subjected to a rewrite instead of a write-back. Alternatively, if the first ferroelectric memory cell 11 reads the digital signal 0 in the reading stage, and the digital signal 1 needs to be written into the first ferroelectric memory cell 11 in the writing stage, the first ferroelectric memory cell 11 can be subjected to a rewrite instead of a write-back.

[0377] In this case, the first ferroelectric memory cell 11 is no longer subjected to a write-back of the signal through the reference voltage terminal Vref, but the output terminal OUT of the storage circuit is multiplexed as the input terminal of the storage circuit (or the comparison circuit), and the input terminal of the storage circuit is used to rewrite the signal of the first ferroelectric memory cell 11.

[0378] In yet another embodiment, the present application also provides a control method of the storage circuit. As shown in FIGS. 9a-12, the circuit structure of the storage circuit is the same as that of the storage circuit in the previous embodiment, and thus will not be described herein.

[0379] S110, the first transistor T1, the second transistor T2, the third transistor T3 are turned on, the second voltage terminal V2 charges the first node A with a voltage of 0V through the third transistor T3, the second transistor T2, the first transistor T1, and also charges the second node B and the second electrode of the storage capacitor TC with a voltage of 0V through the third transistor T3. The first voltage terminal V_boost is at a low level, and after passing through the inverter 131, a high level is input to the first electrode of the storage capacitor TC. Then, the first voltage terminal V_boost is at a high level, and after passing through the inverter 131, 0V is input to the first electrode of the storage capacitor TC, the voltage on the first electrode decreases, and the voltage on the second electrode also decreases under the coupling of the first electrode, and the voltage on the second electrode changes from 0V to a negative number. At this point, the potential of the first node A is 0V, and the voltage of the second node B is a first voltage less than 0V.

[0380] S120, the ferroelectric storage unit 11 inputs a second voltage to the first node A, and since the potential of the first node A is higher than that of the second node B, the ferroelectric storage unit 11 is used to input the second voltage to the second node B through the first node A and the clamping circuit 12, and the second voltage is greater than 0V. Although the ferroelectric storage unit 11 inputs the second voltage to the first node A, the clamping circuit 12 clamps the potential of the first node A at the initial voltage, so the second voltage output by the ferroelectric storage unit 11 passes through the first node A but does not accumulate at the first node A, and the voltage of the first node A remains at the initial voltage.

[0381] The voltage generating circuit 13 is also used to input a third voltage to the second node B, and the potential of the second node B becomes a fourth voltage. The voltage generating circuit 13 is also used to input the fourth voltage to the comparison circuit 14. The fourth voltage is the sum of the first voltage, the second voltage, and the third voltage.

[0382] In the read stage, when the ferroelectric capacitor FE-Cap in the ferroelectric storage unit 11 undergoes polarization reversal, the first ferroelectric storage unit 11 outputs a polarization current; when the ferroelectric capacitor FE-Cap does not undergo polarization reversal, the ferroelectric storage unit 11 outputs a dielectric current. The second voltage output when the ferroelectric capacitor FE-Cap undergoes polarization reversal is greater than the second voltage output when the ferroelectric capacitor FE-Cap does not undergo polarization reversal, so when the ferroelectric capacitor FE-Cap undergoes polarization reversal, the ferroelectric storage unit 11 inputs a second voltage to the second node B through the first node A and the clamping circuit 12, which is greater than the second voltage input by the ferroelectric storage unit 11 to the second node B through the first node A and the clamping circuit 12 when the ferroelectric capacitor FE-Cap does not undergo polarization reversal.

[0383] S130, the comparison circuit 14 receives the fourth voltage input by the second node B, and determines the data read by the ferroelectric memory cell 11 as digital signal 0 or digital signal 1 according to the fourth voltage. The fourth voltage is within the working voltage range of the comparison circuit 14.

[0384] It should be understood that the fourth voltage when reading digital signal 1 by the ferroelectric memory cell 11 is different from the fourth voltage when reading digital signal 0. Only when the fourth voltage when reading digital signal 1 and the fourth voltage when reading digital signal 0 are both within the working voltage range of the comparison circuit 14, the comparison circuit 14 can compare the fourth voltage to determine whether the data indicated by the received fourth voltage is digital signal 1 or digital signal 0.

[0385] Optionally, the working voltage of the comparison circuit 14 is usually positive, and the range can be 0V-3.3V, or 0V-2.5V, etc. After the ferroelectric memory cell 11 inputs the second voltage to the first node A, although the potential of the second node B becomes the sum of the first voltage and the second voltage, the potential of the second node B can still be negative at this time, or the potential of the second node B (the sum of the first voltage and the second voltage) is positive when the ferroelectric capacitor FE-Cap occurs polarization reversal; the potential of the second node B (the sum of the first voltage and the second voltage) is still negative when the ferroelectric capacitor FE-Cap does not occur polarization reversal. Therefore, the voltage generating circuit 13 can also input a third voltage to the second node B, and the third voltage is positive, and the voltage of the second node B is the fourth voltage (the sum of the first voltage, the second voltage and the third voltage) at this time. The specific value of the third voltage is not limited in the embodiment of the application, and the third voltage can be adjusted according to the sum of the first voltage and the second voltage and the working voltage of the comparison circuit 14.

[0386] In some possible implementations, the third voltage can be the absolute value of the first voltage, for example, the voltage generating circuit 13 is used to pull down the second node B by 5V (the first voltage is -5V) first, and then the voltage generating circuit 13 is used to pull up the second node B by 5V (the third voltage is 5V) after the second node B receives the second voltage, so that the fourth voltage obtained is the second voltage input to the second node B by the ferroelectric memory cell 11.

[0387] Of course, in another possible implementation, if the potential of the second node B becomes the sum of the first voltage and the second voltage after the ferroelectric memory cell 11 inputs the second voltage to the first node A, and the sum is already a positive number and is within the working voltage range of the comparison circuit 14, the third voltage can also be 0V, and the voltage generation circuit 13 can no longer provide the third voltage to the second node B. Alternatively, if the potential of the second node B becomes the sum of the first voltage and the second voltage after the ferroelectric memory cell 11 inputs the second voltage to the first node A, and the sum is already a positive number and the fourth voltage is greater than the upper limit of the working voltage of the comparison circuit 14 (for example, 3.3V or 2.5V), the third voltage can also be a negative number.

[0388] In the present application, when reading data, the second voltage of the ferroelectric memory cell 11 is first input to the first node A, and because the potential of the first node A is higher than the potential of the second node B, the ferroelectric memory cell 11 inputs the second voltage to the second node B through the first node A. Whether the ferroelectric capacitor FE-Cap undergoes polarization inversion or not, the data (digital signal 1 or digital signal 0) read by the ferroelectric memory cell 11 is different, and the second voltage input by the ferroelectric memory cell 11 to the second node B is different. In addition to the second voltage, the first voltage when the ferroelectric memory cell 11 reads digital signal 1 is the same as the first voltage when it reads digital signal 0, and the third voltage when the ferroelectric memory cell 11 reads digital signal 1 is the same as the third voltage when it reads digital signal 0, so after the comparison circuit 14 receives the fourth voltage input by the second node B, it can determine whether the data read by the ferroelectric memory cell 11 is digital signal 1 or digital signal 0 according to the fourth voltage.

[0389] At the same time, whether reading digital signal 1 or digital signal 0, the voltage on the bit line BL (first node A) is clamped by the clamping circuit 12 to the initial voltage, on the one hand, the potential difference between the plate line PL and the bit line BL is stabilized at a fixed value, which does not affect the polarization inversion of the ferroelectric capacitor FE-Cap; on the other hand, the potential difference between the plate line PL and the bit line BL is always at a large value, so that the polarization inversion of the ferroelectric capacitor FE-Cap does not become slower and slower, or even insufficient, thereby improving the uniformity and reliability of the storage circuit, and also improving the storage window of the ferroelectric circuit.

[0390] In addition, as mentioned earlier, the comparison circuit 14 in the prior art reads digital signal 1 or digital signal 0 by obtaining the charge on the bit line BL, and the bit line BL is usually connected with multiple ferroelectric memory cells and has a relatively long length, and in a storage chip, the bit line BL inevitably forms a parasitic capacitance Cbl1 with multiple conductive structures, which has a negative impact on the MW of the storage circuit.

[0391] The voltage on the bit line BL (the first node A) of the application is clamped to the initial voltage by the clamping circuit 12, and the parasitic capacitance Cbl cannot be transmitted to the second node B through the bit line BL. The comparison circuit 14 of the application determines the data as digital signal 0 or digital signal 1 according to the fourth voltage transmitted by the second node B. Therefore, the parasitic capacitance Cbl does not have a negative impact on the MW of the storage circuit.

[0392] In some embodiments, as shown in FIG. 12, the storage circuit further comprises a third voltage terminal V3 and a fourth transistor T4. The fourth transistor T4 is an N-type transistor. The gate of the fourth transistor T4 is electrically connected to the second node B. The first pole of the fourth transistor T4 is electrically connected to the third voltage terminal V3. The second pole of the fourth transistor T4 is electrically connected to the input terminal of the comparison circuit 14. On this basis, the storage circuit can further comprise a fifth transistor T5. The fifth transistor T5 is a P-type transistor. The fifth transistor T5 is electrically connected between the fourth transistor T4 and the third voltage terminal V3.

[0393] As mentioned above, the fourth voltage is positive when reading digital signal 1 or digital signal 0. However, the fourth voltage when reading digital signal 1 is different from the fourth voltage when reading digital signal 0.

[0394] As shown in FIG. 9b, it is assumed that the first ferroelectric storage unit 11 undergoes polarization flipping of the ferroelectric capacitor FE-Cap when reading digital signal 1, and does not undergo polarization flipping of the ferroelectric capacitor when reading digital signal 0. Then, the fourth voltage when reading digital signal 1 is greater than the fourth voltage when reading digital signal 0. The conduction degree of the fourth transistor T4 when reading digital signal 1 is greater than the conduction degree of the fourth transistor T4 when reading digital signal 0. The current flowing through the fourth transistor T4 when reading digital signal 1 is more. In a certain period of time, more electric charges are accumulated at the input terminal of the comparison circuit 14. The voltage received by the comparison circuit 14 is more. The comparison circuit 14 determines the data read by the ferroelectric storage unit 11 as digital signal 0 or digital signal 1 according to the size of the received voltage.

[0395] It is assumed that the first ferroelectric storage unit 11 undergoes polarization flipping of the ferroelectric capacitor FE-Cap when reading digital signal 0, and does not undergo polarization flipping of the ferroelectric capacitor when reading digital signal 1. Then, the fourth voltage when reading digital signal 0 is greater than the fourth voltage when reading digital signal 1. The conduction degree of the fourth transistor T4 when reading digital signal 0 is greater than the conduction degree of the fourth transistor T4 when reading digital signal 1. The current flowing through the fourth transistor T4 when reading digital signal 0 is more. In a certain period of time, more electric charges are accumulated at the input terminal of the comparison circuit 14. The voltage received by the comparison circuit 14 is more. The comparison circuit 14 determines the data read by the ferroelectric storage unit 11 as digital signal 0 or digital signal 1 according to the size of the received voltage.

[0396] In this case, since the gate of the fourth transistor T4 is electrically connected with the second node B, the fourth voltage controls the on-off degree of the fourth transistor T4 and the current flowing through the fourth transistor T4, thus the comparison circuit 14 still indirectly determines the data read by the ferroelectric memory cell 11 as digital signal 0 or digital signal 1 according to the fourth voltage. Further, the fourth voltage can also be amplified by means of charge accumulation to improve the reading quality and resolution of the storage circuit.

[0397] S130, in the inverse writing stage, the P-type transistor P1, the second transistor T2 and the first transistor T1 are all turned on, and the comparison circuit 14 inputs the writing signal to the ferroelectric memory cell 11 through the P-type transistor P1, the second transistor T2 and the first transistor T1.

[0398] In addition, other explanations and advantages of the embodiments of the present application are the same as those of the previous embodiments, which will not be repeated here.

[0399] In other embodiments, if the first ferroelectric memory cell 11 reads digital signal 1 in the reading stage, and digital signal 0 needs to be written into the first ferroelectric memory cell 11 in the writing stage, the first ferroelectric memory cell 11 can be rewritten instead of inverse written. Or, if the first ferroelectric memory cell 11 reads digital signal 0 in the reading stage, and digital signal 1 needs to be written into the first ferroelectric memory cell 11 in the writing stage, the first ferroelectric memory cell 11 can be rewritten instead of inverse written.

[0400] In this case, the first ferroelectric memory cell 11 is no longer inverse written with the reference voltage terminal Vref, but the output terminal OUT of the storage circuit is multiplexed as the input terminal of the storage circuit (or the comparison circuit), and the input terminal of the storage circuit is used to rewrite the signal of the first ferroelectric memory cell 11.

[0401] The embodiments of the present application are described above in combination with the drawings, but the present application is not limited to the above specific embodiments, which are only illustrative but not restrictive, and those skilled in the art can make many forms under the inspiration of the present application without departing from the scope of the present application and the protection scope of the claims.

Claims

1. A storage circuit, characterized by comprising: The first ferroelectric memory cell, a first current mirror, a first voltage generating circuit, a comparison circuit, and a first voltage terminal are included. The first current mirror includes a first branch and a second branch, one end of the first branch and one end of the second branch are electrically connected to the first voltage terminal, and the current of the first branch is the same as the current of the second branch. The output end of the first ferroelectric memory cell is electrically connected to the other end of the first branch at a first node, the other end of the second branch is electrically connected to the output end of the first voltage generating circuit and the input end of the comparison circuit at a second node, and the output end of the comparison circuit is electrically connected to the output end of the memory circuit.

2. The storage circuit according to claim 1, characterized by, The first branch includes a first transistor, and the second branch includes a second transistor, and the first transistor is the same as the second transistor. The first pole of the first transistor is electrically connected to the first node, the gate of the first transistor, and the gate of the second transistor, the second pole of the first transistor and the second pole of the second transistor are both electrically connected to the first voltage terminal, and the first pole of the second transistor is electrically connected to the second node. In the read stage, the first voltage terminal is used to input a first voltage to the second pole of the first transistor and the second pole of the second transistor.

3. The storage circuit according to claim 2, characterized by The memory chip further includes a third transistor and a fourth transistor, the third transistor is connected in series between the first node and the first transistor, and the fourth transistor is connected in series between the second node and the second transistor. In the read stage, the third transistor is used to input a clamping voltage to the first pole of the first transistor, and the fourth transistor is used to input a clamping voltage to the first pole of the second transistor.

4. The storage circuit according to claim 2 or 3, characterized by The first voltage generating circuit includes a second voltage terminal and a storage capacitor, and the storage capacitor is electrically connected between the second node and the second voltage terminal. In the read stage, the second voltage terminal is used to input a second voltage to the second node through the storage capacitor.

5. The storage circuit according to claim 4, characterized by The first voltage generating circuit further includes an inverter electrically connected between the second voltage terminal and the storage capacitor.

6. The storage circuit according to claim 4 or 5, characterized by The memory circuit further includes a third voltage terminal and a pre-charge circuit electrically connected between the third voltage terminal and the first node. The memory circuit further includes a plate line and a bit line, the first ferroelectric memory cell is electrically connected between the bit line and the plate line, the bit line, the output end of the first ferroelectric memory cell, and one end of the first branch are electrically connected to the first node; in the pre-charge stage, the third voltage terminal is used to charge an initial voltage to the bit line through the pre-charge circuit.

7. The storage circuit according to claim 6, characterized by The pre-charge circuit includes a first switch and a second switch, the first switch is electrically connected between the input end of the first branch and the output end of the second branch, and the second switch is electrically connected between the third voltage terminal and the second node.

8. The memory circuit of claim 7, wherein In the pre-charge stage, the third voltage terminal is also used to pre-charge the second node through the second switch. In the reading phase, the first switch and the second switch are both open. 9.The storage circuit of any one of claims 6-8, wherein, in the reading phase, the ferroelectric storage unit is configured to input a charge to the first node; the first branch is configured to copy a first current of the first branch to the second branch, and to keep a potential of the first node at an initial voltage according to the first voltage and the initial voltage; the second branch is configured to change a potential of the second node from a second voltage to a third voltage according to the first current, the first voltage, and the second voltage; the comparison circuit is configured to receive the third voltage input by the second node, and to determine whether data read by the first ferroelectric storage unit is a digital signal 0 or 1 according to the third voltage.

10. The storage circuit according to claim 9, characterized by the first transistor and the second transistor are both N-type transistors, the initial voltage and the second voltage are both greater than the first voltage, and the initial voltage is a low voltage; the first branch is configured to extract a charge from the first node according to the first voltage and the initial voltage, so as to keep the potential of the first node at the initial voltage; the second branch is configured to extract a charge from the second node according to the first current, the first voltage, and the second voltage, so as to decrease the potential of the second node from the second voltage to a third voltage. 11.The storage circuit of claim 10, wherein, if the first ferroelectric storage unit reads a digital signal 1 and a polarization of a ferroelectric capacitor in the first ferroelectric storage unit is flipped, the third voltage when the first ferroelectric storage unit reads the digital signal 1 is less than the third voltage when the first ferroelectric storage unit reads a digital signal 0; if the first ferroelectric storage unit reads a digital signal 0 and the polarization of the ferroelectric capacitor in the first ferroelectric storage unit is flipped, the third voltage when the first ferroelectric storage unit reads the digital signal 1 is greater than the third voltage when the first ferroelectric storage unit reads the digital signal 0.

12. The storage circuit of claim 9, wherein, the first transistor and the second transistor are both P-type transistors, the initial voltage and the second voltage are both less than the first voltage, and the initial voltage is a high voltage; the first node is configured to extract a charge from the first branch according to the first voltage and the initial voltage, so as to keep the potential of the first node at the initial voltage; the second node is configured to extract a charge from the second branch according to the first current, the first voltage, and the second voltage, so as to increase the potential of the second node from the second voltage to a third voltage. 13.The storage circuit of claim 12, wherein, if the first ferroelectric storage unit reads a digital signal 1 and a polarization of a ferroelectric capacitor in the first ferroelectric storage unit is flipped, the third voltage when the first ferroelectric storage unit reads the digital signal 1 is greater than the third voltage when the first ferroelectric storage unit reads a digital signal 0. If the first ferroelectric memory cell reads a digital signal 0, and the ferroelectric capacitor in the first ferroelectric memory cell is polarized to flip, then the third voltage when the first ferroelectric memory cell reads a digital signal 0 is greater than the third voltage when the first ferroelectric memory cell reads a digital signal 1.

14. The storage circuit according to any one of claims 1 to 13, characterized by, The storage circuit further comprises a reference voltage terminal; In the reading stage: The reference voltage terminal is configured to input a reference voltage to the comparison circuit, the reference voltage having a voltage value between the third voltage when the first ferroelectric memory cell reads a digital signal 0 and the third voltage when the first ferroelectric memory cell reads a digital signal 1. The comparison circuit is configured to determine whether the data read by the first ferroelectric memory cell is a digital signal 0 or a digital signal 1 according to the third voltage and the reference voltage.

15. The storage circuit of claim 14, wherein, The comparison circuit comprises a fourth voltage terminal, a first P-type transistor, a second P-type transistor, a first N-type transistor, a second N-type transistor, and a ground terminal; the storage circuit further comprises an output terminal; in the reading stage, the fourth voltage terminal is at a high level, and the ground terminal is at a low level. The gate of the first P-type transistor and the gate of the first N-type transistor are electrically connected to the second electrode of the second P-type transistor, the first electrode of the second N-type transistor, and the reference voltage terminal; the first electrode of the first P-type transistor is electrically connected to the fourth voltage terminal; the second electrode of the first P-type transistor is electrically connected to the first electrode of the first N-type transistor and the output terminal; and the second electrode of the first N-type transistor is electrically connected to the ground terminal. The gate of the second P-type transistor and the gate of the second N-type transistor are electrically connected to the second node; the first electrode of the second P-type transistor is electrically connected to the fourth voltage terminal; and the second electrode of the second N-type transistor is electrically connected to the ground terminal.

16. The storage circuit according to claim 14 or 15, characterized by The storage circuit further comprises a reference voltage generation circuit, the reference voltage generation circuit comprising a second ferroelectric memory cell, a third ferroelectric memory cell, a second current mirror, a second voltage generation circuit, and a third node; the circuit structure of the second ferroelectric memory cell and the third ferroelectric memory cell is the same as that of the first ferroelectric memory cell; and the second current mirror comprises a third branch and a fourth branch. In the reading stage: The second voltage generation circuit is configured to input a fourth voltage to the third node, the fourth voltage being the same as the second voltage; The second ferroelectric memory cell is configured to input a second current to the third branch, the second current representing that the second ferroelectric memory cell reads a digital signal 1; The third ferroelectric memory cell is configured to input a third current to the fourth branch, the third current representing that the third ferroelectric memory cell reads a digital signal 0; The third branch is configured to receive the second current and the third current, and copy an average value of the second current and the third current to the fourth branch. The third node is configured to transmit electric charges to the fourth branch according to an average value of the second current and the third current, so that the potential of the third node decreases from the second voltage to a fifth voltage, and the fifth voltage is input to the reference voltage terminal; and the fifth voltage is half of the fourth voltage.

17. The storage circuit of claim 16, wherein, The third branch includes a fifth transistor and a sixth transistor, and the fourth branch includes a seventh transistor; the channel width of the fifth transistor, the sixth transistor and the seventh transistor is the same; the gate of the fifth transistor, the gate of the sixth transistor, the first electrode of the fifth transistor, the first electrode of the sixth transistor and the gate of the seventh transistor are electrically connected to the output terminals of the second ferroelectric storage unit and the third ferroelectric storage unit; the second electrode of the fifth transistor, the second electrode of the sixth transistor and the second electrode of the seventh transistor are electrically connected to the fifth voltage terminal, and the first electrode of the seventh transistor is electrically connected to the third node; or, The third branch includes a fifth transistor, and the fourth branch includes a sixth transistor; the channel width of the fifth transistor is twice the channel width of the sixth transistor; the gate of the fifth transistor, the gate of the sixth transistor and the first electrode of the fifth transistor are electrically connected to the output terminals of the second ferroelectric storage unit and the third ferroelectric storage unit; the second electrode of the fifth transistor and the second electrode of the sixth transistor are electrically connected to the fifth voltage terminal; and the first electrode of the sixth transistor is electrically connected to the third node.

18. The storage circuit according to any one of claims 14 to 17, characterized by The storage circuit further includes a third switch electrically connected between the reference voltage terminal and the first node; In the reading stage, the third switch is turned off; and in the anti-writing stage, the third switch is turned on to input a write signal of the reference voltage terminal to the first ferroelectric storage unit through the first node.

19. A control method of a storage circuit, characterized by, The storage circuit includes a first ferroelectric storage unit, a first current mirror, a first voltage generation circuit, a comparison circuit and a first voltage terminal; the first ferroelectric storage unit and a first branch of the first current mirror are electrically connected to a first node; a second branch of the first current mirror, the first voltage generation circuit and the comparison circuit are electrically connected to a second node. The control method of the storage circuit includes: In a pre-charging stage, the first node is pre-charged so that the potential of the first node is an initial voltage; In a reading stage: a first voltage is input to the first current mirror through the first voltage terminal; electric charges are input to the first node by the first ferroelectric storage unit; a second voltage is input to the second node by the first voltage generation circuit; the initial voltage and the second voltage are both greater than the first voltage, and the initial voltage is a low level; or the initial voltage and the second voltage are both less than the first voltage, and the initial voltage is a high level; and In an anti-writing stage: the third switch is turned on to input a write signal of the reference voltage terminal to the first ferroelectric storage unit through the first node; and the first voltage is input to the first current mirror through the first voltage terminal. The first branch is used to keep the potential of the first node at the initial voltage and copy the first current of the first branch to the second branch according to the first voltage and the initial voltage; The second branch is used to change the potential of the second node from the second voltage to a third voltage according to the first current, the first voltage and the second voltage; The third voltage is received by the comparison circuit, and the data read by the first ferroelectric storage unit is determined as digital signal 0 or 1 according to the third voltage.

20. The control method of a memory circuit according to claim 19, wherein The first transistor and the second transistor are both N-type transistors, and the initial voltage and the second voltage are both greater than the first voltage; The first branch is used to extract charges from the first node according to the first voltage and the initial voltage, so that the potential of the first node is kept at the initial voltage; The second branch is used to extract charges from the second node according to the first current, the first voltage and the second voltage, so that the potential of the second node is reduced from the second voltage to a third voltage.

21. The control method of the storage circuit according to claim 20, wherein If the first ferroelectric storage unit reads digital signal 1 and the ferroelectric capacitor in the first ferroelectric storage unit is polarized to flip, the third voltage when the first ferroelectric storage unit reads digital signal 1 is less than the third voltage when the first ferroelectric storage unit reads digital signal 0; If the first ferroelectric storage unit reads digital signal 0 and the ferroelectric capacitor in the first ferroelectric storage unit is polarized to flip, the third voltage when the first ferroelectric storage unit reads digital signal 1 is greater than the third voltage when the first ferroelectric storage unit reads digital signal 0.

22. The control method of a memory circuit according to claim 19, wherein The first transistor and the second transistor are both P-type transistors, and the initial voltage and the second voltage are both less than the first voltage; The first node is used to extract charges from the first branch according to the first voltage and the initial voltage, so that the potential of the first node is kept at the initial voltage; The second node is used to extract charges from the second branch according to the first current, the first voltage and the second voltage, so that the potential of the second node is increased from the second voltage to a third voltage.

23. The control method of the storage circuit according to claim 22, wherein If the first ferroelectric storage unit reads digital signal 1 and the ferroelectric capacitor in the first ferroelectric storage unit is polarized to flip, the third voltage when the first ferroelectric storage unit reads digital signal 1 is greater than the third voltage when the first ferroelectric storage unit reads digital signal 0; If the first ferroelectric storage unit reads digital signal 0 and the ferroelectric capacitor in the first ferroelectric storage unit is polarized to flip, the third voltage when the first ferroelectric storage unit reads digital signal 0 is greater than the third voltage when the first ferroelectric storage unit reads digital signal 1.

24. The control method of a memory circuit according to any one of claims 19 to 23, characterized by, The control method of the storage circuit further comprises: In the pre-charging phase, the second node is pre-charged.

25. The control method of a memory circuit according to any one of claims 19 to 24, characterized by, The storage circuit further comprises a reference voltage terminal; In the reading phase: The reference voltage terminal inputs a reference voltage to the comparison circuit, the voltage value of the reference voltage is between the third voltage when the first ferroelectric memory unit reads digital signal 0 and the third voltage when the first ferroelectric memory unit reads digital signal 1; The comparison circuit determines the data read by the first ferroelectric memory unit as digital signal 0 or digital signal 1 according to the third voltage and the reference voltage.

26. The control method of a memory circuit according to any one of claims 19 to 25, wherein The storage circuit further comprises a third switch electrically connected between the reference voltage terminal and the first node; In the reading phase, the third switch is turned off; In the writing phase, the third switch is turned on, and the writing signal of the reference voltage terminal is input to the first ferroelectric memory unit through the first node.

27. A storage circuit, comprising: The storage circuit comprises a ferroelectric memory unit, a clamping circuit, a voltage generating circuit, and a comparison circuit. The output terminal of the ferroelectric memory unit and one end of the clamping circuit are electrically connected to the first node; the other end of the clamping circuit, the voltage generating circuit, and the input terminal of the comparison circuit are electrically connected to the second node, and the output terminal of the comparison circuit is electrically connected to the output terminal of the storage circuit.

28. The storage circuit of claim 27, wherein, The voltage generating circuit comprises a first voltage terminal and a storage capacitor, and the storage capacitor is electrically connected between the second node and the first voltage terminal; In the pre-charging phase, the first voltage terminal is used to input the first voltage to the second node through the storage capacitor; In the reading phase, the ferroelectric memory unit is used to input the second voltage to the second node through the first node and the clamping circuit; In the reading phase, the first voltage terminal is used to input the third voltage to the second node through the storage capacitor.

29. The storage circuit of claim 28, wherein, The voltage generating circuit further comprises an inverter electrically connected between the first voltage terminal and the storage capacitor.

30. The storage circuit of claim 28 or 29, wherein, The clamping circuit comprises a first transistor and a second transistor, the first transistor is an N-type transistor, and the second transistor is a P-type transistor; the first transistor is electrically connected between the first node and the second transistor; In the reading phase, while the ferroelectric memory unit inputs the second voltage to the second node through the first node and the clamping circuit, the first transistor and the second transistor are turned on, and the second transistor is used to clamp the potential of the first node at 0V through the first transistor; While the voltage generating circuit inputs the third voltage to the second node, the first transistor is turned off.

31. The storage circuit of claim 30, wherein, The storage circuit further comprises a third transistor and a second voltage terminal; In the pre-charge phase, the second voltage terminal is configured to pre-charge the first node to 0V through the third transistor; wherein in the read phase, the first voltage is less than 0V, the second voltage is greater than 0V, and the voltage of the first node is greater than the sum of the first voltage and the second voltage.

32. The memory circuit of claim 31, wherein, the third transistor is electrically connected between the second node and the second voltage terminal; or, the third transistor is electrically connected between the third node and the second voltage terminal, and the third node is a connection node of the first transistor and the second transistor.

33. The memory circuit of any one of claims 28-32, wherein, in the read phase, the second node is configured to input a fourth voltage to the comparison circuit, and the fourth voltage is the sum of the first voltage, the second voltage, and the third voltage; the comparison circuit is configured to receive the fourth voltage input by the second node, and determine the data read by the ferroelectric memory cell as digital signal 0 or 1 according to the fourth voltage; wherein the fourth voltage is within the working voltage range of the comparison voltage.

34. The storage circuit of claim 30, wherein, the third voltage is the absolute value of the first voltage, and the fourth voltage is equal to the second voltage.

35. The storage circuit of any of claims 27-34, wherein, The memory circuit further comprises a third voltage terminal and a fourth transistor, and the fourth transistor is an N-type transistor. the gate of the fourth transistor is electrically connected to the second node, the first pole of the fourth transistor is electrically connected to the third voltage terminal, and the second pole of the fourth transistor is electrically connected to the input terminal of the comparison circuit.

36. A control method of a storage circuit, characterized by, The memory circuit comprises a ferroelectric memory cell, a clamping circuit, a voltage generation circuit, and a comparison circuit; the ferroelectric memory cell and the clamping circuit are electrically connected to a first node; the clamping circuit, the voltage generation circuit, and the comparison circuit are electrically connected to a second node; in the pre-charge phase, the first node is pre-charged to 0V, and the second node is pre-charged to a first voltage by the voltage generation circuit, and the first voltage is less than 0V; in the read phase: the ferroelectric memory cell inputs a second voltage to the second node through the first node and the clamping circuit, and the second voltage is greater than 0V; the clamping circuit clamps the potential of the first node to 0V; the voltage generation circuit inputs a third voltage to the second node, and the potential of the second node is a fourth voltage; the comparison circuit receives the fourth voltage input by the second node, and determines the data read by the ferroelectric memory cell as digital signal 0 or 1 according to the fourth voltage; wherein the fourth voltage is within the working voltage range of the comparison voltage.

37. The control method of a storage circuit according to claim 36, wherein the third voltage is the absolute value of the first voltage, and the fourth voltage is equal to the second voltage.

38. The control method of a storage circuit according to claim 36 or 37, wherein The memory circuit further comprises a third transistor and a second voltage terminal; and in the pre-charge phase, the first node is pre-charged to 0V, which comprises: In the pre-charge phase, the third transistor is turned on, and the second voltage terminal pre-charges the first node to 0V through the third transistor.

39. A memory, comprising: The memory circuit comprises a controller, and the memory circuit of any one of claims 1-18 or any one of claims 27-35, wherein the controller is configured to control the memory circuit to read and write data.

40. An electronic device, comprising: The memory circuit comprises a circuit board, and the memory circuit of claim 39, wherein the memory circuit is disposed on the circuit board.

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