Chip and electronic device

Abstract

The present application relates to the technical field of chips, and provides a chip and an electronic device, capable of mitigating the problem of insufficient winding resources in standard cells. The chip comprises a substrate and a first metal layer arranged on the substrate. The first metal layer is a metal layer arranged on the front side of the substrate and closest to the substrate. The chip comprises a first standard cell and a second standard cell connected in a first direction. The first standard cell has a first height in the first direction, the second standard cell has a second height in the first direction, and the first height is greater than the second height. The first metal layer comprises multiple first signal lines, multiple second signal lines, and a first dummy signal line, that are arranged in parallel in the first direction. The multiple first signal lines and the first dummy signal line are located in the first standard cell, the multiple second signal lines are located in the second standard cell, and the first dummy signal line is located between the multiple first signal lines and the multiple second signal lines.

Description

Chip and electronic device TECHNICAL FIELD

[0001] The present application relates to the chip technical field, and particularly relates to a chip and an electronic device. BACKGROUND

[0002] The backside power supply technology breaks the long-term tradition of processing signals and power transmission networks on the front side of a silicon wafer, and moves the power delivery network (PDN) from the front side of the wafer to the back side of the wafer. In this way, the IR drop problem is alleviated, the efficiency of the PDN is improved, and the wiring congestion problem of the back end of line (BEOL) is effectively improved. At the level of standard cells, more effective arrangement of interconnections can be achieved through collaborative optimization of design techniques, and the size of logic standard cells can be further reduced and the energy efficiency of standard cells can be optimized.

[0003] As the process node advances, the height of the standard cell (cell height) is continuously reduced, and the integration density is continuously increased. Due to the limitation of process capability, the metal line width often becomes a bottleneck that limits the reduction of the cell height. When the metal line width cannot be further reduced, the number of metal tracks available for winding in the cell often needs to be reduced. In the standard cell library, there are some standard cells with complex logic functions that need to use dense winding. When the number of metal winding roots is reduced, the winding resource is often in short supply. In order to meet the normal standard cell function, the area of the standard cell often needs to be increased, thereby generating additional parasitic capacitance and resistance, slowing down the signal transmission rate, or even failing to complete the winding even if the area is increased, thereby failing to function. SUMMARY

[0004] The present application provides a chip and an electronic device, which can improve the problem of insufficient winding resources in the standard cell.

[0005] The chip includes a substrate and a first metal layer disposed on the substrate. The first metal layer is the closest metal layer to the substrate among a plurality of metal layers disposed on the front surface of the substrate. The chip also includes a first standard cell and a second standard cell disposed in a first direction. The first standard cell has a first height in the first direction, and the second standard cell has a second height in the first direction, with the first height being greater than the second height. The first metal layer includes a plurality of metal wires disposed side by side in the first direction, and the plurality of metal wires includes a plurality of first signal lines, a plurality of second signal lines, and a first dummy signal line. The plurality of first signal lines and the first dummy signal line are located in the first standard cell, the plurality of second signal lines are located in the second standard cell, and the first dummy signal line is located between the plurality of first signal lines and the plurality of second signal lines.

[0006] In the chip provided in the present application, the first standard cell with a larger size and the second standard cell with a smaller size are disposed in the first direction, and the first dummy signal line is disposed in the first standard cell and located in the boundary of the first standard cell on the side close to the second standard cell. In this case, the first dummy signal line is disposed between the plurality of first signal lines and the plurality of second signal lines, thereby preventing crosstalk of signals loaded on the first signal lines and the second signal lines. In this arrangement, since the first dummy signal line is disposed inside the boundary of the first standard cell, no dummy signal line needs to be disposed on the side of the second standard cell close to the first standard cell, thereby reserving more space for the second signal lines. In this way, the number of second signal lines can be increased, thereby alleviating the problem of insufficient wire resources in the second standard cell, and further balancing the utilization of metal wires and balancing the performance of the second standard cell and the first standard cell.

[0007] In some possible implementation manners, the first standard cell is a high performance cell (HPC), and the second standard cell is a low power cell (LPC). The width of an active region in the high performance cell (HPC) is greater than the width of an active region in the low power cell (LPC), the rate of the high performance cell (HPC) is faster than the rate of the low power cell (LPC), and the energy consumption of the low power cell (LPC) is lower than the energy consumption of the high performance cell (HPC).

[0008] In some possible implementation manners, the plurality of metal wires further includes a second dummy signal line. The second dummy signal line is located in the first standard cell, and the second dummy signal line is located on the side of the plurality of first signal lines away from the first dummy signal line. In this case, no dummy signal line is disposed in the second standard cell, thereby more greatly increasing the wire resources of the second standard cell.

[0009] In some possible implementation manners, the first pitch between the metal wires in the first standard cell is the same as the second pitch between the metal wires in the second standard cell. In this way, the area of the standard cell can be guaranteed unchanged, and the process difficulty is not increased.

[0010] In some possible implementation manners, the first pitch between the metal wires in the first standard cell is greater than the second pitch between the metal wires in the second standard cell. By flexibly adjusting the pitch of the metal wires in the first standard cell, which is different from the pitch of the metal wires in the second standard cell, the problem of insufficient wire resources in the second standard cell can be solved, and the performance of the first standard cell can be further improved to meet higher speed requirements.

[0011] In some possible implementation manners, the second standard cell includes a multiplexer (MUX) or a scan D flip-flop (SDFQ). By increasing the wire resources in the second standard cell, the needs of the multiplexer (MUX) or the scan D flip-flop (SDFQ) for the wires can be well met.

[0012] In some possible implementation manners, the number of the plurality of first signal lines is greater than or equal to 4, and the number of the plurality of second signal lines is greater than or equal to 4. In this way, for some standard cells (such as MUX, SDFQ, etc.) that need to use complex wires, the needs of the wires can be well met.

[0013] In some possible implementation manners, the chip further includes a power supply network, and the power supply network is arranged on the back surface of the substrate. The power supply network can also be referred to as a backside power delivery network (BSPDN). In this case, not only can the IR drop (current resistance voltage drop) problem be alleviated, but also the efficiency of the power supply network can be improved, and the wiring congestion problem of the back-end process can also be improved.

[0014] In some possible implementation manners, the back surface of the substrate further includes a third signal line, and the third signal line is located in the first standard cell. In this way, one signal line can be added in the first standard cell, that is, the metal wire resources in the first standard cell are increased.

[0015] In some possible implementation manners, the back surface of the substrate further includes a fourth signal line, and the fourth signal line is located in the second standard cell. In this way, one signal line can be added in the second standard cell, that is, the metal wire resources in the second standard cell are increased.

[0016] In some possible implementation manners, the third signal line, the fourth signal line and the power supply network are located in the metal layer closest to the substrate among the plurality of metal layers on the back surface of the substrate. In this way, it is easier to realize the connection of the third signal line, the fourth signal line and the power supply network with the devices on the front surface of the substrate.

[0017] In some possible implementation manners, the front surface of the substrate is provided with field effect transistors located in the first standard cell and the second standard cell respectively; the field effect transistors include at least one of fin field effect transistors or ring gate field effect transistors. In this case, the chip adopts an advanced process, and the standard cells have higher requirements for wiring resources.

[0018] In some possible implementation manners, the chip further includes: two third standard cells arranged in the first direction in a splicing manner, and two fourth standard cells arranged in the first direction in a splicing manner; wherein the third standard cells are the same type of standard cells as the first standard cells, and the fourth standard cells are the same type of standard cells as the second standard cells. The distance between adjacent active regions in the two third standard cells is W1, and the distance between adjacent active regions in the two fourth standard cells (LPC) is W2. The first standard cell and the second standard cell have a first boundary, and the distance between the first boundary and the active region in the first standard cell is W1 / 2, and the distance between the first boundary and the active region in the second standard cell is W2 / 2. In this case, the boundary position between the first standard cell and the second standard cell in the new splicing manner can be determined by first determining W1 and W2.

[0019] The application also provides an electronic device including a circuit board and a chip provided in any of the possible implementation manners described above, and the chip is electrically connected to the circuit board. BRIEF DESCRIPTION OF DRAWINGS

[0020] FIG. 1 is a schematic diagram of two standard cells with different sizes in a chip according to the prior art;

[0021] FIG. 2 is a schematic diagram of the interlayer structure of the two standard cells with different sizes in FIG. 1;

[0022] FIG. 3 is a schematic diagram of two standard cells with different sizes in a chip according to an embodiment of the application;

[0023] FIG. 4 is a schematic diagram of the interlayer structure of the two standard cells with different sizes in FIG. 3;

[0024] FIG. 5 is a schematic diagram of the distance between active regions in standard cells in a plurality of splicing manners;

[0025] FIG. 6 is a schematic diagram of two standard cells with different sizes in a chip according to an embodiment of the application;

[0026] Fig. 7 is a schematic diagram of a comparison between two standard cells of different sizes in a chip according to the prior art and an embodiment of the present application;

[0027] Fig. 8 is a schematic diagram of an interlayer structure of two standard cells of different sizes in a chip according to an embodiment of the present application. DETAILED DESCRIPTION

[0028] For the purpose of clarity, technical solutions and advantages of the present application will be described below in conjunction with the drawings in the present application. Obviously, the described embodiments are only some of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative work fall within the scope of protection of the present application.

[0029] The terms "first", "second", etc. in the description of the embodiments of the present application and the claims and drawings are only for the purpose of distinguishing description, and cannot be understood as indicating or implying relative importance, nor can they be understood as indicating or implying sequence. "At least one" means one or more, and "multiple" means two or more. "Connection", "connection", etc. should be understood in a broad sense, for example, it can be electrical connection, or mechanical connection; it can be fixed connection, or detachable connection, or integrally connected; it can be direct connection, or indirect through intermediate medium, or internal communication of two elements. In addition, the terms "include" and "have" and any variations thereof are intended to cover non-exclusive inclusion, for example, a series of steps or units. The method, product or device does not have to be limited to those steps or units clearly listed, but can include other steps or units not clearly listed or inherent to these processes, methods, products or devices. "Up", "down", "left", "right", etc. are only used in relation to the orientation of the components in the drawings, and these directional terms are relative concepts, which are used for relative description and clarification, and can change accordingly according to the change of the orientation of the components in the drawings.

[0030] An electronic device is provided in an embodiment of the present application, which adopts a new type of chip. By balancing the winding resources of large size standard cells to small size standard cells, the problem of insufficient winding resources in small size standard cells is improved, and the performance of each standard cell is balanced.

[0031] The electronic device is not limited in the form of the above arrangement, and can be any electronic product provided with the chip, such as consumer electronics, home electronics, vehicle-mounted electronics, financial terminal products, communication electronics, etc.

[0032] The consumer electronic product can be a mobile phone, a tablet computer, a notebook computer, a personal computer (PC), a personal digital assistant (PDA), a smart wearable product (for example, a smart watch, a smart bracelet, etc.), a virtual reality (VR) terminal device, an augmented reality (AR) terminal device, a drone, etc. The home electronic product can be a smart door lock, a television, a smart speaker, a refrigerator, a sweeping robot, etc. The vehicle-mounted electronic product can be a vehicle-mounted navigator, a vehicle-mounted display, etc. The financial terminal product can be an automated teller machine (ATM), a self-service electronic device, etc. The communication electronic product can be a server, a memory, a radar, a base station, etc.

[0033] According to actual needs, other devices such as a printed circuit board (PCB) and an input / output device can be electrically connected to the chip, and the present application does not limit this.

[0034] The following describes a new chip structure provided by the embodiments of the present application in combination with the prior art.

[0040] FIG. 1 is a schematic diagram of two standard cells of different sizes in a chip.

[0036] FIG. 2 is a schematic diagram of the interlayer structure of the two standard cells of different sizes in FIG. 1.

[0037] The X direction and the Y direction in FIG. 1 can be referred to as a horizontal plane, which is substantially parallel to the substrate plane. The Z direction is perpendicular to the horizontal plane and can be referred to as a vertical direction. The Y direction can be referred to as a first direction, the X direction can be referred to as a second direction, and the Z direction can be referred to as a third direction.

[0038] According to actual functional requirements, a plurality of different standard cells (STC) can be provided in the chip, and each standard cell can be designed to perform a predefined function, such as an inverter, an AND gate, a register, a full adder, a multiplexer (MUX), a scan D flip-flop (SDFQ), etc.

[0039] Of course, standard cells with different functions can have different sizes. When a dense-wiring standard cell needs to be provided in a small-size standard cell, such as a MUX or a SDFQ, a problem of insufficient wiring resources may occur.

[0040] The present application is further described below in connection with a high performance cell (HPC) having a large size and a low power cell (LPC) having a small size.

[0041] For example, referring to FIG. 1, according to a functional division, the standard cells in the chip can include a high performance cell (HPC), a low power cell (LPC), and the like. The high performance cell (HPC) has a high speed, and a width of an active area AA (i.e., a region of the NS GAA) arranged inside the high performance cell (HPC) is large, in which case the high performance cell (HPC) has a large cell height (a first height H1). The low power cell (LPC) has a low power consumption, and a width of an active area AA arranged inside the low power cell (LPC) is small, in which case the low power cell (LPC) has a small cell height (a second height H2). The first height H1 is greater than the second height H2 (H1 > H2).

[0042] That is, in the Y direction, a size (H1) of the high performance cell (HPC) is greater than a size (H2) of the low power cell (LPC), a width of the active area AA in the high performance cell (HPC) is greater than a width of the active area AA in the low power cell (LPC), a speed of the high performance cell (HPC) is faster than a speed of the low power cell (LPC), and a power consumption of the low power cell (LPC) is lower than a power consumption of the high performance cell (HPC).

[0043] For example, in some possible implementations, the width of the active area AA in the high performance cell (HPC) can be twice or more than the width of the active area AA in the low power cell (LPC).

[0044] On this basis, continuing to refer to FIG. 2, the chip includes a substrate 10 in a thickness direction, a back surface of the substrate 10 is provided with a back side power supply network BSPDN (which can also be referred to as a back power supply network), and the back side power supply network BSPDN can include power supply lines (VDD, VSS). A front surface of the substrate 10 is provided with a field effect transistor (NS GAA) in a front end of line (FEOL) and a plurality of metal windings (a, b) in a back end of line (BEOL), and the plurality of metal windings (a, b) can meet the supply needs of the standard cells (HPC, LPC).

[0045] In combination with FIG. 1 and FIG. 2, the plurality of metal wires (a, b) are located in the metal layer of the back-end-of-line (BEOL), and the plurality of metal wires (a, b) include a signal line a and a dummy signal line b. Among them, the signal line a is used to transmit signals to meet the interconnection requirements of the standard cell (HPC, LPC), and the dummy signal line b is used to isolate the signal line a in the adjacent standard cell to avoid crosstalk of the signals transmitted by the signal line a in the adjacent standard cell. Of course, the arrangement of the dummy signal line b can better meet the independent design of the standard cell.

[0046] On this basis, with continued reference to FIG. 2, in the prior art, when the high-performance cell (HPC) and the low-power cell (LPC) are arranged in a splicing manner in the Y direction, the dummy signal line b is located on the boundary of the two standard cells (HPC, LPC) arranged in a splicing manner, that is, the dummy signal line b is partially located in the high-performance cell (HPC) and partially located in the low-power cell (LPC) to isolate the two different standard cells and prevent crosstalk of the signals transmitted by the signal line. In this case, as shown in FIG. 2, the high-performance cell (HPC) includes 5 signal lines a and an equivalent dummy signal line b; and the low-power cell (LPC) includes 3 signal lines a and an equivalent dummy signal line b.

[0047] It should be understood that, in the prior art, with reference to FIG. 2, the cell height of the standard cell (such as LPC, HPC) refers to the size in the width direction of the metal wire (a, b) (that is, the first direction Y), which is determined based on the distance between the center lines of the two dummy signal lines b above the standard cell. In this case, the boundary of the standard cell can be determined based on the center line of the dummy signal line b, and for the boundary between the two standard cells (such as LPC and HPC) arranged in a splicing manner, the center line of the dummy signal line b shared by the two standard cells can be used for determination.

[0048] It should also be understood that the greater the cell height of the standard cell, the more metal wires can be arranged, and the more abundant the wire resources.

[0049] That is, the high-performance cell (HPC) has relatively abundant wire resources and can layout more metal wires (a, b), and the wire resources of the low-power cell (LPC) are relatively small and can layout less metal wires (a, b).

[0050] In the low power cell (LPC), when a standard cell with dense routing is needed, such as MUX, SDFQ, etc., 3 signal lines a cannot meet the requirement, which may cause functional failure; or the size along the X direction needs to be increased to layout the signal lines, which may cause waste of chip area, increase of signal line length, and further cause additional parasitic capacitance and resistance, increase of BEOL loading, slow signal transmission speed, and even functional failure even if the area is increased.

[0051] Based on this, the embodiment of the present application provides a new technical solution, which can balance the routing resources in the high performance cell (HPC) to the low power cell (LPC) by rearranging the metal routing (signal line and pseudo signal line), so as to increase the number of signal lines in the low power cell (LPC), thereby solving the problem of insufficient routing resources in the low power cell (LPC), and further balancing the utilization rate of metal routing and balancing the performance of the high performance cell (HPC) and the low power cell (LPC).

[0052] The new chip structure provided by the embodiment of the present application is described below.

[0053] FIG. 3 is a schematic diagram of the splicing of the high performance cell (HPC) and the low power cell (LPC) provided in the embodiment of the present application.

[0054] FIG. 4 is a schematic diagram of the interlayer structure of the high performance cell (HPC) and the low power cell (LPC) in FIG. 3.

[0055] As shown in FIG. 3, the chip includes a high performance cell (HPC) and a low power cell (LPC), and the high performance cell (HPC) and the low power cell (LPC) are spliced along the Y direction. In other words, the layout of the high performance cell (HPC) and the layout of the low power cell (LPC) are spliced along the Y direction.

[0056] As shown in FIG. 4, in the interlayer structure, the chip includes a substrate 10 (such as a silicon substrate), and a field effect transistor in the front-end-of-line (FEOL) and a first metal layer (M0) in the back-end-of-line (BEOL) are arranged on the front surface of the substrate 10. A back surface of the substrate 10 is provided with a power supply network BSPDN, which can include power lines (VDD, VSS). The power lines pass through the substrate and are connected with the field effect transistor (NS GAA) to supply power to the field effect transistor (NS GAA). It should be understood that the power lines (VDD, VSS) can be isolated from the active region on the front surface through the substrate 10, thereby meeting the functional requirements of the chip.

[0057] The above-mentioned field effect transistor can be a gate-all-around field effect transistor (GAA), a finfet (fin field effect transistor), which is not limited in the present application. In the embodiments of the present application, only a nano sheet (NS) type GAA (referred to as NS GAA) is taken as an example for illustration.

[0058] The first metal layer (M0) can be one of the metal layers in the back-end-of-line (BEOL) closest to the substrate 10, that is, the M0 metal layer, which can also be referred to as the frontside metal 1 (FM1).

[0059] As shown in FIGS. 3 and 4, the first metal layer (M0) includes a plurality of metal wires arranged side by side along the Y direction, and the plurality of metal wires include a plurality of first signal lines a1, a plurality of second signal lines a2, a first dummy signal line b1, and a second dummy signal line b2. The plurality of first signal lines a1 are located in the high-performance unit (HPC) and are electrically connected to the field effect transistors (NS GAA) in the high-performance unit (HPC), and signal transmission is performed through the plurality of first signal lines a1 to meet the functional requirements of the high-performance unit (HPC). The plurality of second signal lines a2 are located in the low-power-consumption unit (LPC) and are electrically connected to the field effect transistors (NS GAA) in the low-power-consumption unit (LPC), and signal transmission is performed through the plurality of second signal lines a2 to meet the functional requirements of the low-power-consumption unit (LPC).

[0060] Continuing to refer to FIGS. 3 and 4, unlike the arrangement of the dummy signal lines in FIG. 1, in the design scheme of the present application, the first dummy signal line b1 and the second dummy signal line b2 are arranged in the high-performance unit (HPC), the first dummy signal line b1 is located within the boundary of the high-performance unit (HPC) close to the low-power-consumption unit (LPC), and the second dummy signal line b2 is located within the boundary of the high-performance unit (HPC) away from the low-power-consumption unit (LPC), that is, the first dummy signal line b1 and the second dummy signal line b2 are distributed on both sides of the plurality of first signal lines a1 and are located within the boundary of the high-performance unit (HPC). In this case, the first dummy signal line b1 is arranged between the plurality of first signal lines a1 and the plurality of second signal lines a2, thereby preventing crosstalk of signals loaded on the first signal lines a1 and the second signal lines a2.

[0061] In this arrangement, as shown in FIGS. 3 and 4, since the first dummy signal line b1 is arranged inside the boundary of the high-performance unit (HPC), no dummy signal line is needed to be arranged on the side of the low-power-consumption unit (LPC) close to the high-performance unit (HPC), thereby leaving more space for the arrangement of the second signal line a2, which can increase the number of the second signal line a2, thereby relieving the problem of insufficient routing resources in the low-power-consumption unit (LPC), and further balancing the utilization of metal routing and balancing the performance of the low-power-consumption unit (LPC) and the high-performance unit (HPC).

[0062] It should be noted that in the novel splicing manner of the present application, the position of the dummy signal line is adjusted, and thus the "boundary" between the standard units is different from that in the prior art.

[0063] In the novel splicing manner, the boundary between the high-performance unit (HPC) and the low-power-consumption unit (LPC) can be determined based on the same type of standard units arranged in the chip in the prior manner. The same type of standard units refer to standard units having the same function, and the same type of standard units have the same unit height and the same or approximately the same arrangement of active areas AA.

[0064] For example, as shown in FIG. 5(a), two other high-performance units (HPC) of the same type arranged in the prior manner can be determined in the chip, and the spacing W1 between the two active areas AA on both sides of the boundary. Similarly, as shown in FIG. 5(b), two other low-power-consumption units (LPC) of the same type arranged in the prior manner can be determined in the chip, and the spacing W2 between the two active areas AA on both sides of the boundary. In the high-performance unit (HPC) and the low-power-consumption unit (LPC) in the novel splicing manner, as shown in FIG. 5(c), the distance between the active area AA in the high-performance unit (HPC) and the boundary m is approximately W1 / 2, and the distance between the active area AA in the low-power-consumption unit (LPC) and the boundary m is approximately W2 / 2, i.e., the distance W between the active area AA in the high-performance unit (HPC) and the active area AA in the low-power-consumption unit (LPC) is approximately the sum of W1 / 2 and W2 / 2, i.e., W = W1 / 2 + W2 / 2.

[0065] Therefore, in practice, the position of the boundary m between the high-performance unit (HPC) and the low-power-consumption unit (LPC) in the novel splicing manner can be determined by first measuring W1 and W2.

[0066] In order to relieve the problem of insufficient winding resources of the low power cell (LPC) to a greater extent, with reference to FIG. 3 or FIG. 4, the dummy signal line can be arranged in another high performance cell (HPC) on the side of the low power cell (LPC) away from the high performance cell (HPC). That is, the dummy signal line is not arranged in the low power cell (LPC), so as to reserve more space for the arrangement of the second signal line a2. In this way, the winding resources in the low power cell (LPC) can be reserved for the second signal line a1 entirely, so as to further increase the number of the second signal line a2 and better balance the utilization rate of the metal winding.

[0067] Compared with the winding mode of FIG. 1, the high performance cell (HPC) is arranged with 5 signal lines a and one dummy signal line b (equivalent), and the low power cell (LPC) is arranged with 3 signal lines a and one dummy signal line b (equivalent). However, the new winding mode of the present application is adopted, as shown in FIG. 3, the winding resources of the high performance cell (HPC) are balanced to the low power cell (LPC), so that the high performance cell (HPC) is arranged with 4 signal lines (a1) and 2 dummy signal lines (b1, b2), and the low power cell (LPC) is arranged with 4 signal lines (a2) without dummy signal line. This arrangement mode can realize the circuit function without expanding the area of the low power cell (LPC), or even can reduce the area of the low power cell (LPC). At the same time, this arrangement mode has low process difficulty and does not change the layout distribution of the back side power supply network BSPDN of the substrate 10.

[0068] It should be understood that, compared with some prior art, the size along the Y direction needs to be expanded to layout the signal line, which leads to the waste of the area of the chip and the increase of the length of the signal line. However, by adopting the arrangement mode of the present application, the area can be saved, the winding can be shortened and the RC (resistance-capacitance) benefit can be brought, and the problem of unbalanced loading in the back end (BEOL) can be avoided.

[0069] Through actual layout verification, in the case that the complex standard cell (such as MUX, SDFQ, etc.) is adopted in the low power cell (LPC), the existing design mode cannot generate the layout, but the design mode of the present application can realize the functional circuit without expanding the area of the standard cell, or even reducing the area of the standard cell.

[0070] It should be noted that FIG. 1 and FIG. 3 are only schematic and are used to illustrate the case of balancing one signal line from the high performance cell (HPC) to the low power cell (LPC), but the present application is not limited thereto. In some possible implementation modes, two or more signal lines can be balanced from the high performance cell (HPC) to the low power cell (LPC).

[0071] It should be noted that the number of signal lines in the high performance unit (HPC) and the low power consumption unit (LPC) is 4 in the schematic illustration of FIG. 3 and FIG. 4, but the present application is not limited thereto.

[0072] For example, in some possible implementations, the number of signal lines in the high performance unit (HPC) can be greater than the number of signal lines in the low power consumption unit (LPC).

[0073] For another example, in some possible implementations, the number of signal lines in the high performance unit (HPC) can be less than the number of signal lines in the low power consumption unit (LPC).

[0074] For yet another example, in some possible implementations, the number of signal lines in the high performance unit (HPC) can be equal to the number of signal lines in the low power consumption unit (LPC).

[0075] Of course, in order to better meet the functional requirements of the high performance unit (HPC) and the low power consumption unit (LPC), in some possible implementations, the number of signal lines in the high performance unit (HPC) and the low power consumption unit (LPC) can be set to be greater than or equal to 4, so that in the case that some standard units (such as MUX, SDFQ, etc.) need to use complex winding, the functional requirements thereof can be met.

[0076] Compared with the case that the second dummy signal line b2 is arranged in the high performance unit (HPC) in FIG. 3, the present application further provides another possible implementation, as shown in FIG. 6, the second dummy signal line b2 can be arranged on the boundary of the high performance unit (HPC) away from the low power consumption unit (LPC), part of the second dummy signal line b2 is in the high performance unit (HPC), and the other part can be in another standard unit (HPC or LPC). In this way, the design flexibility of the standard unit can be improved.

[0077] In addition, compared with the case that the low power consumption unit (LPC) is not provided with a dummy signal line in FIG. 3, the present application further provides another possible implementation, as shown in FIG. 6, a dummy signal line can be arranged on the boundary of the low power consumption unit (LPC) away from the high performance unit (HPC), that is, part of the dummy signal line is in the low power consumption unit (LPC), and the other part can be in another standard unit (HPC or LPC). In this way, the design flexibility of the standard unit can be improved.

[0078] In order to facilitate the manufacturing of metal wires and reduce manufacturing costs, in some possible implementation manners, as shown in FIG. 3, the pitch of metal wires in a standard cell can be set, for example, the first signal lines a1, the first dummy signal line b1 and the second dummy signal line b2 in the high performance cell (HPC) are set at the same pitch, and the second signal lines a2 in the low power cell (LPC) are set at the same pitch.

[0079] The pitch mentioned above refers to the center distance between two adjacent metal wires; for metal wires with equal intervals, it can also be the sum of the width of a metal wire and an interval (with the interval of adjacent wires).

[0080] Of course, the present application does not specifically limit the pitch size of metal wires in different standard cells, which can be set as needed in practice.

[0081] For example, in some possible implementation manners, the pitch (first pitch P1) of metal wires (b1, a1) in the high performance cell (HPC) can be set equal to the pitch (second pitch P2) of metal wires (a2) in the low power cell (LPC), that is, P1=P2.

[0082] For another example, in some possible implementation manners, the pitch (first pitch P1) of metal wires (b1, a1) in the high performance cell (HPC) can be set greater than the pitch (second pitch P2) of metal wires (a2) in the low power cell (LPC), that is, P1>P2.

[0083] By using the novel winding manner of the present application, the number of signal lines, the pitch of signal lines and the boundary position of the standard cell in the standard cell can be flexibly adjusted according to actual needs.

[0084] The following will compare the metal wires of the prior art and the present application by combining FIG. 7. In FIG. 7, (1) is a schematic diagram of metal wires of the high performance cell (HPC) and the low power cell (LPC) in the prior art, and (2) is a schematic diagram of the metal wires in (1) adjusted by using the novel winding manner of the present application.

[0085] Referring to (1) shown in FIG. 7, in some prior art, the high performance cell (HPC) has a first height H1, and the high performance cell (HPC) contains 5 signal lines a and one dummy signal line b (equivalent). The low power cell (LPC) has a second height H2 (H2

[0086] Referring to (2) shown in FIG. 7, after adjustment by using the novel winding mode of the present application, the height of the high-performance unit (HPC) and the low-power-consumption unit (LPC) can remain unchanged (i.e., the boundary remains unchanged), while the winding in the high-performance unit (HPC) is adjusted to 4 first signal lines a1 and 2 pseudo signal lines (b1, b2), and the winding in the low-power-consumption unit (LPC) is adjusted to 5 second signal lines a2, without setting a pseudo signal line. Moreover, the pitch of the metal winding (a1, b1, b2) in the high-performance unit (HPC) is adjusted to a first pitch P1, and the first pitch P1 can be greater than the pitch P. The pitch of the metal winding (a2) in the low-power-consumption unit (LPC) is adjusted to a second pitch P2, and the second pitch P2 can be less than the pitch P, i.e., P1>P>P2.

[0087] That is, after adjustment by using the novel winding mode of the present application, the number of signal lines (a2) in the low-power-consumption unit (LPC) can be increased without increasing the area of the low-power-consumption unit (LPC) (i.e., without changing the boundary), the pitch of the metal winding (P2) is reduced, and the pitch of the metal winding (P1) in the high-performance unit (HPC) is increased. In this way, the problem of insufficient winding resources in the low-power-consumption unit (LPC) can be solved, and the performance of the high-performance unit (HPC) can be further improved to meet higher speed requirements.

[0088] In addition, as shown in FIG. 8, in some possible implementations, a third signal line a3 can also be provided on the back surface of the substrate 10, the third signal line a3 being located in the high-performance unit (HPC) and electrically connected to the field effect transistor (NS GAA) in the high-performance unit (HPC) to perform signal transmission through the third signal line a3. In this way, one signal line can be added in the high-performance unit (HPC) to increase the metal winding resources of the high-performance unit (HPC).

[0089] As shown in FIG. 8, for example, 4 signal lines (a1) are provided on the front surface of the substrate 10 in the high-performance unit (HPC), and 1 signal line (a3) is added on the back surface, so that the high-performance unit (HPC) has 5 signal lines.

[0090] Continuing to refer to FIG. 8, in some possible implementations, a fourth signal line a4 can also be provided on the back surface of the substrate 10, the fourth signal line a4 being located in the low-power-consumption unit (LPC) and electrically connected to the field effect transistor (NS GAA) in the low-power-consumption unit (LPC) to perform signal transmission through the fourth signal line a4. In this way, one signal line can be added in the low-power-consumption unit (LPC) to increase the metal winding resources of the low-power-consumption unit (LPC).

[0091] As shown in Fig. 8, in the low power consumption unit (LPC), four signal lines (a2) are arranged on the front side of the substrate 10, and one signal line (a4) is added on the back side, in which case, the low power consumption unit (LPC) has five signal lines.

[0092] In order to simplify the manufacturing process and reduce the manufacturing cost, the third signal line a3 and the fourth signal line a4 can be located in the same metal layer on the back side of the substrate 10. In this way, the manufacturing of the third signal line a3 and the fourth signal line a4 can be completed by one photoetching process.

[0093] Of course, in order to further simplify the manufacturing process and reduce the manufacturing cost, the third signal line a3 and the fourth signal line a4 can be located in the same metal layer as the power lines (VDD, VSS) in the power supply network BSPDN. In this way, the manufacturing of the third signal line a3 and the fourth signal line a4 can be completed at the same time as the manufacturing of the power supply network BSPDN.

[0094] In some possible implementations, the metal layer in which the third signal line a3, the fourth signal line a4 and the power supply network BSPDN can be located can be the metal layer closest to the substrate 10 among the multiple metal layers on the back side of the substrate 10, i.e., the backside first metal layer (BM1). In this way, it is easier to realize the connection of the third signal line a3, the fourth signal line a4 and the power supply network BSPDN with the devices on the front side of the substrate 10.

[0095] It should be noted that the above embodiments are described by taking the large-size high-performance unit (HPC) and the small-size low-power consumption unit (LPC) as examples, and other standard units of different sizes can also be arranged according to the high-performance unit (HPC) and the low-power consumption unit (LPC), which will not be described herein.

[0096] The above description is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art can easily think of changes or replacements within the technical range disclosed in the present application, which should be covered in the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. A chip, characterized by The chip comprises a substrate, a first metal layer; the first metal layer is one of a plurality of metal layers arranged on the front surface of the substrate and closest to the substrate; The chip further comprises a first standard unit and a second standard unit arranged in a first direction; the first standard unit has a first height in the first direction, the second standard unit has a second height in the first direction, and the first height is greater than the second height; The first metal layer comprises a plurality of metal wires arranged side by side in the first direction; the plurality of metal wires comprises a plurality of first signal lines, a plurality of second signal lines, and a first dummy signal line; The plurality of first signal lines and the first dummy signal line are located in the first standard unit, the plurality of second signal lines are located in the second standard unit, and the first dummy signal line is located between the plurality of first signal lines and the plurality of second signal lines.

2. The chip of claim 1, wherein The first standard unit is a high-performance unit, and the second standard unit is a low-power unit.

3. The chip of claim 1 or 2, wherein The plurality of metal wires further comprises a second dummy signal line; The second dummy signal line is located in the first standard unit, and the second dummy signal line is located on the side of the plurality of first signal lines away from the first dummy signal line.

4. The chip of any one of claims 1-3, wherein The metal wires in the first standard unit have a first pitch; The metal wires in the second standard unit have a second pitch; The first pitch is the same as the second pitch.

5. The chip of any one of claims 1-3, wherein The metal wires in the first standard unit have a first pitch; The metal wires in the second standard unit have a second pitch; The first pitch is greater than the second pitch.

6. The chip of any one of claims 1-5, wherein The number of the plurality of first signal lines is greater than or equal to 4; The number of the plurality of second signal lines is greater than or equal to 4.

7. The chip of any one of claims 1-6, wherein The second standard unit is a multiplexer (MUX) or a scan D flip-flop (SDFQ).

8. The chip of claim 7, wherein The chip further comprises a power supply network arranged on the back surface of the substrate.

9. The chip of any one of claims 1-8, wherein The back surface of the substrate further comprises a third signal line, and the third signal line is located in the first standard unit.

10. The chip of any one of claims 1-9, wherein The back surface of the substrate further comprises a fourth signal line, and the fourth signal line is located in the second standard unit.

11. The chip of claim 10, wherein The third signal line, the fourth signal line, and the power supply network are located in the metal layer closest to the substrate among a plurality of metal layers on the back surface of the substrate.

12. The chip of any one of claims 1-11, wherein: the front side of the substrate is provided with field effect transistors located in the first standard cell and the second standard cell, respectively; the field effect transistors comprise at least one of fin field effect transistors or ring gate field effect transistors; a size of the field effect transistors in the first standard cell is greater than a size of the field effect transistors in the second standard cell.

13. The chip of any one of claims 1-12, wherein: the chip further comprises two third standard cells arranged in the first direction and two fourth standard cells arranged in the first direction; the third standard cells are of the same type as the first standard cells, and the fourth standard cells are of the same type as the second standard cells; a spacing between adjacent active regions in the two third standard cells is W1, and a spacing between adjacent active regions in the two fourth standard cells is W2; a first boundary is between the first standard cell and the second standard cell, and a distance between the first boundary and an active region in the first standard cell is W1 / 2, and a distance between the first boundary and an active region in the second standard cell is W2 / 2.

14. An electronic device, comprising: a circuit board, and the chip of any one of claims 1-13, wherein the chip is electrically connected to the circuit board.

Images