Data transmission methods, product, device and medium

Abstract

The present application relates to the technical field of computers. Disclosed are data transmission methods, a product, a device and a medium. In the present solution, a microcontroller is provided at an accelerator end, and is used for receiving DMA configuration information sent by a host end, and transmitting the DMA configuration information to a processor at the accelerator end, that is, an out-of-band configuration method is used; multiple pieces of DMA configuration information can be received in batch, thereby avoiding waiting for one configuration information transmission to complete before initiating the next transmission, and effectively improving the data transmission efficiency; in addition, at the accelerator end, DMA transmission is controlled by the microcontroller, and the processor is only responsible for data transmission and computation, and therefore the logic development difficulty of the processor is reduced. Moreover, in the solution, the DMA configuration information is transmitted by means of a first communication bus, and target data corresponding to the DMA configuration information is transmitted by means of a second communication bus, such that a DMA operation can be executed in real time, thereby improving the real-time performance of data transmission.

Description

Data transmission method, product, device and medium

[0001] Cross-reference to related applications

[0002] The present application claims priority to the Chinese patent application No. 202411329392.6, filed on September 24, 2024, and entitled "A data transmission method, product, device and medium", the content of which is incorporated herein by reference in its entirety. TECHNICAL FIELD

[0003] The present application relates to the technical field of computers, and in particular to a data transmission method, product, device and medium. BACKGROUND

[0004] To meet the increasing demand for computing power of big data, cloud computing and other technologies, data centers often use methods to improve server computing power and expand accelerators. Direct memory access (DMA) as the fastest data transmission method in the Peripheral Component Interconnect Express (PCIE) interface can effectively free up the Central Processing Unit (CPU) and improve transmission efficiency.

[0005] DMA transmission methods include block DMA and chain DMA. When block DMA is transmitted, the CPU sets the source address, destination address and length, and the DMA controller can transmit data, and notifies the host through an interrupt after transmission is completed. However, block DMA can only transmit data of one continuous physical memory block at a time, and the transmission efficiency of discrete memory blocks is low. Chain DMA records the transmission information of discrete memory blocks through descriptors, and the device side performs DMA data transmission according to the descriptors, and continues to perform the next transmission according to the address information in the descriptors after the completion of the transmission, until all descriptors are executed. Although chain DMA can solve the transmission problem of multiple data blocks, the number of blocks transmitted at a time is limited, and the next transmission cannot be initiated until the completion of the current transmission, which is inefficient. SUMMARY

[0006] The purpose of the present application is to provide a data transmission method, product, device and medium to solve the problem of low data transmission efficiency caused by the need to wait for the completion of the current transmission before initiating the next transmission in the current DMA transmission method.

[0007] To solve the above technical problems, the present application provides a data transmission method applied to a host side; the method comprises:

[0008] Obtaining each direct memory access configuration information; wherein the direct memory access configuration information comprises a source address, a destination address and a transmission length;

[0009] Sending each direct memory access configuration information to the microcontroller at the accelerator end through the first communication bus, so that the microcontroller at the accelerator end caches each direct memory access configuration information, and sends each direct memory access configuration information to the processor at the accelerator end, and the processor at the accelerator end calls a direct memory access mover based on each direct memory access configuration information and the direct memory access controller, and obtains target data corresponding to each direct memory access configuration information from the memory at the accelerator end through the direct memory access mover;

[0010] Receiving each target data transmitted by the processor at the accelerator end through the second communication bus.

[0011] In some embodiments, before obtaining each direct memory access configuration information, further comprising:

[0012] Setting a preset number of caches based on the memory application;

[0013] Setting data sending caches and data receiving caches based on all the caches;

[0014] Respectively recording the cache size, the first address and the use state of each cache.

[0015] In some embodiments, obtaining each direct memory access configuration information comprises:

[0016] Monitoring a direct memory access configuration information sending request;

[0017] When receiving the direct memory access configuration information sending request, copying each direct memory access configuration information corresponding to the direct memory access configuration information sending request to each data sending cache;

[0018] According to the first address of each data sending cache, obtaining the direct memory access configuration information in each data sending cache.

[0019] In some embodiments, receiving each target data transmitted by the processor at the accelerator end through the second communication bus comprises:

[0020] Monitoring a target data receiving request;

[0021] When receiving the target data receiving request, determining the size of each target data according to the target data receiving request;

[0022] According to the size of each target data, the cache size and the use state of each data receiving cache, determining a target data receiving cache in all the data receiving caches;

[0023] The first address of each target data receiving buffer is acquired, and each target data is stored in the corresponding target data receiving buffer according to the first address of each target data receiving buffer.

[0024] In some embodiments, the microcontroller at the accelerator end caches each direct memory access configuration information, including:

[0025] The microcontroller at the accelerator end stores each direct memory access configuration information in the corresponding cache queue;

[0026] The microcontroller at the accelerator end sets the state flag of the cache queue storing the direct memory access configuration information to indicate that the cache queue is occupied.

[0027] In some embodiments, the microcontroller at the accelerator end sends each direct memory access configuration information to the processor at the accelerator end, including:

[0028] The microcontroller at the accelerator end acquires each direct memory access configuration information based on each cache queue;

[0029] The microcontroller at the accelerator end sends each direct memory access configuration information to the processor at the accelerator end through the third communication bus.

[0030] In some embodiments, after the microcontroller at the accelerator end sends each direct memory access configuration information to the processor at the accelerator end through the third communication bus, it further includes:

[0031] The microcontroller at the accelerator end monitors the transmission completion information transmitted by the processor at the accelerator end through the third communication bus; wherein the transmission completion information represents that the target data corresponding to the direct memory access configuration information is transmitted;

[0032] When the microcontroller at the accelerator end receives the transmission completion information, it resets the state flag of the cache queue corresponding to the transmission completion information, and clears all data in the cache queue with the reset state flag.

[0033] In some embodiments, after the microcontroller at the accelerator end sends each direct memory access configuration information to the processor at the accelerator end through the third communication bus, it further includes:

[0034] The microcontroller at the accelerator end monitors the state flag of each cache queue to determine whether the state flags of all cache queues have been reset;

[0035] If the microcontroller at the accelerator end confirms that the state flags of all cache queues have been reset, it sets the transmission completion address register.

[0036] In some embodiments, if the microcontroller at the accelerator end confirms that the status flag of the target cache queue is not reset, further comprising:

[0037] The microcontroller at the accelerator end determines whether the duration that the status flag of the target cache queue is set is greater than a preset time threshold;

[0038] If the microcontroller at the accelerator end confirms that the duration that the status flag of the target cache queue is set is greater than the preset time threshold, outputting alarm information representing that the target data transmission corresponding to the target cache queue fails;

[0039] Deleting the direct memory access configuration information in the target cache queue, and resetting the status flag of the target cache queue.

[0040] In some embodiments, further comprising:

[0041] Monitoring the transmission completion address register of the microcontroller at the accelerator end, and determining whether the transmission completion address register of the microcontroller at the accelerator end is set;

[0042] If it is confirmed that the transmission completion address register of the microcontroller at the accelerator end is set, it is confirmed that all the target data transmission is completed, and all the cache is recycled.

[0043] In some embodiments, further comprising:

[0044] Generating a direct memory access data transmission log according to each direct memory access configuration information and the target data corresponding thereto;

[0045] Uploading the direct memory access data transmission log to a server.

[0046] To solve the above technical problems, the application further provides another data transmission method, applied to an accelerator end; the method comprises:

[0047] Receiving each direct memory access configuration information sent by the microcontroller; wherein the direct memory access configuration information comprises a source address, a destination address and a transmission length; each direct memory access configuration information is obtained by a host end, sent to the microcontroller through a first communication bus and cached by the microcontroller;

[0048] Based on each direct memory access configuration information and the direct memory access controller, calling a direct memory access mover, and obtaining target data corresponding to each direct memory access configuration information from the memory through the direct memory access mover;

[0049] Sending each target data to the host end through a second communication bus.

[0050] To solve the above technical problems, the application further provides a computer program product comprising a computer program or instructions, which, when executed by a processor, implement the steps of the above data transmission method.

[0051] To solve the above technical problems, the application further provides a data transmission device comprising:

[0052] a memory for storing a computer program;

[0053] a processor for executing the computer program to implement the steps of the above data transmission method.

[0054] To solve the above technical problems, the application further provides a computer non-volatile readable storage medium, which stores a computer program, and the computer program, when executed by a processor, implements the steps of the above data transmission method.

[0055] The data transmission method provided by the application specifically acquires each direct memory access configuration information; wherein the direct memory access configuration information comprises a source address, a destination address and a transmission length; each direct memory access configuration information is sent to a microcontroller at an accelerator end through a first communication bus, so that the microcontroller at the accelerator end caches each direct memory access configuration information, and sends each direct memory access configuration information to a processor at the accelerator end; the processor at the accelerator end calls a direct memory access mover based on each direct memory access configuration information and the direct memory access controller, and acquires target data corresponding to each direct memory access configuration information from a memory at the accelerator end through the direct memory access mover; and each target data transmitted by the processor at the accelerator end is received through a second communication bus.

[0056] The application has the beneficial effects that the microcontroller is arranged at the accelerator end to receive DMA configuration information sent by a host end and transmit the DMA configuration information to a processor at the accelerator end, that is, an out-of-band configuration mode is adopted, a plurality of DMA configuration information can be received at one time, waiting for completion of transmission of one configuration information before initiating transmission of the next time is avoided, and the data transmission efficiency is effectively improved; at the same time, the DMA transmission is controlled by the microcontroller at the accelerator end, and the processor is only responsible for data transmission and calculation, so that the logical development difficulty of the processor is reduced. In addition, the first communication bus is used to transmit the DMA configuration information, and the second communication bus is used to transmit the target data corresponding to the DMA configuration information, so that real-time execution of the DMA operation is realized, and the real-time performance of the data transmission is improved.

[0057] In another aspect, the host end in the application specifically pre-applies data sending buffer and data receiving buffer before DMA data transmission by the way of memory pre-application, so as to avoid frequent application of memory during data transmission and improve the stability of the system. The microcontroller of the accelerator end specifically stores each direct memory access configuration information into the corresponding buffer queue, sets the state flag of the buffer queue storing the direct memory access configuration information, so as to better store the DMA configuration information. The microcontroller of the accelerator end monitors the transmission completion information transmitted by the processor of the accelerator end through the third communication bus, resets the state flag of the buffer queue corresponding to the transmission completion information when receiving the transmission completion information, and clears all data in the buffer queue with the reset state flag, so as to save the storage space of the microcontroller.

[0058] In addition, the application also provides a computer program product, a data transmission device and a medium, and the effects are the same as above. BRIEF DESCRIPTION OF DRAWINGS

[0059] In order to more clearly illustrate the embodiments of the application, the drawings needed in the embodiments will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the application, and other drawings can be obtained by those skilled in the art without creative labor on the basis of these drawings.

[0060] Fig. 1 is a schematic diagram of a data transmission system provided by some embodiments of the application;

[0061] Fig. 2 is a flowchart of a data transmission method applied to a host end provided by some embodiments of the application;

[0062] Fig. 3 is a schematic diagram of a buffer queue provided by some embodiments of the application;

[0063] Fig. 4 is a flowchart of a data transmission method applied to an accelerator end provided by some embodiments of the application;

[0064] Fig. 5 is a schematic diagram of a data transmission device applied to a host end provided by some embodiments of the application;

[0065] Fig. 6 is a schematic diagram of a data transmission device applied to an accelerator end provided by some embodiments of the application;

[0066] Fig. 7 is a schematic diagram of a data transmission device provided by some embodiments of the application. DETAILED DESCRIPTION

[0067] With reference to the drawings and embodiments of the present application, the technical solutions in the embodiments of the present application will be described clearly and completely. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative work fall within the protection scope of the present application.

[0068] The core of the present application is to provide a data transmission method, product, device and medium to solve the problem that the current DMA transmission mode needs to wait for the completion of a transmission before initiating the next transmission, resulting in low data transmission efficiency.

[0069] In order for those skilled in the art to better understand the present application, the present application will be further described in detail below with reference to the drawings and specific embodiments.

[0070] With the development of big data and cloud computing technology, data centers are facing growing demand for computing power. In order to improve computing power, in addition to improving the performance of servers themselves, data centers also expand artificial intelligence (AI) accelerators such as graphics processing units (GPUs), general-purpose graphics processing units (GPGPUs), and field programmable gate arrays (FPGAs) through PCIE interfaces to enhance parallel computing capabilities. In the PCIE interface, DMA is the fastest data transmission method, which allows the CPU to only control the transmission without participating in the actual transmission, and the DMA controller is responsible for copying data between two address spaces, thereby effectively freeing up the CPU and improving transmission efficiency.

[0071] Currently, there are two common modes of DMA: block DMA and chained DMA. In block DMA transmission, the CPU sets three elements of source address, destination address and length, and the source address and the destination address correspond to the host double data rate (DDR) memory address and the slave DDR address, respectively. After address conversion by an input / output memory management unit (IOMMU) module, the DMA controller performs data transmission between the host and the device according to the configuration information. After the transmission is completed, the host is notified by an interrupt X (INT-X) or a message signaled interrupt (MSI). However, block DMA can only transmit one continuous physical memory block at a time, and the transmission efficiency for discrete memory blocks is low. Chained DMA fills the transmission information of discrete memory blocks into descriptors, and the device first reads the descriptors by DMA transmission, and then performs data transmission according to the information in the descriptors. After one transmission is completed, the next descriptor address recorded in the descriptor is read and the next DMA transmission is performed, until all the descriptors are executed. Then, the host reconfigures the descriptors and initiates the next transmission. Although chained DMA can solve the transmission problem of multiple data blocks, the number of blocks transmitted at a time is limited, and the next transmission must wait for the completion of one chained DMA transmission. Therefore, in order to solve the above problems, the present application provides a data transmission method.

[0072] FIG. 1 is a schematic diagram of a data transmission system provided by some embodiments of the present application. It should be noted that the method provided by the present application is applied to a host as shown in FIG. 1. The host and the accelerator are connected in communication through a first communication bus and a second communication bus. A microcontroller and a processor are arranged in the accelerator, and the host transmits DMA configuration information to the microcontroller through the first communication bus. The microcontroller receives and manages the DMA configuration information, and transmits the DMA configuration information to the processor. The processor completes DMA operation according to the DMA configuration information, obtains target data from the memory, and transmits the target data to the host through the second communication bus, thereby completing DMA data transmission.

[0073] It should be noted that the present application does not limit the specific type of the accelerator, which can be a GPU accelerator, a GPGPU accelerator or an FPGA accelerator, and the processor in the accelerator is not limited, which can correspond to a GPU, a GPGPU or an FPGA, depending on the specific implementation.

[0074] Further, the application is not limited to specific types of the first communication bus and the second communication bus. For example, since the host side and the accelerator side are generally connected by a PCIE bus, in addition to PCIE signals, there is a System Management Bus (SMBUS) interface in the PCIE interface, and thus the first communication bus can be an SMBUS bus and the second communication bus can be a PCIE bus. The application will be described in detail below in combination with specific method steps.

[0075] FIG. 2 is a flowchart of a data transmission method applied to a host side according to some embodiments of the application. As shown in FIG. 2, the method includes the following steps.

[0076] S10: Obtain each direct memory access configuration information.

[0077] The direct memory access configuration information includes a source address, a destination address, and a transmission length.

[0078] In a specific implementation, when performing DMA data transmission, first, the host side obtains each DMA configuration information. It can be understood that the DMA configuration information specifically includes a source address, a destination address, and a transmission length. It should be noted that the application is not limited to the specific manner of obtaining DMA configuration information, which is determined according to the specific implementation.

[0079] S11: Send each direct memory access configuration information to a microcontroller of the accelerator side through the first communication bus, so that the microcontroller of the accelerator side caches each direct memory access configuration information, and sends each direct memory access configuration information to a processor of the accelerator side, and the processor of the accelerator side calls a direct memory access mover based on each direct memory access configuration information and a direct memory access controller, and obtains target data corresponding to each direct memory access configuration information from a memory of the accelerator side through the direct memory access mover.

[0080] In some embodiments, the host side sends each DMA configuration information to the microcontroller of the accelerator side through the first communication bus. After receiving the DMA configuration information, the microcontroller of the accelerator side caches each DMA configuration information. The application is not limited to the specific manner of caching DMA configuration information by the microcontroller, for example, all DMA configuration information can be uniformly stored in a storage space, or each DMA configuration information can be independently stored, which is determined according to the specific implementation.

[0081] The microcontroller at the accelerator side further sends the DMA configuration information to the processor at the accelerator side. It can be understood that the processor at the accelerator side includes a DMA controller and a DMA mover. The DMA controller is a hardware module responsible for managing and controlling DMA transmission. It has transmission control functions and can start and stop DMA transmission according to configuration parameters such as source address, destination address and transmission length. At the same time, the DMA controller is also responsible for address management, which ensures correct access to memory by maintaining source address and destination address counters. Interrupt management is also one of its important functions, which can generate an interrupt when the transmission is completed or an error occurs, notifying the CPU to process. In addition, the DMA controller can exchange data with memory and peripherals directly through the system bus without the participation of the CPU, realizing data transmission.

[0082] The DMA mover is a functional module of the DMA controller, focusing on data transfer. It is responsible for copying data from the source address to the destination address, supporting memory-to-memory, memory-to-peripheral or peripheral-to-memory transmission. The DMA mover supports multiple data transmission modes, including single transmission, block transmission and circular buffer transmission. It can also support different data widths, such as 8 bits, 16 bits or 32 bits, etc. In order to improve transmission efficiency, the DMA mover usually includes a first-in, first-out (FIFO) buffer for temporarily storing data. Through these functions, the DMA mover realizes efficient data transfer and reduces the burden on the CPU.

[0083] The processor at the accelerator side specifically calls the DMA mover based on the DMA configuration information and the DMA controller, obtains the target data corresponding to the DMA configuration information from the memory at the accelerator side through the DMA mover, and executes the DMA operation.

[0084] S12: Receive each target data transmitted by the processor at the accelerator side through the second communication bus.

[0085] Finally, after the DMA mover at the accelerator side processor obtains the target data corresponding to the DMA configuration information from the memory, the target data is transmitted to the host side through the second communication bus, thereby completing the DMA data transmission. It should be noted that the specific way of receiving the target data by the host side is not limited in the present application, which is determined according to the specific implementation.

[0086] In some embodiments, a microcontroller is arranged at the accelerator end to receive the DMA configuration information sent by the host end and transmit the DMA configuration information to the processor at the accelerator end, that is, an out-of-band configuration manner is adopted, a plurality of DMA configuration information can be received at one time, and the efficiency of data transmission is effectively improved, and the processor only needs to be responsible for data transmission and calculation, so that the logical development difficulty of the processor is reduced. In addition, the first communication bus is used to transmit the DMA configuration information, and the second communication bus is used to transmit the target data corresponding to the DMA configuration information, so that the real-time execution of the DMA operation can be realized, and the real-time performance of data transmission is improved.

[0087] In order to improve the stability of the host end system, in some embodiments, before obtaining each direct memory access configuration information, further comprising:

[0088] S13: applying a preset number of caches based on the memory;

[0089] S14: setting data sending cache and data receiving cache based on all the caches;

[0090] S15: recording the cache size, first address and use state of each cache respectively.

[0091] In the specific implementation, before performing DMA data transmission, a preset number of caches are applied based on the memory at the host end, and all the caches are divided into two parts, one part is data sending cache, and the other part is data receiving cache.

[0092] It should be noted that the data sending cache is a cache for storing data to be sent, and the data receiving cache is a cache for storing received data. The preset number of caches is not limited in the present application, for example, 2N caches can be set, and the caches are equally divided into two parts, so that N data sending caches and N data receiving caches are obtained.

[0093] In addition, after setting the data sending cache and the data receiving cache, the cache size, the first address and the use state of each cache need to be recorded respectively, so as to facilitate the calling of the cache during data transmission.

[0094] In some embodiments, the host end applies data sending cache and data receiving cache in advance by the memory pre-application manner before performing DMA data transmission, so as to avoid frequent application of memory during data transmission and improve the stability of the system.

[0095] In some embodiments, obtaining each direct memory access configuration information comprises:

[0096] S101: monitoring the direct memory access configuration information sending request;

[0097] S102: When receiving the direct memory access configuration information sending request, copy each direct memory access configuration information corresponding to the direct memory access configuration information sending request to each data sending buffer;

[0098] S103: Obtain the direct memory access configuration information in each data sending buffer according to the first address of each data sending buffer.

[0099] Since the data sending buffer is set in advance before the DMA data transmission, the host specifically monitors the DMA configuration information sending request when obtaining the DMA configuration information. When the host receives the DMA configuration information sending request, each DMA configuration information corresponding to the DMA configuration information sending request is copied to each data sending buffer. It can be understood that the data sending buffer here should be an unoccupied buffer. When DMA configuration information transmission is needed, the DMA configuration information in each data sending buffer is obtained according to the first address of each data sending buffer, so as to send the DMA configuration information to the microcontroller of the accelerator end.

[0100] In summary, the acquisition of DMA configuration information is realized. By storing each DMA configuration information in the data sending buffer applied in advance, frequent memory application during data transmission is avoided, and the stability of the system is improved.

[0101] In some embodiments, each target data transmitted by the processor of the accelerator end is received through the second communication bus, including:

[0102] S121: Monitor the target data receiving request;

[0103] S122: When receiving the target data receiving request, determine the size of each target data according to the target data receiving request;

[0104] S123: Determine the target data receiving buffer in all data receiving buffers according to the size of each target data, the buffer size and the use state of each data receiving buffer;

[0105] S124: Obtain the first address of each target data receiving buffer, and store each target data in the corresponding target data receiving buffer according to the first address of each target data receiving buffer.

[0106] Since the data receiving buffer is set in advance before the DMA data transmission, the host specifically monitors the target data receiving request when receiving the target data transmitted by the accelerator. When the target data receiving request is received, the size of each target data is determined according to the target data receiving request. In order to select the optimal target data receiving buffer corresponding to the target data, the target data receiving buffer is determined in all data receiving buffers according to the size of each target data, the buffer size and the use state of each data receiving buffer. It can be understood that the use state of the target data receiving buffer should be unused, and the buffer size should be no less than the size of the corresponding target data. Finally, the first address of each target data receiving buffer is obtained, and each target data is stored in the corresponding target data receiving buffer according to the first address of each target data receiving buffer.

[0107] In summary, the host receives and stores the target data. By storing each target data in the target data receiving buffer applied in advance, the frequent application of memory during data transmission is avoided, and the stability of the system is improved.

[0108] In some embodiments, the microcontroller of the accelerator caches each direct memory access configuration information, including:

[0109] S131: The microcontroller of the accelerator stores each direct memory access configuration information in the corresponding cache queue, respectively.

[0110] S132: The microcontroller of the accelerator sets the state flag of the cache queue storing the direct memory access configuration information to indicate that the cache queue is occupied.

[0111] In order to better cache the DMA configuration information, in specific implementation, the microcontroller of the accelerator specifically stores each DMA configuration information in the corresponding cache queue. FIG. 3 is a schematic diagram of a cache queue provided by some embodiments of the present application. As shown in FIG. 3, the microcontroller includes a plurality of cache queues, each cache queue stores a DMA configuration information, that is, stores the source address, the destination address and the transmission length. In addition, each cache queue further includes a corresponding state flag, which is used to indicate whether the corresponding cache queue is occupied; specifically, when the state flag is set, it is confirmed that the corresponding cache queue is occupied, and when the state flag is reset, it is confirmed that the corresponding cache queue is in an idle state. Therefore, after the microcontroller of the accelerator stores each DMA configuration information in the corresponding cache queue, it further needs to set the state flag of the cache queue storing the DMA configuration information to indicate that the cache queue is occupied.

[0112] In some embodiments, the microcontroller at the accelerator end specifically stores each direct memory access configuration information into a corresponding cache queue, and sets a state flag of the cache queue storing the direct memory access configuration information to indicate that the cache queue is occupied, so as to better store the DMA configuration information.

[0113] In some embodiments, the microcontroller at the accelerator end sends each direct memory access configuration information to the processor at the accelerator end, including:

[0114] S133: The microcontroller at the accelerator end acquires each direct memory access configuration information based on each cache queue;

[0115] S134: The microcontroller at the accelerator end sends each direct memory access configuration information to the processor at the accelerator end through the third communication bus.

[0116] In order to send the DMA configuration information to the processor, in a specific implementation, the microcontroller at the accelerator end specifically acquires each DMA configuration information based on each cache queue, and sends each DMA configuration information to the processor at the accelerator end through the third communication bus.

[0117] It should be noted that the present application does not limit the third communication bus, which can be a PCIE bus or a serial peripheral interface (SPI) bus, for example, depending on the specific implementation. In this way, the sending of DMA configuration information from the microcontroller to the processor is achieved.

[0118] In order to save the storage space of the microcontroller, in some embodiments, after the microcontroller at the accelerator end sends each direct memory access configuration information to the processor at the accelerator end through the third communication bus, it further includes:

[0119] S135: The microcontroller at the accelerator end monitors the transmission completion information transmitted by the processor at the accelerator end through the third communication bus.

[0120] The transmission completion information indicates that the transmission of the direct memory access configuration information corresponding to the transmission completion information is completed.

[0121] S136: When the microcontroller at the accelerator end receives the transmission completion information, it resets the state flag of the cache queue corresponding to the transmission completion information, and clears all data in the cache queue with the reset state flag.

[0122] In a specific implementation, after the microcontroller at the accelerator end sends each DMA configuration information to the processor at the accelerator end through the third communication bus, it can further monitor the transmission completion information transmitted by the processor at the accelerator end through the third communication bus.

[0123] It should be noted that the transmission completion information represents that the target data corresponding to the DMA configuration information has completed the transmission from the processor at the accelerator end to the host end, and the current DMA data transmission has been completed. Therefore, when the microcontroller at the accelerator end receives the transmission completion information, it is considered that the target data corresponding to the DMA configuration information has completed the transmission, and the DMA configuration information in the corresponding cache queue is no longer useful. Therefore, the state flag of the cache queue corresponding to the transmission completion information can be reset, and all data in the cache queue with the reset state flag can be emptied, so as to release the storage space of the cache queue and save the storage space of the microcontroller.

[0124] In some embodiments, the microcontroller at the accelerator end monitors the transmission completion information transmitted by the processor at the accelerator end through the third communication bus. When the transmission completion information is received, the state flag of the cache queue corresponding to the transmission completion information is reset, and all data in the cache queue with the reset state flag is emptied, thereby saving the storage space of the microcontroller.

[0125] In order to better know the state of the DMA data transmission, in some embodiments, after the microcontroller at the accelerator end sends each direct memory access configuration information to the processor at the accelerator end through the third communication bus, it further includes:

[0126] S137: The microcontroller at the accelerator end monitors the state flags of each cache queue, and determines whether the state flags of all cache queues have been reset; if the microcontroller at the accelerator end confirms that the state flags of all cache queues have been reset, it proceeds to step S138;

[0127] S138: The microcontroller at the accelerator end sets the transmission completion address register.

[0128] In a specific implementation, the microcontroller at the accelerator end also monitors the state flags of each cache queue, and determines whether the state flags of all cache queues have been reset.

[0129] If the microcontroller at the accelerator end confirms that the state flags of all cache queues have been reset, it confirms that the target data corresponding to the DMA configuration information in all cache queues has been sent, and there is no current DMA data transmission. The microcontroller at the accelerator end sets the transmission completion address register, thereby indicating that the current DMA data transmission has ended.

[0130] If the microcontroller at the accelerator end confirms that there is a target cache queue whose state flag has not been reset, it is considered that the target data corresponding to the DMA configuration information in the current target cache queue has not been sent. In order to prevent the DMA data transmission error from occupying the microcontroller resources for a long time, if the microcontroller at the accelerator end confirms that there is a target cache queue whose state flag has not been reset, it further includes:

[0131] S139: The microcontroller at the accelerator end determines whether the duration for which the status flag of the target cache queue is set is greater than a preset time threshold; if the microcontroller at the accelerator end confirms that the duration for which the status flag of the target cache queue is set is greater than the preset time threshold, step S140 is entered;

[0132] S140: Alarm information indicating that the target data transmission corresponding to the target cache queue fails is outputted.

[0133] S141: The direct memory access configuration information in the target cache queue is deleted, and the status flag of the target cache queue is reset.

[0134] Specifically, if the microcontroller at the accelerator end confirms that the status flag of the target cache queue is not reset, the microcontroller at the accelerator end determines whether the duration for which the status flag of the target cache queue is set is greater than a preset time threshold. The preset time threshold is not limited in the present application, and is determined according to the specific implementation.

[0135] If the microcontroller at the accelerator end confirms that the duration for which the status flag of the target cache queue is set is not greater than the preset time threshold, the monitoring continues. If the microcontroller at the accelerator end confirms that the duration for which the status flag of the target cache queue is set is greater than the preset time threshold, it is confirmed that the target data transmission corresponding to the target cache queue fails, alarm information indicating that the target data transmission corresponding to the target cache queue fails is outputted, so as to prompt the user to check the target data transmission corresponding to the target cache queue in time; at the same time, the DMA configuration information in the target cache queue is deleted, and the status flag of the target cache queue is reset, so as to release the storage space of the target cache queue, so as to facilitate the next DMA data transmission.

[0136] In order to recycle the DMA related resource information at the host end, in some embodiments, the method further comprises:

[0137] S16: The transmission completion address register of the microcontroller at the accelerator end is monitored, and it is determined whether the transmission completion address register of the microcontroller at the accelerator end is set; if it is confirmed that the transmission completion address register of the microcontroller at the accelerator end is set, step S17 is entered;

[0138] S17: It is confirmed that the current all target data transmission is completed, and all caches are recycled.

[0139] In a specific implementation, the host end continuously monitors the transmission completion address register of the microcontroller at the accelerator end, and determines whether the transmission completion address register of the microcontroller at the accelerator end is set. It can be understood that the transmission completion address register is set, which indicates that the current all DMA data transmission is completed.

[0140] If it is confirmed that the transmission completion address register of the microcontroller at the accelerator end is not set, it is confirmed that there is currently target data that has not been transmitted, and the transmission completion address register of the microcontroller at the accelerator end continues to be monitored. If it is confirmed that the transmission completion address register of the microcontroller at the accelerator end is set, it is confirmed that all target data has been transmitted, and all caches are recycled. It can be understood that the recycled caches are the data sending cache and the data receiving cache that are applied based on the host end memory in advance. By recycling all caches, the recycling of the host end DMA related resource information is realized, and the resources of the host end are saved.

[0141] In order to enable the user to better master the whole process of DMA data transmission, in some embodiments, the method further comprises:

[0142] S18: generating a direct memory access data transmission log according to each direct memory access configuration information and the corresponding target data;

[0143] S19: uploading the direct memory access data transmission log to a server.

[0144] Specifically, a DMA data transmission log is generated according to each DMA configuration information and the corresponding target data. In order to enable the user to master the whole DMA transmission process, the configuration information such as the source address, the destination address and the transmission length should be included in the DMA data transmission log, the starting point, the end point and the data volume of data transmission are defined; the data transmission direction, that is, the transmission direction between the memory and the peripheral device; the DMA transmission state, including the start time, the end time and the state changes such as transmission completion, error or interruption; the DMA transmission performance index, such as the transmission rate, the time and the efficiency; the DMA controller model, the version and the related configuration parameters; and the record of the interruption, the exception or other related events generated in the DMA transmission process. These information helps the system administrator or the developer to analyze, debug the DMA transmission process, optimize the system performance, and solve potential problems.

[0145] Finally, uploading the DMA data transmission log to the server can realize the centralized storage and management of the log, facilitate the system administrator to uniformly monitor the DMA transmission of multiple devices; ensure the data security, facilitate the recovery of historical logs for analysis or troubleshooting; the developer or technical support personnel can remotely analyze and debug, improve the work efficiency; by comparing the logs of different time periods or devices, the system performance change trend is evaluated and optimized; the server can analyze the log in real time, identify potential faults or exceptions and timely alarm; meet the compliance requirements, as an audit basis; promote the log sharing and cooperation among team members. This helps to improve the reliability, performance and security of the system.

[0146] FIG. 4 is a flowchart of a data transmission method applied to the accelerator end according to some embodiments of the present application. As shown in FIG. 4, the method comprises:

[0147] S20: receiving each direct memory access configuration information sent by the microcontroller.

[0148] The direct memory access configuration information includes a source address, a destination address and a transmission length; each direct memory access configuration information is obtained by the host end, sent to the microcontroller through the first communication bus and cached by the microcontroller.

[0149] S21: based on each direct memory access configuration information and the direct memory access controller, calling a direct memory access mover to obtain target data corresponding to each direct memory access configuration information from the memory through the direct memory access mover.

[0150] S22: sending each target data to the host end through the second communication bus.

[0151] In some embodiments, a microcontroller is arranged at the accelerator end to receive the DMA configuration information sent by the host end and transmit the DMA configuration information to the processor at the accelerator end, that is, an out-of-band configuration mode is adopted, a plurality of DMA configuration information can be received at one time, and the waiting for the completion of the transmission of one configuration information before initiating the next transmission is avoided, so that the data transmission efficiency is effectively improved; at the same time, since the microcontroller controls the DMA transmission at the accelerator end, the processor is only responsible for data transmission and calculation, so the logical development difficulty of the processor is reduced. In addition, the first communication bus is used to transmit the DMA configuration information and the second communication bus is used to transmit the target data corresponding to the DMA configuration information, so that the real-time execution of the DMA operation can be realized, and the real-time performance of the data transmission is improved.

[0152] In the above embodiments, the data transmission method is described in detail, and the application also provides some embodiments of a data transmission device.

[0153] FIG. 5 is a schematic diagram of a data transmission device applied to the host end according to some embodiments of the application. As shown in FIG. 5, the device includes:

[0154] The first obtaining module 10 is configured to obtain each direct memory access configuration information; wherein the direct memory access configuration information includes a source address, a destination address and a transmission length;

[0155] The first sending module 11 sends each direct memory access configuration information to the microcontroller at the accelerator end through the first communication bus, so that the microcontroller at the accelerator end caches each direct memory access configuration information and sends each direct memory access configuration information to the processor at the accelerator end. The processor at the accelerator end calls a direct memory access mover based on each direct memory access configuration information and the direct memory access controller, and obtains target data corresponding to each direct memory access configuration information from the memory at the accelerator end through the direct memory access mover;

[0156] The first receiving module 12 is configured to receive each target data transmitted by the processor at the accelerator end through the second communication bus.

[0157] Since the embodiments of the device part correspond to the embodiments of the method part, the embodiments of the device part are described in the description of the embodiments of the method part, and are not described here.

[0158] FIG. 6 is a schematic diagram of a data transmission device applied to an accelerator end according to some embodiments of the present application. As shown in FIG. 6, the device includes:

[0159] The second receiving module 13 is configured to receive each direct memory access configuration information sent by the microcontroller. The direct memory access configuration information includes a source address, a destination address and a transmission length. Each direct memory access configuration information is obtained by the host end, sent to the microcontroller through the first communication bus and cached by the microcontroller.

[0160] The second obtaining module 14 is configured to call a direct memory access mover based on each direct memory access configuration information and the direct memory access controller, and obtain target data corresponding to each direct memory access configuration information from the memory through the direct memory access mover.

[0161] The second sending module 15 is configured to send each target data to the host end through the second communication bus.

[0162] Since the embodiments of the device part correspond to the embodiments of the method part, the embodiments of the device part are described in the description of the embodiments of the method part, and are not described here.

[0163] In addition, the present application also provides a computer program product, including a computer program or instructions, which are executed by a processor to realize the steps of the above data transmission method.

[0164] FIG. 7 is a schematic diagram of a data transmission device according to some embodiments of the present application. As shown in FIG. 7, the data transmission device includes:

[0165] The memory 20 is configured to store a computer program.

[0166] The processor 21 is configured to implement the steps of the data transmission method mentioned in the above embodiments when executing a computer program.

[0167] The data transmission device provided by some embodiments of the present application can include, but is not limited to, a smart phone, a tablet computer, a notebook computer, a desktop computer, etc.

[0168] The processor 21 can include one or more processing cores, such as a 4-core processor, an 8-core processor, etc. The processor 21 can be implemented in at least one of a hardware form of a digital signal processor (DSP), a field-programmable gate array (FPGA), a programmable logic array (PLA). The processor 21 can also include a main processor and a coprocessor. The main processor is a processor for processing data in an awake state, also known as a central processing unit (CPU). The coprocessor is a low-power processor for processing data in a standby state. In some embodiments, the processor 21 can be integrated with a graphics processing unit (GPU). The GPU is responsible for rendering and drawing the content to be displayed on the display screen. In some embodiments, the processor 21 can also include an artificial intelligence (AI) processor for processing machine learning-related computing operations.

[0169] The memory 20 can include one or more computer non-volatile readable storage media, which can be non-transitory. The memory 20 can also include a high-speed random access memory and a non-volatile memory such as one or more disk storage devices, flash memory devices. In some embodiments, the memory 20 is at least used to store the following computer program 201, wherein the computer program is loaded and executed by the processor 21, and can implement the related steps of the data transmission method disclosed in any of the preceding embodiments. In addition, the resources stored by the memory 20 can also include an operating system 202 and data 203, etc., and the storage mode can be temporary storage or permanent storage. The operating system 202 can include Windows, Unix, Linux, etc. The data 203 can include, but is not limited to, data related to the data transmission method.

[0170] In some embodiments, the data transmission device can also include a display screen 22, an input / output interface 23, a communication interface 24, a power supply 25, and a communication bus 26.

[0171] Those skilled in the art can understand that the structure shown in FIG. 7 does not constitute a limitation on the data transmission device, and can include more or fewer components than illustrated.

[0172] Finally, the present application also provides a computer non-volatile readable storage medium corresponding embodiment. The computer non-volatile readable storage medium stores a computer program, and the computer program is executed by a processor to implement the steps described in the above method embodiments (which can be a method corresponding to the host side, or a method corresponding to the accelerator side, or a method corresponding to the host side and the accelerator side).

[0173] It can be understood that if the method in the above embodiments is implemented in the form of a software function unit and sold or used as an independent product, it can be stored in a computer non-volatile readable storage medium. Based on such understanding, the technical solutions of the present application essentially or the part of the prior art that contributes to the technical solutions or the whole or part of the technical solutions can be embodied in the form of a software product. The computer software product is stored in a storage medium, and executes all or part of the steps of the various embodiments of the present application. The foregoing storage medium includes: a U disk, a mobile hard disk, a read-only memory (Read-Only Memory, ROM), a random access memory (Random Access Memory, RAM), a magnetic disk or an optical disk, and various program code storage media.

[0174] The above provides a kind of data transmission method, product, equipment and medium provided by the present application in detail. The progressive way is described in each embodiment of the specification, and each embodiment emphasizes the different place with other embodiments, and the same or similar parts of each embodiment can be referred to each other. For the device disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, it is described simply, and the related part is referred to the method part description. It should be pointed out that, for ordinary skilled in the art, without departing from the principles of the present application, the present application can be improved and modified in several ways, and these improvements and modifications also fall within the scope of the present application.

[0175] It also needs to be explained that in the present specification, the relational terms such as first and second and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises", "comprising", or any other variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but can also include other elements not expressly listed or inherent to such process, method, article, or apparatus. An element proceeded by "comprises... a" does not, without more constraints, exclude the existence of additional identical elements in the process, method, article, or apparatus that comprises the element.

Claims

1. A data transmission method, characterized by, The application is applied to a host end, and the method comprises the following steps: Obtaining each direct memory access configuration information, wherein the direct memory access configuration information comprises a source address, a destination address and a transmission length; Sending each direct memory access configuration information to a microcontroller of an accelerator end through a first communication bus, so that the microcontroller of the accelerator end caches each direct memory access configuration information and sends each direct memory access configuration information to a processor of the accelerator end, the processor of the accelerator end calls a direct memory access mover based on each direct memory access configuration information and a direct memory access controller, and obtains target data corresponding to each direct memory access configuration information from a memory of the accelerator end through the direct memory access mover; Receiving each target data transmitted by the processor of the accelerator end through a second communication bus.

2. The data transmission method of claim 1, wherein, Before the step of obtaining each direct memory access configuration information, the method further comprises the following steps: Setting a preset number of caches based on a memory; Setting data sending caches and data receiving caches based on all the caches; Respectively recording cache sizes, first addresses and use states of each cache.

3. The data transmission method of claim 2, wherein, The step of obtaining each direct memory access configuration information comprises the following steps: Monitoring a direct memory access configuration information sending request; When the direct memory access configuration information sending request is received, copying each direct memory access configuration information corresponding to the direct memory access configuration information sending request to each data sending cache; Respectively obtaining the direct memory access configuration information in each data sending cache according to the first addresses of each data sending cache.

4. The data transmission method of claim 2, wherein, The step of receiving each target data transmitted by the processor of the accelerator end through the second communication bus comprises the following steps: Monitoring a target data receiving request; When the target data receiving request is received, determining the size of each target data according to the target data receiving request; Determining target data receiving caches in all the data receiving caches according to the size of each target data, the cache size and the use state of each data receiving cache; Obtaining the first addresses of each target data receiving cache and respectively storing each target data into the corresponding target data receiving cache according to the first addresses of each target data receiving cache.

5. The data transmission method of claim 2, wherein, The step that the microcontroller of the accelerator end caches each direct memory access configuration information comprises the following steps: The microcontroller of the accelerator end respectively stores each direct memory access configuration information into a corresponding cache queue; The microcontroller of the accelerator end sets a state flag of the cache queue storing the direct memory access configuration information, so as to indicate that the cache queue is occupied.

6. The data transmission method of claim 5, wherein, The step that the microcontroller of the accelerator end sends each direct memory access configuration information to the processor of the accelerator end comprises the following steps: The microcontroller of the accelerator end obtains each direct memory access configuration information based on each cache queue; The microcontroller of the accelerator end sends each direct memory access configuration information to the processor of the accelerator end through a third communication bus.

7. The data transmission method of claim 6, wherein, The microcontroller at the accelerator end sends each of the direct memory access configuration information to the processor at the accelerator end through a third communication bus, and further comprises: The microcontroller at the accelerator end monitors the transmission completion information transmitted by the processor at the accelerator end through the third communication bus, wherein the transmission completion information represents that the target data transmission corresponding to the direct memory access configuration information is completed. When the microcontroller at the accelerator end receives the transmission completion information, the microcontroller resets the state flag of the cache queue corresponding to the transmission completion information, and clears all data in the cache queue with the reset state flag.

8. The data transmission method of claim 6, wherein, The microcontroller at the accelerator end sends each of the direct memory access configuration information to the processor at the accelerator end through a third communication bus, and further comprises: The microcontroller at the accelerator end monitors the state flags of each of the cache queues, and determines whether the state flags of all the cache queues have been reset. If the microcontroller at the accelerator end confirms that the state flags of all the cache queues have been reset, the microcontroller sets the transmission completion address register.

9. The data transmission method of claim 8, wherein, If the microcontroller at the accelerator end confirms that there is a target cache queue whose state flag has not been reset, further comprising: The microcontroller at the accelerator end determines whether the duration of the state flag setting of the target cache queue is greater than a preset time threshold. If the microcontroller at the accelerator end confirms that the duration of the state flag setting of the target cache queue is greater than the preset time threshold, the microcontroller outputs alarm information representing that the target data transmission corresponding to the target cache queue fails. The direct memory access configuration information in the target cache queue is deleted, and the state flag of the target cache queue is reset.

10. The data transmission method of claim 9, wherein, Further comprising: If the microcontroller at the accelerator end confirms that the duration of the state flag setting of the target cache queue is not greater than the preset time threshold, the microcontroller continues to monitor the duration of the state flag setting of the target cache queue.

11. The data transmission method of claim 8, wherein, Further comprising: The microcontroller at the accelerator end monitors the transmission completion address register, and determines whether the transmission completion address register of the microcontroller at the accelerator end is set. If it is confirmed that the transmission completion address register of the microcontroller at the accelerator end is set, it is confirmed that all the target data transmission is completed, and all the cache is recycled.

12. The data transmission method of claim 11, wherein, Further comprising: If it is confirmed that the transmission completion address register of the microcontroller at the accelerator end is not set, the microcontroller continues to monitor the transmission completion address register.

13. The data transmission method of claim 1, wherein, The microcontroller at the accelerator end caches each of the direct memory access configuration information, comprising: All the direct memory access configuration information is stored in one storage space, or each of the direct memory access configuration information is independently stored.

14. The data transmission method of claim 1, wherein, The direct memory access controller has a transmission control function, which is configured to start and stop direct memory access transmission according to the direct memory access configuration information; the direct memory access controller also has an interrupt management function, which is configured to generate an interrupt when the transmission is completed or an error occurs.

15. The data transmission method of claim 1, wherein, The direct memory access mover includes a first-in-first-out buffer configured to temporarily store data.

16. The data transmission method according to any one of claims 1 to 15, wherein, Further comprising: According to each of the direct memory access configuration information and its corresponding target data, a direct memory access data transmission log is generated; The direct memory access data transmission log is uploaded to a server.

17. A data transmission method, characterized by, Applied to the accelerator side; the method comprises: Receiving each direct memory access configuration information sent by the microcontroller; wherein the direct memory access configuration information includes source address, destination address and transmission length; each of the direct memory access configuration information is obtained by the host side, sent to the microcontroller through the first communication bus and cached by the microcontroller; Based on each of the direct memory access configuration information and the direct memory access controller, the direct memory access mover is called to obtain the target data corresponding to each of the direct memory access configuration information from the memory through the direct memory access mover; Each of the target data is sent to the host side through the second communication bus.

18. A computer program product comprising computer programs or instructions, characterized in that, The computer program or instructions are executed by the processor to realize the steps of the data transmission method of any one of claims 1 to 17.

19. A data transmission device, characterized by Comprise: a memory configured to store a computer program; a processor configured to execute the computer program to realize the steps of the data transmission method of any one of claims 1 to 17.

20. A computer non-volatile readable storage medium characterized in that, The computer non-volatile readable storage medium stores a computer program, and the computer program is executed by the processor to realize the steps of the data transmission method of any one of claims 1 to 17.

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