Pixel driving circuit and driving method therefor, and display device

Abstract

A pixel driving circuit and a driving method therefor, and a display device. The pixel driving circuit comprises: a first control sub-circuit, a second control sub-circuit, a third control sub-circuit, and a drive sub-circuit. The first control sub-circuit is configured to, under the control of a signal of at least one of a first scanning signal line (Gate1), a fourth scanning signal line (Gate4), and a fifth scanning signal line (Gate5), provide a signal of a data signal line (Data) to a fourth node (N4), control a signal of a fifth node (N5) by means of the signal of the fourth node (N4), and provide the signal of the fifth node (N5) to a first node (N1) and a third node (N3). The second control sub-circuit is configured to, under the control of a signal of at least one of a second scanning signal line (Gate2) and a third scanning signal line (Gate3), provide a signal of a second reference signal line (REF2) to a second node (N2), provide a signal of a first reference signal line (REF1) to the fourth node (N4), provide a signal of a first initial signal line (INIT1) to the fifth node (N5), and provide a signal of a second initial signal line (INIT2) to a sixth node (N6).

Description

Pixel driving circuit, driving method thereof and display device

[0001] The present application claims priority to the Chinese patent application No. 202411391068.7, filed on September 30, 2024, and entitled “Pixel driving circuit, driving method thereof and display device”, the content of which is to be understood as incorporated herein by reference. TECHNICAL FIELD

[0002] The present disclosure relates to, but is not limited to, the technical field of display, in particular to a pixel driving circuit, a driving method thereof and a display device. BACKGROUND

[0003] Organic Light Emitting Diode (OLED) and Quantum-dot Light Emitting Diodes (QLED) are active light-emitting display devices, which have the advantages of self-emission, wide viewing angle, high contrast, low power consumption, extremely high response speed, thinness, flexibility, low cost, etc. With the continuous development of display technology, flexible display devices using OLED or QLED as light-emitting devices and controlled by Thin Film Transistors (TFT) have become the mainstream products in the current display field. SUMMARY

[0004] The following is a summary of the subject matter of the detailed description of the present disclosure. This summary is not intended to limit the scope of protection of the claims.

[0005] In a first aspect, the present disclosure provides a pixel driving circuit configured to drive a light-emitting device to emit light, comprising: a first control sub-circuit, a second control sub-circuit, a third control sub-circuit and a driving sub-circuit.

[0006] The first control sub-circuit is electrically connected with a first scan signal line, a fourth scan signal line, a fifth scan signal line, a data signal line, a first node, a third node, a fourth node and a fifth node, respectively, and is configured to provide a signal of the data signal line to the fourth node under the control of a signal of at least one of the first scan signal line, the fourth scan signal line and the fifth scan signal line, control a signal of the fifth node through a signal of the fourth node, and provide a signal of the fifth node to the first node and the third node.

[0007] The second control sub-circuit is electrically connected with the second scan signal line, the third scan signal line, the first initial signal line, the second initial signal line, the first reference signal line, the second reference signal line, the second node, the fourth node, the fifth node and the sixth node respectively, and is configured to provide the signal of the second reference signal line to the second node, the signal of the first reference signal line to the fourth node, the signal of the first initial signal line to the fifth node and the signal of the second initial signal line to the sixth node under the control of the signal of at least one of the second scan signal line and the third scan signal line.

[0008] The third control sub-circuit is electrically connected with the first light-emitting signal line, the second light-emitting signal line, the first power supply line, the second node, the third node and the sixth node respectively, and is configured to provide the signal of the first power supply line to the second node and the signal of the third node to the sixth node under the control of the signals of the first light-emitting signal line and the second light-emitting signal line.

[0009] The driving sub-circuit is electrically connected with the first node, the second node and the third node respectively, and is configured to provide the driving signal to the third node.

[0010] The light-emitting device is electrically connected with the sixth node and the second power supply line respectively.

[0011] In an exemplary embodiment, the first control sub-circuit comprises a writing sub-circuit, a first storage sub-circuit, a communication sub-circuit and a second storage sub-circuit.

[0012] The writing sub-circuit is electrically connected with the first scan signal line, the data signal line and the fourth node respectively, and is configured to provide the signal of the data signal line to the fourth node under the control of the signal of the first scan signal line.

[0013] The first storage sub-circuit is electrically connected with the fourth node and the fifth node respectively, and is configured to store the voltage difference between the signals of the fourth node and the fifth node.

[0014] The communication sub-circuit is electrically connected with the fourth scan signal line, the fifth scan signal line, the first node, the third node and the fifth node respectively, and is configured to provide the signal of the fifth node to the third node under the control of the signal of the fifth scan signal line and to provide the signal of the fifth node to the first node under the control of the signal of the fourth scan signal line.

[0015] The second storage sub-circuit is electrically connected with the first node and the first power supply line respectively, and is configured to store the voltage difference between the signals of the first node and the first power supply line.

[0016] In an exemplary embodiment, the writing sub-circuit includes a fourth transistor, the first storage sub-circuit includes a first capacitor, the second storage sub-circuit includes a second capacitor, at least one of the first capacitor and the second capacitor includes a first plate and a second plate, and the connecting sub-circuit includes a second transistor and an eighth transistor.

[0017] The control electrode of the second transistor is electrically connected with a fifth scan signal line, the first electrode of the second transistor is electrically connected with a fifth node, and the second electrode of the second transistor is electrically connected with a third node.

[0018] The control electrode of the fourth transistor is electrically connected with a first scan signal line, the first electrode of the fourth transistor is electrically connected with a data signal line, and the second electrode of the fourth transistor is electrically connected with a fourth node.

[0019] The control electrode of the eighth transistor is electrically connected with a fourth scan signal line, the first electrode of the eighth transistor is electrically connected with the fifth node, and the second electrode of the eighth transistor is electrically connected with the first node.

[0020] The first plate of the first capacitor is electrically connected with the fifth node, and the second plate of the first capacitor is electrically connected with the fourth node.

[0021] The first plate of the second capacitor is electrically connected with the first node, and the second plate of the second capacitor is electrically connected with a first power supply line.

[0022] In an exemplary embodiment, the second control sub-circuit includes a first sub-circuit, a second sub-circuit, a third sub-circuit, and a fourth sub-circuit.

[0023] The first sub-circuit is electrically connected with a second scan signal line, a first initial signal line, and a fifth node respectively, and is configured to provide a signal of the first initial signal line to the fifth node under control of a signal of the second scan signal line.

[0024] The second sub-circuit is electrically connected with a third scan signal line, a first reference signal line, and a fourth node respectively, and is configured to provide a signal of the first reference signal line to the fourth node under control of a signal of the third scan signal line.

[0025] The third sub-circuit is electrically connected with the second scan signal line, a second reference signal line, and a second node respectively, and is configured to provide a signal of the second reference signal line to the second node under control of a signal of the second scan signal line.

[0026] The fourth sub-circuit is electrically connected with the second scan signal line, a second initial signal line, and a sixth node respectively, and is configured to provide a signal of the second initial signal line to the sixth node under control of a signal of the second scan signal line.

[0027] In an exemplary embodiment, the first sub-circuit includes a first transistor, the second sub-circuit includes a seventh transistor, the third sub-circuit includes a ninth transistor, and the fourth sub-circuit includes a tenth transistor.

[0028] The control electrode of the first transistor is electrically connected with a second scan signal line, the first electrode of the first transistor is electrically connected with a first initial signal line, and the second electrode of the first transistor is electrically connected with a fifth node;

[0029] The control electrode of the seventh transistor is electrically connected with a third scan signal line, the first electrode of the seventh transistor is electrically connected with a first reference signal line, and the second electrode of the seventh transistor is electrically connected with a fourth node;

[0030] The control electrode of the ninth transistor is electrically connected with the second scan signal line, the first electrode of the ninth transistor is electrically connected with a second reference signal line, and the second electrode of the ninth transistor is electrically connected with a second node;

[0031] The control electrode of the tenth transistor is electrically connected with the second scan signal line, the first electrode of the tenth transistor is electrically connected with a second initial signal line, and the second electrode of the tenth transistor is electrically connected with a sixth node.

[0032] In an exemplary embodiment, the first control sub-circuit includes a second transistor, a fourth transistor, an eighth transistor, a first capacitor and a second capacitor, at least one of the first capacitor and the second capacitor includes a first electrode plate and a second electrode plate, the second control sub-circuit includes a first transistor, a seventh transistor, a ninth transistor and a tenth transistor, the third control sub-circuit includes a fifth transistor and a sixth transistor, and the driving sub-circuit includes a third transistor.

[0033] The control electrode of the first transistor is electrically connected with a second scan signal line, the first electrode of the first transistor is electrically connected with a first initial signal line, and the second electrode of the first transistor is electrically connected with a fifth node;

[0034] The control electrode of the second transistor is electrically connected with a fifth scan signal line, the first electrode of the second transistor is electrically connected with the fifth node, and the second electrode of the second transistor is electrically connected with a third node;

[0035] The control electrode of the third transistor is electrically connected with a first node, the first electrode of the third transistor is electrically connected with a second node, and the second electrode of the third transistor is electrically connected with the third node;

[0036] The control electrode of the fourth transistor is electrically connected with a first scan signal line, the first electrode of the fourth transistor is electrically connected with a data signal line, and the second electrode of the fourth transistor is electrically connected with a fourth node;

[0037] A control electrode of the fifth transistor is electrically connected with the first light-emitting signal line, a first electrode of the fifth transistor is electrically connected with the first power supply line, and a second electrode of the fifth transistor is electrically connected with the second node;

[0038] A control electrode of the sixth transistor is electrically connected with the second light-emitting signal line, a first electrode of the sixth transistor is electrically connected with the third node, and a second electrode of the sixth transistor is electrically connected with the sixth node;

[0039] A control electrode of the seventh transistor is electrically connected with the third scan signal line, a first electrode of the seventh transistor is electrically connected with the first reference signal line, and a second electrode of the seventh transistor is electrically connected with the fourth node;

[0040] A control electrode of the eighth transistor is electrically connected with the fourth scan signal line, a first electrode of the eighth transistor is electrically connected with the fifth node, and a second electrode of the eighth transistor is electrically connected with the first node;

[0041] A control electrode of the ninth transistor is electrically connected with the second scan signal line, a first electrode of the ninth transistor is electrically connected with the second reference signal line, and a second electrode of the ninth transistor is electrically connected with the second node;

[0042] A control electrode of the tenth transistor is electrically connected with the second scan signal line, a first electrode of the tenth transistor is electrically connected with the second initial signal line, and a second electrode of the tenth transistor is electrically connected with the sixth node;

[0043] A first electrode plate of the first capacitor is electrically connected with the fifth node, and a second electrode plate of the first capacitor is electrically connected with the fourth node;

[0044] A first electrode plate of the second capacitor is electrically connected with the first node, and a second electrode plate of the second capacitor is electrically connected with the first power supply line;

[0045] The fifth scan signal line and the first light-emitting signal line are the same signal line.

[0046] The transistor type of the eighth transistor is different from the transistor type of at least one of the first transistor to the seventh transistor, the ninth transistor, and the tenth transistor;

[0047] The eighth transistor is an N-type transistor.

[0048] In a second aspect, the present disclosure further provides a display device, comprising: a substrate and a plurality of sub-pixels arranged in an array on the substrate, at least one sub-pixel of the plurality of sub-pixels comprising the pixel driving circuit.

[0049] In an example embodiment, for at least one row of sub-pixels, two adjacent sub-pixels of the at least one sub-pixel comprise: a first adjacent sub-pixel and a second adjacent sub-pixel;

[0050] The structure of the pixel driving circuit of the at least one sub-pixel is at least partially symmetrical to a straight line extending in the second direction and passing through the structure of the pixel driving circuit of the first adjacent sub-pixel, and the structure of the pixel driving circuit of the at least one sub-pixel is at least partially identical to the structure of the pixel driving circuit of the second adjacent sub-pixel.

[0051] In an example embodiment, further comprising: a plurality of data signal lines, at least one of the plurality of data signal lines extending in the second direction;

[0052] The pixel driving circuit of the at least one sub-pixel comprises a second transistor, a third transistor and a sixth transistor;

[0053] The first pole and the second pole of at least one of the second transistor, the third transistor and the sixth transistor in the pixel driving circuit of the at least one sub-pixel do not overlap in the orthographic projection on the base with at least one data signal line;

[0054] The control pole of the third transistor in the pixel driving circuit of the at least one sub-pixel does not overlap in the orthographic projection on the base with at least one data signal line.

[0055] In an example embodiment, when the fifth scan signal line of the at least one pixel driving circuit is the same signal line as the first light-emitting signal line, the display device further comprises: a plurality of first initial signal lines, a plurality of second initial signal lines, a plurality of first reference signal lines, a plurality of second reference signal lines, a plurality of first scan signal lines, a plurality of second scan signal lines, a plurality of third scan signal lines, a plurality of fourth scan signal lines, a plurality of first light-emitting signal lines and a plurality of second light-emitting signal lines;

[0056] At least part of at least one of the plurality of first initial signal lines, the plurality of second initial signal lines, the plurality of first reference signal lines, the plurality of second reference signal lines, the plurality of first scan signal lines, the plurality of second scan signal lines, the plurality of third scan signal lines, the plurality of fourth scan signal lines, the plurality of first light-emitting signal lines and the plurality of second light-emitting signal lines extends in the first direction, and the first direction intersects the second direction;

[0057] The pixel driving circuit of the at least one sub-pixel comprises a first transistor, a ninth transistor and a tenth transistor;

[0058] The pixel driving circuit of the at least one sub-pixel is electrically connected with two second scan signal lines, a control electrode of a first transistor in the pixel driving circuit of the at least one sub-pixel is electrically connected with a first second scan signal line among the two second scan signal lines connected with the pixel driving circuit of the at least one sub-pixel, and a control electrode of at least one of a ninth transistor and a tenth transistor in the pixel driving circuit of the at least one sub-pixel is electrically connected with the first second scan signal line among the two second scan signal lines connected with the pixel driving circuit of the at least one sub-pixel;

[0059] The normal projection of the first reference signal line connected with the pixel driving circuit of the at least one sub-pixel on the substrate, the normal projection of the third scan signal line on the substrate, the normal projection of the first scan signal line on the substrate, the normal projection of the first second scan signal line on the substrate, the normal projection of the fourth scan signal line on the substrate, the normal projection of the first light-emitting signal line on the substrate, the normal projection of the second light-emitting signal line on the substrate, the normal projection of the first second scan signal line on the substrate, and the normal projection of the second reference signal line on the substrate are sequentially arranged along the second direction;

[0060] The normal projection of the first initial signal line on the substrate is located between the normal projection of the first scan signal line on the substrate and the normal projection of the fourth scan signal line on the substrate, and at least partially overlaps with the normal projection of the first second scan signal line on the substrate;

[0061] The normal projection of the second initial signal line on the substrate is located between the normal projection of the second light-emitting signal line on the substrate and the normal projection of the second reference signal line on the substrate, and at least partially overlaps with the normal projection of the second second scan signal line on the substrate.

[0062] In an example embodiment, the pixel driving circuit of the at least one sub-pixel includes a first capacitor and a second capacitor;

[0063] For the pixel driving circuit of the at least one sub-pixel, the normal projection of the first capacitor on the substrate is located between the normal projection of at least one of the first second scan signal line and the first initial signal line connected with the pixel driving circuit on the substrate and the normal projection of the fourth scan signal line on the substrate;

[0064] The normal projection of the second capacitor on the substrate is located between the normal projection of the first light-emitting signal line connected with the pixel driving circuit on the substrate and the normal projection of the second light-emitting signal line on the substrate.

[0065] In an example embodiment, further including a plurality of first power supply lines, one of the plurality of first power supply lines extends along the second direction;

[0066] The at least one data signal line comprises: a plurality of first data connection portions and a plurality of second data connection portions, the plurality of first data connection portions and the plurality of second data connection portions are arranged alternately, and at least one of the first data connection portion and the second data connection portion extends along the second direction;

[0067] For the data signal line connected by the pixel driving circuit of the at least one sub-pixel, the orthographic projection of the first data connection portion on the substrate at least partially overlaps with the orthographic projection on the substrate of at least one of the first reference signal line, the third scan signal line, the first scan signal line, the first second scan signal line, the first initial signal line, the fourth scan signal line, the first light-emitting signal line, at least one of the signal lines, and at least one of the first capacitor and the second capacitor in the pixel driving circuit of the at least one sub-pixel;

[0068] The orthographic projection of the second data connection portion on the substrate at least partially overlaps with the orthographic projection on the substrate of at least one of the second light-emitting signal line, the second scan signal line, the second initial signal line, and the second reference signal line;

[0069] The length of the first data connection portion along the first direction is greater than the length of the second data connection portion along the first direction.

[0070] In the example embodiment, further comprising: a plurality of data signal lines, a plurality of first power lines, a plurality of first initial signal lines, a plurality of second initial signal lines, a plurality of first reference signal lines, a plurality of second reference signal lines, a plurality of first scan signal lines, a plurality of second scan signal lines, a plurality of third scan signal lines, a plurality of fourth scan signal lines, a plurality of first light-emitting signal lines, and a plurality of second light-emitting signal lines;

[0071] The display device further comprises: a circuit structure layer arranged on the substrate, the circuit structure layer comprises: a first semiconductor layer, a first conductive layer, a second conductive layer, a second semiconductor layer, a third conductive layer, a fourth conductive layer, and a fifth conductive layer arranged in sequence on the substrate, the pixel driving circuit of the at least one sub-pixel comprises: at least one P-type transistor, at least one N-type transistor, and at least one capacitor, and the at least one capacitor comprises: a first electrode plate and a second electrode plate;

[0072] The first semiconductor layer comprises: an active pattern of the at least one P-type transistor of the pixel driving circuit of the at least one sub-pixel;

[0073] The first conductive layer at least comprises: the second scan signal line, the first light-emitting signal line, and the first electrode plate of the at least one capacitor and the control electrode of the at least one P-type transistor of the pixel driving circuit of the at least one sub-pixel;

[0074] The second conductive layer at least includes a second plate of at least one capacitor and a first control electrode of at least one N-type transistor in the pixel driving circuit of the at least one sub-pixel;

[0075] The second semiconductor layer at least includes an active pattern of at least one N-type transistor in the pixel driving circuit of the at least one sub-pixel;

[0076] The third conductive layer at least includes a first initial signal line, a second reference signal line, and a second control electrode of an eighth transistor in the pixel driving circuit of the at least one sub-pixel;

[0077] The fourth conductive layer at least includes a first reference signal line, a first scan signal line, a third scan signal line, a fourth scan signal line, a second light-emitting signal line, a second initial signal line, and a first electrode and a second electrode of at least one transistor in the pixel driving circuit of the at least one sub-pixel;

[0078] The fifth conductive layer pattern at least includes a data signal line and a first power supply line.

[0079] In an example embodiment, the circuit structure layer further includes a light shielding layer located on a side of the first semiconductor layer close to the base, and the light shielding layer includes a light shielding structure of the at least one sub-pixel.

[0080] The light shielding structure of the at least one sub-pixel includes a first light shielding part, a second light shielding part, a first light shielding connecting part, a second light shielding connecting part, and a third light shielding connecting part, the first light shielding connecting part, the first light shielding part, the second light shielding connecting part, the second light shielding part, and the third light shielding connecting part are sequentially arranged along a second direction, the first light shielding part is connected with the first light shielding connecting part and the second light shielding connecting part respectively, and the second light shielding part is connected with the second light shielding connecting part and the third light shielding connecting part respectively.

[0081] At least one of the first light shielding connecting part, the second light shielding connecting part, and the third light shielding connecting part extends along the second direction.

[0082] A length of at least one of the first light shielding part and the second light shielding part along a first direction is greater than a length of at least one of the first light shielding connecting part to the third light shielding connecting part along the first direction.

[0083] The pixel driving circuit of the at least one sub-pixel includes a first capacitor and a second capacitor, and the first capacitor and the second capacitor include a first plate and a second plate.

[0084] A normal projection of the first light shielding part of the light shielding structure of the at least one sub-pixel on the base at least partially overlaps with a normal projection of at least one of the first plate and the second plate of the first capacitor on the base.

[0085] A normal projection on the substrate of a second light shielding part of the light shielding structure of the at least one sub-pixel at least partially overlaps a normal projection on the substrate of at least one of the first plate and the second plate of the second capacitor.

[0086] In an example embodiment, further comprising: at least one of a plurality of power supply connection lines located at the fourth conductive layer and a plurality of reference connection lines located at the fifth conductive layer;

[0087] One of the plurality of power supply connection lines extends in a first direction, and one of the plurality of reference connection lines extends in a second direction.

[0088] The at least one power supply connection line is electrically connected to at least one of the plurality of first power supply lines, and the at least one reference connection line is electrically connected to at least one of the plurality of first reference signal lines.

[0089] A normal projection on the substrate of the at least one power supply connection line is located between a normal projection on the substrate of the at least one first light emitting signal line and a normal projection on the substrate of the at least one second light emitting signal line, and at least partially overlaps a normal projection on the substrate of a second capacitor in a pixel driving circuit of the at least one sub-pixel.

[0090] The at least one reference connection line is located between a first power supply line connected by a pixel driving circuit of the at least one sub-pixel and a first power supply line connected by a pixel driving circuit of a first adjacent sub-pixel, and a center line of the at least one reference connection line extending in the first direction is collinear with a symmetry axis of the pixel driving circuit of the at least one sub-pixel and the pixel driving circuit of the first adjacent sub-pixel.

[0091] The at least one reference connection line is located between a data signal line connected by a pixel driving circuit of the at least one sub-pixel and a first power supply line connected by a pixel driving circuit of a first adjacent sub-pixel.

[0092] In a third aspect, the disclosure also provides a driving method of a pixel driving circuit configured as the pixel driving circuit described above, the method comprising:

[0093] The first control sub-circuit provides a signal of the data signal line to the fourth node under control of a signal of at least one of the first scan signal line, the fourth scan signal line, and the fifth scan signal line, controls a signal of the fifth node through a signal of the fourth node, and provides the signal of the fifth node to the first node and the third node.

[0094] The second control sub-circuit provides a signal of the second reference signal line to the second node, a signal of the first reference signal line to the fourth node, a signal of the first initial signal line to the fifth node, and a signal of the second initial signal line to the sixth node under the control of a signal of at least one of the second scan signal line and the third scan signal line;

[0095] The third control sub-circuit provides a signal of the first power supply line to the second node and a signal of the third node to the sixth node under the control of signals of the first light-emitting signal line and the second light-emitting signal line.

[0096] The driving sub-circuit provides a driving signal to the third node.

[0097] Other aspects can be apparent to those of ordinary skill in the art after reading and understanding the accompanying drawings and detailed description.

[0098] SUMMARY

[0099] The accompanying drawings are used to provide an understanding of the technical solutions of the present application, and constitute a part of the specification, and are used together with embodiments of the present application to explain the technical solutions of the present application, and do not constitute a limitation on the technical solutions of the present application.

[0100] FIG. 1 is a structural schematic diagram of a pixel driving circuit provided by an embodiment of the present disclosure;

[0101] FIG. 2 is a structural schematic diagram of a first control sub-circuit provided by an example embodiment;

[0102] FIG. 3 is an equivalent circuit diagram of the first control sub-circuit provided by FIG. 2;

[0103] FIG. 4 is a structural schematic diagram of a second control sub-circuit provided by an example embodiment;

[0104] FIG. 5 is an equivalent circuit diagram of the second control sub-circuit provided by FIG. 4;

[0105] FIG. 6 is an equivalent circuit diagram of a driving sub-circuit and a third control sub-circuit;

[0106] FIG. 7 is an equivalent circuit diagram of a pixel driving circuit provided by an example embodiment;

[0107] FIG. 8 is a driving timing diagram of the pixel driving circuit provided by FIG. 7 in a refresh frame;

[0108] FIG. 9 is a driving timing diagram of the pixel driving circuit provided by FIG. 7 in a holding frame;

[0109] FIG. 10 is a structural schematic diagram of a display substrate provided by an embodiment of the present disclosure;

[0110] FIG. 11 is a schematic diagram of part of a film layer in FIG. 10;

[0111] Fig. 12 is a schematic view of the partial film layer in Fig. 10;

[0112] Fig. 13 is a schematic view of Fig. 10 after forming a light-shielding layer pattern;

[0113] Fig. 14 is a schematic view of a first semiconductor layer pattern in Fig. 10;

[0114] Fig. 15 is a schematic view of Fig. 10 after forming the first semiconductor layer pattern;

[0115] Fig. 16 is a schematic view of a first conductive layer pattern in Fig. 10;

[0116] Fig. 17 is a schematic view of Fig. 10 after forming the first conductive layer pattern;

[0117] Fig. 18 is a schematic view of a second conductive layer pattern in Fig. 10;

[0118] Fig. 19 is a schematic view of Fig. 10 after forming the second conductive layer pattern;

[0119] Fig. 20 is a schematic view of a second semiconductor layer pattern in Fig. 10;

[0120] Fig. 21 is a schematic view of Fig. 10 after forming the second semiconductor layer pattern;

[0121] Fig. 22 is a schematic view of a third conductive layer pattern in Fig. 10;

[0122] Fig. 23 is a schematic view of Fig. 10 after forming the third conductive layer pattern;

[0123] Fig. 24 is a schematic view of Fig. 10 after forming a sixth insulating layer pattern;

[0124] Fig. 25 is a schematic view of a fourth conductive layer pattern in Fig. 10;

[0125] Fig. 26 is a schematic view of Fig. 10 after forming the fourth conductive layer pattern;

[0126] Fig. 27 is a schematic view of Fig. 10 after forming a first planarization layer pattern;

[0127] Fig. 28 is a schematic view of a fifth conductive layer pattern in Fig. 10;

[0128] Fig. 29 is a schematic view of Fig. 10 after forming the fifth conductive layer pattern.

[0129] Detailed Description

[0130] For the purpose of making the objects, technical solutions and advantages of the present disclosure clearer, below, the embodiments of the present disclosure will be described in detail with reference to the drawings. Note that the embodiments can be implemented in multiple different forms. It will be easily understood by those skilled in the art that the modes and details can be changed into various forms without departing from the spirit and scope of the present disclosure. Therefore, the present disclosure should not be interpreted as being limited to the content described in the following embodiments. The embodiments in the present disclosure and the features in the embodiments can be arbitrarily combined with each other in so far as there is no contradiction in combination unless otherwise specified. In order to keep the following description of the embodiments of the present disclosure clear and concise, detailed description of some known functions and known components is omitted in the present disclosure. The drawings of the embodiments of the present disclosure only involve structures related to the embodiments of the present disclosure, and other structures can be referred to the generally designed

[0131] In the drawings, the size, the thickness, or the region of each constituent element shown in some cases is exaggerated for clarity in some cases. Thus, one embodiment of the present disclosure is not necessarily limited to that illustrated in the drawings. The shapes and the sizes of the components shown in the drawings and the relative arrangement thereof are not necessarily limited to those shown in the drawings. The drawings provided only help for describing some embodiments of the present disclosure and are not intended to limit the spirit of the present disclosure.

[0132] In the present specification, ordinal numbers such as "first", "second", and "third" are used to avoid confusion among components, and are not intended to be limiting in number.

[0133] In the present specification, for convenience of explanation, words indicating directions or positional relationships such as "middle", "upper", "lower", "front", "rear", "vertical", "horizontal", "top", "bottom", "inner", "outer", and the like are used to describe the positional relationship of the components with reference to the drawings, and are only for the convenience of describing the present specification and simplifying the description, and are not intended to indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation on the present disclosure. The positional relationship of the components is appropriately changed according to the direction of describing each component. Therefore, it is not limited to the words described in the specification, and can be appropriately changed according to the situation.

[0134] In the present specification, unless specifically defined and limited otherwise, the terms "mount", "connected", "connection" should be interpreted broadly. For example, it can be fixedly connected, or detachably connected, or integrally connected; it can be mechanically connected, or electrically connected; it can be directly connected, or indirectly connected through an intermediate piece, or the communication inside two elements. The specific meaning of the above terms in the present disclosure can be understood according to the specific circumstances by those skilled in the art.

[0135] In this specification, a transistor means an element including at least three terminals of a gate electrode, a drain electrode, and a source electrode. The transistor has a channel region between the drain electrode (a drain electrode terminal, a drain region, or a drain electrode) and the source electrode (a source electrode terminal, a source region, or a source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that, in this specification, the channel region means a region where current flows mainly.

[0136] In this specification, the first electrode can be a drain electrode and the second electrode can be a source electrode, or the first electrode can be a source electrode and the second electrode can be a drain electrode. The functions of the "source electrode" and the "drain electrode" are sometimes interchanged with each other in the case of using a transistor whose polarity is reversed or in the case where the direction of current flowing in a circuit is changed, for example. Therefore, the "source electrode" and the "drain electrode" can be interchanged with each other in this specification.

[0137] In this specification, "electrically connected" includes the case where components are connected through an element having some function of electricity. The element having some function of electricity is not particularly limited as long as electric signals can be transmitted and received between components to be connected. Examples of the element having some function of electricity include not only an electrode and a wiring but also a switching element such as a transistor, a resistor, an inductor, a capacitor, and another element having some function.

[0138] In this specification, "parallel" means a state where an angle formed between two straight lines is greater than or equal to -10° and less than or equal to 10°, and thus a state where the angle is greater than or equal to -5° and less than or equal to 5° is also included. In addition, "perpendicular" means a state where an angle formed between two straight lines is greater than or equal to 80° and less than or equal to 100°, and thus a state where the angle is greater than or equal to 85° and less than or equal to 95° is also included.

[0139] In this specification, a "film" and a "layer" can be interchanged with each other. For example, a "conductive layer" can be replaced with a "conductive film". Similarly, an "insulating film" can be replaced with an "insulating layer".

[0140] In this specification, "about" means not strictly limited to a limit, and allows a range of values within a process and measurement error.

[0141] In an OLED display product, the compensation process of the pixel driving circuit often occurs with the data writing process, so that the compensation time of the pixel driving circuit is short, which reduces the reliability of the pixel driving circuit.

[0142] Therefore, the present disclosure provides a pixel driving circuit, which separates the compensation process of the pixel driving circuit from the data writing process.

[0143] FIG. 1 is a structural schematic diagram of a pixel driving circuit provided by an embodiment of the present disclosure. As shown in FIG. 1, the pixel driving circuit provided by the embodiment of the present disclosure is configured to drive a light emitting device L to emit light, and the pixel driving circuit comprises a first control sub-circuit, a second control sub-circuit, a third control sub-circuit, and a driving sub-circuit.

[0144] As shown in FIG. 1, the first control sub-circuit is electrically connected with a first scan signal line Gate1, a fourth scan signal line Gate4, a fifth scan signal line Gate5, a data signal line Data, a first power supply line VDD, a first node N1, a third node N3, a fourth node N4, and a fifth node N5 respectively, and is configured to provide a signal of the data signal line Data to the fourth node N4 under the control of a signal of at least one of the first scan signal line Gate1, the fourth scan signal line Gate4, and the fifth scan signal line Gate5, control a signal of the fifth node N5 through the signal of the fourth node N4, and provide the signal of the fifth node N5 to the first node N1 and the third node N3.

[0145] As shown in FIG. 1, the second control sub-circuit is electrically connected with a second scan signal line Gate2, a third scan signal line Gate3, a first initial signal line INIT1, a second initial signal line INIT2, a first reference signal line REF1, a second reference signal line REF2, a second node N2, the fourth node N4, the fifth node N5, and a sixth node N6 respectively, and is configured to provide a signal of the second reference signal line REF2 to the second node N2, provide a signal of the first reference signal line REF1 to the fourth node N4, provide a signal of the first initial signal line INIT1 to the fifth node N5, and provide a signal of the second initial signal line INIT2 to the sixth node N6 under the control of a signal of at least one of the second scan signal line Gate2 and the third scan signal line Gate3.

[0146] As shown in FIG. 1, the third control sub-circuit is electrically connected with a first light emitting signal line EM1, a second light emitting signal line EM2, the first power supply line VDD, the second node N2, the third node N3, and the sixth node N6 respectively, and is configured to provide a signal of the first power supply line VDD to the second node N2 and provide a signal of the third node N3 to the sixth node N6 under the control of signals of the first light emitting signal line EM1 and the second light emitting signal line EM2.

[0147] As shown in FIG. 1, the driving sub-circuit is electrically connected with the first node N1, the second node N2, and the third node N3 respectively, and is configured to provide a driving signal to the third node N3.

[0148] As shown in FIG. 1, the light emitting device L is electrically connected with the sixth node N6 and a second power supply line VSS respectively.

[0149] In an example embodiment, the voltage value of the signal of the first initial signal line INIT1 is constant and is a direct current signal, and the voltage value of the signal of the first initial signal line INIT1 can be -3V. In an example embodiment, the direct current signal can be a signal whose magnitude and direction do not change over time.

[0150] In an example embodiment, the voltage value of the signal of the second initial signal line INIT2 is constant and is a direct current signal, and the voltage value of the signal of the second initial signal line INIT2 can be 0V.

[0151] In an example embodiment, the voltage value of the signal of the first reference signal line REF1 and the second reference signal line REF2 is constant and is a direct current signal.

[0152] In an example embodiment, the first power supply line VDD continuously provides a high level signal, and the second power supply line VSS continuously provides a low level signal.

[0153] In an example embodiment, the light emitting device L can include a current driving type device, and can adopt a current type light emitting diode, such as a Micro Light Emitting Diode (Micro LED) or a Mini Light Emitting Diode (Mini LED) or an Organic Light Emitting Diode (OLED) or a Quantum Light Emitting Diode (QLED). The typical size (e.g. length) of the Micro LED can be less than 100μm, for example 10μm to 50μm. The typical size (e.g. length) of the Mini LED can be about 100μm to 300μm, for example 120μm to 260μm.

[0154] In an example embodiment, the light emitting device L can be an Organic Light Emitting Diode (OLED) including a first electrode (anode), an organic light emitting layer and a second electrode (cathode) stacked. Exemplarily, the anode of the light emitting device L is electrically connected to the sixth node N6, and the cathode of the light emitting device L is electrically connected to the second power supply line VSS.

[0155] In an exemplary embodiment, the organic light-emitting layer can include a hole injection layer (HIL), a hole transport layer (HTL), an electron block layer (EBL), an emitting layer (EML), a hole block layer (HBL), an electron transport layer (ETL), and an electron injection layer (EIL) stacked. In an exemplary embodiment, the hole injection layer of all sub-pixels can be a common layer connected together, the electron injection layer of all sub-pixels can be a common layer connected together, the hole transport layer of all sub-pixels can be a common layer connected together, the electron transport layer of all sub-pixels can be a common layer connected together, the hole block layer of all sub-pixels can be a common layer connected together, the emitting layer of adjacent sub-pixels can have a small amount of overlap, or can be isolated, and the electron block layer of adjacent sub-pixels can have a small amount of overlap, or can be isolated.

[0156] The pixel driving circuit provided by the embodiments of the present disclosure can be arranged in a display substrate using high-low frame frequency switching technology. The display substrate can include a first driving mode and a second driving mode, and the refresh rate of the first driving mode is less than the refresh rate of the second driving mode. For example, the refresh rate of the first driving mode can be 1HZ-60HZ, and the refresh rate of the second driving mode can be 60HZ-480HZ.

[0157] In an exemplary embodiment, the first driving mode can be referred to as a low-frequency driving mode, and the second driving mode can be referred to as a high-frequency driving mode. In an exemplary embodiment, the refresh rate refers to the number of times of refreshing data per second of the display substrate. The refresh rate of the first driving mode arranged in the same display substrate is fixed, and the refresh rate of the first driving mode arranged in different display substrates can be different. The refresh rate of the display substrate in the first driving mode can range from 1Hz to 60Hz. For example, the refresh rate in the first driving mode can be about 10Hz, and the refresh rate in the second driving mode can be 120Hz.

[0158] In an exemplary embodiment, the content displayed by the display substrate includes a plurality of display frames. In the first driving mode, the display frames include refresh frames and at least one holding frame. In the second driving mode, the display frames only include refresh frames.

[0159] The pixel driving circuit provided by the present disclosure can normally work in the refresh frame and the holding frame to ensure normal display of the display substrate.

[0160] The pixel driving circuit provided by the present disclosure can make the threshold compensation stage of the pixel driving circuit independent of the data writing stage through cooperation of the first control sub-circuit, the second control sub-circuit and the third control sub-circuit, can prolong the compensation time of the pixel driving circuit, and further improve the reliability of the pixel driving circuit.

[0161] In an example embodiment, FIG. 2 is a structural schematic diagram of the first control sub-circuit provided by an example embodiment. As shown in FIG. 2, the first control sub-circuit includes a writing sub-circuit, a first storage sub-circuit, a communication sub-circuit and a second storage sub-circuit.

[0162] As shown in FIG. 2, the writing sub-circuit is electrically connected with the first scan signal line Gate1, the data signal line Data and the fourth node N4 respectively, and is configured to provide the signal of the data signal line Data to the fourth node N4 under the control of the signal of the first scan signal line Gate1.

[0163] As shown in FIG. 2, the first storage sub-circuit is electrically connected with the fourth node N4 and the fifth node N5 respectively, and is configured to store the voltage difference between the signals of the fourth node N4 and the fifth node N5.

[0164] As shown in FIG. 2, the communication sub-circuit is electrically connected with the fourth scan signal line Gate4, the fifth scan signal line Gate5, the first node N1, the third node N3 and the fifth node N5 respectively, and is configured to provide the signal of the fifth node N5 to the third node N3 under the control of the signal of the fifth scan signal line Gate5, and provide the signal of the fifth node N5 to the first node N1 under the control of the signal of the fourth scan signal line Gate4.

[0165] As shown in FIG. 2, the second storage sub-circuit is electrically connected with the first node N1 and the first power supply line VDD respectively, and is configured to store the voltage difference between the signals of the first node N1 and the first power supply line VDD.

[0166] In an example embodiment, the signal received by the fifth scan signal line Gate5 can be the same as the signal received by the first emission signal line EM1. For example, the fifth scan signal line Gate5 and the first emission signal line EM1 can be the same signal line.

[0167] In an example embodiment, FIG. 3 is an equivalent circuit diagram of the first control sub-circuit provided in FIG. 2. As shown in FIG. 3, the communication sub-circuit includes: a second transistor T2 and an eighth transistor T8. Wherein, the control electrode of the second transistor T2 is electrically connected with the fifth scan signal line Gate5, the first electrode of the second transistor T2 is electrically connected with the fifth node N5, and the second electrode of the second transistor T2 is electrically connected with the third node N3; the control electrode of the eighth transistor T8 is electrically connected with the fourth scan signal line Gate4, the first electrode of the eighth transistor T8 is electrically connected with the fifth node N5, and the second electrode of the eighth transistor T8 is electrically connected with the first node N1.

[0168] In the present disclosure, the eighth transistor T8 is configured to separate the fifth node N5 and the first node N1 when the eighth transistor is in an off state, thereby reducing the influence of the fifth node N5 on the first node N1.

[0169] In an example embodiment, as shown in FIG. 3, the write sub-circuit includes: a fourth transistor T4. Wherein, the control electrode of the fourth transistor T4 is electrically connected with the first scan signal line Gate1, the first electrode of the fourth transistor T4 is electrically connected with the data signal line Data, and the second electrode of the fourth transistor T4 is electrically connected with the fourth node N4. The fourth transistor T4 can be referred to as a write transistor.

[0170] In an example embodiment, as shown in FIG. 3, the first storage sub-circuit includes: a first capacitor C1. The first capacitor C1 includes: a first plate C11 and a second plate C12. Wherein, the first plate C11 of the first capacitor C1 is electrically connected with the fifth node N5, and the second plate C12 of the first capacitor C1 is electrically connected with the fourth node N4.

[0171] In an example embodiment, as shown in FIG. 3, the second storage sub-circuit includes: a second capacitor C2. The second capacitor C2 includes: a first plate C21 and a second plate C22. Wherein, the first plate C21 of the second capacitor C2 is electrically connected with the first node N1, and the second plate C22 of the second capacitor C2 is electrically connected with the first power supply line VDD.

[0172] In the present disclosure, the second capacitor C2 is configured to ensure the stability of the signal of the first node N1, thereby improving the reliability of the pixel driving circuit.

[0173] An example structure of the first control sub-circuit is shown in FIG. 3. It is easy for those skilled in the art to understand that the implementation of the first control sub-circuit is not limited thereto.

[0174] In an example embodiment, FIG. 4 is a structure schematic diagram of a second control sub-circuit provided in an example embodiment. As shown in FIG. 4, the second control sub-circuit includes: a first sub-circuit, a second sub-circuit, a third sub-circuit and a fourth sub-circuit.

[0175] In an example embodiment, as shown in FIG. 4, the first sub-circuit, electrically connected with the second scan signal line Gate2, the first initial signal line INIT1 and the fifth node N5 respectively, is configured to provide the signal of the first initial signal line INIT1 to the fifth node N5 under the control of the signal of the second scan signal line Gate2.

[0176] In an example embodiment, as shown in FIG. 4, the second sub-circuit, electrically connected with the third scan signal line Gate3, the first reference signal line REF1 and the fourth node N4 respectively, is configured to provide the signal of the first reference signal line REF1 to the fourth node N4 under the control of the signal of the third scan signal line Gate3.

[0177] In an example embodiment, as shown in FIG. 4, the third sub-circuit, electrically connected with the second scan signal line Gate2, the second reference signal line REF2 and the second node N2 respectively, is configured to provide the signal of the second reference signal line REF2 to the second node N2 under the control of the signal of the second scan signal line Gate2.

[0178] In an example embodiment, as shown in FIG. 4, the fourth sub-circuit, electrically connected with the second scan signal line Gate2, the second initial signal line INIT2 and the sixth node N6 respectively, is configured to provide the signal of the second initial signal line INIT2 to the sixth node N6 under the control of the signal of the second scan signal line Gate2.

[0179] In an example embodiment, FIG. 5 is an equivalent circuit diagram of the second control sub-circuit provided in FIG. 4. As shown in FIG. 5, the first sub-circuit includes a first transistor T1. Wherein, the control electrode of the first transistor T1 is electrically connected with the second scan signal line Gate2, the first electrode of the first transistor T1 is electrically connected with the first initial signal line INIT1, and the second electrode of the first transistor T1 is electrically connected with the fifth node N5. The first transistor T1 can be referred to as a first initialization transistor.

[0180] In an example embodiment, as shown in FIG. 5, the second sub-circuit includes a seventh transistor T7. Wherein, the control electrode of the seventh transistor T7 is electrically connected with the third scan signal line Gate3, the first electrode of the seventh transistor T7 is electrically connected with the first reference signal line REF1, and the second electrode of the seventh transistor T7 is electrically connected with the fourth node N4.

[0181] In an example embodiment, as shown in FIG. 5, the third sub-circuit includes a ninth transistor T9. The control electrode of the ninth transistor T9 is electrically connected with the second scan signal line Gate2, the first electrode of the ninth transistor T9 is electrically connected with the second reference signal line REF2, and the second electrode of the ninth transistor T9 is electrically connected with the second node N2. The ninth transistor T9 can be referred to as a bias transistor.

[0182] The arrangement of the ninth transistor T9 in the present disclosure can widen the voltage difference between the control electrode and the first electrode of the third transistor, and can make the third transistor T3 (also a drive transistor) in a bias state for a part of time, thereby improving the hysteresis phenomenon.

[0183] In an example embodiment, as shown in FIG. 5, the fourth sub-circuit includes a tenth transistor T10. The control electrode of the tenth transistor T10 is electrically connected with the second scan signal line Gate2, the first electrode of the tenth transistor T10 is electrically connected with the second initial signal line INIT2, and the second electrode of the tenth transistor T10 is electrically connected with the sixth node N6. The tenth transistor T10 can be referred to as a second initialization transistor.

[0184] An example structure of the second control sub-circuit is shown in FIG. 5. It is easily understood by those skilled in the art that the implementation of the second control sub-circuit is not limited thereto.

[0185] In an example embodiment, FIG. 6 is an equivalent circuit diagram of the drive sub-circuit and the third control sub-circuit. As shown in FIG. 6, the drive sub-circuit includes a third transistor T3. The control electrode of the third transistor T3 is electrically connected with the first node N1, the first electrode of the third transistor T3 is electrically connected with the second node N2, and the second electrode of the third transistor T3 is electrically connected with the third node N3. The third transistor T3 can be referred to as a drive transistor, and the third transistor T3 determines the drive current flowing between the first power supply line VDD and the second power supply line VSS according to the potential difference between its control electrode and second electrode.

[0186] An example structure of the drive sub-circuit is shown in FIG. 6. It is easily understood by those skilled in the art that the implementation of the drive sub-circuit is not limited thereto.

[0187] In an example embodiment, as shown in FIG. 6, the third control sub-circuit includes a fifth transistor T5 and a sixth transistor T6. The control electrode of the fifth transistor T5 is electrically connected with the first light-emitting signal line EM1, the first electrode of the fifth transistor T5 is electrically connected with the first power supply line VDD, and the second electrode of the fifth transistor T5 is electrically connected with the second node N2. The control electrode of the sixth transistor T6 is electrically connected with the second light-emitting signal line EM2, the first electrode of the sixth transistor T6 is electrically connected with the third node N3, and the second electrode of the sixth transistor T6 is electrically connected with the sixth node N6. The fifth transistor T5 can be referred to as a first light-emitting transistor, and the sixth transistor T6 can be referred to as a second light-emitting transistor. When the signals of the first light-emitting signal line EM1 and the second light-emitting signal line EM2 are active level signals, the fifth transistor T5 and the sixth transistor T6 make the light-emitting device emit light by forming a driving current path between the first power supply line VDD and the second power supply line VSS.

[0188] An example structure of the third control sub-circuit is shown in FIG. 6. It is easily understood by those skilled in the art that the implementation of the third control sub-circuit is not limited thereto.

[0189] FIG. 7 is an equivalent circuit diagram of a pixel driving circuit provided by an example embodiment. As shown in FIG. 7, the first control sub-circuit includes a second transistor T2, a fourth transistor T4, an eighth transistor T8, a first capacitor C1 and a second capacitor C2, at least one of the first capacitor C1 and the second capacitor C2 includes a first plate and a second plate, the second control sub-circuit includes a first transistor T1, a seventh transistor T7, a ninth transistor T9 and a tenth transistor T10, the third control sub-circuit includes a fifth transistor T5 and a sixth transistor T6, and the driving sub-circuit includes a third transistor T3. The control electrode of the first transistor T1 is electrically connected with a second scan signal line Gate2, the first electrode of the first transistor T1 is electrically connected with a first initial signal line INIT1, and the second electrode of the first transistor T1 is electrically connected with a fifth node N5; the control electrode of the second transistor T2 is electrically connected with a fifth scan signal line Gate5, the first electrode of the second transistor T2 is electrically connected with the fifth node N5, and the second electrode of the second transistor T2 is electrically connected with a third node N3; the control electrode of the third transistor T3 is electrically connected with a first node N1, the first electrode of the third transistor T3 is electrically connected with a second node N2, and the second electrode of the third transistor T3 is electrically connected with the third node N3; the control electrode of the fourth transistor T4 is electrically connected with a first scan signal line Gate1, the first electrode of the fourth transistor T4 is electrically connected with a data signal line Data, and the second electrode of the fourth transistor T4 is electrically connected with a fourth node N4; the control electrode of the fifth transistor T5 is electrically connected with a first emission signal line EM1, the first electrode of the fifth transistor T5 is electrically connected with a first power supply line VDD, and the second electrode of the fifth transistor T5 is electrically connected with the second node N2; the control electrode of the sixth transistor T6 is electrically connected with a second emission signal line EM2, the first electrode of the sixth transistor T6 is electrically connected with the third node N3, and the second electrode of the sixth transistor T6 is electrically connected with a sixth node N6; the control electrode of the seventh transistor T7 is electrically connected with a third scan signal line Gate3, the first electrode of the seventh transistor T7 is electrically connected with a first reference signal line REF1, and the second electrode of the seventh transistor T7 is electrically connected with the fourth node N4; the control electrode of the eighth transistor T8 is electrically connected with a fourth scan signal line Gate4, the first electrode of the eighth transistor T8 is electrically connected with the fifth node N5, and the second electrode of the eighth transistor T8 is electrically connected with the first node N1.The control electrode of the ninth transistor T9 is electrically connected with the second scan signal line Gate2, the first electrode of the ninth transistor T9 is electrically connected with the second reference signal line REF2, and the second electrode of the ninth transistor T9 is electrically connected with the second node N2; the control electrode of the tenth transistor T10 is electrically connected with the second scan signal line Gate2, the first electrode of the tenth transistor T10 is electrically connected with the second initial signal line INIT2, and the second electrode of the tenth transistor T10 is electrically connected with the sixth node N6; the first plate C11 of the first capacitor C1 is electrically connected with the fifth node N5, and the second plate C12 of the first capacitor C1 is electrically connected with the fourth node N4; the first plate C21 of the second capacitor C2 is electrically connected with the first node N1, and the second plate C22 of the second capacitor C2 is electrically connected with the first power supply line VDD.

[0190] According to the characteristics of the transistor, the transistor can be divided into an N-type transistor and a P-type transistor. When the transistor is a P-type transistor, the on voltage is a low voltage (for example, 0V, -5V, -10V or other suitable voltage), and the off voltage is a high voltage (for example, 5V, 10V or other suitable voltage). When the transistor is an N-type transistor, the on voltage is a high voltage (for example, 5V, 10V or other suitable voltage), and the off voltage is a low voltage (for example, 0V, -5V, -10V or other suitable voltage).

[0191] In an example embodiment, the N-type transistor can be an oxide thin film transistor. The active layer of the oxide thin film transistor adopts an oxide semiconductor. The oxide thin film transistor has the advantages of low leakage current, uniform film formation, good transistor hysteresis characteristics and low manufacturing cost.

[0192] In an example embodiment, the P-type transistor can be a low-temperature polysilicon transistor. The low-temperature polysilicon transistor has the advantages of high mobility and fast charging.

[0193] In an example embodiment, the transistor type of the eighth transistor T8 is different from the transistor type of at least one of the first transistor T1 to the seventh transistor T7, the ninth transistor T9 and the tenth transistor T10.

[0194] In an example embodiment, the eighth transistor T8 is an N-type transistor. The eighth transistor T8 being an N-type transistor can avoid leakage current flowing from the first node N1, can ensure the stability of the signal of the first node N1, can improve the performance of the pixel driving circuit, can reduce the power consumption of the pixel driving circuit, can also avoid flicker of the display substrate on which the pixel driving circuit is located, and improves the display effect of the display substrate.

[0195] In an exemplary embodiment, the transistor type of at least one of the first transistor T1 to the seventh transistor T7, the ninth transistor T9, and the tenth transistor T10 can be a P-type transistor.

[0196] In an exemplary embodiment, when the pixel driving circuit includes a P-type transistor and an N-type transistor, i.e., low-temperature polycrystalline silicon transistors and oxide transistors are integrated on one display substrate to form a low-temperature polycrystalline oxide (LTPO) combined display substrate, the advantages of both can be utilized, low-frequency driving can be achieved, power consumption can be reduced, and display quality can be improved.

[0197] FIG. 8 is a driving timing diagram of the pixel driving circuit provided in FIG. 7 in a refresh frame, and FIG. 9 is a driving timing diagram of the pixel driving circuit provided in FIG. 7 in a hold frame. FIGS. 8 and 9 are described by way of example with the eighth transistor T8 in the pixel driving circuit in FIG. 7 being an N-type transistor, at least one of the first transistor T1 to the seventh transistor T7, the ninth transistor T9, and the tenth transistor T10 being a P-type transistor, and the signal received by the fifth scan signal line Gate5 being the same as the signal received by the first emission signal line EM1.

[0198] As shown in FIG. 8, in a refresh frame, the time period in which the signal of the first emission signal line EM1 is a valid level signal includes a first time period t1 and a second time period t2, and the first time period t1 occurs before the second time period t2.

[0199] In an exemplary embodiment, as shown in FIG. 8, the time in which the signal of the first scan signal line Gate1 is a valid level signal occurs between the first time period t1 and the second time period t2. The signal of the signal line being a valid level signal refers to a signal that causes the transistor connected to the signal line to be in a conductive state, wherein the transistor connected to the signal line includes the connection between the signal line and the control electrode of the transistor.

[0200] In an exemplary embodiment, as shown in FIG. 8, the time period in which the signal of the second scan signal line Gate2 is a valid level signal includes a third time period t3 and a fourth time period t4, the third time period t3 occurs before the first time period t1, and the fourth time period t4 occurs between the first time period t1 and the second time period t2.

[0201] In an exemplary embodiment, as shown in FIG. 8, the time period during which the signal of the third scan signal line Gate3 is the active level signal at least partially overlaps with at least one of the first time period t1 and the third time period t3. Exemplarily, the start time of the time period during which the signal of the third scan signal line Gate3 is the active level signal is later than the start time of the third time period t3 and earlier than the end time of the third time period t3, and the end time of the time period during which the signal of the third scan signal line Gate3 is the active level signal is earlier than the start time of the time period during which the signal of the first scan signal line Gate1 is the active level signal.

[0202] In an exemplary embodiment, as shown in FIG. 8, the time period during which the signal of the fourth scan signal line Gate4 is the active level signal at least partially overlaps with at least one of the first time period t1 and the third time period t3. The start time of the time period during which the signal of the fourth scan signal line Gate4 is the active level signal is later than the start time of the third time period t3 and earlier than the start time of the time period during which the signal of the third scan signal line Gate3 is the active level signal, and the end time of the time period during which the signal of the fourth scan signal line Gate4 is the active level signal is later than the end time of the time period during which the signal of the first scan signal line Gate1 is the active level signal and earlier than the start time of the fourth time period t4.

[0203] In an exemplary embodiment, as shown in FIG. 8, the time during which the signal of the second emission signal line EM2 is the active level signal at least partially overlaps with the second time period t2.

[0204] The working process of the pixel driving circuit exemplified by FIG. 7 is described below to illustrate the exemplary embodiments of the present disclosure. As shown in FIG. 7 and FIG. 8, the working process of the pixel driving circuit provided by FIG. 7 in the refresh frame can include:

[0205] In the first stage P1, the initialization stage, the signals of the first scan signal line Gate1, the third scan signal line Gate3, the fourth scan signal line Gate4, the fifth scan signal line Gate5, the first emission signal line EM1 and the second emission signal line EM2 are high level signals, and the signal of the second scan signal line Gate2 is a low level signal. The first transistor T1, the eighth transistor T8, the ninth transistor T9 and the tenth transistor T10 are turned on, and the second transistor T2, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6 and the seventh transistor T7 are turned off.

[0206] The first transistor T1 is turned on, and the signal from the first initial signal line INIT1 is written to the fifth node N5, initializing the fifth node N5 and clearing its charge. The eighth transistor T8 is turned on, and the signal from the fifth node N5 is written to the first node N1, initializing the first node N1 and clearing its charge. The ninth transistor T9 is turned on, and the signal from the second reference signal line REF is written to the second node. The tenth transistor T10 is turned on, and the signal from the second initial signal line INIT2 is written to the sixth node N6, initializing the sixth node N6 and clearing its charge.

[0207] In this phase, the voltage value V of the signal at the first node N1 N1 =Vinit1, the voltage value V of the signal at the second node N2. N2 =Vref2, the voltage value V of the signal at the fifth node N5. N5 =Vinit1, the voltage value V of the signal at the sixth node N6. N6 =Vinit2, where Vinit1 is the voltage value of the first initial signal line INIT1, Vinit2 is the voltage value of the second initial signal line INIT2, and Vref2 is the voltage value of the second reference signal line REF2.

[0208] In the second stage, P2, the threshold compensation stage, the signals of the first scan signal line Gate1, the second scan signal line Gate2, the fourth scan signal line Gate4, and the second light-emitting signal line EM2 are high-level signals, while the signals of the third scan signal line Gate3, the fifth scan signal line Gate5, and the first light-emitting signal line EM1 are low-level signals. The second transistor T2, the fifth transistor T5, the seventh transistor T7, and the eighth transistor T8 are turned on, while the first transistor T1, the fourth transistor T4, the sixth transistor T6, the ninth transistor T9, and the tenth transistor T10 are turned off.

[0209] When the seventh transistor T7 is turned on, the signal of the first reference signal line REF1 is written to the fourth node N4. The second transistor T2, the fifth transistor T5, and the eighth transistor T8 are turned on, and the signal of the first power line VDD is written to the first node N1 through the turned-on fifth transistor T5, the second node N2, the turned-on third transistor T3, the third node N3, the turned-on second transistor T2, the fifth node N5, and the turned-on eighth transistor T8, until the voltage value of the signal at the first node N1 satisfies V... N1 =Vdd+Vth, where Vdd is the voltage value of the signal on the first power line VDD, and Vth is the threshold voltage of the third transistor T3.

[0210] In this phase, the voltage value V of the signal at the first node N1 N1 =Vdd + Vth, where V is the voltage value of the signal at the second node N2.N2 = Vdd, the voltage value V of the signal of the third node N3 N3 = Vdd+Vth, the voltage value V of the signal of the fourth node N4 N4 = Vref1, the voltage value V of the signal of the fifth node N5 N5 = Vdd+Vth, Vref1 is the voltage value of the signal of the first reference signal line REF1.

[0211] The third stage P3, the data write stage, the signals of the second scan signal line Gate2, the third scan signal line Gate3, the fourth scan signal line Gate4, the fifth scan signal line Gate5, the first light-emitting signal line EM1 and the second light-emitting signal line EM2 are high-level signals, and the signal of the first scan signal line Gate1 is a low-level signal. The fourth transistor T4 and the eighth transistor T8 are turned on. The first transistor T1, the second transistor T2, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, the eighth transistor T8, the ninth transistor T9 and the tenth transistor T10 are turned off.

[0212] The fourth transistor T4 is turned on, and the data signal of the data signal line Data is written to the fourth node N4. Due to the jump of the signal of the fourth node N4, the signal of the fifth node N5 also jumps under the action of the first capacitor C1. The voltage value V of the signal of the fifth node N5 N5 = Vdd+Vth+α(Vdata-Vref1), 0<α<1, Vdata is the voltage value of the data signal of the data signal line, the eighth transistor T8 is turned on, and the signal of the fifth node N5 is written to the first node N1.

[0213] In this stage, the voltage value V of the signal of the first node N1 N1 = Vdd+Vth+α(Vdata-Vref1), the voltage value V of the signal of the fourth node N4 N4 = Vdata, the voltage value V of the signal of the fifth node N5 N5 = Vdd+Vth+α(Vdata-Vref1).

[0214] The fourth stage P4, the bias stage, the signals of the first scan signal line Gate1, the third scan signal line Gate3, the fifth scan signal line Gate5, the first light-emitting signal line EM1 and the second light-emitting signal line EM2 are high-level signals, and the signals of the second scan signal line Gate2 and the fourth scan signal line Gate4 are low-level signals. The first transistor T1, the ninth transistor T9 and the tenth transistor T10 are turned on, and the second transistor T2, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7 and the eighth transistor T8 are turned off.

[0215] The first transistor Tl is turned on, the signal of the first initial signal line INIT1 is written to the fifth node N5, and the first node Nl keeps the signal of the last stage because the eighth transistor T8 is turned off and is not affected by the signal of the fifth node N5. The ninth transistor T9 is turned on, the signal of the second reference signal line REF is written to the second node N2, and the signal of the second reference signal line written to the second node N2 in this stage can bias the third transistor T3 so that the third transistor T3 is in a bias state because the voltage value of the signal of the first node Nl is Vdd+Vth+α(Vdata-Vrefl). The tenth transistor T10 is turned on, the signal of the second initial signal line INIT2 is written to the sixth node N6, the sixth node N6 is initialized, and the charge of the sixth node N6 is cleared.

[0216] In this stage, the voltage value V N1 =Vdd+Vth+α(Vdata-Vrefl) of the signal of the first node Nl, the voltage value V N2 =Vref2 of the signal of the second node N2, the voltage value V N5 =Vinitl of the signal of the fifth node N5, and the voltage value V N6 =Vinit2 of the signal of the sixth node N6.

[0217] The fifth stage P5 is a light emitting stage, the signals of the first scan signal line Gate 1, the second scan signal line Gate2, and the third scan signal line Gate3 are high level signals, and the signals of the fourth scan signal line Gate4, the fifth scan signal line Gate5, the first light emitting signal line EMl, and the second light emitting signal line EM2 are low level signals. The second transistor T2, the fifth transistor T5, and the sixth transistor T6 are turned on,

[0218] The fifth transistor T5 and the sixth transistor T6 are turned on so that the power voltage output by the first power supply line VDD is provided to the sixth node N6 (also the first electrode of the light emitting device L) through the turned-on fifth transistor T5, the second node N2, the turned-on third transistor T3, the third node N3, and the turned-on sixth transistor T6 to drive the light emitting device L to emit light.

[0219] In the driving process of the pixel driving circuit, the driving current flowing through the third transistor T3 (a driving transistor) of each pixel driving circuit is determined by the voltage difference between the gate electrode and the second electrode thereof. Because the voltage of the signal of the first node Nl satisfies V N1 =Vdd+Vth+α(Vdata-Vrefl), the voltage of the signal of the second node N2 satisfies V N2 =Vdd.

[0220] Thus, the driving current I of the third transistor T3 is:

[0221] I = K * (Vgs - Vth) 2

[0222] = K * [Vdd + Vth + a (Vdata - Vrefl) - Vdd - Vth] 2

[0223] = K * [a (Vdata - Vrefl)] 2

[0224] Wherein, I is the driving current flowing through the third transistor T3, that is, the driving current of the light emitting device L, K is a constant related to the process and design of the pixel driving circuit, and Vgs is the voltage difference between the control electrode and the first electrode of the third transistor T3.

[0225] As shown in FIG. 9, in the holding frame, the signals of at least one of the first scan signal line Gate1, the third scan signal line Gate3 and the fourth scan signal line Gate4 are continuously invalid level signals.

[0226] As shown in FIG. 7 and FIG. 9, the working process of the pixel driving circuit provided in FIG. 7 in the holding frame can include:

[0227] The sixth stage P6, the holding bias stage, the signals of the first scan signal line Gate1, the third scan signal line Gate3, the fifth scan signal line Gate5, the first light emitting signal line EM1 and the second light emitting signal line EM2 are high level signals, and the signals of the second scan signal line Gate2 and the fourth scan signal line Gate4 are low level signals. The first transistor T1, the ninth transistor T9 and the tenth transistor T10 are turned on, and the second transistor T2, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7 and the eighth transistor T8 are turned off.

[0228] The first transistor T1 is turned on, and the signal of the first initial signal line INIT1 is written to the fifth node N5. Since the eighth transistor T8 is turned off, the first node N1 keeps the signal of the last stage and is not affected by the signal of the fifth node N5. The ninth transistor T9 is turned on, and the signal of the second reference signal line REF is written to the second node N2. Since the voltage value of the signal of the first node N1 is Vdd+Vth+ a (Vdata-Vrefl), the signal of the second reference signal line written to the second node N2 in this stage can bias the third transistor T3, so that the third transistor T3 is in a bias state. The tenth transistor T10 is turned on, and the signal of the second initial signal line INIT2 is written to the sixth node N6, which initializes the sixth node N6 and clears the charge of the sixth node N6.

[0229] In the seventh stage P7, the signals of the first scan signal line Gate1, the second scan signal line Gate2 and the third scan signal line Gate3 are high level signals, and the signals of the fourth scan signal line Gate4, the fifth scan signal line Gate5, the first light-emitting signal line EM1 and the second light-emitting signal line EM2 are low level signals. The second transistor T2, the fifth transistor T5 and the sixth transistor T6 are turned on,

[0230] The turning on of the fifth transistor T5 and the sixth transistor T6 enables the power supply voltage output by the first power supply line VDD to be provided to the sixth node N6 (also the first electrode of the light-emitting device L) through the turned-on fifth transistor T5, the second node N2, the turned-on third transistor T3, the third node N3 and the turned-on sixth transistor T6, so as to drive the light-emitting device L to emit light.

[0231] According to the working process of the pixel driving circuit, it can be known that the threshold compensation stage and the data writing stage of the pixel driving circuit provided by the present disclosure are independently set, and the time of threshold compensation depends on the time length of the first time period in which the first light-emitting signal line is an effective level signal. The pixel driving circuit provided by the present disclosure can prolong the threshold compensation time of the pixel driving circuit, so that the threshold compensation is more sufficient. Not only the display effect of the display substrate can be improved, but also the threshold voltage of the third transistor can be kept stable, which can greatly improve the residual image and further improve the display effect of the display substrate.

[0232] The present disclosure further provides a driving method of a pixel driving circuit, which is configured as the pixel driving circuit provided by any one of the foregoing embodiments. The driving method of the pixel driving circuit can include the following steps:

[0233] In step 100, the first control sub-circuit provides, under the control of the signals of at least one of the first scan signal line, the fourth scan signal line and the fifth scan signal line, the signal of the data signal line to the fourth node, controls the signal of the fifth node through the signal of the fourth node, and provides the signal of the fifth node to the first node and the third node.

[0234] In step 200, the second control sub-circuit provides, under the control of the signals of at least one of the second scan signal line and the third scan signal line, the signal of the second reference signal line to the second node, the signal of the first reference signal line to the fourth node, the signal of the first initial signal line to the fifth node, and the signal of the second initial signal line to the sixth node.

[0235] In step 300, the third control sub-circuit provides, under the control of the signals of the first light-emitting signal line and the second light-emitting signal line, the signal of the first power supply line to the second node and the signal of the third node to the sixth node.

[0236] Step 400, the driving sub-circuit provides a driving signal to the third node.

[0237] FIG. 10 is a structural schematic diagram of a display substrate provided by an embodiment of the present disclosure. As shown in FIG. 10, the display device provided by the embodiment of the present disclosure further includes: a display substrate, the display substrate includes: a substrate and a plurality of sub-pixels arranged in an array on the substrate, at least one sub-pixel of the plurality of sub-pixels includes the pixel driving circuit provided by any one of the foregoing embodiments. FIG. 10 is an example of illustrating one row and three columns of pixel driving circuits, and the fifth scan signal line connected to at least one pixel driving circuit is the same as the first light-emitting signal line.

[0238] In an example embodiment, as shown in FIG. 10, for at least one row of sub-pixels, two adjacent sub-pixels of the at least one sub-pixel include: a first adjacent sub-pixel and a second adjacent sub-pixel. The structure of the pixel driving circuit of the at least one sub-pixel is at least partially symmetrical to the structure of the pixel driving circuit of the first adjacent sub-pixel along a straight line extending in the second direction D2, and the structure of the pixel driving circuit of the at least one sub-pixel is at least partially the same as the structure of the pixel driving circuit of the second adjacent sub-pixel. In FIG. 10, the pixel driving circuit of the at least one sub-pixel is P2, the pixel driving circuit of the first adjacent sub-pixel is P1, and the pixel driving circuit of the second adjacent sub-pixel is P3.

[0239] In an example embodiment, as shown in FIG. 10, the display device further includes: a plurality of data signal lines Data, one of the plurality of data signal lines Data extends along the second direction D2.

[0240] In an example embodiment, for at least one row of sub-pixels, the plurality of data signal lines Data connected to the pixel driving circuit of the at least one sub-pixel and the plurality of data signal lines Data connected to the pixel driving circuit of the first adjacent sub-pixel are arranged symmetrically along a straight line extending in the second direction, and the plurality of data signal lines Data connected to the pixel driving circuit of the at least one sub-pixel and the plurality of data signal lines Data connected to the pixel driving circuit of the second adjacent sub-pixel are arranged symmetrically.

[0241] In an example embodiment, FIG. 11 is a schematic diagram of the partial film layer in FIG. 10. As shown in FIGS. 10 and 11, the pixel driving circuit of the at least one sub-pixel includes a second transistor T2, a third transistor T3, and a sixth transistor T6. The first electrode and the second electrode of at least one of the second transistor T2, the third transistor T3, and the sixth transistor T6 in the pixel driving circuit of the at least one sub-pixel do not overlap in the orthogonal projection on the base. The control electrode of the third transistor in the pixel driving circuit of the at least one sub-pixel does not overlap in the orthogonal projection on the base. The third transistor in FIGS. 10 and 11 is covered by the second capacitor.

[0242] The orthogonal projection of the at least one data signal line Data and the first electrode and the second electrode of at least one of the second transistor T2, the third transistor T3, and the sixth transistor T6 in the pixel driving circuit of the at least one sub-pixel on the base in the present disclosure can avoid the influence of the data signal line on the signal of the fourth node in the pixel driving circuit, can ensure the stability of the signal of the fourth node in the pixel driving circuit, and improves the reliability of the pixel driving circuit.

[0243] The orthogonal projection of the at least one data signal line Data and the control electrode of the third transistor T3 in the pixel driving circuit of the at least one sub-pixel on the base in the present disclosure can avoid the influence of the data signal line on the signal of the first node in the pixel driving circuit, can ensure the stability of the signal of the first node in the pixel driving circuit, and improves the reliability of the pixel driving circuit.

[0244] In an example embodiment, as shown in FIG. 10, the display device further includes a plurality of second scan signal lines Gate2, and the plurality of second scan signal lines Gate2 extend at least partially along the first direction D1, and the first direction D1 intersects the second direction D2.

[0245] As shown in FIG. 11, the pixel driving circuit of the at least one sub-pixel includes a first transistor T1, a ninth transistor T9, and a tenth transistor T10.

[0246] As shown in FIGS. 10 and 11, the pixel driving circuit of the at least one sub-pixel is electrically connected with two second scan signal lines Gate2, the control electrode of the first transistor T1 in the pixel driving circuit of the at least one sub-pixel is electrically connected with the first second scan signal line Gate2 of the two second scan signal lines Gate2 to which the pixel driving circuit of the at least one sub-pixel is connected, and the control electrode of at least one of the ninth transistor T9 and the tenth transistor T10 in the pixel driving circuit of the at least one sub-pixel is electrically connected with the first second scan signal line Gate2 of the two second scan signal lines Gate2 to which the pixel driving circuit of the at least one sub-pixel is connected.

[0247] In an exemplary embodiment, as shown in FIGS. 10 and 11, the display device further comprises a plurality of first initial signal lines INIT1, a plurality of second initial signal lines INIT2, a plurality of first reference signal lines REF1, a plurality of second reference signal lines REF2, a plurality of first scan signal lines Gate1, a plurality of third scan signal lines Gate3, a plurality of fourth scan signal lines Gate4, a plurality of first emission signal lines EM1, and a plurality of second emission signal lines EM2.

[0248] In an exemplary embodiment, at least part of at least one of the plurality of first initial signal lines INIT1, the plurality of second initial signal lines INIT2, the plurality of first reference signal lines REF1, the plurality of second reference signal lines REF2, the plurality of first scan signal lines Gate1, the plurality of third scan signal lines Gate3, the plurality of fourth scan signal lines Gate4, the plurality of first emission signal lines EM1, and the plurality of second emission signal lines EM2 extends along the first direction D1.

[0249] In an exemplary embodiment, the orthogonal projection of the first reference signal line REF1 to which the pixel driving circuit of the at least one sub-pixel is connected, the orthogonal projection of the third scan signal line Gate3, the orthogonal projection of the first scan signal line Gate1, the orthogonal projection of the first second scan signal line Gate2, the orthogonal projection of the fourth scan signal line Gate4, the orthogonal projection of the first emission signal line EM1, the orthogonal projection of the second emission signal line EM2, the orthogonal projection of the first second scan signal line Gate2, and the orthogonal projection of the second reference signal line REF2 on the substrate are arranged in sequence along the second direction D2.

[0250] In an exemplary embodiment, the orthogonal projection of the first initial signal line INIT1 on the substrate is located between the orthogonal projection of the first scan signal line Gate1 and the orthogonal projection of the fourth scan signal line Gate4 on the substrate, and at least partially overlaps with the orthogonal projection of the first second scan signal line Gate2 on the substrate.

[0251] In an exemplary embodiment, the orthogonal projection of the second initial signal line INIT2 on the substrate is located between the orthogonal projection of the second light-emitting signal line EM2 on the substrate and the orthogonal projection of the second reference signal line REF2 on the substrate, and at least partially overlaps the orthogonal projection of the second second scan signal line Gate2 on the substrate.

[0252] In an exemplary embodiment, as shown in FIGS. 10 and 11, the pixel driving circuit of the at least one sub-pixel includes a first capacitor C1 and a second capacitor C2; for the pixel driving circuit of the at least one sub-pixel, the orthogonal projection of the first capacitor C1 on the substrate is located between the orthogonal projection of at least one of the first second scan signal line Gate2 and the first initial signal line INIT1 connected with the pixel driving circuit on the substrate and the orthogonal projection of the fourth scan signal line Gate4 on the substrate.

[0253] In an exemplary embodiment, as shown in FIGS. 10 and 11, the orthogonal projection of the second capacitor C2 on the substrate is located between the orthogonal projection of the first light-emitting signal line EM1 connected with the pixel driving circuit on the substrate and the orthogonal projection of the second light-emitting signal line EM2 on the substrate.

[0254] In an exemplary embodiment, as shown in FIG. 10, the display device can further include a plurality of first power supply lines VDD, one of the plurality of first power supply lines VDD extends along the second direction D2.

[0255] In an exemplary embodiment, for the at least one row of sub-pixels, the first power supply line connected with the pixel driving circuit of the at least one sub-pixel and the first power supply line connected with the pixel driving circuit of the first adjacent sub-pixel are symmetrically arranged along a straight line extending in the second direction, and the first power supply line connected with the pixel driving circuit of the at least one sub-pixel and the first power supply line connected with the pixel driving circuit of the second adjacent sub-pixel are structurally identical.

[0256] In an exemplary embodiment, as shown in FIG. 10, the at least one data signal line Data includes a plurality of first data connection portions DA and a plurality of second data connection portions DB, the plurality of first data connection portions DA and the plurality of second data connection portions DB are alternately arranged, and at least one of the first data connection portion DA and the second data connection portion DB extends along the second direction D2.

[0257] In an exemplary embodiment, as shown in FIG. 10, the orthogonal projection of the first data connection part DA on the substrate at least partially overlaps with the orthogonal projection on the substrate of at least one of the first reference signal line REF1, the third scan signal line Gate3, the first scan signal line Gate1, the first second scan signal line Gate2, the first initial signal line INIT1, the fourth scan signal line Gate4, the first emission signal line EM1, at least one of the signal lines among the power connection lines, and at least one of the first capacitor C1 and the second capacitor C2 in the pixel driving circuit of the at least one sub-pixel.

[0258] In an exemplary embodiment, as shown in FIG. 10, the orthogonal projection of the second data connection part DB on the substrate at least partially overlaps with the orthogonal projection on the substrate of at least one of the second emission signal line EM2, the second scan signal line, the second initial signal line INIT2, and the second reference signal line REF2.

[0259] In an exemplary embodiment, as shown in FIG. 10, the length of the first data connection part DA along the first direction D1 is greater than the length of the second data connection part DB along the first direction D1.

[0260] In an exemplary embodiment, the display device further comprises: a circuit structure layer disposed on the substrate, the circuit structure layer comprising: a first semiconductor layer, a first conductive layer, a second conductive layer, a second semiconductor layer, a third conductive layer, a fourth conductive layer, and a fifth conductive layer, which are sequentially stacked on the substrate.

[0261] In an exemplary embodiment, the pixel driving circuit of the at least one sub-pixel comprises: at least one P-type transistor, at least one N-type transistor, and at least one capacitor, the at least one capacitor comprising: a first electrode plate and a second electrode plate. Exemplarily, the at least one P-type transistor comprises: a first transistor T1 to a seventh transistor T7, a ninth transistor T9, and a tenth transistor T10, the at least one N-type transistor comprises: an eighth transistor T8, and the at least one capacitor comprises: a first capacitor and a second capacitor.

[0262] In an exemplary embodiment, the first semiconductor layer comprises: an active pattern of the at least one P-type transistor of the pixel driving circuit of the at least one sub-pixel.

[0263] In an exemplary embodiment, the first conductive layer at least comprises: the second scan signal line Gate2, the first emission signal line EM1, and the first electrode plate of the at least one capacitor and the control electrode of the at least one P-type transistor of the pixel driving circuit of the at least one sub-pixel.

[0264] In an exemplary embodiment, the second conductive layer at least includes: a second plate of at least one capacitor and a first control electrode of at least one N-type transistor in the pixel driving circuit of the at least one sub-pixel.

[0265] In an exemplary embodiment, the second semiconductor layer at least includes: an active pattern of at least one N-type transistor in the pixel driving circuit of the at least one sub-pixel.

[0266] In an exemplary embodiment, the third conductive layer at least includes: a first initial signal line INIT1, a second reference signal line REF2, and a second control electrode of an eighth transistor in the pixel driving circuit of the at least one sub-pixel.

[0267] In an exemplary embodiment, the fourth conductive layer at least includes: a first reference signal line REF1, a first scan signal line Gate1, a third scan signal line Gate3, a fourth scan signal line Gate4, a second emission signal line EM2, a second initial signal line INIT2, and a first electrode and a second electrode of at least one transistor in the pixel driving circuit of the at least one sub-pixel.

[0268] In an exemplary embodiment, the fifth conductive layer pattern at least can include: a data signal line Data and a first power supply line VDD.

[0269] In an exemplary embodiment, FIG. 12 is a schematic diagram of the partial film layer in FIG. 10. As shown in FIG. 12, the circuit structure layer further includes: a light shielding layer on the first semiconductor layer close to the substrate side, the light shielding layer includes: a light shielding structure in the at least one sub-pixel. In FIG. 12, at least one capacitor in the last sub-pixel is not drawn for clarity.

[0270] For at least one row of sub-pixels, as shown in FIG. 12, the light shielding structure of the at least one sub-pixel and the light shielding structure of the first adjacent sub-pixel are arranged symmetrically along a straight line extending in the second direction, and the light shielding structure of the at least one sub-pixel and the light shielding structure of the second adjacent sub-pixel are at least partially the same.

[0271] As shown in FIG. 12, the light shielding structure in the at least one sub-pixel includes: a first light shielding part SL1, a second light shielding part SL2, a first light shielding connecting part SL3, a second light shielding connecting part SL4, and a third light shielding connecting part SL5, the first light shielding connecting part SL3, the first light shielding part SL1, the second light shielding connecting part SL4, the second light shielding part SL2, and the third light shielding connecting part SL5 are arranged in sequence along the second direction D2, the first light shielding part SL1 is connected with the first light shielding connecting part SL3 and the second light shielding connecting part SL4 respectively, and the second light shielding part SL2 is connected with the second light shielding connecting part SL4 and the third light shielding connecting part SL5 respectively.

[0272] As shown in FIG. 12, at least one of the first light-shielding connection portion SL3, the second light-shielding connection portion SL4, and the third light-shielding connection portion SL5 extends along the second direction D2.

[0273] As shown in FIG. 12, a length of at least one of the first light-shielding portion SL1 and the second light-shielding portion SL2 along the first direction D1 is greater than a length of at least one of the first light-shielding connection portion to the third light-shielding connection portion SL5 along the first direction D1.

[0274] In an example embodiment, as shown in FIG. 12, the second light-shielding portions in the light-shielding structures of adjacent sub-pixels in the same row are connected to each other.

[0275] In an example embodiment, as shown in FIG. 12, the pixel driving circuit of at least one sub-pixel includes a first capacitor C1 and a second capacitor C2, and the first capacitor C1 and the second capacitor C2 include first and second plates.

[0276] In an example embodiment, as shown in FIG. 12, a normal projection of the first light-shielding portion SL1 of the light-shielding structure of at least one sub-pixel on the substrate at least partially overlaps with a normal projection of at least one of the first plate C11 and the second plate C12 of the first capacitor C1 on the substrate.

[0277] In an example embodiment, as shown in FIG. 12, a normal projection of the second light-shielding portion SL2 of the light-shielding structure of at least one sub-pixel on the substrate at least partially overlaps with a normal projection of at least one of the first plate C21 and the second plate C22 of the second capacitor C2 on the substrate.

[0278] In an example embodiment, as shown in FIG. 10, the display device further includes a plurality of power supply connection lines VDL on the fourth conductive layer, and one of the plurality of power supply connection lines VDL extends along the first direction D1.

[0279] In an example embodiment, as shown in FIG. 10, at least one of the power supply connection lines VDL is electrically connected to at least one of the first power supply lines VDD.

[0280] In an example embodiment, as shown in FIG. 10, a normal projection of at least one of the power supply connection lines on the substrate is between a normal projection of at least one of the first light-emitting signal lines EM1 on the substrate and a normal projection of at least one of the second light-emitting signal lines EM2 on the substrate, and at least partially overlaps with a normal projection of the second capacitor C2 in the pixel driving circuit of at least one sub-pixel on the substrate.

[0281] In the example embodiment, the plurality of first power lines VDD and the plurality of power connection lines VDL form a mesh structure in communication with each other, which can ensure that the signals of the first power lines in the plurality of pixel driving circuits in the display substrate are consistent, and can ensure the display uniformity of the display substrate.

[0282] In the example embodiment, as shown in FIG. 10, the display device further includes a plurality of reference connection lines REFCL located in the fifth conductive layer, and one of the plurality of reference connection lines REFCL extends along the second direction D2.

[0283] In the example embodiment, as shown in FIG. 10, at least one reference connection line REFCL is electrically connected with at least one first reference signal line REF1 of the plurality of first reference signal lines REF1.

[0284] In the example embodiment, the plurality of first reference signal lines REF1 and the plurality of reference connection lines REFCL form a mesh structure in communication with each other, which can ensure that the signals of the first reference signal lines in the plurality of pixel driving circuits in the display substrate are consistent, and can ensure the display uniformity of the display substrate.

[0285] In the example embodiment, as shown in FIG. 10, at least one reference connection line is located between the first power line VDD connected by the pixel driving circuit of the at least one sub-pixel and the first power line VDD connected by the pixel driving circuit of the first adjacent sub-pixel, and the center line of the at least one reference connection line extending along the first direction D1 is collinear with the symmetry axis of the pixel driving circuit of the at least one sub-pixel and the pixel driving circuit of the first adjacent sub-pixel.

[0286] In the example embodiment, as shown in FIG. 10, at least one reference connection line is located between the data signal line Data connected by the pixel driving circuit of the at least one sub-pixel and the first power line VDD connected by the pixel driving circuit of the first adjacent sub-pixel.

[0287] In the example embodiment, the display substrate can be a Low Temperature Polycrystalline Oxide (LTPO) display substrate.

[0288] The structure of the display substrate is described below by taking an example of a preparation process of the display substrate. The "patterning process" in the present disclosure includes deposition of a film layer, coating of photoresist, mask exposure, development, etching, and stripping of photoresist. The deposition can use any one or more of sputtering, evaporation, and chemical vapor deposition, the coating can use any one or more of spraying and spin coating, and the etching can use any one or more of dry etching and wet etching. The "film" refers to a thin film of a material made on a substrate by a deposition or coating process. If the "film" does not need to be patterned during the entire manufacturing process, the "film" can also be referred to as a "layer". If the "film" needs to be patterned during the entire manufacturing process, it is referred to as a "film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern". The "A and B are disposed in the same layer" in the present disclosure means that A and B are formed at the same time by one patterning process.

[0289] FIGS. 13-29 are schematic diagrams of a preparation process of a display substrate according to an example embodiment. FIGS. 13-29 are described by taking a row of three column pixel driving circuits as an example.

[0290] The preparation process of the display substrate provided by the present disclosure can include the following steps according to FIGS. 13-29:

[0291] (1) Forming a light shielding layer pattern, in the example embodiment, forming the light shielding layer pattern includes: depositing a light shielding film on the substrate, and patterning the light shielding film by a patterning process to form the light shielding layer pattern. As shown in FIG. 13, FIG. 13 is a schematic diagram of the display substrate after the light shielding layer pattern is formed in FIG. 10.

[0292] In the example embodiment, as shown in FIG. 13, the light shielding layer pattern can include a light shielding structure of at least one sub-pixel.

[0293] In the example embodiment, for the same row of sub-pixels, the light shielding structure of the at least one sub-pixel and the light shielding structure of the first adjacent sub-pixel are disposed at least partially symmetrically with respect to a straight line extending along the second direction D2, and the light shielding structure of the at least one sub-pixel in the same row and the light shielding structure of the second adjacent sub-pixel are at least partially the same.

[0294] In an exemplary embodiment, the light shielding structure of the at least one sub-pixel comprises a first light shielding portion SL1, a second light shielding portion SL2, a first light shielding connecting portion SL3, a second light shielding connecting portion SL4, and a third light shielding connecting portion SL5. The first light shielding connecting portion SL3, the first light shielding portion SL1, the second light shielding connecting portion SL4, the second light shielding portion SL2, and the third light shielding connecting portion SL5 are arranged in sequence along the second direction D2. The first light shielding portion SL1 is connected to the first light shielding connecting portion SL3 and the second light shielding connecting portion SL4, respectively. The second light shielding portion SL2 is connected to the second light shielding connecting portion SL4 and the third light shielding connecting portion SL5, respectively.

[0295] In an exemplary embodiment, the first light shielding portion SL1 and the second light shielding portion SL2 are rectangular in shape. At least one of the first light shielding connecting portion SL3, the second light shielding connecting portion SL4, and the third light shielding connecting portion SL5 extends along the second direction D2.

[0296] In an exemplary embodiment, the second light shielding portion SL2 in the light shielding structure of the adjacent sub-pixel in the same row is connected.

[0297] In an exemplary embodiment, for the same column of sub-pixels, the first light shielding connecting portion SL3 in the light shielding structure of the at least one row of sub-pixels is connected to the third light shielding connecting portion SL5 of the light shielding structure of the previous row of sub-pixels. The third light shielding connecting portion SL5 in the light shielding structure of the at least one row of sub-pixels is connected to the first light shielding connecting portion SL3 of the light shielding structure of the next row of sub-pixels.

[0298] In an exemplary embodiment, the length of at least one of the first light shielding portion SL1 and the second light shielding portion SL2 along the first direction D1 is greater than the length of at least one of the first light shielding connecting portion SL3 to the third light shielding connecting portion SL5 along the first direction D1.

[0299] (2) Forming a first semiconductor layer pattern. In an exemplary embodiment, forming a first semiconductor layer pattern can include sequentially depositing a first insulating thin film and a first semiconductor thin film on a substrate, patterning the first semiconductor thin film by a patterning process, forming a first insulating layer covering the substrate and a first semiconductor layer pattern disposed on the first insulating layer, as shown in FIGS. 14 and 15. FIG. 14 is a schematic diagram of the first semiconductor layer pattern in FIG. 10, and FIG. 15 is a schematic diagram of FIG. 10 after forming the first semiconductor layer pattern.

[0300] In an exemplary embodiment, as shown in FIGS. 14 and 15, the first semiconductor layer pattern can at least include: the active pattern 11 of the first transistor, the active pattern 21 of the second transistor, the active pattern 31 of the third transistor, the active pattern 41 of the fourth transistor, the active pattern 51 of the fifth transistor, the active pattern 61 of the sixth transistor, the active pattern 71 of the seventh transistor, the active pattern 91 of the ninth transistor, and the active pattern 101 of the tenth transistor of at least one sub-pixel.

[0301] In an exemplary embodiment, for the same row of sub-pixels, the active pattern of the at least one transistor of the at least one sub-pixel is at least partially symmetrically arranged with respect to the active pattern of the at least one transistor of the first adjacent sub-pixel along a straight line extending in the second direction D2, and the active pattern of the at least one transistor of the at least one sub-pixel is at least partially identical to the active pattern of the at least one transistor of the second adjacent sub-pixel.

[0302] In an exemplary embodiment, the orthographic projection of the light-shielding structure of the at least one sub-pixel on the substrate at least partially overlaps the orthographic projection of the active pattern of the at least one transistor in the pixel driving circuit of the at least one sub-pixel on the substrate. Exemplarily, the orthographic projection of the second light-shielding portion of the light-shielding structure of the at least one sub-pixel on the substrate at least partially overlaps the orthographic projection of the active pattern of the third transistor in the pixel driving circuit of the at least one sub-pixel on the substrate.

[0303] In an exemplary embodiment, for the same sub-pixel, the active pattern 21 of the second transistor, the active pattern 31 of the third transistor, the active pattern 51 of the fifth transistor, the active pattern 61 of the sixth transistor, the active pattern 91 of the ninth transistor, and the active pattern 101 of the tenth transistor are a unitary structure. The active pattern 41 of the fourth transistor and the active pattern 71 of the seventh transistor are a unitary structure. The active pattern 11 of the first transistor is separately arranged.

[0304] In the exemplary embodiment, for the pixel driving circuit of at least one row of sub-pixels, the integrated structure of the active pattern 21 of the second transistor, the active pattern 31 of the third transistor, the active pattern 51 of the fifth transistor, the active pattern 61 of the sixth transistor, the active pattern 91 of the ninth transistor and the active pattern 101 of the tenth transistor is arranged along the second direction D2, and the integrated structure of the active pattern 41 of the fourth transistor and the active pattern 71 of the seventh transistor is located at the side of the integrated structure of the active pattern 21 of the second transistor, the active pattern 31 of the third transistor, the active pattern 51 of the fifth transistor, the active pattern 61 of the sixth transistor, the active pattern 91 of the ninth transistor and the active pattern 101 of the tenth transistor close to the upper row of sub-pixels. The active pattern 11 of the first transistor is located between the integrated structure of the active pattern 41 of the fourth transistor and the active pattern 71 of the seventh transistor and the integrated structure of the active pattern 21 of the second transistor, the active pattern 31 of the third transistor, the active pattern 51 of the fifth transistor, the active pattern 61 of the sixth transistor, the active pattern 91 of the ninth transistor and the active pattern 101 of the tenth transistor.

[0305] In the exemplary embodiment, in the first direction D1, the active pattern 51 of the fifth transistor and the active pattern 91 of the ninth transistor can be located at the same side of the active pattern 31 of the third transistor, the active pattern 21 of the second transistor, the active pattern 61 of the sixth transistor and the active pattern 101 of the tenth transistor can be located at the same side of the active pattern 31 of the third transistor, the active pattern 51 of the fifth transistor and the active pattern 61 of the sixth transistor can be located at different sides of the active pattern 31 of the third transistor. In the second direction D2, the active pattern 11 of the first transistor, the active pattern 21 of the second transistor, the active pattern 41 of the fourth transistor, the active pattern 51 of the fifth transistor and the active pattern 71 of the seventh transistor are located at the side of the active pattern 31 of the third transistor in the pixel driving circuit of the present sub-pixel close to the pixel driving circuit of the upper row of sub-pixels, the active pattern 61 of the sixth transistor, the active pattern 91 of the ninth transistor and the active pattern 101 of the tenth transistor can be located at the side of the pixel driving circuit of at least one row of sub-pixels close to the pixel driving circuit of the lower row of sub-pixels. At least one row of the active pattern 71 of the seventh transistor is located at the side of the active pattern 41 of the fourth transistor close to the lower row of sub-pixels.

[0306] In the exemplary embodiment, for the same sub-pixel, the active pattern 51 of the fifth transistor and the active pattern 91 of the ninth transistor are arranged along the second direction D2, and the active pattern 21 of the second transistor, the active pattern 61 of the sixth transistor and the active pattern 101 of the tenth transistor are arranged in sequence along the second direction D2.

[0307] In an exemplary embodiment, the shape of the active pattern 31 of the third transistor may be an inverted "Ω" shape.

[0308] In an exemplary embodiment, the active pattern 11 of the first transistor is in a "one" shape.

[0309] In an exemplary embodiment, the active patterns 21, 41, 51, 61, 91 and 101 of the second, fourth, fifth, sixth, ninth and tenth transistors are in an "I" shape.

[0310] In an exemplary embodiment, the active pattern 71 of the seventh transistor may be in a zigzag shape and at least partially extend along the second direction D2.

[0311] In an exemplary embodiment, the active pattern of each transistor may include a first region, a second region, and a channel region located between the first region and the second region. In an exemplary embodiment, for the pixel driving circuit of at least one sub-pixel, the first region 31-1 of the active pattern 31 of the third transistor may simultaneously serve as the second region 51-2 of the active pattern 51 of the fifth transistor and the second region 21-2 of the active pattern 91 of the ninth transistor. The second region 31-2 of the active pattern 31 of the third transistor may serve as the second region 21-2 of the active pattern of the second transistor and the first region 61-1 of the active pattern 61 of the sixth transistor. The second region 41-2 of the active pattern 41 of the fourth transistor may serve as the second region 71-2 of the active pattern 71 of the seventh transistor. The second region 61-2 of the active pattern 61 of the sixth transistor may serve as the second region 101-2 of the active pattern 101 of the tenth transistor. The first region 11-1 and the second region 11-2 of the active pattern 11 of the first transistor, the first region 41-1 of the active pattern 41 of the fourth transistor, the first region 51-1 of the active pattern 51 of the fifth transistor, the first region 71-1 of the active pattern 71 of the seventh transistor, the first region 91-1 of the active pattern 91 of the ninth transistor, and the first region of the active pattern 101 of the tenth transistor may be separately provided.

[0312] In an exemplary embodiment, the first region 101-1 of the active pattern 101 of the tenth transistor in the pixel driving circuit of at least one sub-pixel and the pixel driving circuit of the first adjacent sub-circuit may be the same region.

[0313] (3) forming a first conductive layer pattern, in an exemplary embodiment, forming the first conductive layer pattern can include: sequentially depositing a second insulating thin film and a first conductive thin film on the substrate on which the aforementioned pattern is formed, patterning the second insulating thin film and the first conductive thin film through a patterning process, forming a second insulating layer pattern and a first conductive layer pattern on the second insulating layer, as shown in FIG. 16 and FIG. 17, wherein FIG. 16 is a schematic diagram of the first conductive layer pattern in FIG. 10, and FIG. 17 is a schematic diagram of FIG. 10 after the first conductive layer pattern is formed. In an exemplary embodiment, the first conductive layer can be referred to as a first gate metal (GATE1) layer.

[0314] In an exemplary embodiment, as shown in FIG. 16 and FIG. 17, the first conductive layer pattern can include: a second scan signal line Gate2, a first emission signal line EM1, and a first plate C11 of a first capacitor of a pixel driving circuit of at least one sub-pixel, a second plate C21 of a second capacitor, a control electrode 11 of a first transistor, a control electrode 22 of a second transistor, a control electrode 32 of a third transistor, a control electrode 42 of a fourth transistor, a control electrode 52 of a fifth transistor, a control electrode 62 of a sixth transistor, a control electrode 72 of a seventh transistor, a control electrode 92 of a ninth transistor, and a control electrode 102 of a tenth transistor.

[0315] In the exemplary embodiment, for the same row of sub-pixels, the first plate C11 of the first capacitor, the second plate C21 of the second capacitor, the control electrode 11 of the first transistor, the control electrode 22 of the second transistor, the control electrode 32 of the third transistor, the control electrode 42 of the fourth transistor, the control electrode 52 of the fifth transistor, the control electrode 62 of the sixth transistor, the control electrode 72 of the seventh transistor, the control electrode 92 of the ninth transistor, and the control electrode 102 of the tenth transistor in the pixel driving circuit of the at least one sub-pixel are arranged at least partially symmetrically with respect to a straight line extending along the second direction D2 from the first plate C11 of the first capacitor, the second plate C21 of the second capacitor, the control electrode 11 of the first transistor, the control electrode 22 of the second transistor, the control electrode 32 of the third transistor, the control electrode 42 of the fourth transistor, the control electrode 52 of the fifth transistor, the control electrode 62 of the sixth transistor, the control electrode 72 of the seventh transistor, the control electrode 92 of the ninth transistor, and the control electrode 102 of the tenth transistor in the pixel driving circuit of the first adjacent sub-pixel, and the structure of the first plate C11 of the first capacitor, the second plate C21 of the second capacitor, the control electrode 11 of the first transistor, the control electrode 22 of the second transistor, the control electrode 32 of the third transistor, the control electrode 42 of the fourth transistor, the control electrode 52 of the fifth transistor, the control electrode 62 of the sixth transistor, the control electrode 72 of the seventh transistor, the control electrode 92 of the ninth transistor, and the control electrode 102 of the tenth transistor in the pixel driving circuit of the first adjacent sub-pixel is at least partially the same.

[0316] In the exemplary embodiment, the second scan signal line Gate2 connected by the pixel driving circuit of the at least one row of sub-pixels includes two.

[0317] For the at least one row of sub-pixels, the first second scan signal line Gate2, the first emission signal line EM1, and the second second scan signal line Gate2 connected by the pixel driving circuit are arranged in sequence along the second direction D2, and the first second scan signal line Gate2 is located on the side of the first emission signal line EM1 close to the previous row of sub-pixels, and the second second scan signal line Gate2 is located on the side of the first emission signal line EM1 close to the next row of sub-pixels.

[0318] In an example embodiment, the first second scan signal line Gate2 can have a shape of a line with a main body extending along the first direction D1. The region where the first second scan signal line Gate2 connected to the pixel driving circuit of at least one row of sub-pixels overlaps with the active pattern of the first transistor can be the control electrode 12 of the first transistor.

[0319] In an example embodiment, the second second scan signal line Gate2 can have a shape of a line with a main body extending along the first direction D1. The region where the second second scan signal line Gate2 connected to the pixel driving circuit of at least one row of sub-pixels overlaps with the active pattern of the ninth transistor can be the control electrode 92 of the ninth transistor, and the region where the second second scan signal line Gate2 connected to the pixel driving circuit of at least one row of sub-pixels overlaps with the active pattern of the tenth transistor can be the control electrode 102 of the tenth transistor.

[0320] In an example embodiment, the first emission signal line EM1 can have a shape of a line with a main body extending along the first direction D1. The region where the first emission signal line EM1 connected to the pixel driving circuit of at least one row of sub-pixels overlaps with the active pattern of the second transistor can be the control electrode 22 of the second transistor, and the region where the first emission signal line EM1 connected to the pixel driving circuit of at least one row of sub-pixels overlaps with the active pattern of the fifth transistor can be the control electrode 52 of the fifth transistor.

[0321] In an example embodiment, for at least one sub-pixel, the first plate C11 of the first capacitor in the pixel driving circuit is located between the first second scan signal line Gate2 and the first emission signal line EM1 connected to the pixel driving circuit. The shape of the first plate C11 of the first capacitor can be a rectangular shape, the corner of the rectangular shape can be provided with a chamfer, and the orthographic projection of the first plate C11 of the first capacitor on the base at least partially overlaps with the orthographic projection of the first light shielding portion of the light shielding structure on the base. Illustratively, the orthographic projection of the first plate C11 of the first capacitor on the base is located within the range of the orthographic projection of the first light shielding portion of the light shielding structure on the base.

[0322] In an example embodiment, for at least one sub-pixel, the first plate C21 of the second capacitor in the pixel driving circuit is located between the second second scan signal line Gate2 and the first emission signal line EM1 connected to the pixel driving circuit. The shape of the first plate C21 of the second capacitor can be a rectangular shape, the corner of the rectangular shape can be provided with a chamfer, and the orthographic projection of the first plate C21 of the second capacitor on the base at least partially overlaps with the orthographic projection of the second light shielding portion of the light shielding structure on the base. Illustratively, the orthographic projection of the first plate C21 of the second capacitor on the base is located within the range of the orthographic projection of the second light shielding portion of the light shielding structure on the base.

[0323] In an example embodiment, in the at least one sub-pixel, the first plate C21 of the second capacitor of the pixel driving circuit can serve as the control electrode 32 of the third transistor.

[0324] In an example embodiment, in the at least one sub-pixel, the control electrode 42 of the fourth transistor is separately provided and shaped as a horizontally flipped "7".

[0325] In an example embodiment, in the at least one sub-pixel, the control electrode 62 of the sixth transistor is separately provided. The control electrode 62 of the sixth transistor is in a strip shape and extends along the first direction D1.

[0326] In an example embodiment, the control electrode of the sixth transistor of the pixel driving circuit of the at least one sub-pixel and the pixel driving circuit of the first adjacent sub-pixel is the same electrode.

[0327] In an example embodiment, in the at least one sub-pixel, the control electrode 72 of the seventh transistor is separately provided. The control electrode 72 of the seventh transistor is in a strip shape and extends along the first direction D1.

[0328] In an example embodiment, the control electrode of the seventh transistor of the pixel driving circuit of the at least one sub-pixel and the pixel driving circuit of the first adjacent sub-pixel is the same electrode.

[0329] In an example embodiment, the second scan signal line Gate2 and the first light-emitting signal line EM1 can be designed with equal width or can be designed with non-equal width, can be a straight line or can be a broken line, which not only facilitates the layout of the pixel structure, but also reduces the parasitic capacitance between the signal lines, which is not limited in the present disclosure.

[0330] In an example embodiment, after forming the first conductive layer pattern, the first conductive layer can be used as a shield to conduct the first semiconductor layer. The first semiconductor layer in the area shielded by the first conductive layer forms the channel region of the first to seventh transistors and the ninth transistor. The first semiconductor layer in the area not shielded by the first conductive layer is conductive, i.e., the first and second regions of at least one of the first to seventh transistors, the ninth transistor and the tenth transistor are conductive. After the conductive, the first region of the active pattern of the third transistor (also the second region of the active pattern of the fifth transistor and the second region of the ninth transistor) is multiplexed as the first electrode 33 of the third transistor (also the second electrode 54 of the fifth transistor and the second electrode 94 of the ninth transistor), and the second region of the active pattern of the third transistor (also the second region of the active pattern of the second transistor and the first region of the active pattern of the sixth transistor) is multiplexed as the second electrode 34 of the third transistor (also the second electrode 24 of the second transistor and the first electrode 63 of the sixth transistor).

[0331] In the example embodiment, the control electrode of the first transistor is disposed across the active pattern of the first transistor, the control electrode of the second transistor is disposed across the active pattern of the second transistor, the control electrode of the third transistor is disposed across the active pattern of the third transistor, the control electrode of the fourth transistor is disposed across the active pattern of the fourth transistor, the control electrode of the fifth transistor is disposed across the active pattern of the fifth transistor, the control electrode of the sixth transistor is disposed across the active pattern of the sixth transistor, the control electrode of the seventh transistor is disposed across the active pattern of the seventh transistor, the control electrode of the ninth transistor is disposed across the active pattern of the ninth transistor, and the control electrode of the tenth transistor is disposed across the active pattern of the tenth transistor, that is, the extension direction of the control electrode of at least one transistor is perpendicular to the extension direction of the active pattern.

[0332] (4) Forming a second conductive layer pattern. In the example embodiment, forming the second conductive layer pattern can include: sequentially depositing a third insulating thin film and a second conductive thin film on the substrate on which the aforementioned patterns are formed, and patterning the third insulating thin film and the second conductive thin film by a patterning process to form a third insulating layer pattern and a second conductive layer pattern on the third insulating layer, as shown in FIG. 18 and FIG. 19. FIG. 18 is a schematic diagram of the second conductive layer pattern in FIG. 10, and FIG. 19 is a schematic diagram of FIG. 10 after the second conductive layer pattern is formed. In the example embodiment, the second conductive layer can be referred to as a second gate metal (GATE2) layer.

[0333] In the example embodiment, as shown in FIG. 18 and FIG. 19, the second conductive layer pattern can include the second plate C12 of the first capacitor, the second plate C22 of the second capacitor, and the first control electrode 82A of the eighth transistor in the pixel driving circuit of at least one sub-pixel.

[0334] In the example embodiment, for the same row of sub-pixels, the second plate C12 of the first capacitor, the second plate C22 of the second capacitor, and the first control electrode 82A of the eighth transistor in the pixel driving circuit of at least one sub-pixel are at least partially symmetrically disposed with respect to a straight line extending in the second direction D2 with the second plate C12 of the first capacitor, the second plate C22 of the second capacitor, and the first control electrode 82A of the eighth transistor in the pixel driving circuit of the first adjacent sub-pixel. The structure of the second plate C12 of the first capacitor, the second plate C22 of the second capacitor, and the first control electrode 82A of the eighth transistor in the pixel driving circuit of at least one sub-pixel is at least partially the same as the structure of the second plate C12 of the first capacitor, the second plate C22 of the second capacitor, and the first control electrode 82A of the eighth transistor in the pixel driving circuit of the second adjacent sub-pixel.

[0335] In an example embodiment, the main body profile of the second plate C12 of the first capacitor can be rectangular, and the corners of the rectangular shape can be chamfered. The second plate C12 of the first capacitor is arranged on the substrate such that the orthographic projection of the second plate C12 of the first capacitor on the substrate at least partially overlaps the orthographic projection of the first plate of the first capacitor on the substrate. The second plate C12 of the first capacitor is provided with a first opening H1, which can be rectangular in shape and can be located in the middle of the second plate C12 of the first capacitor, so that the second plate C12 of the first capacitor forms a ring structure. The first opening H1 exposes the third insulating layer covering the first plate of the first capacitor, and the orthographic projection of the first plate of the first capacitor on the substrate covers the orthographic projection of the first opening H1 on the substrate. In an example embodiment, the first opening H1 exposes the first plate of the first capacitor, so that the second electrode of the first transistor (also the first electrode of the second transistor and the first electrode of the eighth transistor) formed subsequently is connected to the first plate of the first capacitor.

[0336] In an example embodiment, the second plate C22 of the second capacitor includes a capacitor body part C22A and a capacitor connecting part C22B. The capacitor body part C22A and the capacitor connecting part C22B are arranged along the first direction D1 and are connected to each other.

[0337] In an example embodiment, the main body profile of the capacitor body part C22A of the second plate C22 of the second capacitor can be rectangular, and the corners of the rectangular shape can be chamfered. The capacitor body part C22A of the second plate C22 of the second capacitor is arranged on the substrate such that the orthographic projection of the capacitor body part C22A of the second plate C22 of the second capacitor on the substrate at least partially overlaps the orthographic projection of the first plate of the second capacitor on the substrate. The capacitor body part C22A of the second plate C22 of the second capacitor is provided with a second opening H2, which can be rectangular in shape and can be located in the middle of the second plate C22 of the second capacitor, so that the second plate C22 of the second capacitor forms a ring structure. The second opening H2 exposes the third insulating layer covering the first plate of the second capacitor, and the orthographic projection of the first plate of the second capacitor on the substrate contains the orthographic projection of the second opening H2 on the substrate. In an example embodiment, the second opening H2 exposes the first plate of the second capacitor, so that the second electrode of the second transistor formed subsequently is connected to the first plate of the second capacitor (also the control electrode of the third transistor).

[0338] In an example embodiment, the second plates C22 of the second capacitors of the pixel driving circuits of adjacent sub-pixels in the same row are electrically connected.

[0339] In an example embodiment, the capacitor body portion of the second plate of the second capacitor in the pixel driving circuit of the at least one sub-pixel is connected to the capacitor body portion of the second plate of the second capacitor in the pixel driving circuit of the first adjacent sub-pixel, and the capacitor connection portion of the second plate of the second capacitor in the pixel driving circuit of the at least one sub-pixel is connected to the capacitor connection portion of the second plate of the second capacitor in the pixel driving circuit of the second adjacent sub-pixel.

[0340] In an example embodiment, the first control electrode 82A of the eighth transistor is separately provided. The first control electrode 82A of the eighth transistor is located between the second plate of the first capacitor and the second plate of the second capacitor. The shape of the first control electrode 82A of the eighth transistor is strip-shaped and extends along the first direction D1.

[0341] In an example embodiment, for the at least one sub-pixel, the orthogonal projection of the first control electrode 82A of the eighth transistor on the substrate at least partially overlaps the orthogonal projection of the second light-shielding connection portion in the light-shielding structure on the substrate.

[0342] (5) Forming a second semiconductor layer pattern. In an example embodiment, forming the second semiconductor layer pattern can include: on the substrate on which the aforementioned pattern is formed, including: sequentially depositing a fourth insulating thin film and a second semiconductor thin film on the substrate, patterning the fourth insulating thin film and the second semiconductor thin film by a patterning process, forming a fourth insulating layer pattern and a second semiconductor layer pattern on the third insulating layer, as shown in FIGS. 20 and 21, FIG. 20 is a schematic diagram of the second semiconductor layer pattern in FIG. 10, and FIG. 21 is a schematic diagram of FIG. 10 after forming the second semiconductor layer pattern.

[0343] In an example embodiment, as shown in FIGS. 20 and 21, the second semiconductor layer pattern can include: the active pattern 81 of the eighth transistor of the pixel driving circuit of the at least one sub-pixel.

[0344] In an example embodiment, for the same row of sub-pixels, the active pattern of the eighth transistor of the pixel driving circuit of the at least one sub-pixel and the active pattern of the eighth transistor of the pixel driving circuit of the first adjacent sub-pixel are at least partially symmetrically arranged relative to a straight line extending along the second direction. The structure of the active pattern of the eighth transistor of the pixel driving circuit of the at least one sub-pixel and the active pattern of the eighth transistor of the pixel driving circuit of the second adjacent sub-pixel is at least partially the same.

[0345] In an example embodiment, as shown in FIGS. 20 and 21, the shape of the active pattern 81 of the eighth transistor is in the shape of an “I” letter.

[0346] In an example embodiment, the active pattern of each transistor can include a first region, a second region, and a channel region between the first region and the second region. In an example embodiment, for the pixel driving circuit of at least one sub-pixel, the first region 81-1 and the second region 81-2 of the active pattern 81 of the eighth transistor are separately provided.

[0347] In an example embodiment, the active pattern 81 of the eighth transistor extends over the first control electrode of the eighth transistor.

[0348] (6) Forming a third conductive layer pattern, in an example embodiment, forming the second semiconductor layer pattern can include: on the substrate on which the aforementioned patterns are formed, sequentially depositing a fifth insulating thin film and a third conductive thin film, patterning the fifth insulating thin film and the third conductive thin film through a patterning process, forming a fifth insulating layer pattern and a third conductive layer pattern on the fifth insulating layer, as shown in FIG. 22 and FIG. 23, FIG. 22 is a schematic diagram of the third conductive layer pattern in FIG. 10, and FIG. 23 is a schematic diagram after forming the third conductive layer pattern in FIG. 10. In an example embodiment, the third conductive layer can be referred to as a third gate metal (GATE3) layer.

[0349] In an example embodiment, as shown in FIG. 22 and FIG. 23, the third conductive layer pattern can include: a first initial signal line INIT1, a second reference signal line REF2, and a second control electrode 82B of the eighth transistor in the pixel driving circuit of at least one sub-pixel.

[0350] In an example embodiment, for the same row of sub-pixels, the second control electrode of the eighth transistor of the pixel driving circuit of at least one sub-pixel and the second control electrode of the eighth transistor of the pixel driving circuit of the first adjacent sub-pixel are at least partially symmetrically arranged with respect to a straight line extending in the second direction. The structure of the second control electrode of the eighth transistor of the pixel driving circuit of at least one sub-pixel and the second control electrode of the eighth transistor of the pixel driving circuit of the second adjacent sub-pixel is at least partially the same.

[0351] In an example embodiment, the shape of the first initial signal line INIT1 can be a linear shape with a main body portion extending along the first direction D1. The orthographic projection of the first initial signal line INIT1 on the substrate is located on the side away from the orthographic projection of the first light-emitting signal line on the substrate of the orthographic projection of the main body portion of the first second scan signal line on the substrate.

[0352] In an example embodiment, the shape of the second reference signal line REF2 can be a linear shape with a main body portion extending along the first direction D1. The orthographic projection of the second reference signal line REF2 on the substrate is located on the side away from the orthographic projection of the first light-emitting signal line on the substrate of the orthographic projection of the main body portion of the second second scan signal line on the substrate.

[0353] In the example embodiment, the second control electrode 82B of the eighth transistor is separately provided. The second control electrode 82B of the eighth transistor is in a strip shape and extends along the first direction D1.

[0354] In the example embodiment, the second control electrode 82B of the eighth transistor is separately provided. The second control electrode 82B of the eighth transistor is in a strip shape and extends along the first direction D1.

[0355] In the example embodiment, the first initial signal line and the second reference signal line can be designed in equal width or in non-equal width, and can be a straight line or a broken line. This not only facilitates the layout of the pixel structure, but also reduces the parasitic capacitance between the signal lines, which is not limited in the present disclosure.

[0356] (7) Forming a sixth insulating layer pattern, comprising: depositing a sixth insulating thin film on the substrate on which the aforementioned pattern is formed, and patterning the sixth insulating thin film by a patterning process to form a sixth insulating layer pattern covering the aforementioned pattern, the sixth insulating layer being provided with a plurality of via hole patterns, as shown in FIG. 24, which is a schematic diagram after the sixth insulating layer pattern is formed in FIG. 10.

[0357] In the example embodiment, as shown in FIG. 24, the plurality of via holes of the sixth insulating layer pattern at least include a first via hole V1 to a twenty-third via hole V23 of the pixel driving circuit of at least one sub-pixel.

[0358] In the example embodiment, for at least one row of sub-pixels, the tenth via hole V10 of the pixel driving circuit of at least one sub-pixel and the tenth via hole V10 of the pixel driving circuit of the first adjacent sub-pixel are the same via hole.

[0359] In the example embodiment, for at least one row of sub-pixels, the thirteenth via hole V13 of the pixel driving circuit of at least one sub-pixel and the thirteenth via hole V13 of the pixel driving circuit of the first adjacent sub-pixel are the same via hole.

[0360] In the example embodiment, the first via hole V1 is located within the range of the first region of the active pattern of the first transistor on the substrate, the fifth insulating layer, the fourth insulating layer, the third insulating layer and the second insulating layer in the first via hole V1 are etched away, exposing the surface of the first region of the active layer of the first transistor, and the first via hole V1 is configured to connect the first region of the active layer of the first transistor and the first electrode of the first transistor formed subsequently through the via hole.

[0361] In an example embodiment, the second via V2 is configured such that the second electrode of the first transistor (also the first electrode of the second transistor and the first electrode of the eighth transistor) is connected to the second region of the active pattern of the first transistor through the via.

[0362] In an example embodiment, the third via V3 is configured such that the second electrode of the first transistor (also the first electrode of the second transistor and the first electrode of the eighth transistor) is connected to the first region of the active pattern of the second transistor through the via.

[0363] In an example embodiment, the fourth via V4 is configured such that the first electrode of the fourth transistor is connected to the first region of the active pattern of the fourth transistor through the via.

[0364] In an example embodiment, the fifth via V5 is configured such that the second electrode of the fourth transistor (also the second electrode of the seventh transistor) is connected to the second region of the active pattern of the fourth transistor (also the second region of the active pattern of the seventh transistor) through the via.

[0365] In the example embodiment, the sixth via V6 is configured such that the first electrode of the fifth transistor formed subsequently is connected to the first region of the active pattern of the fifth transistor through the via.

[0366] In the example embodiment, the seventh via V7 is configured such that the second electrode of the sixth transistor formed subsequently is connected to the second region of the active pattern of the sixth transistor (also the second region of the active pattern of the tenth transistor) through the via.

[0367] In the example embodiment, the eighth via V8 is configured such that the first electrode of the seventh transistor formed subsequently is connected to the first region of the active pattern of the seventh transistor through the via.

[0368] In the example embodiment, the ninth via V9 is configured such that the first electrode of the ninth transistor formed subsequently is connected to the first region of the active pattern of the ninth transistor through the via.

[0369] In the example embodiment, the tenth via V10 is configured such that the first electrode of the tenth transistor formed subsequently is connected to the first region of the active pattern of the tenth transistor through the via.

[0370] In the example embodiment, the normal projection of the eleventh via V11 on the substrate is located within the range of the normal projection of the control electrode of the fourth transistor on the substrate, the fifth insulating layer, the fourth insulating layer and the third insulating layer within the eleventh via V11 are etched away, exposing the surface of the control electrode of the fourth transistor, and the eleventh via V11 is configured to enable the first scan signal line formed subsequently to be connected to the control electrode of the fourth transistor through the via.

[0371] In the example embodiment, the normal projection of the twelfth via V12 on the substrate is located within the range of the normal projection of the control electrode of the sixth transistor on the substrate, the fifth insulating layer, the fourth insulating layer and the third insulating layer within the twelfth via V12 are etched away, exposing the surface of the control electrode of the sixth transistor, and the twelfth via V12 is configured to enable the second light-emitting signal line formed subsequently to be connected to the control electrode of the sixth transistor through the via.

[0372] In the example embodiment, the normal projection of the thirteenth via V13 on the substrate is located within the range of the normal projection of the control electrode of the seventh transistor on the substrate, the fifth insulating layer, the fourth insulating layer and the third insulating layer within the thirteenth via V13 are etched away, exposing the surface of the control electrode of the seventh transistor, and the thirteenth via V13 is configured to enable the third scan signal line formed subsequently to be connected to the control electrode of the seventh transistor through the via.

[0373] In the example embodiment, the normal projection of the fourteenth via V14 on the substrate is located within the range of the normal projection of the first plate of the first capacitor on the substrate, the fifth insulating layer, the fourth insulating layer and the third insulating layer within the fourteenth via V14 are etched away, exposing the surface of the first plate of the first capacitor, and the fourteenth via V14 is configured to enable the second electrode of the first transistor (also the first electrode of the second transistor and the first electrode of the eighth transistor) formed subsequently to be connected to the first plate of the first capacitor through the via.

[0374] In the example embodiment, the normal projection of the fifteenth via V15 on the substrate is located within the range of the normal projection of the first plate of the second capacitor (also the control electrode of the third transistor) on the substrate, the fifth insulating layer, the fourth insulating layer and the third insulating layer within the fifteenth via V15 are etched away, exposing the surface of the first plate of the second capacitor (also the control electrode of the third transistor), and the fifteenth via V15 is configured to enable the second electrode of the eighth transistor formed subsequently to be connected to the first plate of the second capacitor (also the control electrode of the third transistor) through the via.

[0375] In an exemplary embodiment, the first via V1 is configured to expose a surface of the first control electrode of the first transistor, and the second via V2 is configured to expose a surface of the first control electrode of the second transistor.

[0376] In an exemplary embodiment, the seventh via V7 is configured to expose a surface of the first control electrode of the third transistor, and the eighth via V8 is configured to expose a surface of the first control electrode of the fourth transistor.

[0377] In an exemplary embodiment, the ninth via V9 is configured to expose a surface of the first control electrode of the fifth transistor, and the tenth via V10 is configured to expose a surface of the first control electrode of the sixth transistor.

[0378] In an exemplary embodiment, the eleventh via V11 is configured to expose a surface of the first control electrode of the seventh transistor, and the twelfth via V12 is configured to expose a surface of the first control electrode of the eighth transistor.

[0379] In an exemplary embodiment, the thirteenth via V13 is configured to expose a surface of the first control electrode of the ninth transistor, and the fourteenth via V14 is configured to expose a surface of the first control electrode of the tenth transistor.

[0380] In an exemplary embodiment, the fifteenth via V15 is configured to expose a surface of the first control electrode of the eleventh transistor, and the sixteenth via V16 is configured to expose a surface of the first control electrode of the twelfth transistor.

[0381] In an exemplary embodiment, a normal projection of the twenty-second via V22 on the substrate is within a range of a normal projection of the first initial signal line on the substrate, the twenty-second via V22 exposes a surface of the first initial signal line, and the twenty-second via V22 is configured to connect the first electrode of the first transistor formed later with the first initial signal line through the via.

[0382] In an exemplary embodiment, a normal projection of the twenty-third via V23 on the substrate is within a range of a normal projection of the second reference signal line on the substrate, the twenty-third via V23 exposes a surface of the second reference signal line, and the twenty-third via V23 is configured to connect the first electrode of the ninth transistor formed later with the second reference signal line through the via.

[0383] (8) Forming a fourth conductive layer pattern. In an exemplary embodiment, forming the fourth conductive layer pattern can include: depositing a fourth conductive thin film on the substrate on which the aforementioned patterns are formed, and patterning the fourth conductive thin film through a patterning process, thereby forming the fourth conductive layer pattern, as shown in FIGS. 25 and 26, FIG. 25 is a schematic diagram of the fourth conductive layer pattern in FIG. 10, and FIG. 26 is a schematic diagram of FIG. 10 after the fourth conductive layer pattern is formed.

[0384] In an exemplary embodiment, as shown in FIGS. 25 and 26, the fourth conductive layer pattern can include: a first reference signal line REF1, a first scan signal line Gate1, a third scan signal line Gate3, a fourth scan signal line Gate4, a second emission signal line EM2, a second initial signal line INIT2, a power connection line VDL located at the first electrode 13 and the second electrode 14 of the first transistor, the first electrode 23 of the second transistor, the first electrode 43 and the second electrode 44 of the fourth transistor, the first electrode 53 of the fifth transistor, the second electrode 64 of the sixth transistor, the first electrode 73 and the second electrode 74 of the seventh transistor, the first electrode 83 and the second electrode 84 of the eighth transistor, the first electrode 93 of the ninth transistor, and the first electrode 103 and the second electrode 104 of the tenth transistor of the pixel driving circuit of at least one sub-pixel.

[0385] In the exemplary embodiment, for the same row of sub-pixels, the first electrode 13 and the second electrode 14 of the first transistor, the first electrode 23 of the second transistor, the first electrode 43 and the second electrode 44 of the fourth transistor, the first electrode 53 of the fifth transistor, the second electrode 64 of the sixth transistor, the first electrode 73 and the second electrode 74 of the seventh transistor, the first electrode 83 and the second electrode 84 of the eighth transistor, the first electrode 93 of the ninth transistor, and the first electrode 103 and the second electrode 104 of the tenth transistor in the pixel driving circuit of at least one sub-pixel are arranged at least partially symmetrically with respect to a straight line extending along the second direction D2, the structure of the first electrode 13 and the second electrode 14 of the first transistor, the first electrode 23 of the second transistor, the first electrode 43 and the second electrode 44 of the fourth transistor, the first electrode 53 of the fifth transistor, the second electrode 64 of the sixth transistor, the first electrode 73 and the second electrode 74 of the seventh transistor, the first electrode 83 and the second electrode 84 of the eighth transistor, the first electrode 93 of the ninth transistor, and the first electrode 103 and the second electrode 104 of the tenth transistor of at least one sub-pixel is at least partially the same as the first electrode 13 and the second electrode 14 of the first transistor, the first electrode 23 of the second transistor, the first electrode 43 and the second electrode 44 of the fourth transistor, the first electrode 53 of the fifth transistor, the second electrode 64 of the sixth transistor, the first electrode 73 and the second electrode 74 of the seventh transistor, the first electrode 83 and the second electrode 84 of the eighth transistor, the first electrode 93 of the ninth transistor, and the first electrode 103 and the second electrode 104 of the tenth transistor of the first adjacent sub-pixel, and the first electrode 13 and the second electrode 14 of the first transistor, the first electrode 23 of the second transistor, the first electrode 43 and the second electrode 44 of the fourth transistor, the first electrode 53 of the fifth transistor, the second electrode 64 of the sixth transistor, the first electrode 73 and the second electrode 74 of the seventh transistor, the first electrode 83 and the second electrode 84 of the eighth transistor, the first electrode 93 of the ninth transistor, and the first electrode 103 and the second electrode 104 of the tenth transistor of the second adjacent sub-pixel.

[0386] In the exemplary embodiment, the shape of the first reference signal line REF1 can be a linear shape with a main body portion extending along the first direction D1. The orthographic projection of the first reference signal line REF1 on the substrate is located on the side of the orthographic projection of the third scan signal line Gate3 on the substrate away from the orthographic projection of the first scan signal line Gate1 on the substrate. The region where the first reference signal line REF1 overlaps with the first region of the active pattern of the seventh transistor can serve as the first electrode 73 of the seventh transistor. The first electrode 73 of the seventh transistor is connected with the first region of the active pattern of the seventh transistor through the eighth via hole.

[0387] In an exemplary embodiment, the third scan signal line Gate3 can have a shape of a line with a main body extending along the first direction D1. The orthogonal projection of the third scan signal line Gate3 on the base is located between the orthogonal projection of the first reference signal line REF1 on the base and the orthogonal projection of the first scan signal line Gate1 on the base. The third scan signal line Gate3 is connected to the control electrode of the seventh transistor through the thirteenth via.

[0388] In an exemplary embodiment, the first scan signal line Gate1 can have a shape of a line with a main body extending along the first direction D1. The orthogonal projection of the first scan signal line Gate1 on the base is located between the orthogonal projection of the third scan signal line Gate3 on the base and the orthogonal projection of the first initial signal line INIT1 on the base. The first scan signal line Gate1 is connected to the control electrode of the fourth transistor through the eleventh via.

[0389] In an exemplary embodiment, the fourth scan signal line Gate4 can have a shape of a line with a main body extending along the first direction D1. The orthogonal projection of the fourth scan signal line Gate4 on the base is located between the orthogonal projection of the first initial signal line on the base and the orthogonal projection of the first emission signal line on the base. The fourth scan signal line Gate4 is connected to the first control electrode of the eighth transistor through the sixteenth via and to the second control electrode of the eighth transistor through the twenty-first via.

[0390] In an exemplary embodiment, the power supply connection line VDL can have a shape of a line with a main body extending along the first direction D1. The orthogonal projection of the power supply connection line VDL on the base is located between the orthogonal projection of the first emission signal line on the base and the orthogonal projection of the second emission signal line on the base, and at least partially overlaps the orthogonal projection of the second capacitor in the pixel driving circuit of at least one sub-pixel on the base. The power supply connection line VDL is connected to the second plate of the second capacitor through the eighteenth via.

[0391] In an exemplary embodiment, the second emission signal line EM2 can have a shape of a line with a main body extending along the first direction D1. The orthogonal projection of the second emission signal line EM2 on the base is located between the orthogonal projection of the power supply connection line VDL on the base and the orthogonal projection of the second scan signal line on the base. The second emission signal line EM2 is connected to the control electrode of the sixth transistor through the twelfth via.

[0392] In an exemplary embodiment, the shape of the second initial signal line INIT2 can be a linear shape with a main body portion extending along the first direction D1. The orthographic projection of the second initial signal line INIT2 on the substrate at least partially overlaps the orthographic projection of the second second scan signal line on the substrate, and is located between the orthographic projection of the second emission signal line EM2 on the substrate and the orthographic projection of the second reference signal line on the substrate. The region where the second initial signal line INIT2 overlaps the first region of the active pattern of the tenth transistor can serve as the first electrode 103 of the tenth transistor. The first electrode 103 of the tenth transistor is connected to the first region of the active pattern of the tenth transistor through the tenth via hole.

[0393] In an exemplary embodiment, the first reference signal line REF1, the first scan signal line Gate1, the third scan signal line Gate3, the fourth scan signal line Gate4, the second emission signal line EM2, the second initial signal line INIT2, and the power connection line VDL can be designed with equal widths, or can be designed with non-equal widths, and can be straight lines or broken lines. This not only facilitates the layout of the pixel structure, but also reduces the parasitic capacitance between the signal lines, which is not limited in the present disclosure.

[0394] In an exemplary embodiment, the first electrode 13 of the first transistor of the pixel driving circuit of at least one sub-pixel is the same electrode as the first electrode 13 of the first transistor of the pixel driving circuit of the first adjacent sub-pixel.

[0395] In an exemplary embodiment, the first electrode 103 of the tenth transistor of the pixel driving circuit of at least one sub-pixel is the same electrode as the first electrode 103 of the tenth transistor of the pixel driving circuit of the first adjacent sub-pixel.

[0396] In an exemplary embodiment, the first electrode 13 of the first transistor is separately provided and has a shape of a strip extending at least partially along the first direction D1. The first electrode 13 of the first transistor is connected to the first region of the active layer of the first transistor through the first via hole, and is electrically connected to the first initial signal line through the twenty-second via hole.

[0397] In an exemplary embodiment, the second electrode 14 of the first transistor, the first electrode 23 of the second transistor, and the first electrode 83 of the eighth transistor are an integral structure and have a shape of a strip extending at least partially along the second direction D2. The second electrode 14 of the first transistor (also the first electrode 23 of the second transistor and the first electrode 83 of the eighth transistor) is connected to the second region of the active pattern of the first transistor through the second via hole, to the first region of the active pattern of the second transistor through the third via hole, to the first plate of the first capacitor through the fourteenth via hole, and to the second region of the active pattern of the eighth transistor through the nineteenth via hole.

[0398] In the exemplary embodiment, the first electrode 43 of the fourth transistor is provided separately and has a shape of a strip extending in the first direction D1. The first electrode 43 of the fourth transistor is connected to the first region of the active layer of the fourth transistor through the fourth via.

[0399] In the exemplary embodiment, the second electrode 44 of the fourth transistor and the second electrode 74 of the seventh transistor are in an integral structure and have a shape of a strip extending in the first direction D1. The second electrode 44 of the fourth transistor (also the second electrode 74 of the seventh transistor) is connected to the second region of the active pattern of the fourth transistor (also the second region of the active pattern of the seventh transistor) through the fifth via and to the second plate of the first capacitor through the seventeenth via.

[0400] In the exemplary embodiment, the first electrode 53 of the fifth transistor is provided separately and has a shape of a strip extending at least partially in the first direction D1. The first electrode 53 of the fifth transistor is connected to the first region of the active layer of the fifth transistor through the sixth via and to the second plate of the capacitor through the eleventh via.

[0401] In the exemplary embodiment, the second electrode 64 of the sixth transistor (also the second electrode 104 of the tenth transistor) has a shape of a line extending in the second direction D2. The second electrode 64 of the sixth transistor (also the second electrode 104 of the tenth transistor) is connected to the second region of the active pattern of the sixth transistor (also the second region of the active pattern of the tenth transistor) through the seventh via.

[0402] In the exemplary embodiment, the second electrode 84 of the eighth transistor is provided separately and has a shape of a strip extending at least partially in the second direction D2. The second electrode 84 of the eighth transistor is connected to the first plate of the second capacitor (also the control electrode of the third transistor) through the fifteenth via and to the second region of the active pattern of the eighth transistor through the twentieth via.

[0403] In the exemplary embodiment, the first electrode 93 of the ninth transistor is provided separately and has a shape of a strip extending at least partially in the first direction D1. The first electrode 93 of the ninth transistor is connected to the first region of the active pattern of the ninth transistor through the ninth via and to the second reference signal line through the twenty-third via.

[0404] (9) forming a first planar layer pattern. In an exemplary embodiment, forming the first planar layer pattern can include: on the substrate on which the aforementioned pattern is formed, depositing a seventh insulating thin film, patterning the seventh insulating thin film by a patterning process to form a seventh insulating layer, coating a first planar thin film on the seventh insulating layer, patterning the first planar thin film by a patterning process to form a first planar layer pattern covering the aforementioned pattern, the first planar layer being provided with a plurality of via hole patterns, as shown in FIG. 27, which is a schematic view after the first planar layer pattern is formed in FIG. 10.

[0405] In an exemplary embodiment, as shown in FIG. 27, the plurality of via hole patterns on the first planar layer pattern include: a twenty-fourth via hole V24 to a twenty-eighth via hole V28.

[0406] In an exemplary embodiment, a normal projection of the twenty-fourth via hole V24 on the substrate is located within a range of a normal projection of the first electrode of the fourth transistor on the substrate, the seventh insulating layer in the twenty-fourth via hole V24 is etched away to expose a surface of the first electrode of the fourth transistor, and the twenty-fourth via hole V24 is configured to enable a data signal line to be formed subsequently to pass through the via hole to connect with the first electrode of the fourth transistor.

[0407] In an exemplary embodiment, a normal projection of the twenty-fifth via hole V25 on the substrate is located within a range of a normal projection of the first electrode of the fifth transistor on the substrate, the seventh insulating layer in the twenty-fifth via hole V25 is etched away to expose a surface of the first electrode of the fifth transistor, and the twenty-fifth via hole V25 is configured to enable a first power supply line to be formed subsequently to pass through the via hole to connect with the first electrode of the fifth transistor.

[0408] In an exemplary embodiment, a normal projection of the twenty-sixth via hole V26 on the substrate is located within a range of a normal projection of the second electrode of the sixth transistor (also the second electrode of the tenth transistor) on the substrate, the seventh insulating layer in the twenty-sixth via hole V26 is etched away to expose a surface of the second electrode of the sixth transistor (also the second electrode of the tenth transistor), and the twenty-sixth via hole V26 is configured to enable an anode connection electrode to be formed subsequently to pass through the via hole to connect with the second electrode of the sixth transistor (also the second electrode of the tenth transistor).

[0409] In an exemplary embodiment, a normal projection of the twenty-seventh via hole V27 on the substrate is located within a range of a normal projection of the first reference connection line on the substrate, the seventh insulating layer in the twenty-seventh via hole V27 is etched away to expose a surface of the first reference connection line, and the twenty-seventh via hole V27 is configured to enable a reference connection line to be formed subsequently to pass through the via hole to connect with the first reference connection line.

[0410] In the exemplary embodiment, the normal projection of the twenty-eighth via hole V28 on the substrate is located within the range of the normal projection of the power connection line on the substrate, the seventh insulating layer in the twenty-eighth via hole V28 is etched away to expose the surface of the power connection line, and the twenty-eighth via hole V28 is configured to enable the first power line formed subsequently to be connected to the power connection line through the via hole.

[0411] (10) Forming a fifth conductive layer pattern. In the exemplary embodiment, forming the fifth conductive layer pattern can include: depositing a fifth conductive thin film on the substrate on which the aforementioned patterns are formed, and patterning the fifth conductive thin film through a patterning process to form the fifth conductive layer pattern, as shown in FIGS. 28 and 29. FIG. 28 is a schematic diagram of the fifth conductive layer pattern in FIG. 10, and FIG. 29 is a schematic diagram of FIG. 10 after the fifth conductive layer pattern is formed.

[0412] In the exemplary embodiment, as shown in FIGS. 28 and 29, the fifth conductive layer pattern can include at least: a data signal line Data, a first power line VDD, a reference connection line REFCL, and an anode connection electrode AL located in at least one sub-pixel.

[0413] In the exemplary embodiment, for the same row of sub-pixels, the data signal line Data connected to the pixel driving circuit of the at least one sub-pixel and the data signal line Data connected to the first adjacent sub-pixel are at least partially symmetrically arranged with respect to a straight line extending along the second direction D2. The data signal line Data connected to the pixel driving circuit of the at least one sub-pixel and the data signal line Data connected to the second adjacent sub-pixel are at least partially the same in structure.

[0414] In the exemplary embodiment, the data signal line Data can have a linear shape with a main body portion extending along the second direction D2, and is electrically connected to the first electrode of the twenty-fourth transistor through the twenty-fourth via hole.

[0415] In the exemplary embodiment, for the same row of sub-pixels, the first power line VDD connected to the pixel driving circuit of the at least one sub-pixel and the first power line VDD connected to the first adjacent sub-pixel are at least partially symmetrically arranged with respect to a straight line extending along the second direction D2. The first power line VDD connected to the pixel driving circuit of the at least one sub-pixel and the first power line VDD connected to the second adjacent sub-pixel are at least partially the same in structure.

[0416] In the exemplary embodiment, the data signal line VDD can have a linear shape with a main body portion extending along the second direction D2. The data signal line VDD is electrically connected to the first electrode of the twenty-fifth transistor through the twenty-fifth via hole, and is electrically connected to the power connection line through the twenty-eighth via hole.

[0417] In an example embodiment, a normal projection of the data signal line VDD on the substrate at least partially overlaps with a normal projection of at least one of the first capacitor and the second capacitor on the substrate.

[0418] In an example embodiment, the data signal line includes a plurality of first data connection portions DA and a plurality of second data connection portions DB. The plurality of first data connection portions DA and the plurality of second data connection portions DB are arranged alternately. At least one of the first data connection portions DA and the second data connection portions DB extends along the second direction D2.

[0419] In an example embodiment, a length of the first data connection portion DA along the first direction D1 is greater than a length of the second data connection portion DB along the first direction D1.

[0420] In an example embodiment, a normal projection of the first data connection portion DA on the substrate at least partially overlaps with a normal projection of at least one of the first reference signal line, the third scan signal line, the first scan signal line, the first second scan signal line, the first initialization signal line, the fourth scan signal line, the first light-emitting signal line, and the power connection line on the substrate.

[0421] In an example embodiment, a normal projection of the first data connection portion DA on the substrate at least partially overlaps with a normal projection of at least one of the first capacitor and the second capacitor on the substrate.

[0422] In an example embodiment, a normal projection of the second data connection portion DB on the substrate at least partially overlaps with a normal projection of at least one of the second light-emitting signal line, the second scan signal line, the second initialization signal line, and the second reference signal line on the substrate.

[0423] In an example embodiment, the reference connection line REFCL can have a linear shape with a main body portion extending along the second direction D2. The reference connection line REFCL is electrically connected to the first reference signal line through the twenty-seventh via.

[0424] In an example embodiment, at least one reference connection line is located between a first power line connected to a pixel driving circuit of the at least one sub-pixel and a first power line connected to a pixel driving circuit of a first adjacent sub-pixel, and a center line of the at least one reference connection line extending along the first direction is collinear with a symmetry axis of the pixel driving circuit of the at least one sub-pixel and the pixel driving circuit of the first adjacent sub-pixel.

[0425] In an example embodiment, at least one reference connection line is located between a data signal line connected to a pixel driving circuit of the at least one sub-pixel and a first power line connected to a pixel driving circuit of a second adjacent sub-pixel.

[0426] In an exemplary embodiment, the anode connecting electrode AL is in a strip shape extending at least partially along the first direction D1, and is electrically connected to the second electrode of the sixth transistor (also the second electrode of the tenth transistor) through the twenty-sixth via hole.

[0427] So far, the circuit structure layer is prepared on the substrate. In a plane parallel to the display substrate, the circuit structure layer can include a plurality of pixel driving circuits and a plurality of signal lines connected to the pixel driving circuits. In a plane perpendicular to the display substrate, the circuit structure layer can be disposed on the substrate. The pixel driving circuit of at least one sub-pixel includes at least one P-type transistor, at least one N-type transistor, and at least one capacitor, the capacitor including: a first electrode plate and a second electrode plate.

[0428] The pixel driving circuit layer can include, in sequence on the substrate, a light shielding layer, a first insulating layer, a first semiconductor layer, a second insulating layer, a first conductive layer, a third insulating layer, a second conductive layer, a fourth insulating layer, a second semiconductor layer, a fifth insulating layer, a third conductive layer, a sixth insulating layer, a fourth conductive layer, a seventh insulating layer, a first planarization layer, and a fifth conductive layer. The first semiconductor layer can include at least an active pattern of at least one P-type transistor, the first conductive layer can include at least a second scan signal line, a first light-emitting signal line, a control electrode of at least one P-type transistor, and a first electrode plate of at least one capacitor, the second conductive layer can include at least a second electrode plate of at least one capacitor and a first control electrode of at least one N-type transistor, the second semiconductor layer includes at least: an active pattern of at least one N-type transistor, the third conductive layer can include at least: a first initial signal line, a second reference signal line, and a second control electrode of at least one N-type transistor, the fourth conductive layer can include at least: a first reference signal line, a first scan signal line, a third scan signal line, a fourth scan signal line, a second light-emitting signal line, a second initial signal line, a power connection line at the first electrode and the second electrode of at least one transistor of the pixel driving circuit of at least one sub-pixel, and the fifth conductive layer can include at least: a data signal line, a first power line, a reference connection line, and an anode connecting electrode, the power connection line is connected to the first power line through a via hole, and the reference connection line is connected to the first reference signal line through a via hole.

[0429] In an exemplary embodiment, the first semiconductor layer can be an amorphous silicon layer or a polycrystalline silicon layer.

[0430] In an exemplary embodiment, the second semiconductor layer can be a metal oxide layer. The metal oxide layer can be an oxide containing indium and tin, an oxide containing tungsten and indium, an oxide containing tungsten, indium and zinc, an oxide containing titanium and indium, an oxide containing titanium, indium and tin, an oxide containing indium and zinc, an oxide containing silicon, indium and tin, or an oxide containing indium or gallium and zinc. The metal oxide layer can be a single layer, or can be a double layer, or can be a multi-layer.

[0431] In the exemplary embodiments, the light shielding layer, at least one of the first conductive layer to the fifth conductive layer can adopt a metal material, such as any one or more of silver (Ag), copper (Cu), aluminum (Al) and molybdenum (Mo), or an alloy material with conductivity, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb), can be a single layer structure, or a multi-layer composite structure, such as Mo / Cu / Mo, etc. For example, the first conductive layer can be made of molybdenum.

[0432] In the exemplary embodiments, the first insulating layer, the second insulating layer, the third insulating layer, the fourth insulating layer, the fifth insulating layer, the sixth insulating layer and the seventh insulating layer can adopt any one or more of silicon oxide (SiOx), silicon nitride (SiNx) and silicon oxynitride (SiON), can be a single layer, a multi-layer or a composite layer.

[0433] In the exemplary embodiments, the first planar layer can adopt an organic material.

[0434] In the exemplary embodiments, after the circuit structure layer is prepared, a light emitting structure layer is prepared on the circuit structure layer, and the preparation process of the light emitting structure layer can include the following operations.

[0435] On the substrate with the aforementioned pattern, an anode conductive film is deposited, and the anode conductive film is patterned by a patterning process to form an anode conductive layer pattern disposed on the second planar layer, on the substrate with the aforementioned pattern, a pixel definition film is deposited, and the pixel definition film is patterned by a patterning process to form a pixel definition layer pattern exposing the anode conductive layer pattern, on the substrate with the pixel definition layer pattern, an organic light emitting material is coated, and the organic light emitting material is patterned by a patterning process to form an organic structure layer pattern, on the substrate with the organic material layer pattern, a cathode conductive film is deposited, and the cathode conductive film is patterned by a patterning process to form a cathode conductive layer.

[0436] Thus far, the light emitting structure layer is prepared on the substrate.

[0437] In the exemplary embodiments, the anode conductive layer at least includes anodes of a plurality of light emitting devices.

[0438] In the exemplary embodiments, the anode conductive layer adopts a single layer structure, such as indium tin oxide (ITO) or indium zinc oxide (IZO), or can adopt a multi-layer composite structure, such as ITO / Ag / ITO, etc.

[0439] In the exemplary embodiments, the organic structure layer at least can include an organic light emitting layer of a light emitting device.

[0440] In an exemplary embodiment, the cathode conductive layer can at least include a cathode of a plurality of light emitting devices.

[0441] In an exemplary embodiment, the cathode layer can be made of a metal material, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), and molybdenum (Mo), or an electrically conductive alloy material, such as an aluminum-neodymium alloy (AlNd) or a molybdenum-niobium alloy (MoNb), and can be a single layer structure or a multi-layer composite structure, such as Mo / Cu / Mo, etc. Exemplarily, the fourth conductive layer can be a three-layer stacked structure of titanium, aluminum, and titanium.

[0442] In an exemplary embodiment, the subsequent manufacturing process can include forming an encapsulation structure layer on the cathode conductive layer, the encapsulation structure layer can include a first encapsulation layer, a second encapsulation layer, and a third encapsulation layer stacked together, the first encapsulation layer and the third encapsulation layer can be made of an inorganic material, the second encapsulation layer can be made of an organic material, and the second encapsulation layer is arranged between the first encapsulation layer and the third encapsulation layer to prevent external water vapor from entering the light emitting structure layer.

[0443] The display substrate provided by the embodiments of the present disclosure can be applied to any resolution display product.

[0444] In an exemplary embodiment, the display device can be any product or component with display function, such as electronic paper, an OLED panel, an active-matrix organic light emitting diode (AMOLED) panel, a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, etc.

[0445] The drawings in the present disclosure only relate to the structures involved in the embodiments of the present disclosure, and other structures can be referred to the general design.

[0446] For the sake of clarity, the thickness and size of a layer or microstructure are exaggerated in the drawings used to describe embodiments of the present disclosure. It can be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" or "under" another element, it can be "directly" on or under the other element, or there can be an intermediate element.

[0447] Although the embodiments disclosed in the present disclosure are as described above, the content described is only an embodiment adopted for the purpose of facilitating the understanding of the present disclosure, and is not intended to limit the present disclosure. Any person skilled in the art of the present disclosure can make any modification and change in the form and details without departing from the spirit and scope of the present disclosure, but the patent protection scope of the present disclosure shall be subject to the scope defined by the appended claims.

Claims

1. A pixel driving circuit configured to drive a light emitting device to emit light, comprising: The first control sub-circuit, the second control sub-circuit, the third control sub-circuit and the driving sub-circuit; The first control sub-circuit is electrically connected with the first scan signal line, the fourth scan signal line, the fifth scan signal line, the data signal line, the first node, the third node, the fourth node and the fifth node respectively, and is configured to provide the signal of the data signal line to the fourth node under the control of the signal of at least one of the first scan signal line, the fourth scan signal line and the fifth scan signal line, control the signal of the fifth node through the signal of the fourth node, and provide the signal of the fifth node to the first node and the third node; The second control sub-circuit is electrically connected with the second scan signal line, the third scan signal line, the first initial signal line, the second initial signal line, the first reference signal line, the second reference signal line, the second node, the fourth node, the fifth node and the sixth node respectively, and is configured to provide the signal of the second reference signal line to the second node under the control of the signal of at least one of the second scan signal line and the third scan signal line, provide the signal of the first reference signal line to the fourth node, provide the signal of the first initial signal line to the fifth node, and provide the signal of the second initial signal line to the sixth node; The third control sub-circuit is electrically connected with the first light-emitting signal line, the second light-emitting signal line, the first power supply line, the second node, the third node and the sixth node respectively, and is configured to provide the signal of the first power supply line to the second node under the control of the signals of the first light-emitting signal line and the second light-emitting signal line, and provide the signal of the third node to the sixth node; The driving sub-circuit is electrically connected with the first node, the second node and the third node respectively, and is configured to provide a driving signal to the third node; The light-emitting device is electrically connected with the sixth node and the second power supply line respectively.

2. The pixel driving circuit according to claim 1, wherein The first control sub-circuit comprises a write sub-circuit, a first storage sub-circuit, a communication sub-circuit and a second storage sub-circuit; The write sub-circuit is electrically connected with the first scan signal line, the data signal line and the fourth node respectively, and is configured to provide the signal of the data signal line to the fourth node under the control of the signal of the first scan signal line; The first storage sub-circuit is electrically connected with the fourth node and the fifth node respectively, and is configured to store the voltage difference between the signals of the fourth node and the fifth node; The communication sub-circuit is electrically connected with the fourth scan signal line, the fifth scan signal line, the first node, the third node and the fifth node respectively, and is configured to provide the signal of the fifth node to the third node under the control of the signal of the fifth scan signal line, and provide the signal of the fifth node to the first node under the control of the signal of the fourth scan signal line; The second storage sub-circuit is electrically connected with the first node and the first power supply line respectively, and is configured to store the voltage difference between the signals of the first node and the first power supply line.

3. The pixel driving circuit of claim 2, wherein, The write sub-circuit comprises a fourth transistor, the first storage sub-circuit comprises a first capacitor, the second storage sub-circuit comprises a second capacitor, at least one of the first capacitor and the second capacitor comprises a first electrode plate and a second electrode plate, and the communication sub-circuit comprises a second transistor and an eighth transistor. The control electrode of the second transistor is electrically connected with the fifth scan signal line, the first electrode of the second transistor is electrically connected with the fifth node, and the second electrode of the second transistor is electrically connected with the third node; The control electrode of the fourth transistor is electrically connected with the first scan signal line, the first electrode of the fourth transistor is electrically connected with the data signal line, and the second electrode of the fourth transistor is electrically connected with the fourth node; The control electrode of the eighth transistor is electrically connected with the fourth scan signal line, the first electrode of the eighth transistor is electrically connected with the fifth node, and the second electrode of the eighth transistor is electrically connected with the first node; The first electrode plate of the first capacitor is electrically connected with the fifth node, and the second electrode plate of the first capacitor is electrically connected with the fourth node; The first electrode plate of the second capacitor is electrically connected with the first node, and the second electrode plate of the second capacitor is electrically connected with the first power supply line.

4. The pixel driving circuit of claim 1, wherein, The second control sub-circuit comprises a first sub-circuit, a second sub-circuit, a third sub-circuit and a fourth sub-circuit; The first sub-circuit is electrically connected with the second scan signal line, the first initial signal line and the fifth node respectively, and is configured to provide the signal of the first initial signal line to the fifth node under the control of the signal of the second scan signal line; The second sub-circuit is electrically connected with the third scan signal line, the first reference signal line and the fourth node respectively, and is configured to provide the signal of the first reference signal line to the fourth node under the control of the signal of the third scan signal line; The third sub-circuit is electrically connected with the second scan signal line, the second reference signal line and the second node respectively, and is configured to provide the signal of the second reference signal line to the second node under the control of the signal of the second scan signal line; The fourth sub-circuit is electrically connected with the second scan signal line, the second initial signal line and the sixth node respectively, and is configured to provide the signal of the second initial signal line to the sixth node under the control of the signal of the second scan signal line.

5. The pixel driving circuit of claim 4, wherein, The first sub-circuit comprises a first transistor, the second sub-circuit comprises a seventh transistor, the third sub-circuit comprises a ninth transistor, and the fourth sub-circuit comprises a tenth transistor; The control electrode of the first transistor is electrically connected with the second scan signal line, the first electrode of the first transistor is electrically connected with the first initial signal line, and the second electrode of the first transistor is electrically connected with the fifth node; The control electrode of the seventh transistor is electrically connected with the third scan signal line, the first electrode of the seventh transistor is electrically connected with the first reference signal line, and the second electrode of the seventh transistor is electrically connected with the fourth node; The control electrode of the ninth transistor is electrically connected with the second scan signal line, the first electrode of the ninth transistor is electrically connected with the second reference signal line, and the second electrode of the ninth transistor is electrically connected with the second node; The control electrode of the tenth transistor is electrically connected with the second scan signal line, the first electrode of the tenth transistor is electrically connected with the second initial signal line, and the second electrode of the tenth transistor is electrically connected with the sixth node.

6. The pixel driving circuit of claim 1, wherein, The first control sub-circuit comprises a second transistor, a fourth transistor, an eighth transistor, a first capacitor and a second capacitor, at least one of the first capacitor and the second capacitor comprises a first plate and a second plate, the second control sub-circuit comprises a first transistor, a seventh transistor, a ninth transistor and a tenth transistor, the third control sub-circuit comprises a fifth transistor and a sixth transistor, and the driving sub-circuit comprises a third transistor; a control electrode of the first transistor is electrically connected with the second scan signal line, a first electrode of the first transistor is electrically connected with the first initial signal line, and a second electrode of the first transistor is electrically connected with the fifth node; a control electrode of the second transistor is electrically connected with the fifth scan signal line, a first electrode of the second transistor is electrically connected with the fifth node, and a second electrode of the second transistor is electrically connected with the third node; a control electrode of the third transistor is electrically connected with the first node, a first electrode of the third transistor is electrically connected with the second node, and a second electrode of the third transistor is electrically connected with the third node; a control electrode of the fourth transistor is electrically connected with the first scan signal line, a first electrode of the fourth transistor is electrically connected with the data signal line, and a second electrode of the fourth transistor is electrically connected with the fourth node; a control electrode of the fifth transistor is electrically connected with the first emitting signal line, a first electrode of the fifth transistor is electrically connected with the first power supply line, and a second electrode of the fifth transistor is electrically connected with the second node; a control electrode of the sixth transistor is electrically connected with the second emitting signal line, a first electrode of the sixth transistor is electrically connected with the third node, and a second electrode of the sixth transistor is electrically connected with the sixth node; a control electrode of the seventh transistor is electrically connected with the third scan signal line, a first electrode of the seventh transistor is electrically connected with the first reference signal line, and a second electrode of the seventh transistor is electrically connected with the fourth node; a control electrode of the eighth transistor is electrically connected with the fourth scan signal line, a first electrode of the eighth transistor is electrically connected with the fifth node, and a second electrode of the eighth transistor is electrically connected with the first node; a control electrode of the ninth transistor is electrically connected with the second scan signal line, a first electrode of the ninth transistor is electrically connected with the second reference signal line, and a second electrode of the ninth transistor is electrically connected with the second node; a control electrode of the tenth transistor is electrically connected with the second scan signal line, a first electrode of the tenth transistor is electrically connected with the second initial signal line, and a second electrode of the tenth transistor is electrically connected with the sixth node; a first plate of the first capacitor is electrically connected with the fifth node, and a second plate of the first capacitor is electrically connected with the fourth node; a first plate of the second capacitor is electrically connected with the first node, and a second plate of the second capacitor is electrically connected with the first power supply line; the fifth scan signal line and the first emitting signal line are the same signal line; a transistor type of the eighth transistor is different from that of at least one of the first transistor to the seventh transistor, the ninth transistor and the tenth transistor; the eighth transistor is an N-type transistor.

7. A display device comprising: a substrate and a plurality of sub-pixels arranged in an array on the substrate, at least one of the plurality of sub-pixels comprises the pixel driving circuit according to any one of claims 1 to 6.

8. The display device of claim 7, wherein, For at least one row of sub-pixels, two adjacent sub-pixels of the at least one sub-pixel include: a first adjacent sub-pixel and a second adjacent sub-pixel; The structure of the pixel driving circuit of the at least one sub-pixel is at least partially symmetrical to the straight line extending in the second direction of the structure of the pixel driving circuit of the first adjacent sub-pixel, and the structure of the pixel driving circuit of the at least one sub-pixel is at least partially the same as the structure of the pixel driving circuit of the second adjacent sub-pixel.

9. The display device of claim 8, further comprising: A plurality of data signal lines, one of the plurality of data signal lines extending in the second direction; The pixel driving circuit of the at least one sub-pixel includes: a second transistor, a third transistor, and a sixth transistor; The first pole and the second pole of at least one transistor in the second transistor, the third transistor, and the sixth transistor in the pixel driving circuit of the at least one sub-pixel do not overlap in the orthographic projection on the substrate of at least one data signal line; The control pole of the third transistor in the pixel driving circuit of the at least one sub-pixel does not overlap in the orthographic projection on the substrate of at least one data signal line.

10. The display device of claim 8, wherein, When the fifth scan signal line of the at least one pixel driving circuit is the same signal line as the first light-emitting signal line, the display device further includes: a plurality of first initial signal lines, a plurality of second initial signal lines, a plurality of first reference signal lines, a plurality of second reference signal lines, a plurality of first scan signal lines, a plurality of second scan signal lines, a plurality of third scan signal lines, a plurality of fourth scan signal lines, a plurality of first light-emitting signal lines, and a plurality of second light-emitting signal lines; At least part of at least one of the plurality of first initial signal lines, the plurality of second initial signal lines, the plurality of first reference signal lines, the plurality of second reference signal lines, the plurality of first scan signal lines, the plurality of second scan signal lines, the plurality of third scan signal lines, the plurality of fourth scan signal lines, the plurality of first light-emitting signal lines, and the plurality of second light-emitting signal lines extends in the first direction, and the first direction intersects the second direction; The pixel driving circuit of the at least one sub-pixel includes: a first transistor, a ninth transistor, and a tenth transistor; The pixel driving circuit of the at least one sub-pixel is electrically connected to two second scan signal lines, the control pole of the first transistor in the pixel driving circuit of the at least one sub-pixel is electrically connected to a first second scan signal line of the two second scan signal lines connected to the pixel driving circuit of the at least one sub-pixel, and the control pole of at least one of the ninth transistor and the tenth transistor in the pixel driving circuit of the at least one sub-pixel is electrically connected to the first second scan signal line of the two second scan signal lines connected to the pixel driving circuit of the at least one sub-pixel; The orthographic projection on the substrate of the first reference signal line connected to the pixel driving circuit of the at least one sub-pixel, the orthographic projection on the substrate of the third scan signal line, the orthographic projection on the substrate of the first scan signal line, the orthographic projection on the substrate of the first second scan signal line, the orthographic projection on the substrate of the fourth scan signal line, the orthographic projection on the substrate of the first light-emitting signal line, the orthographic projection on the substrate of the second light-emitting signal line, the orthographic projection on the substrate of the first second scan signal line, and the orthographic projection on the substrate of the second reference signal line are arranged in the second direction in sequence. The normal projection of the first initial signal line on the substrate is located between the normal projection of the first scanning signal line on the substrate and the normal projection of the fourth scanning signal line on the substrate, and at least partially overlaps the normal projection of the first second scanning signal line on the substrate; The normal projection of the second initial signal line on the substrate is located between the normal projection of the second light-emitting signal line on the substrate and the normal projection of the second reference signal line on the substrate, and at least partially overlaps the normal projection of the second second scanning signal line on the substrate.

11. The display device of claim 10, wherein, The pixel driving circuit of at least one sub-pixel comprises: A first capacitor and a second capacitor; For the pixel driving circuit of at least one sub-pixel, the normal projection of the first capacitor on the substrate is located between the normal projection of at least one of the first second scanning signal line and the first initial signal line connected with the pixel driving circuit on the substrate and the normal projection of the fourth scanning signal line on the substrate; The normal projection of the second capacitor on the substrate is located between the normal projection of the first light-emitting signal line connected with the pixel driving circuit on the substrate and the normal projection of the second light-emitting signal line on the substrate.

12. The display device of claim 10, further comprising: A plurality of first power supply lines, one of the plurality of first power supply lines extends along the second direction; At least one data signal line comprises: a plurality of first data connection parts and a plurality of second data connection parts, the plurality of first data connection parts and the plurality of second data connection parts are arranged alternately, and at least one of the first data connection part and the second data connection part extends along the second direction; For the data signal line connected with the pixel driving circuit of at least one sub-pixel, the normal projection of the first data connection part on the substrate at least partially overlaps the normal projection of at least one of the first reference signal line, the third scanning signal line, the first scanning signal line, the first second scanning signal line, the first initial signal line, the fourth scanning signal line, the first light-emitting signal line, the power supply connection line, and at least one of the first capacitor and the second capacitor in the pixel driving circuit of at least one sub-pixel on the substrate; The normal projection of the second data connection part on the substrate at least partially overlaps the normal projection of at least one of the second light-emitting signal line, the second second scanning signal line, the second initial signal line and the second reference signal line on the substrate; The length of the first data connection part along the first direction is greater than the length of the second data connection part along the first direction.

13. The display device of claim 7, further comprising: A plurality of data signal lines, a plurality of first power supply lines, a plurality of first initial signal lines, a plurality of second initial signal lines, a plurality of first reference signal lines, a plurality of second reference signal lines, a plurality of first scanning signal lines, a plurality of second scanning signal lines, a plurality of third scanning signal lines, a plurality of fourth scanning signal lines, a plurality of first light-emitting signal lines and a plurality of second light-emitting signal lines; The display device further comprises: a circuit structure layer arranged on the substrate, the circuit structure layer comprises: a first semiconductor layer, a first conductive layer, a second conductive layer, a second semiconductor layer, a third conductive layer, a fourth conductive layer and a fifth conductive layer arranged in sequence on the substrate, the pixel driving circuit of at least one sub-pixel comprises: at least one P-type transistor, at least one N-type transistor and at least one capacitor, and the at least one capacitor comprises: a first electrode plate and a second electrode plate; The first semiconductor layer comprises: an active pattern of at least one P-type transistor of a pixel driving circuit of at least one sub-pixel; The first conductive layer comprises at least: a second scan signal line, a first light-emitting signal line, and a first plate of at least one capacitor and a control electrode of at least one P-type transistor of a pixel driving circuit of at least one sub-pixel; The second conductive layer comprises at least: a second plate of at least one capacitor and a first control electrode of at least one N-type transistor in a pixel driving circuit of at least one sub-pixel; The second semiconductor layer comprises at least: an active pattern of at least one N-type transistor of a pixel driving circuit of at least one sub-pixel; The third conductive layer comprises at least: a first initial signal line, a second reference signal line, and a second control electrode of an eighth transistor in a pixel driving circuit of at least one sub-pixel; The fourth conductive layer comprises at least: a first reference signal line, a first scan signal line, a third scan signal line, a fourth scan signal line, a second light-emitting signal line, a second initial signal line, and a first electrode and a second electrode of at least one transistor of a pixel driving circuit of at least one sub-pixel; The fifth conductive layer pattern comprises at least: a data signal line and a first power supply line.

14. The apparatus of claim 13, wherein, The circuit structure layer further comprises: a light shielding layer on a side of the first semiconductor layer close to the substrate, the light shielding layer comprising: a light shielding structure of at least one sub-pixel; The light shielding structure of at least one sub-pixel comprises: a first light shielding part, a second light shielding part, a first light shielding connecting part, a second light shielding connecting part, and a third light shielding connecting part, the first light shielding connecting part, the first light shielding part, the second light shielding connecting part, the second light shielding part, and the third light shielding connecting part being arranged in sequence along a second direction, the first light shielding part being connected to the first light shielding connecting part and the second light shielding connecting part respectively, and the second light shielding part being connected to the second light shielding connecting part and the third light shielding connecting part respectively; At least one of the first light shielding connecting part, the second light shielding connecting part, and the third light shielding connecting part extends along the second direction; A length of at least one of the first light shielding part and the second light shielding part along a first direction is greater than a length of at least one of the first light shielding connecting part to the third light shielding connecting part along the first direction; The pixel driving circuit of at least one sub-pixel comprises: a first capacitor and a second capacitor, the first capacitor and the second capacitor comprising a first plate and a second plate; A normal projection of the first light shielding part of the light shielding structure of at least one sub-pixel on the substrate at least partially overlaps a normal projection of at least one of the first plate and the second plate of the first capacitor on the substrate; A normal projection of the second light shielding part of the light shielding structure of at least one sub-pixel on the substrate at least partially overlaps a normal projection of at least one of the first plate and the second plate of the second capacitor on the substrate.

15. The display device of claim 13, further comprising: At least one of a plurality of power supply connecting lines of the fourth conductive layer and a plurality of reference connecting lines of the fifth conductive layer; One of the plurality of power supply connecting lines extends along a first direction, and one of the plurality of reference connecting lines extends along a second direction; The at least one power connection line is electrically connected with at least one of the plurality of first power lines, and the at least one reference connection line is electrically connected with at least one of the plurality of first reference signal lines; A projection of the at least one power connection line on the substrate is located between a projection of the at least one first light-emitting signal line on the substrate and a projection of the at least one second light-emitting signal line on the substrate, and at least partially overlaps with a projection of the second capacitor in the pixel driving circuit of the at least one sub-pixel on the substrate; The at least one reference connection line is located between a first power line connected by the pixel driving circuit of the at least one sub-pixel and a first power line connected by the pixel driving circuit of the first adjacent sub-pixel, and a middle line of the at least one reference connection line extending in the first direction is a same straight line as a symmetry axis of the pixel driving circuit of the at least one sub-pixel and the pixel driving circuit of the first adjacent sub-pixel; The at least one reference connection line is located between a data signal line connected by the pixel driving circuit of the at least one sub-pixel and a first power line connected by the pixel driving circuit of the first adjacent sub-pixel.

16. A driving method of a pixel driving circuit, configured to drive the pixel driving circuit according to any one of claims 1 to 6, the method comprising: The first control sub-circuit provides a signal of the data signal line to the fourth node, controls a signal of the fifth node through the signal of the fourth node, and provides the signal of the fifth node to the first node and the third node under control of a signal of at least one of the first scan signal line, the fourth scan signal line and the fifth scan signal line; The second control sub-circuit provides a signal of the second reference signal line to the second node, a signal of the first reference signal line to the fourth node, a signal of the first initial signal line to the fifth node, and a signal of the second initial signal line to the sixth node under control of a signal of at least one of the second scan signal line and the third scan signal line; The third control sub-circuit provides a signal of the first power line to the second node and a signal of the third node to the sixth node under control of signals of the first light-emitting signal line and the second light-emitting signal line; The driving sub-circuit provides a driving signal to the third node.

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