Integrated circuit, preparation method for integrated circuit, and electronic device

Abstract

Embodiments of the present application provide an integrated circuit, a preparation method for the integrated circuit, and an electronic device. The integrated circuit comprises a memory provided on a package substrate, and the memory comprises a plurality of memory chips stacked in a direction perpendicular to the package substrate, wherein the projections of any two adjacent memory chips on the package substrate have a non-overlapping region. Each memory chip comprises a logic die and a memory die which are stacked, the logic die and the memory die are electrically connected by means of a first connection structure, and the logic die or the memory die is electrically connected to the package substrate by means of a second connection structure. In each memory chip, the memory die comprises at least one memory array for storing data, the logic die comprises at least one computing unit, and each computing unit is used for processing data of the at least one memory array. By implementing the embodiments of the present application, application requirements for large capacity and high bandwidth of memories can be met while packaging yield is improved.

Description

An integrated circuit, a manufacturing method of the integrated circuit, and an electronic device

[0001] The present application claims priority to the Chinese patent application No. 202411337548.5, filed on September 24, 2024, with the State Intellectual Property Office of China, and entitled "An integrated circuit, a manufacturing method of the integrated circuit, and an electronic device", the entire contents of which are incorporated herein by reference. TECHNICAL FIELD

[0002] The present application relates to the technical field of semiconductor technology, and in particular, to an integrated circuit, a manufacturing method of the integrated circuit, and an electronic device. BACKGROUND

[0003] Recently, with the rapid development of the electronic industry and user demand, electronic devices have developed towards miniaturization, multifunctionalization, and large capacity. Correspondingly, the development direction of storage technology is higher storage density to obtain higher storage capacity. Currently, the industry provides a three-dimensional dynamic random access memory (3D-DRAM), which is prepared in a storage array chip (Array die) and a logic chip (Logic die) respectively. In this way, the area utilization efficiency of the storage layer array can be improved, thereby achieving the purpose of improving the storage capacity per unit area (i.e., storage density).

[0004] However, the current 3D-DRAM is often composed of a storage array chip and a logic chip directly aligned and stacked, and the storage chip and the logic chip are connected through multiple through silicon vias. The stacking process under this packaging form will introduce additional yield problems, affect the performance of the memory, and also increase the cost of the memory, thereby reducing its competitiveness in the market. Moreover, the data stored in the current storage array chip needs to be transmitted to the central processing unit (CPU) for calculation. At this time, due to the limitation of the data transmission path and the current transmission interface bandwidth, it is difficult to meet the needs of some large-capacity and high-bandwidth application scenarios.

[0005] Therefore, how to improve the packaging yield of the memory while meeting the application requirements of large capacity and high bandwidth is a technical problem to be solved. SUMMARY

[0006] The embodiments of the present application provide an integrated circuit, a manufacturing method of the integrated circuit, and an electronic device, which can improve the packaging yield of the memory while meeting the application requirements of large capacity and high bandwidth.

[0007] In a first aspect, an embodiment of the present application provides an integrated circuit, comprising a package substrate and a memory, the memory is arranged on the package substrate, the memory comprises a plurality of memory particles arranged in a stack in a direction perpendicular to the package substrate, wherein a projection of any two adjacent memory particles on the package substrate has a non-overlapping area; each of the memory particles comprises a logic chip and a memory chip arranged in a stack in a direction perpendicular to the package substrate, the logic chip and the memory chip are electrically connected through a first connection structure, and the logic chip or the memory chip is electrically connected to the package substrate through a second connection structure; in each of the memory particles, the memory chip comprises at least one memory array, and each of the memory arrays is used for storing data; the logic chip comprises at least one computing unit, and each of the computing units is used for processing data of the at least one memory array.

[0008] In the prior art, the memory is often composed of a plurality of memory array chips and a logic chip stacked directly and connected through a through silicon via. This method introduces additional yield problems, affects the performance of the memory, and increases the cost. Moreover, due to the limitation of the data transmission path and the current transmission interface bandwidth, it is difficult to meet the needs of some large-capacity and high-bandwidth application scenarios. To this end, an embodiment of the present application provides an integrated circuit, which comprises a memory composed of a plurality of misaligned memory particles, wherein each memory particle comprises a memory chip and a logic chip, and adjacent memory particles in the memory are misaligned and stacked. This can meet the mechanical stress requirement and reduce the probability of damage to the memory during packaging or use. Moreover, this misaligned and stacked arrangement can reduce packaging requirements and packaging costs, does not require strict alignment of each memory particle, and can better adapt to various connection methods (such as bonding connection, welding connection, etc.), avoiding yield problems introduced by connection technologies such as through silicon via. This can meet more circuit design and process scene requirements, greatly improve the packaging yield, and reduce the packaging cost. In addition, each memory particle internally comprises a logic chip with at least one computing unit, which can directly operate the data stored in the memory array of the memory chip, without the need to transmit the data to the CPU for data processing. This greatly meets the needs of large-capacity and high-bandwidth application scenarios under the limitation of the data transmission path and the current transmission interface bandwidth. Therefore, the integrated circuit provided by the present application can improve the yield and reduce the packaging cost while meeting the current large-capacity and high-bandwidth application requirements.

[0009] In a possible implementation, the logic chip further includes a first substrate, and the at least one computing unit is arranged inside the first substrate on a side close to the memory chip; the memory chip further includes a second substrate, and the at least one memory array is arranged on a side of the second substrate close to the logic chip, where the at least one memory array is arranged in a face-to-face electrical connection with the at least one computing unit.

[0010] In the embodiments of the present application, the logic chip and the memory chip are connected in a face-to-face manner through the first connection structure, and the memory array in the memory chip and the computing unit in the logic chip are arranged close to each other, which can facilitate reducing wiring and shortening a transmission path between the memory array and the computing unit, so that the computing unit can reduce transmission time and power consumption when performing computation on data of the memory array. Moreover, in a packaging process, the computing unit and the memory array can be protected from being damaged, thereby greatly improving a packaging yield of the device and reducing packaging cost.

[0011] In a possible implementation, the logic chip further includes a first metal layer, a first dielectric layer, and a complementary metal oxide semiconductor (CMOS) device, the CMOS device is arranged inside the first substrate on a side close to the memory chip, and the first dielectric layer covers the at least one computing unit and the CMOS device; the first metal layer is arranged in the first dielectric layer, and the at least one computing unit and the CMOS device are electrically connected with the first connection structure through the first metal layer; and the CMOS device is configured to transmit a memory control signal to the memory chip.

[0012] In the embodiments of the present application, the CMOS device in the logic chip is equivalent to a logic control circuit, and a memory control signal (such as a signal sensitive amplifier, a word line driver, a word line / bit line decoder, and the like, which are necessary for implementing a storage function) can be transmitted to the memory chip through a metal network structure (i.e., the first metal layer), so as to control the memory array in the memory chip to store data.

[0013] In a possible implementation, the logic chip further includes an input / output device, the input / output device is arranged inside the first substrate on a side close to the memory chip, and the input / output device is electrically connected with the at least one computing unit, the first connection structure, or the second connection structure through the first metal layer; and the input / output device is configured to transmit data acquired from the at least one memory array or data processed by the at least one computing unit.

[0014] In the embodiments of the present application, the data in the memory (such as the data stored by the storage array or the data processed by the computing unit) can be transmitted to the external circuit (such as a package substrate, a CPU, etc.) connected thereto through the input and output device (such as a high-speed IO), thereby realizing high-speed communication between the memory and the processor, avoiding a large amount of data from being transmitted through the traditional transmission interface and then being calculated, relieving the limitation of the bandwidth of the traditional transmission interface, improving the data processing efficiency, and meeting the demand of high bandwidth.

[0015] In a possible implementation, the storage chip further includes a second metal layer and a second dielectric layer, the second dielectric layer is arranged on the side of the second substrate close to the logic chip, and the at least one storage array and the second metal layer are arranged in the second dielectric layer, and the at least one storage array is electrically connected to the first connection structure through the second metal layer.

[0016] In the embodiments of the present application, the storage chip can receive the storage control signal from the logic chip through the metal network structure (i.e., the second metal layer) to store data. Moreover, the additional yield problem introduced by the connection mode of the through silicon via is avoided, and the connection cost is greatly reduced.

[0017] In a possible implementation, the first connection structure includes a bonding connection structure or a soldering connection structure.

[0018] In the embodiments of the present application, the first connection structure can be formed by different connection modes. For example, the bonding connection structure can be formed by the bonding connection mode, or the soldering connection structure can be formed by the soldering connection mode, to realize the electrical connection between the chips. Moreover, the first connection structure avoids the additional yield problem introduced by the connection mode of the through silicon via, greatly reduces the connection cost, and the bonding connection or soldering connection mode used in the storage grain can meet different process requirements and circuit requirements.

[0019] In a possible implementation, the first connection structure includes a first bonding pad and a second bonding pad; in each of the storage grains, the logic chip is arranged with the first bonding pad on the side close to the storage chip, the storage chip is arranged with the second bonding pad on the side close to the logic chip, and the first bonding pad is bonded to the second bonding pad.

[0020] In the embodiments of the present application, the first connection structure is a connection structure formed by the mixed bonding mode, the mixed bonding connection mode is to bond the logic chip and the storage chip together through the first bonding pad and the second bonding pad, so that the logic chip and the storage chip in each storage grain are electrically connected. Moreover, the process flow of the mixed bonding mode is simple, and the packaging is convenient.

[0021] In a possible implementation, the first connection structure includes a micro bump.

[0022] In the embodiments of the present application, the first connection structure is a micro bump, and the bonding mode of the micro bump is wafer-level bonding, which can better bond the logic chip and the memory chip together and is conducive to reducing the packaging size of the memory.

[0023] In a possible implementation, the second connection structure is arranged on a side of the logic chip away from the memory chip, or the second connection structure is arranged on a side of the memory chip away from the logic chip; and a projection of the second connection structure on the packaging substrate does not overlap with a projection of at least one adjacent memory particle on the packaging substrate.

[0024] In the embodiments of the present application, the second connection structure needs to be arranged on a side of the logic chip away from the memory chip or on a side of the memory chip away from the logic chip, so as to be able to connect the packaging substrate. Moreover, after the second connection structure electrically connects the memory particles and the external device, the memory particles can communicate with the external device, that is, each layer of memory particles can relatively independently communicate with the external device through the second connection structure. In addition, the second connection structure can be arranged at the misalignment position of the memory particles, thereby reducing the packaging cost, meeting the electrical connection and packaging requirements, and reducing the probability of damage to the memory during packaging or use.

[0025] In a possible implementation, the second connection structure includes a bonding pad and a bonding wire; in each memory particle, one side of the bonding pad is electrically connected with the first connection structure, the other side of the bonding pad is electrically connected with one end of the bonding wire, and the other end of the bonding wire is electrically connected with the packaging substrate.

[0026] In the embodiments of the present application, the second connection structure is a bonding structure formed by a wire bonding bonding mode, which is used to connect the memory particles and the packaging substrate. The wire bonding bonding mode is a mature technology, and the process flow is simple and the cost is low, which is conducive to packaging and ensuring the yield of the memory device. Moreover, the wire bonding bonding mode is not easy to be damaged during packaging or use.

[0027] In a possible implementation, an insulating structure is arranged between any two adjacent memory particles, and the insulating structure is used to insulate and connect the two adjacent memory particles.

[0028] In the embodiments of the present application, the insulating structure insulates the two adjacent memory particles, that is, each memory particle is independent of each other. When part of the memory particles of the memory are damaged, other memory particles can still be used for data storage, which greatly improves the reliability of the memory.

[0029] In a possible implementation, the insulating structure is a wafer bonding film.

[0030] In the embodiments of the present application, the insulating structure can be a wafer bonding film, which has good adhesion and good heat conduction performance, can protect the chip from being damaged and displaced, and increase heat dissipation.

[0031] In a second aspect, the embodiments of the present application provide a preparation method of an integrated circuit, the integrated circuit comprising a packaging substrate and a memory, the method comprising: packaging a plurality of memory particles stacked in a direction perpendicular to the packaging substrate; wherein projections of any two adjacent memory particles on the packaging substrate have non-overlapping regions; each of the memory particles comprises a logic chip and a memory chip stacked in a direction perpendicular to the packaging substrate, and the logic chip and the memory chip are electrically connected through a first connecting structure; the logic chip or the memory chip in each of the memory particles is electrically connected to the packaging substrate through a second connecting structure; wherein in each of the memory particles, the memory chip comprises at least one memory array, and each of the memory arrays is used for storing data; the logic chip comprises at least one computing unit, and each of the computing units is used for processing data of the at least one memory array.

[0032] In a possible implementation, before the packaging of the plurality of memory particles stacked in the direction perpendicular to the packaging substrate, the method further comprises forming a memory particle, and the forming of the memory particle comprises: connecting the logic chip and the memory chip through the first connecting structure in the direction perpendicular to the packaging substrate; wherein the logic chip further comprises a first substrate, and the at least one computing unit is arranged inside the first substrate on a side close to the memory chip; the memory chip further comprises a second substrate, and the at least one memory array is arranged on a side of the second substrate close to the logic chip, wherein the at least one memory array and the at least one computing unit are arranged in face-to-face electrical connection.

[0033] In a possible implementation, the logic chip further comprises an input-output device, and the input-output device is used for transmitting data obtained from the at least one memory array or data processed by the at least one computing unit.

[0034] In a possible implementation, the connecting of the logic chip and the memory chip through the first connecting structure in the direction perpendicular to the packaging substrate comprises: bonding or welding the logic chip and the memory chip through the first connecting structure in the direction perpendicular to the packaging substrate.

[0035] In a possible implementation, the first connection structure includes a first bonding pad and a second bonding pad; and the bonding connection of the logic chip and the memory chip through the first connection structure includes: bonding connection of the first bonding pad of the logic chip and the second bonding pad of the memory chip, wherein the first bonding pad is arranged on a side of the logic chip close to the memory chip, and the second bonding pad is arranged on a side of the memory chip close to the logic chip.

[0036] In a possible implementation, the first connection structure includes a micro bump, and the bonding connection of the logic chip and the memory chip through the first connection structure includes: bonding connection of the logic chip and the memory chip through the micro bump.

[0037] In a possible implementation, the second connection structure is arranged on a side of the logic chip away from the memory chip, or the second connection structure is arranged on a side of the memory chip away from the logic chip; and a projection of the second connection structure on the packaging substrate does not overlap with a projection of at least one adjacent memory particle on the packaging substrate.

[0038] In a possible implementation, the second connection structure includes a pad and a bonding lead; and the electrical connection of the logic chip or the memory chip in each memory particle to the packaging substrate through the second connection structure includes: electrical connection of the pad to the packaging substrate through the bonding lead; wherein one side of the pad is electrically connected to the first connection structure, the other side of the pad is electrically connected to one end of the bonding lead, and the other end of the bonding lead is electrically connected to the packaging substrate.

[0039] In a possible implementation, the packaging of the plurality of memory particles in a direction perpendicular to the packaging substrate includes: insulating connection of two memory particles through an insulating structure in a direction perpendicular to the packaging substrate.

[0040] In a third aspect, an electronic device is provided, which includes a circuit board and the integrated circuit provided in the first aspect.

[0041] It should be understood that the preparation method of the integrated circuit provided in the second aspect and the electronic device provided in the third aspect are consistent with the technical solution of the first aspect, and the specific content and beneficial effects can be referred to the integrated circuit provided in the first aspect, which will not be repeated here. BRIEF DESCRIPTION OF DRAWINGS

[0042] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the background art, the drawings needed to be used in the embodiments of the present application or the background art will be described below.

[0043] Fig. 1 is a cross-sectional schematic diagram of a memory in the prior art according to an embodiment of the present application.

[0044] Fig. 2 is a cross-sectional schematic diagram of an integrated circuit according to an embodiment of the present application.

[0045] Fig. 3A is a structural schematic diagram of an integrated circuit according to an embodiment of the present application.

[0046] Fig. 3B is a top view schematic diagram of a group of integrated circuits according to an embodiment of the present application.

[0047] Fig. 4 is a functional schematic diagram of a storage grain according to an embodiment of the present application.

[0048] Fig. 5 is a cross-sectional schematic diagram of another integrated circuit according to an embodiment of the present application.

[0049] Fig. 6 is a cross-sectional schematic diagram of still another integrated circuit according to an embodiment of the present application.

[0050] Fig. 7 is a top view schematic diagram of an integrated circuit according to an embodiment of the present application.

[0051] Fig. 8A is a cross-sectional schematic diagram of still another integrated circuit according to an embodiment of the present application.

[0052] Fig. 8B is a cross-sectional schematic diagram of still another integrated circuit according to an embodiment of the present application.

[0053] Fig. 9A and Fig. 9B are cross-sectional schematic diagrams of a group of integrated circuits according to an embodiment of the present application.

[0054] Fig. 10A-13 are cross-sectional schematic diagrams of a group of integrated circuits according to an embodiment of the present application.

[0055] Fig. 10A-13 are cross-sectional schematic diagrams of a group of integrated circuits according to an embodiment of the present application. DETAILED DESCRIPTION

[0056] The embodiments of the present application will be described below with reference to the drawings in the embodiments of the present application.

[0057] The terms "first" and "second" and the like in the description and in the claims of the present application and in the accompanying drawings are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. Furthermore, the terms "comprises", "comprising", "includes", "including", "has", "having" and the like are intended to cover a non-exclusive inclusion such that a process, method, article, system or apparatus that comprises, includes or has a list of elements does not include only those elements but can include other elements not expressly listed or inherent to such process, method, article, system or apparatus. Additionally, the term "coupled" and variations thereof, as used herein, mean the elements or objects have some link or connection between them, which can be either direct or indirect.

[0058] It should be understood that, in the present application, "at least one" means one or more, and "multiple" means two or more. "And / or", used to describe the relationship between associated objects, means that there can be three relationships, for example, "A and / or B" can mean: only A, only B, and A and B exist at the same time, where A and B can be singular or plural. The character " / " generally represents an "or" relationship between the associated objects. "At least one of the following" or the like means any combination of these items, including single or multiple combinations of items. For example, at least one of a, b or c can mean: a, b, c, "a and b", "a and c", "b and c", or "a and b and c", where a, b, and c can be singular or plural.

[0059] For the convenience of description, the embodiments of the present application can use spatial relationship words such as "under", "below", "lower than", "under", "above", "upper" and the like to describe the relationship of one element or feature shown in the drawings with other elements or features. It will be understood that these spatial relationship words are intended to include other directions of the device in use or operation in addition to the directions depicted in the drawings. For example, if the device in the drawing is turned over, the direction of the element described as "below" or "under" or "under" the other element or feature will be changed to "above" the other element or feature. Therefore, the example words "below" and "under" can include both the upper and lower directions. The device can also have other orientations (rotated 90 degrees or in other directions), so the spatial relationship description words used herein should be interpreted accordingly. In addition, it will also be understood that when a layer is referred to as "between" two layers, it can be the only layer between the two layers, or there can be one or more intervening layers.

[0060] Reference herein to "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment can be included in at least one embodiment of the application. The appearances of the phrase in various places in the specification are not necessarily all referring to the same embodiment, nor are they necessarily mutually exclusive of one another. As will be apparent to those of ordinary skill in the art, embodiments described herein can be combined with other embodiments.

[0061] First, in order to facilitate the understanding of the embodiments of the present application, the technical problems to be solved by the embodiments of the present application and the applicable application scenarios are specifically analyzed as follows.

[0062] With the development of technology, the development direction of storage technology is higher storage density to obtain higher storage capacity. Currently, the industry provides a three-dimensional dynamic random access memory (3Dimensional-Dynamic Random Access Memory, 3D-DRAM), which is in the form of preparing a traditional DRAM chip in a storage array chip (Array die) and a logic chip (Logic die) two chips respectively.

[0063] Please refer to FIG. 1, which is a cross-sectional schematic diagram of a memory in the prior art provided by an embodiment of the present application. As shown in FIG. 1, the memory is stacked together by a plurality of storage chips and a logic chip (which can also be referred to as a control chip, etc.), wherein each storage chip and the logic chip can be connected by a plurality of through-silicon vias (TSVs). The TSVs can realize the electrical connection between the chips. The stacking process and the TSV process under this packaging form will introduce additional yield problems, affect the performance of the memory, and also increase the cost of the memory, thereby reducing its competitiveness in the market. In addition, the data stored in the storage chip needs to be transmitted to the central processing unit (CPU) for calculation. At this time, due to the long transmission path of the data, the power consumption will increase. Moreover, due to the limitation of the bandwidth of the current transmission interface, it often leads to the inability to transmit all the data to be calculated to the CPU in time, so the current 3D-DRAM is also difficult to meet the needs of some large-capacity, high-bandwidth application scenarios.

[0064] To this end, the embodiment of the present application provides an integrated circuit comprising a memory, the memory comprising a plurality of misaligned storage particles, wherein adjacent storage particles in the memory are misaligned and stacked, so as to meet the mechanical stress requirement and reduce the probability of damage to the memory during packaging or use. Moreover, the misaligned and stacked arrangement can reduce packaging requirements and packaging costs, and each storage particle does not need to be strictly aligned, and can be better applied to various connection modes (such as bonding connection, welding connection, etc.), so as to avoid yield problems caused by the use of connection technologies such as through silicon vias, and can meet more circuit design and process scene requirements, greatly improve the packaging yield, and reduce the packaging cost. In addition, each storage particle comprises a storage chip and a logic chip, and the logic chip comprises at least one computing unit, which can directly operate the data stored in the storage array of the storage chip, without the need to transmit the data to the CPU for data processing. The data transmission path and the limitation of the current transmission interface bandwidth greatly meet the demand of large capacity and high bandwidth application scenarios. Therefore, the integrated circuit provided by the present application can meet the current large capacity and high bandwidth application requirements, improve the yield and reduce the packaging cost.

[0065] The specific structure of the integrated circuit can also correspond to the description of the related embodiments described below.

[0066] Secondly, based on the above-mentioned technical problems, and in order to facilitate the understanding of the embodiments of the present application, the following describes several integrated circuits based on the embodiments of the present application.

[0067] The embodiment of the present application provides an integrated circuit, which comprises a packaging substrate and a memory arranged on the packaging substrate, the memory comprising a plurality of storage particles stacked in a direction perpendicular to the packaging substrate; each of the storage particles comprises a logic chip and a storage chip stacked in a direction perpendicular to the packaging substrate, the logic chip and the storage chip being electrically connected through a first connection structure, and the logic chip or the storage chip being electrically connected with the packaging substrate through a second connection structure for data transmission; in each of the storage particles, the storage chip comprises at least one storage array, and each of the storage arrays is used for storing data; the logic chip comprises at least one computing unit, and each of the computing units is used for processing the data of the at least one storage array.

[0068] Taking the data transmission of the logic chip through the second connection structure as an example, and by way of example, referring to FIG. 2, which is a cross-sectional schematic diagram of an integrated circuit provided in an embodiment of the present application. As shown in FIG. 2: the memory 10 in the integrated circuit can be disposed on the packaging substrate 101, the memory 10 includes a plurality of memory grains 201 disposed in a staggered manner along the direction perpendicular to the packaging substrate 101 (equivalent to along the thickness direction of the memory 10); wherein each memory grain 201 includes a logic chip 301 and a memory chip 302 stacked along the direction perpendicular to the packaging substrate 101, the logic chip 301 and the memory chip 302 are electrically connected through the first connection structure 303, and the logic chip 301 performs data transmission through the second connection structure 304, that is, the logic chip 301 and the packaging substrate 101 are electrically connected through the second connection structure 304 for data transmission. In each memory grain, the memory chip 302 includes at least one memory array 3021, and each memory array 3021 can be used to store data; the logic chip 301 includes at least one computing unit 3011, and each computing unit 3011 is used to process the data of the at least one memory array 3021.

[0069] As shown in FIG. 2, any two adjacent memory grains 201 in the memory are disposed in a staggered manner, that is, the projections of any two adjacent memory grains 201 on the packaging substrate have non-overlapping areas. This staggered arrangement can meet the mechanical stress requirement and reduce the probability of damage to the memory during packaging or use. Moreover, this staggered stacking arrangement can reduce packaging requirements and packaging costs, does not require strict alignment of each memory grain, and can better adapt to various connection methods (such as bonding connection, welding connection, etc.), avoid yield problems introduced by connection technologies such as through silicon vias, meet more circuit design and process scene requirements, greatly improve the packaging yield, and reduce the packaging cost.

[0070] In other embodiments, the plurality of memory grains 201 can also be disposed in other manners, for example, the memory grain 201 can be disposed in a staggered manner with both adjacent memory grains 201, or can be disposed in a staggered manner with one adjacent memory grain 201 and directly overlapped with the other memory grain 201, that is, the projections of part of the memory grains 201 in the memory on the packaging substrate can have non-overlapping areas (i.e., staggered arrangement), and the projections of part of the memory grains 201 on the packaging substrate can be completely overlapped (i.e., overlapped arrangement). The specific arrangement of the memory grain 201 is not specifically limited in the embodiments of the present application.

[0071] It should be noted that in the embodiments of the present application and the following related embodiments, the memory is disposed on the packaging substrate 101 as an example for illustrative description, and the specific arrangement of the memory is not specifically limited in the present application.

[0072] It should be noted that, in the embodiments of the present application and the following related embodiments, the direction parallel to the surface of the packaging substrate 101 and parallel to one side of the memory 10 is the X-axis direction, i.e., the left-right direction parallel to the surface of the packaging substrate 101 as shown in FIG. 2. The direction parallel to the surface of the packaging substrate 101 and perpendicular to the X-axis direction is the Y-axis direction, i.e., the front-back direction parallel to the surface of the packaging substrate 101 as shown in FIG. 2. The direction perpendicular to the surface of the packaging substrate 101 as shown in FIG. 2, i.e., the thickness direction of the memory 10, is the Z-axis direction, i.e., the vertical direction of the surface of the packaging substrate 101 as shown in FIG. 2. Among them, the X-axis direction, the Y-axis direction and the Z-axis direction are perpendicular to each other.

[0073] It can be understood that the above-mentioned FIG. 2 only illustrates 2 storage particles 201, and the memory is composed of a plurality of storage particles, for example, please refer to FIG. 3A, which is a structural schematic diagram of an integrated circuit provided by an embodiment of the present application. As shown in FIG. 3A, the adjacent storage particles 201 in the memory are all arranged in staggered stacking along the X-axis. This arrangement can not only reduce the probability of damage to the memory during packaging or use, but also avoid the additional yield problem introduced by the packaging form when directly stacking through the through silicon via. In addition, the size of the logic chip 301 and the storage chip 302 in each storage particle 201 can be consistent, which can meet the demand of mechanical stress and further reduce the probability of damage to the memory during packaging or use. For example, when the size of the logic chip 301 and the storage chip 302 is inconsistent, the storage particle may be damaged due to uneven stress during packaging. In some other embodiments, the size of the logic chip 301 and the storage chip 302 can be inconsistent, which is not specifically limited by the embodiments of the present application.

[0074] It can also be understood that any two adjacent memory particles 201 in the memory shown in FIG. 2 or FIG. 3A are staggered in the X-axis direction. In other embodiments, any two adjacent memory particles 201 are staggered in the Y-axis direction or other directions parallel to the packaging substrate 101. Please refer to FIG. 3B, which is a top view of a group of integrated circuits according to an embodiment of the present application. As shown in (1) of FIG. 3B, the adjacent memory particles 201 in the memory can also be staggered in the Y-axis direction; or as shown in (2) of FIG. 3B, the adjacent memory particles 201 in the memory can also be staggered in more other directions parallel to the packaging substrate 101. That is, in the same memory, the direction of the staggered memory particles can not be limited, for example, part of the memory particles 201 can be staggered in the X-axis direction, and the other part of the memory particles 201 can be staggered in the Y-axis direction, that is, the projections of the spaced memory particles on the packaging substrate can not overlap, and the present application does not make specific limitations in this regard. This staggered and stacked arrangement in different directions can reduce packaging requirements and packaging costs, and can stack as many memory particles as possible to improve the storage density of the memory while meeting the mechanical stress requirements.

[0075] Please refer to FIG. 4, which is a functional diagram of a memory particle according to an embodiment of the present application. As shown in FIG. 4, each memory particle includes a logic chip 301 corresponding to a memory chip 302, wherein the memory chip 302 can include at least one memory array 3021, each memory array can also be understood as a storage group Bank, and each memory array can be used to store data. Therefore, the memory formed by stacking a plurality of memory particles can greatly improve the storage capacity density of the memory. The logic chip 301 can include at least one computing unit (equivalent to the computing unit 3011 shown in FIG. 2), and the number of computing units can be less than or equal to the number of memory arrays. For example, each computing unit can correspond to one memory array for computing data in the corresponding memory array, and the computing efficiency is better; each computing unit can also correspond to at least two memory arrays for computing data in the at least two memory arrays. In addition, each memory array corresponds to one computing unit, but one computing unit can correspond to one or more memory arrays, and the present application does not make specific limitations in this regard.

[0076] As shown in FIG. 4, the computing unit in the logic chip can achieve high-speed computing by using the Bank-level bandwidth of the storage array, and directly transmit the computing result to an external device connected to the memory, such as a package substrate or a processor, through the second connection structure, without the need to transmit data to the CPU for data processing, thereby greatly reducing the data transmission distance and data transmission time, and reducing power consumption. Moreover, when the data volume is too large, the transmission speed of the traditional transmission interface is not limited, and each computing unit in the logic chip can directly process the data of at least one storage array, and the processing result can be directly transmitted to the CPU, without the need to transmit data through the traditional transmission interface and then perform computing, thereby relieving the limitation of the bandwidth of the current transmission interface, and further greatly improving the efficiency of processing data. For example, each storage array or Bank can have 64-bit data transmission each time, the time delay tCCD of accessing the same storage array or Bank each time is 2.5 ns, and the bandwidth of the storage array or Bank is 25.6 Gbps. Therefore, when a storage chip has 64 storage arrays or Banks, the total Bank bandwidth corresponding to the logic chip can be 409.6 Gbps, and high-speed computing can be achieved. Moreover, computing in the storage grain can further shorten the transmission path of the storage data, reduce power consumption, and reduce the time for processing data.

[0077] As shown in FIG. 2, the first connection structure 303 is arranged between the logic chip 301 and the storage chip 302 in each storage grain 201. The first connection structure 303 can electrically connect the logic chip 301 and the storage chip 302, so that the logic chip 301 and the storage chip 302 in the storage grain 201 can transmit signals and data, that is, the electrical connection in the storage grain.

[0078] The first connection structure 303 can include a bonding connection structure or a welding connection structure. That is, the first connection structure can be formed by different connection methods. For example, the bonding connection structure can be formed by a bonding connection method, or the welding connection structure can be formed by a welding connection method, to achieve electrical connection between chips. Different connection methods can meet different process and circuit requirements. The bonding connection structure refers to a connection structure formed by a bonding connection method, for example, a ball bonding connection or a wedge bonding connection. The bonding connection method can connect the chips by heat, pressure, and ultrasonic waves, to achieve the flow of electric current. The welding connection structure refers to a connection structure formed by a welding connection method, for example, corresponding materials can be welded together under various conditions (such as high temperature, vacuum, atmosphere, etc.), to achieve the flow of electric current.

[0079] In addition, as shown in FIG. 1, since the storage chip and the logic chip are connected by a plurality of through silicon vias, the stacking and the through silicon via process in this packaging form can introduce additional yield problems, and can also increase the cost of the particle and reduce the competitiveness of the particle in the market. The first connection structure of the embodiment avoids the additional yield problems introduced by the connection mode of the through silicon via, greatly reduces the connection cost and the particle cost, and the internal bonding connection or welding connection of the storage particle can meet different process requirements and circuit requirements.

[0080] Taking the first connection structure 303 as a bonding connection structure as an example, in some embodiments, the first connection structure includes a first bonding pad and a second bonding pad. In each storage particle, the first bonding pad is arranged on the side of the logic chip close to the storage chip, and the second bonding pad is arranged on the side of the storage chip close to the logic chip, and the first bonding pad is bonded to the second bonding pad.

[0081] Please refer to FIG. 5, which is a cross-sectional view of another integrated circuit according to an embodiment of the present application. As shown in FIG. 5, in each storage particle 201, a plurality of first bonding pads 3031 are arranged on the side of the logic chip 301 close to the storage chip 302, and a plurality of second bonding pads 3032 are arranged on the side of the storage chip 302 close to the logic chip 301, wherein the plurality of first bonding pads 3031 correspond to the plurality of second bonding pads 3032 one by one and are bonded. For example, the data in the storage array of the storage chip 302 can be transmitted to the calculation unit of the logic chip 301 for operation through the second bonding pad 3032 and the first bonding pad 3031 corresponding to the second bonding pad 3032. The relevant storage control signal in the logic chip 301 can be transmitted to the storage array of the storage chip 302 for data storage, access or deletion through the first bonding pad 3031 and the second bonding pad 3032 corresponding to the first bonding pad 3031.

[0082] In addition, the first bonding pad 3031 and the second bonding pad 3032 are made of the same material, for example, metal material such as copper, gold, tungsten, etc. The bonding connection mode is a mature process, and compared with the connection mode of the through silicon via, the yield is higher, and the packaging cost is also reduced.

[0083] It should be noted that the first bonding pad 3031 and the second bonding pad 3032 can also be referred to as a hybrid bonding pad or a bonding pad, and the present application does not make specific limitations thereon. In addition, a bonding dielectric can also be arranged around the first bonding pad 3031 and the second bonding pad 3032 (i.e., at the first connection structure 303 between the logic chip 301 and the memory chip 302), so as to protect and insulate the adjacent bonding pads. The material forming the bonding dielectric can be an insulating material, such as silicon oxide, silicon nitride, etc., and the present application does not make specific limitations thereon.

[0084] In some embodiments, the first connection structure includes a micro bump. Please refer to FIG. 6, which is a schematic cross-sectional view of another integrated circuit according to an embodiment of the present application. As shown in FIG. 6, the first connection structure 303 can also be a micro bump, that is, the logic chip 301 and the memory chip 302 are connected by micro bump bonding. The material forming the micro bump can include at least one of the following materials: tin, silver, copper, gold, etc. In addition, the present application does not make specific limitations on the shape of the micro bump, for example, it can be spherical, hemispherical, circular truncated cone, etc. The bonding method of the micro bump is wafer-level bonding, which can better bond the logic chip and the memory chip together, and is also conducive to reducing the packaging size and packaging cost of the memory.

[0085] As shown in FIG. 2, the logic chip 301 in each of the memory particles 201 is also provided with a second connection structure 304, which is used for data transmission of the memory particle 201 to the outside, for example, the electrical connection between the memory particle 201 and the packaging substrate 101, that is, the electrical connection between the memory particle and the external circuit.

[0086] In some embodiments, the second connection structure is arranged on the side of the logic chip away from the memory chip, or the second connection structure is arranged on the side of the memory chip away from the logic chip. The projection of the second connection structure on the packaging substrate does not overlap with the projection of the adjacent memory particle on the packaging substrate.

[0087] As shown in FIG. 5 and FIG. 6, the logic chip 301 is further provided with a second connection structure 304 on the side away from the memory chip 302. As shown in FIG. 5 or FIG. 6, the second connection structure 304 can be a bonding structure formed by wire bonding technology. Therefore, in some embodiments, the second connection structure includes a pad and a bonding wire. The pad is electrically connected to the first connection structure on one side, and the pad is electrically connected to one end of the bonding wire on the other side, and the other end of the bonding wire is electrically connected to the packaging substrate for data transmission.

[0088] For example, the second connection structure 304 can include a pad (provided inside the memory grain) and a bonding wire. Inside the memory grain 201, one side of the pad is further electrically connected to the first connection structure 303 (not shown), and the other side of the pad is electrically connected to one end of the bonding wire, and the other end of the bonding wire is electrically connected to the packaging substrate 101. That is, the bonding wire can electrically connect the packaging substrate 101 and the memory grain 201. The bonding wire can include a metal wire with good electrical conductivity and good ductility, such as gold wire or copper wire. For this purpose, the embodiments of the present application do not specifically limit the material and size of the bonding wire. Compared with the through-silicon via connection mode, the bonding wire connection mode can reduce the packaging cost of the memory and improve the packaging yield.

[0089] The second connection structure 304 is arranged at the misalignment position of the memory grain 201, that is, the projection of the second connection structure on the packaging substrate does not overlap the projection of at least one adjacent memory grain on the packaging substrate. For example, the projection of the second connection structure on the packaging substrate overlaps the projection of one adjacent memory grain on the packaging substrate, and does not overlap the projection of another adjacent memory grain on the packaging substrate. For this purpose, the embodiments of the present application do not specifically limit the number of adjacent memory grains. Arranging the second connection structure at the misalignment position of the memory grain can reduce the packaging cost, meet the electrical connection and packaging requirements in different scenarios, and reduce the probability of damage to the memory during packaging or use.

[0090] It should be noted that the embodiments of the present application do not specifically limit the material and size of the pad. For example, the pad can be a conductive material with good electrical conductivity, such as copper, gold, etc. The diameter of the pad can be greater than the diameter of the bonding wire.

[0091] It should be noted that, in the above-mentioned embodiments, the second connection structure (e.g., a pad) is arranged at the bottom of the substrate, i.e., each memory particle is connected to other devices from the bottom (in the Z-axis direction). The present application does not limit the arrangement of the second connection structure (e.g., a pad). For example, the second connection structure (e.g., a pad) can also be arranged on the sidewall of the bottom of the substrate, i.e., each memory particle is connected to other devices from the side (in the X-axis direction).

[0092] Please refer to FIG. 7, which is a top view of an integrated circuit according to an embodiment of the present application. As shown in FIG. 7, the projection of the second connection structure 304 on the packaging substrate 101 of each memory particle 201 does not overlap with the projection of the adjacent memory particle 201 on the packaging substrate 101. In order to connect each memory particle 201 on the packaging substrate, the projection of the second connection structure 304 on the packaging substrate 101 of any memory particle 201 can not overlap. In this staggered arrangement, the signals of the multi-layer memory particles can be extracted through the respective second connection structures 304 after the multi-layer memory particles are stacked, and the stacking of the multi-layer memory particles is achieved, and the connection error is avoided. In addition, each layer of memory particles can independently communicate with external devices and is not affected by other memory particles. In particular, when some memory particles of the memory are damaged, other memory particles can still be used to store data.

[0093] In addition, as shown in FIG. 7, each memory particle 201 includes other pads or pins for connecting to other devices in addition to the second connection structure 304. The present application does not limit the specific arrangement of the pads or pins.

[0094] In addition, the length L of the staggered arrangement of the adjacent memory particles 201 can be greater than or equal to the length of the pad PAD in the second connection structure 304, and less than or equal to 100 microns.

[0095] In some embodiments, the second connection structure can be a bonding structure formed by a vertical wire fan out (VFO) technology. Please refer to FIG. 8A, which is a schematic cross-sectional view of an integrated circuit according to an embodiment of the present application. As shown in FIG. 8A, a plurality of memory particles 201 are arranged in a staggered manner. The second connection structure can include a pad (arranged inside the memory particle) and a bonding vertical wire. Inside the memory particle 201, one side of the pad is electrically connected to the first connection structure 303 (not shown), and the other side of the pad is electrically connected to one end of the bonding vertical wire. The other end of the bonding vertical wire is electrically connected to other devices (such as a package substrate) for data transmission, such as the package substrate 101. The bonding vertical wire is vertically arranged along the Z-axis direction to electrically connect the memory particle 201 and the package substrate 101. Compared with a bonding structure formed by a wire bonding technology, the bonding structure formed by the VFO technology can reduce the package thickness of the packaged memory. In addition, the material and size of the bonding vertical wire are not limited in the present application. The bonding vertical wire can be a vertical conductive wire with good conductivity, and can also be used to support the staggered arrangement of the memory particles, which is better suited for mechanical stress requirements to reduce the probability of damage to the memory during packaging or use.

[0096] It should be noted that the present application does not limit the relative positions of the logic chip 301 and the memory chip 302 in each memory particle. For example, as shown in FIG. 5 or FIG. 6, the logic chip 301 is located above the memory chip 302 in each memory particle. As shown in FIG. 8A, the logic chip 301 is located below the memory chip 302 in each memory particle.

[0097] In some embodiments, an insulating structure is arranged between any two adjacent memory particles, and the insulating structure is used to insulate and connect the two adjacent memory particles.

[0098] As shown in FIG. 5, FIG. 6, or FIG. 8A, an insulating structure 305 can be arranged between any two adjacent memory particles, and the insulating structure 305 is used to insulate and connect the two adjacent memory particles.

[0099] In some embodiments, the insulating structure 305 can be a wafer bonding film, which is used to insulate and connect two adjacent memory particles, i.e., the two adjacent memory particles cannot be directly electrically connected. The wafer bonding film has good adhesion and good thermal conductivity, which can protect the chip from being damaged and displaced, and increase heat dissipation.

[0100] It should be noted that in another embodiment, the insulating structure 305 can also be other types of insulating films or insulating connection structures, which are not limited in the present application.

[0101] It should be further noted that the above-mentioned embodiments are all illustratively described with the logic chip performing data transmission through the second connection structure, i.e., electrically connected to the packaging substrate. In other embodiments, the storage chip in the storage grain can also perform data transmission through the second connection structure, i.e., electrically connected to the packaging substrate. Please refer to FIG. 8B, which is a cross-sectional view of another integrated circuit provided by an embodiment of the present application. As shown in FIG. 8B, the storage chip 302 in the storage grain can perform data transmission with other devices through the second connection structure 304, i.e., the second connection structure 304 electrically connects the storage chip 302 to the packaging substrate 101. The embodiments of the present application do not make specific limitations on this.

[0102] In other embodiments, part of the storage grains in the memory can be electrically connected to other devices through the logic chip, and another part of the storage grains can be electrically connected to other devices through the storage chip. The embodiments of the present application do not make specific limitations on this.

[0103] In some embodiments, the logic chip 301 further includes a first substrate 3012, and the at least one computing unit 3011 is arranged inside the first substrate 3012 on a side close to the storage chip. The storage chip 302 further includes a second substrate 3022, and the at least one storage array 3021 is arranged on a side of the second substrate 3022 close to the logic chip 301, wherein the at least one storage array 3021 is arranged face-to-face with the at least one computing unit 3011 and is electrically connected through the first connection structure.

[0104] Please refer to FIG. 9A and FIG. 9B, which are cross-sectional views of a group of integrated circuits provided by an embodiment of the present application. As shown in FIG. 9A, the logic chip 301 in the storage grain 201 can further include a first substrate 3012. The first substrate 3012 can be used to support the logic chip 301. Illustratively, the computing unit 3011 is arranged in the front-end-of-line (FEOL) 3013 of the first substrate 3012, i.e., the computing unit 3011 is located inside the first substrate 3012 on a side close to the storage chip.

[0105] The storage chip 302 can further include a second substrate 3022, which can be used to support the storage chip. The second substrate of the storage chip 302 is provided with the storage array 3021 on a side close to the logic chip, i.e., the storage array 3021 is arranged on a side of the second substrate close to the logic chip and is located outside the second substrate 3022.

[0106] In addition, the material of the first substrate 3012 and the second substrate 3022 can be silicon, sapphire, silicon carbide, or the like, and the material of the first substrate 3012 and the second substrate 3022 can be the same or different.

[0107] In the above-mentioned Figure 9A, the storage array 3021 in the storage chip 302 and the computing unit 3011 (also: front 3013) in the logic chip 301 are arranged in a face-to-face electrical connection. The storage array 3021 in the storage chip 302 and the computing unit 3011 in the logic chip 301 are arranged in close proximity. This arrangement can shorten the transmission path between the storage array 3021 and the computing unit 3011, reduce wiring, and reduce transmission time and power consumption when the computing unit 3011 calculates data in the storage array 3021. Moreover, this arrangement can allow the first substrate 3012 of the logic chip 301 and the second substrate 3022 of the storage chip 302 to be externally arranged, so that the computing unit of the logic chip 301 and the storage array of the storage chip 302 can be protected during packaging, thereby improving product yield.

[0108] In some embodiments, the logic chip 301 further comprises a first metal layer 3016, a first dielectric layer 3017, and a CMOS device 3015 arranged inside the first substrate 3012 on the side close to the storage chip 302 (i.e., the front 3013), and the first dielectric layer 3017 covers the at least one computing unit 3011 and the CMOS device 3015, wherein the first metal layer 3016 is arranged in the first dielectric layer 3017, and the at least one computing unit 3011 and the CMOS device 3015 are electrically connected to the first connection structure 303 through the first metal layer 3016. That is, one side of the first metal layer 3016 is electrically connected to the at least one computing unit 3011 and the CMOS device 3015, and the other side of the first metal layer 3016 is electrically connected to the first connection structure 303; and the CMOS device 3015 is used to transmit storage control signals to the storage chip.

[0109] As shown in FIG. 9A, the CMOS device 3015 can be disposed in the front-end 3013 of the logic chip 301, and located on the side of the first substrate 3012 close to the memory chip 302. The CMOS device 3015 can be a logic control circuit as shown in FIG. 4, and can perform command decoding, data serial-to-parallel conversion, etc., to achieve data transmission that meets the demand of high bandwidth while improving the storage capacity density. For example, the CMOS device 3015 can include logic units necessary for implementing storage functions, such as signal sensitive amplifiers, word line drivers, word line / bit line decoders, data buffers, etc., and can also include control units such as storage controllers, control circuits, power conversion circuits, etc. The storage control signals necessary for implementing storage functions can be transmitted through the metal network structure (i.e., the first metal layer 3016). The computing unit 3011 is different from the CMOS device 3015, and does not need to be used for implementing storage functions. The computing unit 3011 can only be used for performing arithmetic processing on data of the memory array 3021, i.e., the computing unit 3011 and the CMOS device 3015 have similar hardware structures, but the computing unit 3011 and the CMOS device 3015 are modules for implementing different functions, respectively.

[0110] The first metal layer 3016 and the first dielectric layer 3017 in the logic chip 301 are disposed in the back-end-of-line (BEOL) of the logic chip 301, i.e., located on the side of the first substrate 3012 close to the memory chip 302, and do not need to be disposed inside the first substrate 3012. The first dielectric layer 3017 wraps the first metal layer 3016 to protect and insulate the first metal layer 3016. The first metal layer 3016 is composed of multiple metal wires, and is used for electrical connection of various devices inside the logic chip 301, e.g., the computing unit or the CMOS device can be electrically connected to the memory chip 302 through the first metal layer 3016 and the first connection structure 303, or the computing unit or the CMOS device can be electrically connected to the second connection structure 304 through the first metal layer 3016.

[0111] In some embodiments, the logic chip 301 further includes an input / output device 3014 disposed inside the first substrate 3012 on the side close to the memory chip 302, and the input / output device 3014 is electrically connected to the at least one computing unit 3011, the first connection structure 303, or the second connection structure 304 through the first metal layer 3016. The input / output device 3014 is used for transmitting data obtained from the at least one memory array 3021 or data processed by the at least one computing unit 3011.

[0112] The input / output device 3014 can be a high-speed IO interface as shown in FIG. 4, which can be used to transmit data of the storage array 3021 to the second connection structure 304 or transmit data processed by the computing unit 3011 to the second connection structure 304, so that the storage array can be connected to other devices through the second connection structure 304, thereby realizing high-speed communication between the storage array and the processor. The data in the storage array (such as data stored by the storage array or data processed by the computing unit) can be transmitted to the external circuit (such as a package substrate, a CPU, etc.) connected thereto through the input / output device (such as a high-speed IO), thereby realizing high-speed communication between the storage array and the processor, avoiding a large amount of data from being transmitted through a traditional transmission interface for processing, relieving the limitation of the bandwidth of the traditional transmission interface, improving the data processing efficiency, and meeting the demand for high bandwidth.

[0113] As shown in FIG. 9A, the input / output device 3014 can be arranged inside the first substrate 3012, i.e., in the front channel 3013, and can be located between the computing unit 3011 and the second connection structure 304. The input / output device 3014 can transmit data to other devices (such as a package substrate or a processor) connected to the storage array through the second connection structure 304.

[0114] In some embodiments, the input / output device 3014 can also be arranged above or below the computing unit, i.e., on the side different from the computing unit 3011. In this embodiment, the specific position of the input / output device 3014 is not limited.

[0115] In some embodiments, the storage chip further includes a second metal layer and a second dielectric layer, the second dielectric layer is arranged on the side of the second substrate close to the logic chip, the at least one storage array and the second metal layer are arranged in the second dielectric layer, and the at least one storage array is electrically connected to the first connection structure through the second metal layer.

[0116] As shown in FIG. 9A, the memory chip 302 can further include a second metal layer 3023 and a second dielectric layer 3024, which are disposed in the back-end-of-line (BEOL) of the memory chip 302, i.e., the second dielectric layer 3024 is located on the side of the second substrate 3022 close to the logic chip 301, and does not need to be disposed inside the first substrate 3012. In addition, the second dielectric layer 3024 also wraps the memory array 3021 and the second metal layer 3023 to protect the memory array 3021. The second metal layer 3023 is located on the side of the memory array 3021 away from the second substrate 3022, and can be electrically connected to the first connection structure 303 to realize electrical connection between various devices inside the memory chip 302. For example, the memory array 3021 can be electrically connected to the first connection structure 303 through the second metal layer 3023.

[0117] In addition, the material of the second dielectric layer 3024 can be the same as or different from that of the first dielectric layer 3017. The second dielectric layer 3024 can be an insulating material such as silicon oxide or silicon nitride.

[0118] In some other embodiments, as shown in FIG. 9B, the memory chip 302 can further include a complementary metal-oxide-semiconductor (CMOS) device 3025, which can be located inside the side of the second substrate 3022 close to the logic chip 301. The CMOS device 3025 can include logic units such as a signal sensitive amplifier, a word line driver, a word line / bit line decoder, etc. In this case, other CMOS devices 3015 in the logic chip 301 can be reserved to implement other memory control functions. The CMOS device 3025 can be used to provide necessary decoding, driving, control, power conversion, etc. functions for the memory array 3021, and the embodiments of the present application do not make specific limitations thereon.

[0119] Therefore, the integrated circuit provided in the present application can meet the application requirements of large capacity and high bandwidth, improve the yield, and reduce the packaging cost.

[0120] Secondly, the present application provides a preparation method of the integrated circuit, which can be used to manufacture the memory mentioned in the above embodiments. Please refer to FIGS. 10A-13, which are a group of cross-sectional schematic diagrams of the preparation method of the integrated circuit provided in the present application.

[0121] The method comprises the following steps:

[0122] Step one: forming a plurality of storage particles.

[0123] Specifically, before the plurality of storage particles are packaged and stacked in the direction perpendicular to the packaging substrate, the method further comprises forming the storage particles. Each storage particle comprises a logic chip and a storage chip stacked in the direction perpendicular to the packaging substrate, and the logic chip and the storage chip are electrically connected through a first connection structure. In each storage particle, the storage chip comprises a storage array for storing data, and the logic chip comprises a calculation unit for processing the data of the storage array.

[0124] In some embodiments, forming the memory grain includes: providing a logic chip and a memory chip respectively as shown in FIG. 10A, it is to be noted that part of the structure in the second connection structure (such as the pad located inside the logic chip or the memory chip) can be prepared when packaging the plurality of memory grains in layers, at this time the provided logic chip or memory chip does not need to be prepared with the pad structure.

[0125] In addition, as shown in FIG. 10B, part of the structure in the second connection structure can also be prepared together with the logic chip or the memory chip, that is, the provided logic chip or memory chip needs to be prepared in advance with the pad structure, and during the subsequent preparation process, the substrate of the logic chip or the memory chip prepared with the pad structure can be thinned until the pad structure is exposed, so as to be electrically connected subsequently. The embodiments of the present application do not make specific limitations thereto.

[0126] As shown in FIG. 11, the logic chip and the memory chip are connected through the first connection structure in the direction perpendicular to the packaging substrate. The logic chip further includes a first substrate, and the at least one computing unit is arranged inside the first substrate near the side of the memory chip. The memory chip further includes a second substrate, and the at least one memory array is arranged on the second substrate near the side of the logic chip, wherein the at least one memory array and the at least one computing unit are arranged in face-to-face electrical connection.

[0127] In some embodiments, the connecting the logic chip and the memory chip through the first connection structure in the direction perpendicular to the packaging substrate includes: bonding or welding the logic chip and the memory chip through the first connection structure in the direction perpendicular to the packaging substrate.

[0128] Taking the bonding connection as an example, in some embodiments, the first connection structure shown in FIG. 11 is hybrid bonding, that is, the first connection structure includes a first bonding pad and a second bonding pad. The bonding connection of the logic chip and the memory chip through the first connection structure includes: bonding the first bonding pad of the logic chip and the second bonding pad of the memory chip, wherein the first bonding pad is arranged on the side of the logic chip near the memory chip, and the second bonding pad is arranged on the side of the memory chip near the logic chip.

[0129] In other embodiments, the first connection structure includes a micro-bump, and the bonding connection of the logic chip and the memory chip through the first connection structure includes: bonding the logic chip and the memory chip through the micro-bump. The embodiments of the present application are not shown in the figure.

[0130] It should be noted that the first connection structure can be prepared together with the corresponding logic chip and the storage chip, or the preparation of the first connection structure can be performed after the preparation of the logic chip and the storage chip is completed. The embodiments of the present application do not specifically limit the preparation sequence of the first connection structure.

[0131] Step two: encapsulating the stacked plurality of storage particles in a direction perpendicular to the packaging substrate.

[0132] Specifically, the stacked plurality of storage particles is encapsulated in a direction perpendicular to the packaging substrate, wherein any two adjacent storage particles can be arranged in a staggered manner, or two adjacent storage particles can be arranged in a completely overlapping manner. The embodiments of the present application do not specifically limit this.

[0133] The stacked plurality of storage particles encapsulated in a direction perpendicular to the packaging substrate includes: insulatingly connecting two storage particles through an insulating structure in a direction perpendicular to the packaging substrate.

[0134] In some embodiments, for each storage particle, the stacked plurality of storage particles encapsulated in a direction perpendicular to the packaging substrate includes: insulatingly connecting two storage particles through an insulating structure. As shown in FIG. 12, two storage particles 201 are insulatingly connected through a wafer bonding film.

[0135] In addition, when or after the stacked plurality of storage particles is encapsulated, each storage particle can be electrically connected to other devices (such as a packaging substrate) through a second connection structure.

[0136] Step three: electrically connecting the logic chip or the storage chip in each storage particle to the packaging substrate through a second connection structure.

[0137] Specifically, when encapsulating, the logic chip or the storage chip in each storage particle can be electrically connected to the packaging substrate through a second connection structure, so that each storage particle transmits data to the packaging substrate through the second connection structure. As shown in the above embodiments, the specific preparation sequence of the second connection structure is not specifically limited by the embodiments of the present application.

[0138] In some embodiments, the second connection structure is arranged on a side of the logic chip away from the storage chip, or the second connection structure is arranged on a side of the storage chip away from the logic chip; wherein a projection of the second connection structure on the packaging substrate does not overlap with a projection of at least one adjacent storage particle on the packaging substrate.

[0139] As shown in FIG. 13, the second connection structure 304 includes a pad and a bonding wire; the electrically connecting the logic chip or the storage chip in each of the storage particles to the package substrate through the second connection structure includes: electrically connecting the pad to the package substrate through the bonding wire; wherein one side of the pad is electrically connected to the first connection structure, the other side of the pad is electrically connected to one end of the bonding wire, and the other end of the bonding wire is electrically connected to the package substrate.

[0140] It should be noted that the structure of the first connection structure 303 and the second connection structure 304 is only an example of an embodiment, and the specific connection structure of the embodiment is not limited.

[0141] The embodiment of the application further provides an electronic device, which comprises a circuit board and the integrated circuit of the above-mentioned embodiment, and the circuit board is electrically connected to the integrated circuit.

[0142] It should be understood that the memory preparation method, the integrated circuit and the electronic device provided by the application can be consistent with the memory technology scheme provided by the application, and the specific content and beneficial effects can refer to the memory mentioned in the above-mentioned embodiments of FIGS. 2-9B, which will not be repeated here.

[0143] It should be noted that for the above-mentioned method embodiments, in order to simply describe, they are all expressed as a series of action combinations, but those skilled in the art should know that the application is not limited by the action sequence described, because according to the application, some steps can be performed in other order or simultaneously. Secondly, those skilled in the art should know that the embodiments described in the specification all belong to preferred embodiments, and the actions and modules involved are not necessarily necessary for the application.

[0144] In several embodiments provided by the application, it should be understood that the disclosed device can be implemented by other ways. For example, the device embodiments described above are only schematic, and for example, the division of the units is only a logical function division, and there can be another division manner in actual implementation, for example, a plurality of units or components can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the coupling or direct coupling or communication connection between the units shown or discussed can be indirect coupling or communication connection through some interfaces, devices or units, and can be electrical or other forms.

[0145] The units described as separate components above can or can not be physically separate, and the components displayed as units can or can not be physical units, i.e., can be located in one place, or can be distributed to multiple network units. Part or all of the units can be selected according to actual needs to achieve the purpose of the embodiment scheme.

[0146] In addition, each functional unit in each embodiment of the present application can be integrated in one processing unit, or each unit can exist physically, or two or more units can be integrated in one unit. The integrated unit can be realized in the form of hardware or in the form of a software functional unit.

[0147] The above description and the above embodiments are only used to illustrate the technical solutions of the present application, and not to limit them; although the present application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that the technical solutions recorded in the foregoing embodiments can still be modified, or some technical features can be replaced by equivalents; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present application.

Claims

1. An integrated circuit, characterized by The integrated circuit comprises a package substrate and a memory, the memory is arranged on the package substrate, the memory comprises a plurality of memory particles arranged in a stacking direction perpendicular to the package substrate, wherein projections of any two adjacent memory particles on the package substrate have non-overlapping regions; Each of the memory particles comprises a logic chip and a memory chip arranged in a stacking direction perpendicular to the package substrate, the logic chip and the memory chip are electrically connected by a first connection structure, and the logic chip or the memory chip is electrically connected to the package substrate by a second connection structure; In each of the memory particles, the memory chip comprises at least one memory array, and each of the memory arrays is used for storing data; the logic chip comprises at least one computing unit, and each of the computing units is used for processing data of the at least one memory array.

2. The integrated circuit of claim 1, wherein, The logic chip further comprises a first substrate, and the at least one computing unit is arranged inside the first substrate on a side close to the memory chip; The memory chip further comprises a second substrate, and the at least one memory array is arranged on a side of the second substrate close to the logic chip, wherein the at least one memory array and the at least one computing unit are arranged in a face-to-face electrical connection mode.

3. The integrated circuit of claim 2, wherein, The logic chip further comprises a first metal layer, a first dielectric layer and a complementary metal oxide semiconductor (CMOS) device; The CMOS device is arranged inside the first substrate on a side close to the memory chip, the first dielectric layer covers the at least one computing unit and the CMOS device, and the first metal layer is arranged in the first dielectric layer, the at least one computing unit and the CMOS device are electrically connected to the first connection structure through the first metal layer; The CMOS device is used for transmitting a memory control signal to the memory chip.

4. The integrated circuit of claim 3, wherein The logic chip further comprises an input / output device, the input / output device is arranged inside the first substrate on a side close to the memory chip, and the input / output device is electrically connected to the at least one computing unit, the first connection structure or the second connection structure through the first metal layer; The input / output device is used for transmitting data obtained from the at least one memory array or data processed by the at least one computing unit.

5. The integrated circuit of any one of claims 2-4, wherein The memory chip further comprises a second metal layer and a second dielectric layer, the second dielectric layer is arranged on a side of the second substrate close to the logic chip, the at least one memory array and the second metal layer are arranged in the second dielectric layer, and the at least one memory array is electrically connected to the first connection structure through the second metal layer.

6. The integrated circuit of any of claims 1-5, wherein, The first connection structure comprises a bonding connection structure or a soldering connection structure.

7. The integrated circuit of claim 6, wherein, The first connection structure comprises a first bonding pad and a second bonding pad; The first bonding pad is arranged on one side of the logic chip close to the memory chip, and the second bonding pad is arranged on one side of the memory chip close to the logic chip.

8. The integrated circuit of claim 7, wherein, The first connecting structure comprises micro-bumps.

9. The memory of any of claims 1-8, wherein, The second connecting structure is arranged on one side of the logic chip away from the memory chip, or the second connecting structure is arranged on one side of the memory chip away from the logic chip. The projection of the second connecting structure on the packaging substrate does not overlap with the projection of at least one adjacent memory particle on the packaging substrate.

10. The memory of any of claims 1-9, wherein, The second connecting structure comprises a bonding pad and a bonding wire. In each memory particle, one side of the bonding pad is electrically connected to the first connecting structure, and the other side of the bonding pad is electrically connected to one end of the bonding wire, and the other end of the bonding wire is electrically connected to the packaging substrate.

11. The integrated circuit of any of claims 1-10, wherein, An insulating structure is arranged between any two adjacent memory particles, and the insulating structure is used for insulating and connecting the two adjacent memory particles.

12. The integrated circuit of claim 11, wherein, The insulating structure is a wafer bonding film.

13. A method of fabricating an integrated circuit, characterized by: The integrated circuit comprises a packaging substrate and a memory, and the method comprises: stacking a plurality of memory particles in a direction perpendicular to the packaging substrate; wherein the projections of any two adjacent memory particles on the packaging substrate have a non-overlapping area; Each memory particle comprises a logic chip and a memory chip stacked in a direction perpendicular to the packaging substrate, and the logic chip and the memory chip are electrically connected by a first connecting structure; The logic chip or the memory chip in each memory particle is electrically connected to the packaging substrate by a second connecting structure; In each memory particle, the memory chip comprises at least one memory array, and each memory array is used for storing data; the logic chip comprises at least one computing unit, and each computing unit is used for processing data of the at least one memory array.

14. The preparation method according to claim 13, characterized in that, Before the plurality of memory particles are stacked in the direction perpendicular to the packaging substrate, the method further comprises forming a memory particle, and the forming of the memory particle comprises: connecting the logic chip and the memory chip by a first connecting structure in a direction perpendicular to the packaging substrate; The logic chip further comprises a first substrate, and the at least one computing unit is arranged inside the first substrate close to one side of the memory chip; the memory chip further comprises a second substrate, and the at least one memory array is arranged on one side of the second substrate close to the logic chip, wherein the at least one memory array and the at least one computing unit are arranged face to face and electrically connected.

15. The method of claim 13 or 14, wherein the step of applying the coating is performed by a method selected from the group consisting of: spray coating, dip coating, spin coating, and combinations thereof. The logic chip further comprises an input / output device for transmitting data obtained from the at least one memory array or data processed by the at least one computing unit.

16. The method of any one of claims 13-15, wherein, The connecting of the logic chip and the memory chip by the first connecting structure in the direction perpendicular to the packaging substrate comprises: The logic chip and the memory chip are bonded or soldered by the first connecting structure in a direction perpendicular to the packaging substrate.

17. The preparation method according to claim 16, characterized in that, The first connecting structure comprises a first bonding pad and a second bonding pad; the bonding of the logic chip and the memory chip by the first connecting structure comprises: bonding the first bonding pad of the logic chip and the second bonding pad of the memory chip, wherein the first bonding pad is arranged on a side of the logic chip close to the memory chip, and the second bonding pad is arranged on a side of the memory chip close to the logic chip.

18. The preparation method according to claim 16, characterized in that, The first connecting structure comprises micro-bumps, and the bonding of the logic chip and the memory chip by the first connecting structure comprises: bonding the logic chip and the memory chip by the micro-bumps.

19. The method of any one of claims 13-18, wherein, The second connecting structure is arranged on a side of the logic chip away from the memory chip, or the second connecting structure is arranged on a side of the memory chip away from the logic chip; wherein a projection of the second connecting structure on the packaging substrate does not overlap with a projection of at least one adjacent memory particle on the packaging substrate.

20. The preparation method according to claim 19, characterized in that, The second connecting structure comprises a solder pad and a bonding lead; The electrical connection of the logic chip or the memory chip in each memory particle to the packaging substrate by the second connecting structure comprises: electrical connection of the solder pad to the packaging substrate by the bonding lead; wherein one side of the solder pad is electrically connected to the first connecting structure, the other side of the solder pad is electrically connected to one end of the bonding lead, and the other end of the bonding lead is electrically connected to the packaging substrate.

21. The method of any one of claims 13-20, wherein, The preparation of the stacked memory particles in a direction perpendicular to the packaging substrate comprises: insulation connection of two memory particles by an insulation structure in a direction perpendicular to the packaging substrate.

22. An electronic device, comprising: The electronic device comprises a circuit board and an integrated circuit as claimed in any one of claims 1-12, and the integrated circuit is electrically connected to the circuit board.

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