Method and circuit structure for improving data transmission stability of 4g gateway USB2.0 interface

Abstract

The embodiments of the present invention belong to the technical field of circuit design. Provided are a method and circuit structure for improving the data transmission stability of a 4G gateway USB2.0 interface. The method comprises: on the basis of component selection, selecting a bidirectional TVS electrostatic protection diode that satisfies a preset encapsulation requirement and a preset junction capacitance value; on the basis of a 4G gateway schematic diagram, designing the layout of the bidirectional TVS electrostatic protection diode on a PCB, so as to obtain a 4G gateway USB2.0 interface circuit; using a simulation model to calculate and analyze the 4G gateway USB2.0 interface circuit under a preset control variable condition, so as to obtain an eye diagram of a differential-line receiving end of a 4G gateway USB2.0 interface; and using the eye diagram to evaluate the data transmission quality of the 4G gateway USB2.0 interface. The circuit structure of the present invention effectively reduces the impacts of junction capacitance of a TVS electrostatic protection diode on the integrity of a differential signal and the continuity of differential impedance, thereby improving the data transmission stability of a 4G gateway USB2.0 interface.

Description

Method for improving data transmission stability of 4G gateway USB2.0 interface and circuit structure thereof TECHNICAL FIELD

[0001] The present application belongs to the technical field of circuit design, and particularly relates to a method for improving data transmission stability of a 4G gateway USB2.0 interface and a circuit structure thereof. BACKGROUND

[0002] With the development of communication technology, gateways play an important role in data transmission. However, factors such as whether the signal is complete, the degree of noise interference, and whether there is obvious delay can cause data transmission errors or data loss, which will seriously affect the stability of data transmission. If the signal integrity during transmission is poor, the transmitted signal may be distorted, jittered, or have errors, which will cause the receiving end to be unable to correctly parse the signal, resulting in data transmission errors or loss. Especially when the signal is transmitted from one medium to another (such as a data gateway), impedance mismatch may cause signal reflection, causing changes in signal amplitude and waveform distortion, thereby seriously affecting signal integrity and reducing the signal transmission quality of the data gateway. Inappropriate selection of components and unreasonable circuit layout can cause changes or distortion of the signal waveform at the receiving end, seriously affecting the accuracy and reliability of data transmission.

[0003] Taking the differential signal lines of the USB2.0 interface in the 4G gateway as an example, during the process of transmitting data using differential signal lines, differential impedance is the most important electrical characteristic of differential signals. Therefore, when laying out differential signal lines, the continuity of differential impedance should be maintained as much as possible. Reflection noise caused by discontinuity of differential impedance should be reduced as much as possible to ensure the stability of differential signals during transmission.

[0004] In the design of a 4G gateway, a TVS static protection tube is commonly provided in the circuit structure of the USB2.0 interface for static protection. However, inappropriate selection of TVS static protection tubes and PCB layout can directly cause discontinuity of differential impedance. On the one hand, unnecessary noise components are introduced based on the original signal, reducing the signal-to-noise ratio of the differential signal. On the other hand, impedance mismatch in the transmission path of the signal can cause signal reflection, resulting in a backhook phenomenon at the rising edge of the original signal, causing more significant delay and jitter during data transmission, and seriously damaging the transmission synchronization of the differential signal.

[0005] Therefore, it is necessary to optimize the circuit structure of the USB2.0 interface of the 4G gateway to solve the above problems in whole or in part. SUMMARY

[0006] In order to solve at least one aspect of the above problems and defects in the prior art, embodiments of the present application provide a method for improving the stability of 4G gateway USB2.0 interface data transmission and a circuit structure thereof. By optimizing the selection of TVS static protection tube and its layout on the PCB circuit board, the influence of TVS static protection tube junction capacitance on differential signal integrity and differential impedance continuity is reduced, and the stability of 4G gateway USB2.0 interface data transmission is improved. The technical solution is as follows:

[0007] According to one aspect of the present application, a method for improving the stability of 4G gateway USB2.0 interface data transmission is provided, which comprises:

[0008] Based on the selection of components, a bidirectional TVS static protection tube that meets the preset packaging requirements and the preset junction capacitance value is selected;

[0009] Based on the 4G gateway schematic diagram, the layout of the bidirectional TVS static protection tube on the PCB circuit board is designed to obtain a 4G gateway USB2.0 interface circuit;

[0010] The 4G gateway USB2.0 interface circuit is calculated and analyzed under the condition of the preset control variable using a simulation model, and the eye diagram of the differential line receiving end of the 4G gateway USB2.0 interface is obtained;

[0011] The eye diagram is used to evaluate the data transmission quality of the 4G gateway USB2.0 interface.

[0012] In some embodiments, the preset junction capacitance value is less than or equal to the maximum capacitance allowed by the 4G gateway USB2.0 interface circuit, and the calculation formula of the maximum capacitance is C max <RT / (5*Z0), where Z0 is the characteristic impedance of the 4G gateway USB2.0 interface differential line, RT is the signal rising edge time, and C max is the maximum capacitance allowed by the 4G gateway USB2.0 interface circuit.

[0013] In some embodiments, when the characteristic impedance Z0 of the 4G gateway USB2.0 interface differential line is 50Ω and the signal rising edge time RT is 0.2ns, the preset junction capacitance value is less than or equal to 0.8pf.

[0014] In some embodiments, based on the 4G gateway schematic diagram, the layout of the bidirectional TVS static protection tube on the PCB circuit board is designed to obtain a 4G gateway USB2.0 interface circuit, which comprises the following steps:

[0015] A PCB circuit board is provided;

[0016] The first interface differential line and the second interface differential line are arranged in parallel in the 4G gateway USB2.0 interface circuit;

[0017] Parallelly connecting one TVS static protection tube on the first interface differential line and the second interface differential line respectively, and symmetrically arranging the two TVS static protection tubes in staggered positions to form a bidirectional TVS static protection tube.

[0018] In some embodiments, the setting parameters of the first interface differential line and the second interface differential line include line width and line spacing, which are used to control the continuity of differential impedance.

[0019] In some embodiments, the two TVS static protection tubes have a first preset spacing, which is the vertical center distance of the two TVS static protection tubes in the staggered direction; each of the two TVS static protection tubes has a second preset spacing between the corresponding pad and the adjacent GND copper skin.

[0020] In some embodiments, the preset control variable condition includes: when simulating and calculating each 4G gateway USB2.0 interface circuit, the number of layers, thickness and material of the PCB circuit board and the wiring mode of the interface differential line are unchanged.

[0021] In some embodiments, the evaluation parameters of the data transmission quality of the 4G gateway USB2.0 interface using the eye diagram include eye signal-to-noise ratio and eye opening degree, wherein the higher the value of the eye signal-to-noise ratio, the less the noise of signal transmission, and the higher the value of the eye opening degree, the weaker the crosstalk of signal transmission.

[0022] According to another aspect of the present application, a USB2.0 interface circuit structure for a 4G gateway is provided, which uses the method for improving the data transmission stability of the 4G gateway USB2.0 interface described in the above aspect to select and layout the TVS tube on the PCB circuit board, and the USB2.0 interface circuit structure comprises:

[0023] a PCB circuit board;

[0024] an interface differential line, which is arranged on the PCB circuit board, and comprises a first interface differential line and a second interface differential line, and a first pad is arranged on the first interface differential line and a second pad is arranged on the second interface differential line;

[0025] a TVS static protection tube, which comprises a first TVS static protection tube and a second TVS static protection tube connected in parallel on the first interface differential line and the second interface differential line respectively, the first TVS static protection tube is arranged on the first pad, and the second TVS static protection tube is arranged on the second pad;

[0026] wherein the first interface differential line and the second interface differential line are parallel, and the first TVS static protection tube and the second TVS static protection tube are symmetrically arranged in staggered positions along the differential signal transmission direction.

[0027] In some embodiments, the package size of the TVS static protection tube is 0.6mm*0.3mm, and the package type is 0201 package TVS tube; the junction capacitance value of the TVS static protection tube is 0.05pf.

[0028] In some embodiments, the line width of the first interface differential line and the second interface differential line is equal, and the line width ranges from 10 to 15 mil; the line spacing of the first interface differential line and the second interface differential line ranges from 4 to 8 mil.

[0029] In some embodiments, the first preset spacing between the first TVS static protection tube and the second TVS static protection tube ranges from 50 to 70 mil.

[0030] In some embodiments, the second preset spacing between the first pad and the second pad and the corresponding adjacent GND copper skin respectively ranges from 5 to 7 mil, and the first pad and the second pad are respectively filled with solid filling treatment between the corresponding adjacent GND copper skin.

[0031] The method for improving the data transmission stability of the USB2.0 interface of the 4G gateway and the circuit structure thereof provided by the embodiments of the present application have at least one or part of the following advantages:

[0032] (1) The method for improving the data transmission stability of the USB2.0 interface of the 4G gateway and the circuit structure thereof provided by the embodiments of the present application, by optimizing the selection of the TVS tube, selecting a small size package and a junction capacitance value far lower than the maximum capacitance of the circuit, reduces the influence of the TVS tube on the signal integrity of the differential signal, and improves the data transmission stability;

[0033] (2) The method for improving the data transmission stability of the USB2.0 interface of the 4G gateway and the circuit structure thereof provided by the embodiments of the present application, by optimizing the layout mode of the TVS static protection tube in the PCB circuit, the bidirectional TVS static protection tube connected in parallel in the circuit is arranged in a staggered manner under the condition of a preset spacing, the differential impedance of the USB2.0 differential line is ensured to be continuous, the noise is reduced, the signal-to-noise ratio of the differential signal is improved, and the data transmission quality is improved;

[0034] (3) The method for improving the data transmission stability of the USB2.0 interface of the 4G gateway and the circuit structure thereof provided by the embodiments of the present application, by optimizing the line width and line spacing of the differential line in the PCB circuit, further weakening the influence of the circuit and the TVS static protection tube on the continuity of the differential impedance, improving the data transmission stability;

[0035] (4) The embodiment of the present application provides a method for improving the data transmission stability of a 4G gateway USB2.0 interface and a circuit structure thereof, TVS static protection tubes with small package size and small junction capacitance are selected, so that the impedance matching degree of the signal on the transmission path is improved, and signal reflection and crosstalk are reduced;

[0036] (5) The embodiment of the present application provides a method for improving the data transmission stability of a 4G gateway USB2.0 interface and a circuit structure thereof, the bidirectional TVS static protection tube is arranged in a staggered manner at a preset interval on the PCB circuit, so that the hook phenomenon of the original signal at the rising edge is effectively reduced, the delay and jitter in the data transmission process are reduced, and the synchronization of the differential signal transmission is improved.

[0037] (6) The embodiment of the present application provides a method for improving the data transmission stability of a 4G gateway USB2.0 interface and a circuit structure thereof, the line width and line spacing of the differential lines of the parallel bidirectional TVS static protection tube are optimized, the continuity of the differential impedance is ensured, the problems of data transmission error and packet loss are avoided, the overall transmission performance of the 4G gateway USB2.0 interface is improved, and the user experience is improved. BRIEF DESCRIPTION OF DRAWINGS

[0038] These and / or other aspects and advantages of the present application will become apparent and readily understood from the following description, taken in connection with the accompanying drawings, in which:

[0039] Fig. 1 is a flowchart of a method for improving the data transmission stability of a 4G gateway USB2.0 interface according to an embodiment of the present application;

[0040] Fig. 2 is a schematic diagram of a USB2.0 interface circuit for a 4G gateway obtained using the method shown in Fig. 1;

[0041] Fig. 3 is a structural diagram of the USB2.0 interface circuit for the 4G gateway obtained according to Fig. 2;

[0042] Fig. 4 is a schematic diagram of a USB2.0 interface circuit of Comparative Example 1;

[0043] Fig. 5 is a schematic diagram of a USB2.0 interface circuit of Comparative Example 2;

[0044] Fig. 6 is a structural diagram of the USB2.0 interface circuit of Comparative Example 2 shown in Fig. 5;

[0045] Fig. 7 is an eye diagram of a differential signal at the receiving end of the USB2.0 interface circuit of Scheme 1 obtained by simulation;

[0046] Fig. 8 is an eye diagram of a differential signal at the receiving end of the USB2.0 interface circuit of Scheme 2 obtained by simulation;

[0047] Fig. 9 is an eye diagram of a differential signal at a receiving end of the USB2.0 interface circuit of the embodiment shown in Fig. 3 obtained through simulation;

[0048] Fig. 10 is a TDR waveform diagram of a differential signal at a receiving end of the USB2.0 interface circuit of the embodiment shown in Fig. 3 obtained through simulation;

[0049] Fig. 11 is a TDR waveform diagram of a differential signal at a receiving end of the USB2.0 interface circuit of the comparative example 2 obtained through simulation;

[0050] Fig. 12 is an eye diagram of a differential signal at a receiving end of the USB2.0 interface circuit of the scheme 3 obtained through simulation;

[0051] Fig. 13 is an eye diagram of a differential signal at a receiving end of the USB2.0 interface circuit of the scheme 4 obtained through simulation. DETAILED DESCRIPTION

[0052] The technical solutions of the present application will be further described below by means of examples in conjunction with the accompanying drawings. In the description, identical or similar reference numerals indicate identical or similar components. The following description of the embodiments of the present application with reference to the accompanying drawings is intended to explain the general inventive concept of the present application and should not be construed as a limitation of the present application.

[0053] The current 4G gateway design provides a TVS static protection tube in the circuit structure of the USB2.0 interface for static protection. However, the existing TVS static protection tube selection and PCB layout are not reasonable or non-adaptive, which easily causes discontinuous differential impedance and reduces the signal-to-noise ratio of the differential signal, thereby affecting the data transmission stability of the USB2.0 interface.

[0054] One aspect of the embodiment of the present application provides a method for improving the data transmission stability of the USB2.0 interface of the 4G gateway, which redesigns and layouts the circuit structure of the USB2.0 interface from the aspects of component selection and 4G gateway schematic design. The eye diagram of the differential line receiving end of the USB2.0 interface obtained through simulation model analysis and calculation verifies that the circuit structure of the USB2.0 interface significantly improves the signal transmission quality and data transmission stability of the 4G gateway.

[0055] Referring to Fig. 1, the specific steps of the method for improving the data transmission stability of the USB2.0 interface of the 4G gateway according to the embodiment of the present application are shown:

[0056] Step S100: based on component selection, selecting a bidirectional TVS static protection tube satisfying the preset packaging requirements and the preset junction capacitance value;

[0057] Step S200: Based on the 4G gateway schematic diagram, the layout of the bidirectional TVS static protection tube on the PCB circuit board is designed using the bidirectional TVS static protection tube of step S100, and the 4G gateway USB2.0 interface circuit is obtained;

[0058] Step S300: Using the simulation model, the 4G gateway USB2.0 interface circuit of step S200 is calculated and analyzed under the condition of the preset control variable, and the eye diagram of the differential line receiving end of the 4G gateway USB2.0 interface is obtained.

[0059] Step S400: The data transmission quality of the 4G gateway USB2.0 interface is evaluated using the eye diagram of step S300.

[0060] In one example, the selection of the TVS static protection tube used in the 4G gateway USB2.0 interface circuit is optimized first. Specifically, the selection of the TVS static protection tube includes screening its package structure or package size and screening its junction capacitance value. Since the TVS static protection tube forms a load capacitance in the circuit, the TVS static protection tube with an adaptive package structure and an adaptive junction capacitance value can effectively reduce the influence of the TVS static protection tube on the signal integrity in the process of high-speed signal transmission.

[0061] Specifically, in one example, the preset package requirements based on the selection of components of step S100 generally include the external shape of the TVS static protection tube after packaging, the overall package size parameter, etc. For example, when the overall package size of the TVS static protection tube is large, its layout on the PCB circuit board will be limited, causing a layout that cannot achieve the optimal signal-to-noise ratio performance. For another example, a large package size of the TVS static protection tube will also increase the volume of its pads, which will also cause discontinuity of differential impedance, thereby affecting the performance of signal and data transmission.

[0062] Specifically, in one example, the preset junction capacitance value based on the selection of components of step S100 should be less than or equal to the maximum capacitance of the 4G gateway USB2.0 interface circuit within the allowable range of reflected noise, and preferably, the smaller the preset junction capacitance value, the smaller the capacitive mutation it can produce, so that excessive reflected noise caused by capacitive mutation can be effectively avoided.

[0063] Further, in one example, the constraint relationship between the load capacitance and the signal rising edge of the single-ended signal line of the 4G gateway USB2.0 interface is used to calculate the maximum capacitance allowed by the USB2.0 interface circuit. The constraint relationship is C max <RT / (5*Z0), where Z0 is the characteristic impedance of the differential line of the 4G gateway USB2.0 interface, RT is the signal rising edge time, and C max is the maximum capacitance allowed by the 4G gateway USB2.0 interface circuit.

[0064] When designing a specific 4G gateway USB 2.0 interface circuit, the maximum allowable capacitance C is first calculated using the aforementioned constraint relationships. max Theoretically speaking, as long as the junction capacitance value is subsequently chosen to be less than or equal to the maximum capacitance C, max All TVS electrostatic discharge tubes can be used as selection targets for TVS electrostatic discharge tubes. Then, the performance of multiple models of TVS electrostatic discharge tubes within the selection target range can be compared and selected by simulation model.

[0065] Preferably, in one example, a specific set of values ​​is assigned to the parameters of the 4G gateway USB 2.0 interface circuit, and its maximum allowable capacitance C is calculated according to the above constraint relationship. max Specifically, when the characteristic impedance Z0 of the differential line of the 4G gateway USB 2.0 interface is 50Ω and the signal rise time RT is 0.2ns, the calculated preset junction capacitance is less than or equal to 0.8pF. Then, TVS diodes with junction capacitance less than or equal to 0.8pF need to be selected, and their performance in the 4G gateway USB 2.0 interface circuit needs to be analyzed to obtain the optimal TVS diode selection parameters.

[0066] In one example, after obtaining the preferred TVS electrostatic protection tube in step S100, the PCB board of the 4G gateway USB 2.0 interface can be laid out in step S200 to obtain its USB 2.0 interface circuit structure. The specific steps for laying out the PCB board include:

[0067] Step S210: Provide a PCB circuit board;

[0068] Step S220: Set the first interface differential line and the second interface differential line in parallel in the 4G gateway USB2.0 interface circuit;

[0069] Step S230: Connect a TVS electrostatic protection tube obtained in step S100 in parallel on the first interface differential line and the second interface differential line in step S220, and arrange the two TVS electrostatic protection tubes in a staggered and symmetrical manner to form a bidirectional TVS electrostatic protection tube on the PCB circuit board.

[0070] Typically, the USB 2.0 interface of a 4G gateway uses differential signaling to transmit data. Differential impedance is the most important electrical characteristic of differential signals. The value of differential impedance is usually controlled between 90Ω and 100Ω. Therefore, when laying out the PCB circuit board, the continuity of differential impedance should be maintained as much as possible to reduce the reflection noise caused by the discontinuity of differential impedance and ensure the stability of differential signal transmission.

[0071] Specifically, in one example, in order to control the continuity of the differential impedance in the signal transmission process, avoid the reflection noise generated due to the discontinuity of the differential impedance, it is necessary to set the line width and the line spacing of the first interface differential line and the second interface differential line of the USB2.0 interface circuit. The line width and the line spacing of the interface differential line have a certain coupling relationship. For example, when the line spacing between the interface differential lines remains unchanged, if the line width becomes smaller, the differential impedance will become larger; on the contrary, when the line width of the interface differential line remains unchanged, if the line spacing of the two interface differential lines becomes larger, the differential impedance will also increase accordingly. The change of the differential impedance inevitably causes the problem of signal reflection noise, thereby affecting the signal integrity of the USB2.0 interface differential signal.

[0072] In addition to the coupling change of the line width and the line spacing of the interface differential line which has a relatively significant impact on the differential impedance, the capacitance value of the capacitive load (for example, the junction capacitance value of the parallel TVS static protection tube) parallelly connected on the interface differential line will also cause the discontinuity of the differential impedance. The larger the capacitance value of the capacitive load, the more severe the change of the differential impedance, the greater the reflection noise on the interface differential line, and the more obvious the distortion of the original signal.

[0073] Specifically, in one example, in order to further control the capacitance value of the capacitive load of the TVS static protection tube parallelly connected on the interface differential line, it is necessary to design the layout of the two TVS static protection tubes on the PCB circuit board. Preferably, the two TVS static protection tubes have a first preset spacing, which is the vertical center distance of the two TVS static protection tubes in the staggered direction; the pad corresponding to each of the two TVS static protection tubes and the adjacent GND copper skin should also have a second preset spacing.

[0074] In theory, after steps S100 and S200, a 4G gateway USB2.0 interface circuit schematic diagram and a circuit structure with relatively optimal transmission performance can be obtained. In order to further verify the actual performance of the circuit structure before producing the circuit structure, in the embodiment of the present application, the performance of the 4G gateway USB2.0 interface circuit is calculated and analyzed in advance according to step S300 using a simulation model, and the eye diagram of the differential line receiving end in the simulation result is used to evaluate the data transmission quality of the 4G gateway USB2.0 interface circuit.

[0075] In one example, preferably, the eye diagram of the receiving end of the differential line of each 4G gateway USB2.0 interface circuit is obtained by simulation calculation using Ansys SIwave simulation software. Of course, those skilled in the art can also use other simulation models and simulation software for simulation calculation, and this is only a demonstrative example, and those skilled in the art should not understand it as a limitation of the present application.

[0076] Another aspect of the embodiments of the present application also provides a USB2.0 interface circuit structure for a 4G gateway, which is designed by using the method for improving the data transmission stability of the USB2.0 interface of the 4G gateway described in the above aspects and embodiments thereof. Referring to FIGS. 2 and 3, the schematic diagram and the circuit structure diagram of the USB2.0 interface circuit 100 are shown, respectively. Specifically, as shown in FIG. 3, the USB2.0 interface circuit structure 100 includes:

[0077] a PCB circuit board 10;

[0078] an interface differential line 20 disposed on the PCB circuit board 10, wherein the interface differential line 20 includes a first interface differential line 21 and a second interface differential line 22, and a first pad 211 is disposed on the first interface differential line 21 and a second pad 221 is disposed on the second interface differential line 22;

[0079] a TVS static protection tube 30 including a first TVS static protection tube 31 and a second TVS static protection tube 32 connected in parallel to the first interface differential line 21 and the second interface differential line 22, respectively, wherein the first TVS static protection tube 31 is disposed on the first pad 211 and the second TVS static protection tube 32 is disposed on the second pad 221;

[0080] wherein the first interface differential line 21 is parallel to the second interface differential line 22, and the first TVS static protection tube 31 and the second TVS static protection tube 32 are arranged in a staggered and symmetrical manner along the differential signal transmission direction.

[0081] The method for improving the data transmission stability of the USB2.0 interface of the 4G gateway and the circuit structure thereof of the present application are described in more detail below through the specific setting parameters and simulation results of one preferred embodiment of the USB2.0 interface circuit structure 100.

[0082] Preferably, in one example, based on the component selection, by selecting a TVS static protection tube that meets the preset packaging requirements and the preset junction capacitance value, a TVS static protection tube with a junction capacitance value of 0.05 pf is screened. Alternatively, the junction capacitance values of the 0201 model, 0402 model and 0805 model packaged TVS static protection tubes produced by Taijiao Electronics can all reach 0.05 pf. Preferably, the 0201 model packaged TVS static protection tube has the smallest packaging size of 0.6 mm*0.3 mm.

[0083] Further, based on the 4G gateway schematic diagram, the 0201 model packaged TVS static protection tube with a junction capacitance value of 0.05 pf is used on the PCB circuit board, and the layout of the TVS static protection tube on the PCB circuit board is designed, to obtain a 4G gateway USB2.0 interface circuit.

[0084] Specifically, in one example, the parameters of the PCB circuit board are first optimized. Preferably, the thickness of the PCB circuit board of the present embodiment is 1.6 mm, and a resin composite material with a flame resistance material grade reaching FR4 is selected as the filling material (alternatively, for example, an epoxy board, an epoxy resin board, a glass fiber board, etc.), and the dielectric constant reaches 4.2.

[0085] Specifically, in one example, the 4G gateway USB2.0 interface differential line and the bidirectional TVS static protection tube are laid out on the PCB circuit board. As shown in FIGS. 2 and 3, the 4G gateway USB2.0 interface differential line 20 includes a first interface differential line 21 and a second interface differential line 22 arranged in parallel along the differential signal transmission direction. The first interface differential line 21 is named USB_DM in the figure, and the second interface differential line 22 is named USB_DP in the figure. Then, a 0201 packaged TVS static protection tube with a junction capacitance value of 0.05 pf is connected in parallel at the 1st position and the 2nd position corresponding to the first interface differential line 21 (USB_DM) and the second interface differential line 22 (USB_DP), respectively.

[0086] As shown in FIG. 3, the 1st position of the first interface differential line 21 (USB_DM) is named as bit D25, and a first TVS static protection tube 31 is connected in parallel to the GND plane at the bit D25. Similarly, the 2nd position of the second interface differential line 22 (USB_DP) is named as bit D26, and a second TVS static protection tube 32 is connected in parallel to the GND plane at the bit D26. At this time, the first TVS static protection tube 31 and the second TVS static protection tube 33 are placed in a layout mode of staggered symmetry along the differential signal transmission direction.

[0087] Further, in one example, the line width of the first interface differential line 21 (USB_DM) and the second interface differential line 22 (USB_DP) is equal, and the line width ranges from 10 to 15 mil, and the line spacing ranges from 4 to 8 mil.

[0088] Further, in one example, the first TVS static protection tube 31 and the second TVS static protection tube 32 have a first preset spacing, and the first preset spacing ranges from 50 to 70 mil. The first pad 211 and the second pad 221 have a second preset spacing with the corresponding adjacent GND copper skin, and the second preset spacing ranges from 5 to 7 mil. At the same time, the first pad 211 and the second pad 221 are filled with solid between the corresponding adjacent GND copper skin.

[0089] Preferably, in one example, the line width of the first interface differential line 21 (USB_DM) and the second interface differential line 22 (USB_DP) is 12 mil, and the line spacing is 6 mil. The first preset spacing between the first TVS static protection tube 31 and the second TVS static protection tube 32 is 60 mil. The first pad 211 on which the first TVS static protection tube 31 on the bit number D25 is located is 6 mil away from the center of the GND copper skin on the right side, and the second pad 221 on which the second TVS static protection tube 32 on the bit number D26 is located is 6 mil away from the center of the GND copper skin on the left side.

[0090] In one example, when the selection of the TVS static protection tube is completed, and the layout of the PCB circuit board on which the TVS static protection tube is located is optimized, alternatively, a simulation model (such as Ansys SIwave simulation software) is used to calculate and analyze the 4G gateway USB2.0 interface circuit under the condition of a preset control variable, to obtain the eye diagram of the differential line receiving end of the 4G gateway USB2.0 interface, and the eye diagram is used to evaluate the data transmission quality of the 4G gateway USB2.0 interface.

[0091] In one example, the eye diagram waveform of the USB2.0 interface receiving end is generally coupled with many factors, such as the wiring mode of the USB2.0 differential line, the junction capacitance value of the TVS static protection tube connected to the differential line, and the parameters such as the number of layers, thickness and material of the PCB circuit board. Therefore, when using the simulation model to analyze the USB2.0 interface circuit, a preset control variable condition is set, which includes that when simulating each 4G gateway USB2.0 interface circuit, the number of layers, thickness and material of the PCB circuit board and the wiring mode of the interface differential line are unchanged. After such setting, the eye diagram waveform obtained by using the simulation model to analyze and calculate is only related to the junction capacitance value of the TVS static protection tube in the USB2.0 interface circuit and the layout mode thereof.

[0092] In one example, when the eye diagram of the USB2.0 interface circuit is obtained, the evaluation parameters of the data transmission quality of the 4G gateway USB2.0 interface include eye signal-to-noise ratio and eye opening. The higher the value of the eye signal-to-noise ratio, the less the noise of the signal transmission, and the higher the value of the eye opening, the weaker the crosstalk of the signal transmission.

[0093] The simulation analysis calculation of the preferred embodiment is preferably performed by Ansys SIwave. The following compares the simulation data of several comparative examples with the preferred USB2.0 interface circuit of the present embodiment to further illustrate the beneficial effects of the preferred embodiment on data transmission performance and transmission quality.

[0094] First, referring to Table 1, three examples of 4G gateway USB2.0 interface circuits are shown, including the present example (the preferred embodiment of the present application), Comparative Example 1, and Comparative Example 2. Specifically, the present example uses a TVS static protection tube with a package model TPESD0201G05V produced by Taijue Electronics and a junction capacitance value of 0.05 pf, and the PCB circuit board is laid out as shown in FIGS. 2 and 3. Comparative Example 1 uses a TVS static protection tube with a package model ESDBL5V0Y1 produced by Hangzhou Tuoya Information Technology Co., Ltd. and a junction capacitance value of 12 pf, and the circuit is laid out as shown in FIG. 4. Comparative Example 2 uses a TVS static protection tube with a package model ESD9B5VL produced by United Microelectronics Corporation and a junction capacitance value of 1 pf, and the PCB circuit board is laid out as shown in FIGS. 5 and 6. Corresponding to the PCB circuit board of the present example, the USB2.0 interface circuit structure 100' of Comparative Example 2 shown in FIG. 6 includes: a PCB circuit board 10'; an interface differential line 20' disposed on the PCB circuit board 10', wherein the interface differential line 20' includes a third interface differential line 21' and a fourth interface differential line 22', and a third pad 211' is disposed on the third interface differential line 21' and a fourth pad 221' is disposed on the fourth interface differential line 22'; a TVS static protection tube 30' including a third TVS static protection tube 32' and a fourth TVS static protection tube 31' connected in parallel to the third interface differential line 21' and the fourth interface differential line 22', respectively, wherein the third TVS static protection tube 31' is disposed on the third pad 221' (bit number D29), and the fourth TVS static protection tube 32' is disposed on the fourth pad 211' (bit number D28).

[0095] Table 1 4G gateway USB2.0 interface circuit examples

[0096] The simulation performance comparison of the present example, Comparative Example 1, and Comparative Example 2 includes two aspects:

[0097] One aspect is that all comparative examples use the PCB layout of the present example (as shown in Fig. 3). Therefore, in addition to the present example, comparative example 1 (TVS static protection tube of comparative example 1 is connected in parallel on the PCB of the present example) and comparative example 2 (TVS static protection tube of comparative example 2 is connected in parallel on the PCB of the present example) are also designed.

[0098] Another aspect is that the same model of TVS static protection tube is arranged on PCBs with different layouts. Therefore, comparative example 3 (TVS static protection tube of comparative example 2 is connected in parallel on the PCB designed by itself as shown in Fig. 6) and comparative example 4 (TVS static protection tube of the present example is connected in parallel on the PCB of comparative example 2) are also designed. Moreover, comparative example 3 is compared with comparative example 2, and comparative example 4 is compared with the present example.

[0099] Referring to Fig. 7, an eye diagram of a receiving end differential signal obtained by simulation calculation of comparative example 1 is shown. Comparative example 1 is that the TVS static protection tube (junction capacitance value is 12 pf) of comparative example 1 is connected in parallel on the PCB as shown in Fig. 3 of the present example. In the eye diagram as shown in Fig. 7, the eye signal-to-noise ratio of comparative example 1 is 61.1529, and the eye opening degree is 0.9836. At this time, the signal rising edge at the position shown by block 1 in the figure produces a relatively obvious hook phenomenon.

[0100] Referring to Fig. 8, an eye diagram of a receiving end differential signal obtained by simulation calculation of comparative example 2 is shown. Comparative example 2 is that the TVS static protection tube (junction capacitance value is 1 pf) of comparative example 2 is connected in parallel on the PCB as shown in Fig. 3 of the present example. In the eye diagram as shown in Fig. 8, the eye signal-to-noise ratio of comparative example 2 is 77.7936, and the eye opening degree is 0.9871. As compared with Fig. 7, since the junction capacitance value of the TVS static protection tube used by comparative example 2 is obviously reduced (junction capacitance value is 1 pf), comparative example 2 obviously improves the eye opening degree of the receiving end eye diagram and the signal-to-noise ratio of the differential signal. Moreover, the hook phenomenon of the signal rising edge caused by the too large capacitive load value in the interconnection line is obviously weakened. At this time, the stability of the USB 2.0 interface data transmission is improved to a certain extent.

[0101] Referring to Fig. 9, an eye diagram of a receiving end differential signal obtained by simulation calculation of the present example is shown. In the eye diagram as shown in Fig. 9, the eye signal-to-noise ratio of the present example is 326.4256, and the eye opening degree is 0.9969. As compared with Figs. 7 and 8, the USB 2.0 interface circuit of the present example not only effectively avoids the hook phenomenon of the signal rising edge caused by the too large capacitive load value in the interconnection line, but also obviously improves the eye opening degree of the receiving end eye diagram and the signal-to-noise ratio of the differential signal.

[0102] On the other hand, by improving the layout of the TVS static protection tube in the PCB circuit, the differential impedance of the interface differential line can be kept continuous as much as possible. In the process of signal transmission, if there is impedance discontinuity, reflection noise will be generated, and the original signal will be superimposed with reflection noise, which will cause ringing phenomenon. The more obvious the ringing phenomenon is, the greater the reflection noise superimposed on the original signal is, and the worse the stability of signal transmission is. Therefore, optimizing the layout of the TVS static protection tube in the PCB circuit and improving the continuity of the differential impedance can help improve the stability of signal transmission.

[0103] Referring to FIG. 10, the TDR waveform of the receiving end obtained by simulation calculation in the present example is shown. Referring to FIG. 11, the TDR waveform of the receiving end obtained by simulation calculation in Comparative Example 2 is shown. In FIG. 10 and FIG. 11, the TDR impedance waveform of the AB segment is circled with a box corresponding to the position of the AB segment interface differential line in the PCB circuit (as shown in FIG. 3) of the present example and the PCB circuit (as shown in FIG. 6) of Comparative Example 2. By comparing FIG. 10 and FIG. 11, the influence of the packaging of the TVS static protection tube and the line width and line spacing of the interface differential line on the TDR impedance of the AB segment differential line can be obviously seen. As shown in FIG. 10, the AB segment differential line has two impedance discontinuity points with an impedance of 122Ω.

[0104] As shown in FIG. 11, due to the use of the PCB circuit layout method (as shown in FIG. 6) of Comparative Example 2, the line width and line spacing between the differential lines of the AB segment have changed dramatically, the differential impedance is as high as 124Ω or more, and there is an impedance discontinuity point with an impedance of 176.5Ω and two impedance discontinuity points with an impedance of 158.8Ω.

[0105] Further, referring to FIG. 12, the eye diagram of the differential signal of Scheme 3 obtained by simulation calculation is shown. Scheme 3 is the TVS static protection tube (junction capacitance value of 1 pf) of Comparative Example 2 connected in parallel to its own PCB circuit board (as shown in FIG. 6). In the eye diagram as shown in FIG. 12, the eye signal-to-noise ratio of Scheme 3 is 44.6, and the eye opening degree is 0.9776. At the same time, in the 2nd box and the 3rd box marked in the figure, the original signal generates reflection noise due to impedance mismatch on the transmission line, thereby causing a relatively serious ringing phenomenon. By comparing with Scheme 2 shown in FIG. 8, by improving the layout of the PCB circuit board (using the PCB circuit board layout of the present example as shown in FIG. 3), the eye signal-to-noise ratio is improved from 44.6 to 77.7936, and the eye opening degree is improved from 0.9776 to 0.9871. At the same time, in the 2nd box and the 3rd box marked in FIG. 8, the reflection noise generated due to impedance mismatch is also obviously reduced.

[0106] Referring to FIG. 13, an eye diagram of a received differential signal obtained by simulation calculation of scheme 4 is shown, and the scheme 4 is that the TVS static protection tube (junction capacitance value is 0.05 pf) in the example is connected in parallel to the PCB circuit board (as shown in FIG. 6) of the comparative example 2. In the eye diagram as shown in FIG. 13, the eye signal-to-noise ratio of the scheme 4 is 202.9840, and the eye opening degree is 0.9951. The signal transmission quality of the receiving end is obviously improved compared with the scheme 2 (as shown in FIG. 8) and the scheme 3 (as shown in FIG. 12). However, in the box marked in FIG. 13, there is still reflection noise due to the mismatch of the differential impedance. And compared with the scheme (as shown in FIG. 9) in the example, the eye signal-to-noise ratio of the scheme 4 is reduced from 326.4256 to 202.9840, and the eye opening degree is reduced from 0.9969 to 0.9951 due to the use of the non-optimized PCB circuit board layout.

[0107] The simulation results of the data signal transmission performance of the above comparative schemes and the example are summarized in Table 2. It can be seen that by optimizing the selection of the TVS static protection tube of the USB2.0 interface circuit in the 4G gateway schematic diagram and improving the layout method of the TVS static protection tube on the PCB circuit board, the problems of large reflection noise, signal distortion, jitter and the like of the USB2.0 interface signal transmission caused by the discontinuity of the differential impedance due to the intermediate capacitive load in the interconnection line and the improper component packaging are significantly reduced, thereby effectively improving the stability of the USB2.0 interface signal transmission.

[0108] Table 2 Simulation results of transmission performance of each scheme (including the example)

[0109] The method for improving the data transmission stability of the USB2.0 interface of the 4G gateway and the circuit structure thereof provided by the embodiments of the present application have at least one or part of the following advantages:

[0110] (1) The method for improving the data transmission stability of the USB2.0 interface of the 4G gateway and the circuit structure thereof provided by the embodiments of the present application, by optimizing the selection of the TVS static protection tube, selecting a small size package and a junction capacitance value far lower than the maximum capacitance allowed by the circuit, reduce the influence of the TVS static protection tube on the signal integrity of the differential signal, improve the data transmission stability;

[0111] (2) The method for improving the data transmission stability of the USB2.0 interface of the 4G gateway and the circuit structure thereof provided by the embodiments of the present application, by optimizing the layout method of the TVS static protection tube in the PCB circuit, the bidirectional TVS static protection tube connected in parallel into the circuit is arranged in a staggered manner under the condition of a preset spacing, the differential impedance of the USB2.0 differential line is kept continuous, the noise is reduced, the signal-to-noise ratio of the differential signal is improved, and the data transmission quality is improved;

[0112] (3) The embodiment of the present application provides a method for improving data transmission stability of a 4G gateway USB2.0 interface and a circuit structure thereof, the method improves the data transmission stability by optimizing the line width and line spacing of differential lines in a PCB circuit, further weakening the influence of the circuit and a TVS static protection tube on the continuity of differential impedance, and improving the data transmission stability;

[0113] (4) The embodiment of the present application provides a method for improving data transmission stability of a 4G gateway USB2.0 interface and a circuit structure thereof, the method improves the data transmission stability by selecting a TVS static protection tube with a small package size and a small junction capacitance, improving the impedance matching degree of the signal on the transmission path, and reducing signal reflection and crosstalk;

[0114] (5) The embodiment of the present application provides a method for improving data transmission stability of a 4G gateway USB2.0 interface and a circuit structure thereof, the method effectively reduces the hook phenomenon of the original signal at the rising edge, reduces the delay and jitter in the data transmission process, and improves the synchronization of differential signal transmission by arranging the bidirectional TVS static protection tube on the PCB circuit at a preset interval.

[0115] (6) The embodiment of the present application provides a method for improving data transmission stability of a 4G gateway USB2.0 interface and a circuit structure thereof, the method guarantees the continuity of differential impedance by optimizing the line width and line spacing of the differential lines of the parallel bidirectional TVS static protection tube, avoids data transmission errors and packet loss, improves the overall transmission performance of the 4G gateway USB2.0 interface, and improves the user experience.

[0116] Although some embodiments of the present general inventive concept have been shown and described, it would be understood by those of ordinary skill in the art that changes might be made thereto without departing from the principles and spirit of the present general inventive concept, the scope of which is defined in the claims and their equivalents.

Claims

1. A method for improving the stability of data transmission of a 4G gateway USB 2.0 interface, characterized in that, The method comprises: Based on the component selection, a bidirectional TVS static protection tube satisfying the preset packaging requirements and the preset junction capacitance value is selected; Based on the 4G gateway schematic diagram, the layout of the bidirectional TVS static protection tube on the PCB circuit board is designed, and a 4G gateway USB2.0 interface circuit is obtained; Using a simulation model, the 4G gateway USB2.0 interface circuit is calculated and analyzed under the preset control variable condition, and an eye diagram of a differential line receiving end of the 4G gateway USB2.0 interface is obtained; The data transmission quality of the 4G gateway USB2.0 interface is evaluated using the eye diagram.

2. The method of claim 1, wherein the preset junction capacitance value is less than or equal to the maximum capacitance allowed by the 4G gateway USB2.0 interface circuit, and the maximum capacitance is calculated according to the formula:

3. The method of claim 2, wherein when the characteristic impedance Z0 of the 4G gateway USB2.0 interface differential line is 50Ω and the signal rising edge time RT is 0.2ns, the preset junction capacitance value is less than or equal to 0.8pf. C max < RT / (5*Z0), Wherein Z0 is the characteristic impedance of the 4G gateway USB2.0 interface differential line, RT is the signal rising edge time, C max is the maximum capacitance allowed by the 4G gateway USB2.0 interface circuit.

4. The method of any one of claims 1-3, wherein the step of designing the layout of the bidirectional TVS static protection tube on the PCB circuit board based on the 4G gateway schematic diagram to obtain the 4G gateway USB2.0 interface circuit comprises: providing a PCB circuit board; parallelly arranging a first interface differential line and a second interface differential line in the 4G gateway USB2.0 interface circuit; parallelly connecting a TVS static protection tube to each of the first interface differential line and the second interface differential line, and symmetrically arranging the two TVS static protection tubes in a staggered manner to form a bidirectional TVS static protection tube.

5. The method of claim 4, wherein the arrangement parameters of the first interface differential line and the second interface differential line include line width and line spacing, which are used to control the continuity of the differential impedance.

6. The method of claim 5, wherein the two TVS static protection tubes have a first preset spacing therebetween, and the first preset spacing is the vertical center distance of the two TVS static protection tubes in the staggered direction; and each of the two TVS static protection tubes has a second preset spacing between the corresponding pad and the adjacent GND copper skin.

7. The method of claim 6, wherein the preset control variable condition comprises: when simulating and calculating each 4G gateway USB2.0 interface circuit, the number of layers, thickness and material of the PCB circuit board and the wiring mode of the interface differential line are kept unchanged.

8. The method of claim 7, wherein the evaluation parameters for evaluating the data transmission quality of the 4G gateway USB2.0 interface using the eye diagram include eye signal-to-noise ratio and eye opening degree, and the higher the value of the eye signal-to-noise ratio, the less the noise of the signal transmission, and the higher the value of the eye opening degree, the weaker the crosstalk of the signal transmission. The USB2.0 interface circuit structure comprises: a PCB circuit board; ​ ​ ​ ​ ​ ​ 9. A USB2.0 interface circuit structure for a 4G gateway, the USB2.0 interface circuit structure is designed using the method according to any one of claims 1-8, characterized in that, ​ ​ An interface differential line is arranged on the PCB circuit board, the interface differential line comprises a first interface differential line and a second interface differential line, a first pad is arranged on the first interface differential line, and a second pad is arranged on the second interface differential line; A TVS static protection tube comprises a first TVS static protection tube and a second TVS static protection tube which are connected in parallel to the first interface differential line and the second interface differential line respectively, the first TVS static protection tube is arranged on the first pad, and the second TVS static protection tube is arranged on the second pad; The first interface differential line is parallel to the second interface differential line, and the first TVS static protection tube and the second TVS static protection tube are arranged in a staggered and symmetrical manner along a differential signal transmission direction.

10. The USB2.0 interface circuit structure according to claim 9, wherein The package size of the TVS static protection tube is 0.6mm*0.3mm, and the package type is 0201 package TVS tube. The junction capacitance of the TVS static protection tube is 0.05pf.

11. The USB2.0 interface circuit structure according to claim 10, wherein The line width of the first interface differential line and the second interface differential line is equal, and the line width ranges from 10mil to 15mil. The line spacing of the first interface differential line and the second interface differential line ranges from 4mil to 8mil.

12. The USB2.0 interface circuit structure according to claim 11, wherein The first preset spacing between the first TVS static protection tube and the second TVS static protection tube ranges from 50mil to 70mil.

13. The USB2.0 interface circuit structure according to claim 12, wherein The second preset spacing between the first pad and the second pad and the corresponding adjacent GND copper ranges from 5mil to 7mil. The first pad and the second pad are filled with solid respectively between the corresponding adjacent GND copper.

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