Capacitive energy store with controlled inrush current and embedded equipment equipped with such a capacitive energy store

Abstract

The invention relates to a capacitive energy store (108) for a piece of embedded equipment (100), comprising: a succession of storage capacitors (3, 4, 5, 6) that are connected in parallel and that each have a capacitance less than 25,000 μF; a buffer capacitor (2) of lower capacitance; a switch (20) for connecting / disconnecting the buffer capacitor to / from a power supply (102) of the equipment; switches (30, 40, 50, 60) for connecting / disconnecting each storage capacitor to / from the preceding capacitor; a sequencer (8), configured to measure the voltage across the terminals of the buffer capacitor and of the storage capacitors and, when the equipment is switched on, control the various switches according to an initial charging process comprising a succession of cycles of charging / discharging the buffer capacitor (2) into the succession of storage capacitors.

Description

[0001] DESCRIPTION

[0002] TITLE: Controlled inrush current capacitive energy reserve and on-board equipment equipped with such a capacitive energy reserve

[0003] technical field

[0004] This application relates to a capacitive energy reserve with controlled inrush current, a method for managing this energy reserve, and on-board equipment equipped with such an energy reserve.

[0005] The invention is particularly applicable to the field of transport, especially aeronautics - civil or military - and rail, and to the space field, the energy reserve being intended to power an on-board equipment or system.

[0006] Previous Art

[0007] To ensure the proper functioning of onboard equipment in the event of a brief interruption in its power supply, a capacitive energy reserve, implemented using capacitors, is provided. This energy reserve is designed to power the onboard equipment when the input voltage is interrupted, for a period known as the "transparency time," which is typically 200 ms. It should be noted that such energy reserves are also used in the nuclear sector, for shorter transparency times.

[0008] The capacitive energy reserve is recharged when the equipment is powered on. Due to the very low internal series resistance of the capacitors, powering on the equipment and its energy reserve induces a very high current inrush.

[0009] In order to limit this inrush current, in most cases, the management of the capacitive energy reserve of the on-board equipment is carried out using a management circuit comprising one or more series resistors and one or more diodes.

[0010] The drawback of this solution is that it is not robust enough with regard to the current values ​​involved. Furthermore, given these current values, it requires one or more high-current and / or high-power resistors and diodes (between 50W and 100W), the size of which poses a problem. For example, a 50W resistor such as the one sold under the name RH-50 by VISHAY® measures 50mm x 28mm. Similarly, a 43mF capacitor such as the one sold under the reference ALS80A433NF100 by KEMET® is cylindrical, 105mm long and 77mm in diameter.

[0011] Therefore, neither the capacitive energy reserve nor its management circuit can be built on the printed circuit board of the onboard equipment. The aforementioned resistors and diodes are oversized for circuit boards; they are mounted in the management circuit by screwing and secured with lugs.

[0012] In general, known capacitive energy reserve charge management circuits that use diodes and resistors have a significant size and weight that penalizes their use in embedded equipment.

[0013] Besides their own bulk, the aforementioned components have the major disadvantage of generating significant heat, which prohibits their implementation in unventilated embedded equipment or requires additional means (heat sink) to dissipate the heat that these components generate.

[0014] More advanced solutions exist, such as the use of specific current-limiting components, like a bidirectional converter. The drawback of these solutions is that they are single-source, meaning they are developed and offered by a single supplier and therefore entirely dependent on that supplier. Consequently, a defective or obsolete component cannot be replaced quickly or at a controlled cost. Any single-source solution is therefore considered unsustainable.

[0015] Another, simpler solution would be to increase the power supply's output to provide the necessary current during the capacitor charging phase, but this solution is not feasible for an aircraft-mounted system. Indeed, not only is this solution incompatible with aeronautical standards, but it would also lead to an undesirable increase in the power supply's size, generally incompatible with the available space. Providing a "large" power supply, from 100W to 300W for example, solely to power the energy reserve charging phase is not satisfactory.

[0016] The invention aims to overcome at least one of the aforementioned drawbacks by providing a capacitive energy reserve for on-board equipment that is not single-source and / or generates sufficiently little heat to be suitable for unventilated on-board equipment and / or has a reduced volume.

[0017] Description of the invention

[0018] To achieve this, the invention proposes a capacitive energy reserve for embedded equipment, said capacitive energy reserve comprising:

[0019] - an input terminal to connect the capacitive energy reserve to a power supply for the on-board equipment,

[0020] - an output terminal, to connect the capacitive energy reserve to a voltage bus of the on-board equipment,

[0021] - a series of capacitors, called reserve capacitors, connected in parallel and each having a capacitance of less than 25,000 pF, for example on the order of 10,000 pF, the series of reserve capacitors comprising a first reserve capacitor, a last reserve capacitor and optionally one or more intermediate reserve capacitors,

[0022] - a switch, called the output switch, located between the last reserve capacitor and the output terminal,

[0023] - a charge management circuit between the input terminal and the first reserve capacitor.

[0024] The capacitive energy reserve according to the invention is characterized in that:

[0025] - the charge management circuit includes a capacitor, called a buffer capacitor, of lower capacitance than the reserve capacitors, said buffer capacitor being connected on one side to the input terminal of the capacitive energy reserve, and on the other side to an input of the succession of reserve capacitors, - the charge management circuit includes a switch, called the buffer capacitor charge switch, located between the input terminal and the buffer capacitor, and allowing the buffer capacitor to be connected / disconnected from the equipment's power supply when the input terminal is connected to said power supply;

[0026] - the capacitive energy reserve includes, for each of the reserve capacitors, a charge switch for said reserve capacitor, located upstream of the reserve capacitor and allowing said reserve capacitor to be connected / disconnected with the preceding reserve capacitor and / or the buffer capacitor,

[0027] - The load management circuit includes a sequencer, configured to measure the voltage across the buffer capacitor and across each of the reserve capacitors, and to, upon power-up of the equipment, control the various switches of the capacitive energy reserve according to an initial charging process during which the output switch remains open, said initial charging process comprising a succession of charge / discharge cycles of the buffer capacitor, each of said cycles comprising:

[0028] -- a buffer capacitor charging stage, in which the buffer capacitor charging switch is closed and the first reserve capacitor charging switch is open, the charge management circuit thus being isolated from the succession of reserve capacitors while the buffer capacitor is energized,

[0029] -- a discharge stage of the buffer capacitor in the succession of reserve capacitors, in which the charge switch of the buffer capacitor is open and the charge switch of the first reserve capacitor is closed,

[0030] - When the voltage (V3) across the first reserve capacitor equals the voltage (V2) across the buffer capacitor, the series of reserve capacitors is disconnected from the charge management circuit by opening the charge switch (30) of the first reserve capacitor, thus ending the charge / discharge cycle of the buffer capacitor. Note that, throughout this description, the terms "upstream" and "downstream," "previous" and "next," "first" and "last," etc., refer to the direction of current flow from the equipment's power supply through the capacitive energy reserve.

[0031] The invention extends to a method of charge management of the capacitive energy reserve, characterized by the initial charging process defined above.

[0032] According to particular embodiments of the invention, the capacitive energy reserve and / or the charge management method thereof also have the following characteristics, implemented individually or in any technically possible and operational combination.

[0033] In some embodiments, the load management circuit further includes a current limiter connected to the input terminal, which is configured to impose a predetermined limited current value at its output. The buffer capacitor is thus supplied with a limited current. Since its capacitance is chosen to be relatively low, this current limitation does not prevent the buffer capacitor from fully and efficiently charging. At the same time, the current limitation helps to limit the heat dissipated by the load management circuit, which, combined with the use of reserve capacitors with relatively small capacitances, makes the capacitive energy reserve according to the invention compatible with unventilated equipment.

[0034] In some embodiments, the sequencer is configured to, during each buffer capacitor charging step, keep the charging switches of all reserve capacitors closed except for the charging switch of the first reserve capacitor (the latter allowing the succession of reserve capacitors to be isolated from the charge management circuit during the charging of the buffer capacitor), for the purpose of balancing the charges between the reserve capacitors.

[0035] Thus, while the buffer capacitor is charging, the charges accumulated during previous cycles in the succession of reserve capacitors are distributed among the various reserve capacitors until equilibrium is reached; in other words, the first reserve capacitor, which has accumulated additional charges (compared to the other reserve capacitors) during the discharge stage of the buffer capacitor in the previous cycle, discharges in cascade into the following reserve capacitors, until all the reserve capacitors have the same amount of energy.

[0036] In some embodiments, the initial recharging process of the capacitive energy reserve includes:

[0037] - an indirect charging phase using the buffer capacitor, which indirect charging phase includes the previously defined charge / discharge cycles of the buffer capacitor,

[0038] - and a direct charging phase, in which the charging switch (20) of the buffer capacitor and the charging switches (30, 40, 50, 60) of all the reserve capacitors are closed. During this phase, the reserve capacitors are therefore connected to the equipment's power supply and directly charged by it.

[0039] If the spare capacitors were not at least partially charged by the previous indirect charging phase, connecting them to the equipment's power supply would generate a large, undesirable current inrush. Since they are already partially charged, this current inrush is limited and acceptable.

[0040] To ensure that this current draw is truly limited, and for example less than a given value, the sequencer can be configured to:

[0041] - at the end of each charge / discharge cycle of the buffer capacitor (in indirect charging phase), determine a charge rate of the first reserve capacitor, defined as the ratio (Vs / Vaiim) between the voltage (V3) across the terminals of the first reserve capacitor and the voltage (Vaiim) of the equipment's power supply,

[0042] - and switch from the indirect charging phase to the direct charging phase if the charge level of the first capacitor exceeds a predetermined threshold value. This threshold value can be between 70% and 90%; for example, it is equal to 80%, or start a new charge / discharge cycle of the buffer capacitor (i.e., continue the indirect charging phase) otherwise.

[0043] Alternatively, the sequencer can be configured to switch from the indirect charging phase to the direct charging phase after a predetermined number of charge / discharge cycles of the buffer capacitor.

[0044] In some embodiments, the load management circuit includes a protection filter arranged between the current limiter and the buffer capacitor, for example between the current limiter and the buffer capacitor charging switch.

[0045] In some embodiments, the capacitive energy reserve includes an ideal diode between the output switch and the output terminal.

[0046] In some embodiments, the succession of reserve capacitors comprises four capacitors each having a capacitance of approximately 10,000pF, and the buffer capacitor has a capacitance of approximately 2,200pF.

[0047] The invention extends to embedded equipment comprising a voltage bus and a power supply, the voltage bus being connected to the power supply by a power supply circuit. The embedded equipment according to the invention is characterized in that it comprises a capacitive energy reserve as previously described, arranged in parallel with said power supply circuit, the input terminal of the capacitive energy reserve being connected to the power supply of the embedded equipment and the output terminal of the capacitive energy reserve being connected to the voltage bus of the embedded equipment.

[0048] Brief description of the drawings

[0049] The invention, according to an exemplary embodiment, will be well understood and its advantages will become more apparent upon reading the following detailed description, given by way of example and not limiting, with reference to the accompanying drawings in which: o Figure 1 is an electrical diagram representing an exemplary embodiment of equipment with a capacitive energy reserve according to the invention; o Figure 2 represents a part of the capacitive energy reserve of Figure 1 during a charging stage of its buffer capacitor; o Figure 3 represents a part of the capacitive energy reserve of Figures 1 and 2 during a discharging stage of said buffer capacitor.

[0050] Detailed description

[0051] Identical elements represented in the aforementioned figures are identified by identical numerical references.

[0052] Figure 1 represents a piece of equipment 100, which is, for example, equipment installed on an aircraft or a spacecraft. This piece of equipment 100 includes:

[0053] - a 102 power supply, which is for example a 32V power supply delivering direct current,

[0054] - a secure voltage bus 104, electrically powered by the power supply 102 via a power supply circuit 106 comprising an ideal diode 1062 which ensures that current can only flow in the direction from the power supply 102 to the voltage bus 104 of the equipment;

[0055] - a capacitive energy reserve 108 according to the invention.

[0056] This capacitive energy reserve 108 comprises an input terminal 1081 through which it is connected to the equipment's power supply 102, and an output terminal 1082 through which it is connected to the equipment's voltage bus 104. Note that the term "terminal" here does not imply the presence of an electrode or other connector or physical contact; it simply designates a point in the circuit.

[0057] The capacitive energy reserve 108 also includes:

[0058] - A series of 3 to 6 spare capacitors connected in parallel. These spare capacitors are chosen from commercially available standard capacitors to avoid dependence on a single supplier, and are small enough to be mounted directly on the printed circuit board that serves as the equipment's control unit. These spare capacitors also have the advantage of not dissipating heat. The number and capacity of the spare capacitors are chosen based on the total capacity required to ensure proper equipment operation in the event of a brief power interruption, and also on construction constraints such as available space, acceptable heat dissipation, etc.In the illustrated example, the capacitive energy reserve comprises four reserve capacitors 3, 4, 5, 6, and each of these reserve capacitors has a capacitance of 10 00000F. In this example, the series of reserve capacitors therefore has a capacitance of 40 00000F. Each reserve capacitor is connected to the circuit by a load switch 30, 40, 50, 60. Given the architecture of the circuit and the position of said load switches 30-60, the reserve capacitors are connected in parallel and their capacitances add up when all the load switches 30-60 are closed, and the opening of the load switch of one of the reserve capacitors (for example the load switch 40) isolates from the circuit not only said reserve capacitor (in the example capacitor 4) but also the reserve capacitors which follow in the circuit architecture (i.e. capacitors 5 and 6);.

[0059] - an output switch 70, between the last reserve capacitor 6 and the output terminal 1082, in order to be able to connect / disconnect the succession of reserve capacitors 3 to 6 with the voltage bus 104 of the equipment;

[0060] - a buffer capacitor 2, having a capacitance of 2200pF for example, which buffer capacitor is mounted in parallel and upstream of the series of reserve capacitors 3 to 6; its capacitance being less than the capacitance of each of the reserve capacitors and the total capacitance of the series of reserve capacitors, the charging of this buffer capacitor (when it is separated from the series of reserve capacitors) generates a current inrush much lower than that which the series of reserve capacitors would generate if it were directly connected to the power supply 102; the capacitance of the buffer capacitor is chosen sufficiently low to generate an acceptable current inrush, depending on the power supply 102 and the environment of the equipment; - a current limiter 10 immediately downstream of the input terminal 1081 of the capacitive energy reserve;This current limiter 10 limits the intensity of the current, supplied by the power supply 102, which enters the capacitors of the capacitive energy reserve 108, and in particular the buffer capacitor 2;

[0061] - a protective filter 12 arranged between the current limiter 10 and the load switch 20 of the buffer capacitor 2,

[0062] - a voltage control and measurement sequencer 8, which is configured to control the load switches 20, 30, 40, 50, 60 of each of the capacitors (reserve and buffer) as well as the output switch 70, via control wires 22, 32, 42, 52, 62 and 72 respectively; the sequencer is also configured to measure the voltage across each of the capacitors (reserve and buffer) via measurement wires 24, 34, 44, 54, 64.

[0063] The capacitive energy reserve 108 may also include an ideal diode 14 between the output switch 70 and the output terminal 1082 to ensure that current can only flow in the direction from the capacitive energy reserve 108 to the voltage bus 104.

[0064] The circuit formed by the current limiter 10, the protection filter 12, the buffer capacitor 2, the load switch 20 of the latter and the sequencer 8 constitutes a load management circuit which allows the management of the charge (and discharge in the equipment) of the energy reserve.

[0065] When the equipment is powered on, i.e. when its connection to the power supply 102 is activated, an initial recharging process of the capacitive energy reserve, managed by the sequencer 8, begins.

[0066] This process comprises two phases: an indirect charging phase and a direct charging phase. Throughout the initial charging process of the capacitive energy reserve, the output switch 70 is held open by the sequencer 8 in order to disconnect the capacitive energy reserve from the voltage bus 104.

[0067] The indirect charging phase consists of using the buffer capacitor 2 to gradually charge the succession of reserve capacitors 3 to 6, in the manner of communicating vessels, by repeating charge / discharge cycles of the buffer capacitor.

[0068] Each cycle begins with a charging step for buffer capacitor 2, illustrated in Figure 2. To initiate this step, sequencer 8 commands the opening of the charging switch 30 for the first reserve capacitor and the closing of the charging switch 20 for the buffer capacitor. The circuit upstream of the series of reserve capacitors is then closed and isolated from said series of reserve capacitors. Buffer capacitor 2 is powered by the equipment's power supply 102. Current flows only in the upstream portion of the capacitive energy reserve, located to the left (in the figure) of the charging switch 30. The current flow is represented by a connected dashed line. The intensity of this current is limited due to the low capacitance of buffer capacitor 2. Sequencer 8 monitors the voltage across the buffer capacitor.The charging of said buffer capacitor is complete when this voltage reaches the voltage imposed by the power supply 102, that is to say here 32V.

[0069] At this point, a discharge stage begins for buffer capacitor 2 through the series of reserve capacitors, as illustrated in Figure 3. To initiate this stage, as soon as the voltage across buffer capacitor 2 reaches 32V, sequencer 8 triggers the opening of the buffer capacitor's charging switch 20 and the closing of the charging switch 30 of the first reserve capacitor. The current generated during this discharge stage of the buffer capacitor is shown in the figure as a dashed line. The charges accumulated in buffer capacitor 2 discharge to the first reserve capacitor 3, as long as the voltage across buffer capacitor 2 is greater than the voltage across the first reserve capacitor 3.When these voltages balance, to prevent the charges transferred to the reserve capacitor 3 from flowing in the opposite direction, the sequencer 8 opens the charging switch 30, ending the discharge phase of the buffer capacitor 2. As the indirect charging phase of the reserve capacitors progresses, the reserve capacitor 3 fills, and the voltage difference between the terminals of the buffer capacitor 2 and those of the first reserve capacitor 3 at the beginning of the cycle decreases. The discharge step of the buffer capacitor 2 into the first reserve capacitor 3 thus becomes increasingly shorter and less efficient. As the voltage difference decreases with the progress of the process, a point is reached where the voltage across the buffer capacitor 2 at the end of the charging step does not exceed the voltage across the reserve capacitor 3, making any discharge into this capacitor impossible.

[0070] The buffer capacitor 2 can then no longer be used to charge the succession of reserve capacitors, and the initial charging process continues with the direct charging phase, in which the reserve capacitors are directly connected to the power supply 102. To this end, the sequencer 8 commands the closing of the charge switch 20 of the buffer capacitor and the charge switches 30, 40, 50 and 60 of all the reserve capacitors.

[0071] Since the reserve capacitor series is already partially charged, the current surge generated during the forward charging phase is lower compared to that which would be generated without a prior indirect charging phase. However, to further limit this current surge, the indirect charging phase is preferably optimized as follows. Furthermore, the presence of the current limiter 10 ensures that the current flowing through the capacitive energy reserve remains limited.

[0072] During the charging stages of buffer capacitor 2, the charging switches 40, 50, and 60 of all the reserve capacitors are closed, with the exception of the charging switch 30 of the first reserve capacitor, which is open. The charges accumulated in the succession of reserve capacitors during the previous charge / discharge cycles of the buffer capacitor are then distributed equally among all the reserve capacitors. This limits the amount of charge present in the first capacitor 3 and consequently maintains, for a certain number of cycles, a voltage difference between the buffer capacitor and the first reserve capacitor (a difference measured at the end of the buffer capacitor charging stage) sufficient to allow the charges accumulated in the buffer capacitor during the charging stage to be discharged, at least partially, to the first reserve capacitor.

[0073] During the indirect charging phase, at the end of each charge / discharge cycle of the buffer capacitor, the voltage V3 across the first reserve capacitor 3 is measured and compared to the supply voltage Vaiim (here, 32V). If the charge ratio Vs / Vaiim of the first reserve capacitor at the end of the cycle, which also corresponds to the ratio V3 / V2 at the end of the charging stage of the following cycle (where V2 represents the voltage across buffer capacitor 2), is greater than or equal to a predetermined threshold value, for example, 80%, it is estimated that the indirect charging will no longer be sufficiently efficient in the next cycle, and the process continues with the direct charging phase. Therefore, if at the end of a cycle Vs / Vaiim has exceeded 80%, the sequencer 8 closes switches 20, 30, 40, 50, and 60 so that all the reserve capacitors are connected to the supply 102 and charge directly.

[0074] When the voltage measured across each of the reserve capacitors 3 to 6 reaches 32V, the initial charging process of the capacitive energy reserve is complete; the reserve is now operational, and the sequencer 8 commands the opening of the output switch 70 so that the stored energy can be delivered to the equipment's voltage bus 104 in the event of a micro-interruption in the equipment's power supply voltage. The charging switches for the reserve capacitors and the buffer capacitor remain closed.

Claims

DEMANDS 1. Capacitive energy reserve (108) for on-board equipment (100), said capacitive energy reserve comprising: - an input terminal (1081) for connecting the capacitive energy reserve to a power supply (102) of the on-board equipment, - an output terminal (1082) for connecting the capacitive energy reserve to a voltage bus (104) of the on-board equipment, - a series of capacitors, called reserve capacitors, connected in parallel and each having a capacitance of less than 25 OOPoF, the series of reserve capacitors comprising a first reserve capacitor (3), a last reserve capacitor (6) and optionally one or more intermediate reserve capacitors (4, 5), - a switch (70), called the output switch, located between the last reserve capacitor (6) and the output terminal (1082), - a charge management circuit (110) between the input terminal (1081) and the first reserve capacitor (3), characterized in that: - The load management circuit (110) includes a capacitor (2), called the buffer capacitor, of lower capacitance than the reserve capacitors (3-6), said buffer capacitor being connected, on the one hand, to the input terminal (1081), and on the other hand, to an input of the series of reserve capacitors (3-6), - The load management circuit (110) includes a switch (20), called the buffer capacitor charging switch, located between the input terminal (1081) of the equipment and the buffer capacitor (2) and allowing the buffer capacitor (2) to be connected / disconnected from the power supply (102) of the equipment when the input terminal is connected to said power supply, - the capacitive energy reserve includes, for each of the reserve capacitors (3, 4, 5, 6), a load switch (30, 40, 50, 60) for said reserve capacitor, located upstream of the reserve capacitor and allowing said reserve capacitor to be connected / disconnected with the preceding reserve capacitor and / or the buffer capacitor, - The charge management circuit (110) includes a sequencer (8), configured to measure the voltage across the buffer capacitor (2) and across each of the reserve capacitors (3-6), and to, upon power-up of the equipment (100), control the various switches (20, 30, 40, 50, 60, 70) of the capacitive energy reserve according to an initial charging process during which the output switch (70) remains open, said initial charging process comprising a succession of charge / discharge cycles of the buffer capacitor (2), each of said cycles comprising: -- a charging stage of the buffer capacitor (2) in which the charging switch (20) of the buffer capacitor is closed and the charging switch (30) of the first reserve capacitor is open, the charge management circuit being thereby isolated from the succession of reserve capacitors while the buffer capacitor is energized, -- a discharge step of the buffer capacitor (2) in the succession of reserve capacitors (3-6), in which the charging switch (20) of the buffer capacitor is open and the charging switch (30) of the first reserve capacitor is closed, - when the voltage (V3) across the first reserve capacitor equals the voltage (V2) across the buffer capacitor, the succession of reserve capacitors is disconnected from the charge management circuit (110) by opening the charge switch (30) of the first reserve capacitor, which ends said charge / discharge cycle of the buffer capacitor.

2. Capacitive energy reserve according to claim 1, characterized in that the charge management circuit (110) includes a current limiter (10) connected to the input terminal (1081), which current limiter is configured to impose a predetermined limited current value on its output.

3. Capacitive energy reserve according to claim 1 or 2, characterized in that the sequencer (8) is configured to, during each charging step of the buffer capacitor (2), keep the charging switches (40, 50, 60) of all the reserve capacitors closed except for the charge switch (30) of the first reserve capacitor, for the purpose of balancing the charges between the reserve capacitors (3-6).

4. Capacitive energy reserve according to any one of claims 1 to 3, characterized in that the initial charging process comprises: - an indirect charging phase using the buffer capacitor, which indirect charging phase includes the charge / discharge cycles of the buffer capacitor, - and a direct charging phase, in which the charge switch (20) of the buffer capacitor and the charge switches (30, 40, 50, 60) of all the reserve capacitors are closed.

5. Capacitive energy reserve according to claim 4, characterized in that the sequencer (8) is configured to: - at the end of each charge / discharge cycle of the buffer capacitor, determine a charge rate of the first reserve capacitor (3), defined as the ratio (Vs / Vaiim) between the voltage (V3) across the terminals of the first reserve capacitor and the voltage (Vaiim) of the equipment's power supply, - and switch from the indirect charging phase to the direct charging phase if the charge rate of the first capacitor (Vs / Vaiim) is greater than a predetermined threshold value or start a new charge / discharge cycle of the buffer capacitor otherwise.

6. Capacitive energy reserve according to claim 4, characterized in that the sequencer (8) is configured to switch from the indirect charging phase to the direct charging phase after a predetermined number of charge / discharge cycles of the buffer capacitor.

7. Capacitive energy reserve according to claim 2, characterized in that the charge management circuit includes a protection filter (12) arranged between the current limiter (10) and the buffer capacitor (2).

8. Capacitive energy reserve according to any one of claims 1 to 7, characterized in that it comprises an ideal diode (14) between the output switch (70) and the output terminal (1082).

9. Capacitive energy reserve according to any one of claims 1 to 8, characterized in that the succession of reserve capacitors comprises four reserve capacitors (3, 4, 5, 6) each having a capacitance of the order of 10 OOOpF, and in that the buffer capacitor (2) has a capacitance of the order of 2 200pF.

10. On-board equipment (100) comprising a voltage bus (104) and a power supply (102), the voltage bus being connected to the power supply by a power supply circuit (106), characterized in that it comprises a capacitive energy reserve (108) according to any one of claims 1 to 9, arranged in parallel with said power supply circuit, the input terminal (1081) of the capacitive energy reserve being connected to the power supply (102) of the on-board equipment and the output terminal (1082) of the capacitive energy reserve being connected to the voltage bus (104) of the on-board equipment.

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