Method for testing a PCB through the use of augmented reality, related algorithm and augmented reality application

Abstract

Method for testing a printed circuit board or PCB (3) through the use of augmented reality. The method comprises the following consecutive steps: extracting schematic data of said printed circuit board or PCB (3), comprising components (U) and signals (S) of said printed circuit board or PCB (3), from a first data file (Fl) relating to said printed circuit board or PCB (3); extracting physical and topological data of said printed circuit board or PCB (3), concerning components (U) and traces or tracks (T) of said printed circuit board or PCB (3), from a second data file (F2) relating to said printed circuit board or PCB (3); correlating said signals (S) and said components (U), extracted from said first file (Fl), with the physical traces or tracks (T) and components (U) of said printed circuit board or PCB (3), extracted from said second file ( F2 ); saving to a database (D) the data obtained from the previous steps of the present method, said database (D) being adapted to be used by an augmented reality application (A), said augmented reality application (A) being adapted to control a suitable digital visor or digital glasses (G); executing said augmented reality application (A), thus transmitting data to said digital visor or glasses (G) and allowing a test operator (0), who is wearing said digital visor of glasses (G), to view in augmented reality, over said printed circuit board or PCB (3), the trace or track (T) to be tested.

Description

[0001] TITLE : METHOD FOR TESTING A RGB THROUGH THE USE OF AUGMENTED REALITY, RELATED ALGORITHM AND AUGMENTED REALITY APPLICATION .

[0002] The present invention relates to a method for testing electronic boards , printed circuit boards , or RGBs , through the use of augmented reality .

[0003] The present invention also relates to an algorithm implemented by means of a computer for testing electronic boards , printed circuit boards , or RGBs , through the use of augmented reality .

[0004] The present invention further concerns an augmented reality application adapted to allow a test operator wearing a digital visor or digital glasses to view in augmented reality, over said printed circuit board or PCB, a trace or track to be tested .

[0005] - PRIOR ART -

[0006] It is known that the component density of modern printed circuit boards is constantly growing . The SMD ( Surface Mounted Device ) components in use comprise , in turn, a plurality of pins that are very close to each other . Test operators , entrusted with testing electronic devices , i . e . SMD components and the printed circuits boards on which they are mounted, often find it di f ficult to correctly identi fy the traces or tracks to be tested and the correct pins where measurements have to be taken . Tests on printed circuit boards become even more complex when it is necessary to keep in mind the positions of multiple signals at the same time , which is often the case , resulting in wasted time and less ef ficiency of the test operator, with the risk that the test operator might perform the test on the wrong signals .

[0007] As is well known to those skilled in the art , a printed circuit board ( PCB ) is a complex set of electric and electronic components mutually connected by traces or tracks of conductive material and connected to the outside world through sensors and connectors of various types . Designing a printed circuit board or PCB is a complex task that requires some experience , since the designer has to take into account a number of factors . The designer starts from a schematic file , which shows all components and their interconnections , but in which no indication is given as to the physical and topological parameters and data of the printed circuit board or PCB . As a matter of fact , there is no indication about the positions of the components or the interconnections which will become the traces or tracks of the printed circuit board or PCB that will conduct the signals to be tested . Thus , as is well known, the designer must separate the analogue parts from the digital ones to prevent electromagnetic noise from adversely af fecting analogue measurements , which are very sensitive to noise . The designer must also ensure proper tolerance between the various tracks and components to avoid any short circuits or the creation of any parasitic components , in particular parasitic capacitance and inductance , and / or any interference between the signals , in particular cross-talk . Furthermore , the designer must guarantee a sharp separation between low-voltage lines and high-voltage lines , in addition to including elements that can quickly supply power during high-activity periods , such as , for example , bulk and decoupl ing capacitors . Last but not least , the designer is increasingly asked to minimi ze the PCB area to reduce production costs and improve the portability of the final product .

[0008] All such ef forts that the designer is required to make when designing a printed circuit board or PCB result in a data file in Gerber format , which is a standardi zed format dedicated to PCB description, or in files in other standardi zed formats , hereafter generally referred to as proj ect files , having di f ferent characteristics that depend on the computer-aided design ( CAD) program in use .

[0009] Those skilled in the art also know that Gerber files and proj ect files contain a large amount of information, such as track dimensions , track type , writings to be applied onto the PCB surface , ground plane distribution, and so forth .

[0010] Furthermore , those skilled in the art also know that , in addition to the Gerber file and the proj ect files , a number of placement files are also generated when designing a printed circuit board or PCB, which files are generally available to final users and show where each component is placed within the printed circuit board or PCB, wherein a name is typically associated with each component to identi fy its function . Such placement files are known as silkscreen, and are normally freely accessible to third parties . Such files are however distinct and di f ferent from the placement fi les used by PCB manufacturing machines to pick up and position the devices on the printed circuit board or PCB . This latter file type is called CPL ( Component Placement List ) . This latter file type is typically not made accessible to third parties for obvious reasons related to the production and manufacturing of printed circuit boards or PCBs .

[0011] Technologies are known which make it possible to analyze the data contained in Gerber files to drive devices, e.g. as shown in document KR101008585B1. Furthermore, patent application US20200386807A1 discloses a technology for identifying the components of a printed circuit board or PCB starting from an image of the printed circuit board or PCB.

[0012] It is also well known that every company that manufactures printed circuit boards or electronic components fabricates printed circuit boards or PCBs by using proprietary project files protected by duty of confidentiality, which are not therefore freely accessible to third parties, who may want to analyze such project files in more detail. In fact, although the files of said printed circuit board or PCBs are in standardized formats, which depend on the CAD programs employed, they are nonetheless kept secret, for obvious reasons, by the owning company .

[0013] Technologies are also known which exploit the data contained in such project files, which are proprietary and not accessible to the public, e.g. as disclosed in documents: US11042981B2, EP3891519A1.

[0014] It is also known, in general, that augmented reality is a technology that adds virtual objects to the real world through the use of dedicated visors.

[0015] In a working environment, for example, designers can view the parts that they are designing on their PC with their real dimensions and can observe the prototype from different angles in a natural and realistic manner. This technology is also used for remote assistance purposes, so that an operator can indicate to a user, in real time, the steps to be taken in order to carry out a given operation.

[0016] An implementation solution is known wherein the characteristics of a printed circuit board or PCB can be viewed in augmented reality. Such a solution lacks, however, a part where the data of a printed circuit board or PCB to be tested are automatically analyzed.

[0017] In the field of PCB tests and measurements, several technologies are known which exploit augmented reality, as described, for example, in the following publications: US11650225B2; R. D. Bauer, S. S. Agati, M. da Silva Hounsell and A. T. da Silva, "Manual PCB assembly using Augmented Reality towards Total Quality," 2020 22nd Symposium on Virtual and Augmented Reality (SVR) , Porto de Galinhas, Brazil, 2020, pp . 189-198, doi: 10.1109 / SVR51698 .2020.00040; J. M. Run j i and C. -Y . Lin, "Automatic Optical Inspection aided Augmented Reality-based PCBA Inspection: A Development," 2019 IEEE Jordan International Joint Conference on Electrical Engineering and Information Technology (JEEIT) , Amman, Jordan, 2019, pp. 667-671, doi 10.1109 / JEEIT .2019.8717385.

[0018] Those skilled in the art also know that testing printed circuit boards and their components is a crucial phase during the development of a new product. Whether the item to be tested is a microcontroller with its test PCB or a printed circuit board intended for mass production, it is important that all design specifications are met, and that no systematical problems arise in the making of the final printed circuit board. Tests on printed circuit boards require manual measurements, especially in delicate situations and for investigation purposes . Manual tests are largely used by companies operating in this field .

[0019] Skilled test operators manually position probes connected to measurement instruments in order to analyze the behaviour of the printed circuit board and identi fy any problems . It is apparent that , in order to save time and minimi ze the probability of error, much experience is needed when the test operator has to test two or more signals at the same time .

[0020] A solution is known which tries to solve the technical problem of facilitating the taking of manual measurements on printed circuit boards , wherein a PC webcam i s used in order to show the tracks on the PC screen . Although this may help the test operator, such a solution still requires the test operator to have a certain ability .

[0021] Another known technology is based on a proj ector placed over the printed circuit board to highlight the tracks of interest with a light streak . The drawback of using a proj ector lies in the fact that it is not portable and requires a dedicated work area, in addition to needing the use of many expensive sensors distributed in the structure . Moreover, the proj ector solution requires the use of a high-resolution proj ector and a dedicated PC . Furthermore , such technology only permits displaying manually preset data, since no automatic analysis of the files that define the printed circuit board is provided . As a matter of fact , simple buttons are used to turn on / of f programmer-predefined parts on a single printed circuit board . As is known, manual signal assignment is prone to errors and requires many labour hours . This translates into higher costs incurred by the company and a longer time-to- market of new devices .

[0022] - OBJECT0E THEINVENTION -

[0023] The obj ect of the present invention is a method based on augmented reality, adapted for examining, preferably in an automatic manner, files concerning printed circuit boards , e . g . schematic files and topological files , such as , for example , proj ect files or placement files , in order to identi fy relevant signals and viewing them, in particular by means of digital visors or glasses .

[0024] One aspect of the present invention relates to a method for testing a printed circuit board or FOB having the features set out in the appended claim 1 .

[0025] The present invention also relates to an algorithm based on augmented reality, which assists test operators in finding signals on printed circuit boards or PCBs by automatically analyzing the files of the printed circuit boards in order to identi fy relevant signals and di splaying them as required by the user .

[0026] A further aspect of the present invention relates to an algorithm, implemented on a computer, for testing printed circuit boards or PCBs , having the features set out in claim 12 .

[0027] The present invention further concerns an augmented reality application allowing a test operator wearing a digital visor or digital glasses to view in augmented reality, over said printed circuit board or PCB, a trace or track to be tested .

[0028] Yet another aspect of the present invention concerns an augmented reality application for testing printed circuit boards or PCBs , having the features set out in claim 14 .

[0029] The features of the method, algorithm and application according to the present invention will be described in detail below with reference to the following non-limiting and merely explanatory embodiments and implementations and to the accompanying drawings , wherein :

[0030] Figure 1 shows , by way of non-limiting example , a printed circuit board or PCB comprising a plurality of components and traces or tracks whereto the method of the present invention can be applied;

[0031] Figures 2A, 2B, 2C and 2D are graphic representations o f first files concerning di f ferent circuit diagrams of the printed circuit board or PCB of Figure 1 , showing all components and all interconnections between said components , as well as the signals at said interconnections . In particular : Figure 2A shows a first portion of the circuit diagram relating to that part of the circuit which concerns the input connectors provided on the printed circuit board or PCB shown in Figure 1 ; Figure 2B shows a second portion of the circuit diagram relating to the integrated circuits performing the functions of the printed circuit board or PCB shown in Figure 1 ; Figure 2C shows a third portion of the circuit diagram relating to the test connectors provided on the printed circuit board or PCB shown in Figure 1 ; Figure 2D shows a fourth portion of the circuit diagram relating to the power supply for the LED devices and the power circuits provided on the printed circuit board or PCB shown in Figure 1 ;

[0032] Figure 3 is a graphic representation of a second file relating to the placement o f the various components , showing the physical and topological data of the components provided on the printed circuit board or PCB shown in Figure 1 ;

[0033] Figure 4 shows , by way of example , a schematic image showing how a test operator may visuali ze over the printed circuit board or PCB of Figure 1 , through a digital visor or digital glasses , by executing the method according to the present invention .

[0034] - DETAILED DESCRIPTION OF THE INVENTION -

[0035] With reference to the above-listed figures , the method according to the present invention is a method for testing a printed circuit board or PCB 3 through the use of augmented reality .

[0036] For the purposes of the present description, reference numeral 3 refers to the printed circuit board or PCB as a whole and as such .

[0037] Said printed circuit board or PCB 3 comprises one or more components "U" , one or more traces or tracks "T" , and one or more signals "S" .

[0038] The method for testing a printed circuit board or PCB 3 comprises the following steps , preferably executed in succession : extracting schematic data of said printed circuit board or PCB 3 from a first data file " Fl" relating to said printed circuit board or PCB 3 , wherein said schematic data comprise components "U" and signals "S" of said printed circuit board or PCB 3 ; extracting physical and topological data of said printed circuit board or PCB 3 from a second data f ile " F2" relating to said printed circuit board or PCB 3 , wherein said physical or topological data concern said components U" , and preferably also said traces or tracks "T" , of said printed circuit board or PCB 3 ; correlating said data concerning said signals "S" and said components "U" , extracted from said first file " Fl", with said data concerning said components "U" , and preferably also said traces or tracks "T" , extracted from said second file " F2" ; saving to a database "D" said data obtained from the previous steps of the present method; the data contained in said database "D" being adapted to be used by an augmented reality application "A" ; said augmented reality application "A" being adapted to control a suitable digital visor or digital glasses "G" ; executing said augmented reality application "A" ; said augmented reality application "A" transmitting data to said digital visor or glasses "G" , thus allowing a test operator "0" , while wearing said digital visor or glasses "G" , to view in augmented reality, over said printed circuit board or PCB 3 , trace or track "T" to be tested .

[0039] The present invention assists test operators "0" in finding signals " S" and traces or tracks "T" on the printed circuit board or PCB 3 to be tested .

[0040] The method according to the present invention allows extracting both schematic data, e . g . schematic parameters , which comprise components "U" and signals "S" on printed circuit board or PCB 3 , and physical and topological data, e . g . physical and topological parameters of said printed circuit board or PCB 3 , relating to components "U" , and preferably also to said traces or tracks "T" , that are present on printed circuit board or PCB 3 . Therefore , said schematic data of printed circuit board or PCB 3 comprise said components "U" and said signals "S" of said printed circuit board or PCB 3 , and such data vary from board to board; whereas the physical and topological data of said printed circuit board or PCB 3 concern said components "U" , and preferably also said traces or tracks "T" , of said printed circuit board or PCB 3 , and such data vary from board to board .

[0041] For the purposes of the present description, the term test refers to one or more of : tests carried out during the prototyping phase ; tests for validating electronic products , or tests conducted on printed circuit boards or PCBs and microcontrollers . For example , a test may be a debugging procedure and / or a process of validating printed circuit boards or PCBs 3 .

[0042] For the purposes of the present description, term component "U" refers to any electronic, electrical and / or mechanical component or device which is present on a printed circuit board or PCB 3 , and which is also included in both said first file " Fl" and said second file " F2" concerning a printed circuit board or PCB 3 .

[0043] For the purposes of the present description, traces or tracks "T" refer to physical traces or tracks formed from copper or another conductive material on one or more layers or faces of printed circuit board or PCB 3 , as well as to the connectors and / or pins of a component "U" which are connected to an associated physical trace or track; said traces or tracks "T" being adapted to connect components "U" , in particular the connectors and / or pins of said components "U" , to each other and to conduct said signals "S" . For the purposes of the present description, the term signal "S" refers to an electrical or electronic signal , whether digital or analogue , which is conducted on traces or tracks "T" , wherein said signal "S" may be generated, received and / or transmitted by, or through, a component "U" .

[0044] The present invention simpli fies the operations necessary for testing printed circuit boards or PCBs 3 , facilitating both the test part carried out by the test operator "0" and the preparation part necessary for the execution of tests on said printed circuit board or PCB 3 , so that they are easily applicable to any printed circuit boards or PCBs 3 for which a file containing schematic data and a file containing physical and topological data are available .

[0045] Preferably, said augmented reality application "A" makes it possible to view in augmented reality, over said printed circuit board or PCB 3 , trace or track "T" to be tested, by highlighting it , contouring it , and / or indicating it in a colour other than the colour of printed circuit board or PCB 3 , so that it can be easily and precisely identi fied by a test operator "0" , e . g . with luminous and / or text indications superimposed on printed circuit board or PCB 3 and on components "U" of interest .

[0046] This solution allows test operator "0" to immediately locate trace or track "T" to be tested, and hence components "U" involved in the test , e . g . in order to determine signal "S" to be tested .

[0047] In one possible , but merely illustrative and nonlimiting, embodiment of the method according to the present invention, said step of executing said augmented reality application "A" requires that said augmented reality application "A" is adapted to allow a test operator "0" , while wearing said digital visor or glasses "G" , to view in augmented reality signal "S" that is present on said trace or track "T" to be tested, e . g . on a floating display visible through said digital visor or glasses "G" .

[0048] The present embodiment permits , for example , viewing in augmented reality signal "S" that test operator "0" is currently measuring on trace or track "T" , and / or s ignal "S" that should theoretically be found on trace or track "T" to be tested . This solution reduces the time necessary for conducting tests on printed circuit board or PCB 3 .

[0049] In a preferred embodiment of the method according to the present invention, said first file " Fl" , used during the step of extracting the schematic data of printed circuit board or PCB 3 , is a circuit diagram describing all components "U" , all interconnections between said components "U" , and, preferably, signals "S" that are present at said interconnections .

[0050] The present embodiment makes it possible to analyze the circuit diagram of printed circuit board or PCB 3 . In fact, as previously mentioned herein, prior to the fabrication of printed circuit board or PCB 3 , the electrical and / or electronic circuit is designed as a circuit diagram showing all components and their interconnections . No topological information is available on this circuit diagram, since all connections are j ust ideal . In general , said circuit diagram is a freely accessible file .

[0051] Generally, said first file " Fl" , in the form of a circuit diagram, is saved in PDF format . In a preferred embodiment of the method according to the present invention, said step of extracting schematic data of printed circuit board or PCB 3 comprises a sub-step of extracting a name of each component "U" and of each interconnection or connection between said components "U" .

[0052] Through said sub-step, the method according to the present invention extracts the names of components "U" and of their interconnections or connections . The present solution also identi fies signals "S" that are present at the interconnections or connections between various components "U" included in printed circuit board or PCB 3 .

[0053] In a preferred embodiment of the method according to the present invention, said sub-step of extracting a name of each component "U" and of each interconnection or connection between said components "U" is carried out by means of a machine learning algorithm . Since said first file " Fl" is generally saved in PDF format , the sub-step of extracting a name of each component "U" and of each interconnection or connection between said components "U" can, in fact , be conducted by means of a machine learning algorithm adapted to analyze said first file "Fl" as a whole , e . g . identi fying components "U" from their outlines and extracting the names thereof , and identi fying various signals "S" outputted by a component "U" and extracting the names of said signals "S" , and so forth .

[0054] The present solution makes it possible to automate the method according to the present invention . Moreover, the present solution provides the automatic execution of the step of extracting schematic data of said printed circuit board or PCB 3 from a first file " Fl" . In one possible embodiment of the method according to the present invention, said second file "F2", which is used in the step of extracting physical and topological data of said printed circuit board or PCB 3, is a Gerber file and / or a project file.

[0055] In the present embodiment of the method, once components "U" and signals "S" of said printed circuit board or PCB 3 have been extracted, the method starts analyzing said second file "F2" comprising physical and topological data. Said second file "F2" is, for example, a PCB project file. This file type contains the physical description of the circuit, with an accurate topological description of the same. The use of a Gerber file and / or of project files permits, during the step of extracting physical and topological data of said printed circuit board or PCB 3 from a second file "F2", extracting the physical and topological data relating to said components "U and said traces or tracks "T" of said printed circuit board or PCB 3.

[0056] The present solution makes it possible to automate the step of extracting physical and topological data of said printed circuit board or PCB 3 from a second file "F2", e.g. by means of a suitable algorithm capable of operating on such standardized file type.

[0057] The use of such file types also makes it possible to work on printed circuit boards or PCBs 3 comprising two or more layers. Various traces or tracks "T" that are present on each layer of the printed circuit board or PCB 3 are made from copper or another conductive material which can conduct signals "S" indicated in the first file "Fl", i.e. the circuit diagram. As is known, proj ect files also include the names of each trace or track "T" and their signals "S" , which normally correspond to the names contained in the schematic first file " Fl" . In case of mismatching, the method according to the present invention comprises , during the step of correlating said data, a sub-step of associating each trace or track "T" with the respective signal "S" , such sub-step being conducted, for example , by the test operator "0" by manually entering the data . During this sub-step, any missing data will be entered by the user, e . g . a test operator "0" , who will correct any ambiguity in signals "S" and / or in traces or tracks "T" that cannot be reconstructed by means of the steps of the method according to the present invention .

[0058] In an alternative embodiment of the method according to the present invention, said second file " F2" , used during the step o f extracting physical and topological data of said the printed circuit board or PCB 3 , is a placement file concerning components "U" . In the present embodiment , said placement file concerning components "U" contains no information about traces or tracks "T" that carry signals "S" .

[0059] In the present embodiment of the method, the placement files concerning components "U" can be used for implementing the method according to the present invention as an alternative to Gerber files and / or proj ect files , which might not be available to the final user, e . g . the test operator . Placement files contain no information about traces or tracks "T" that carry signal "S" , but through said schematic first file " Fl" it is possible to go back to the various connections between components "U" and identi fy said traces or tracks "T" on printed circuit board or PCB

[0060] 3 .

[0061] In that embodiment of the method according to the present invention in which said second file " F2" is a placement file concerning components "U" , said step of correlating, or said step of extracting physical and topological data of said printed circuit board or PCB 3 from a second file " F2" , comprises a sub-step of extrapolating the physical and topological data of said printed circuit board or PCB 3 , relating to said traces or tracks "T" . Said sub-step of extrapolating may be carried out through a dedicated algorithm, e . g . a machine learning algorithm . Preferably, said sub-step uses the data contained in said first file " Fl" to extrapolate the physical and topological data of said traces or tracks "T" .

[0062] In that embodiment of the method according to the present invention in which said second file " F2" is a placement file concerning components "U" , said step of extracting physical and topological data of said printed circuit board or PCB 3 may optionally comprise the following sub-steps : acquiring said second file " F2" concerning the placement of components "U" , wherein at least one image of the printed circuit board or PCB 3 is acquired by means of an image acquisition device , e . g . a webcam, a smartphone , or said digital visor or glasses "G" suitably equipped with a camera ;

[0063] - defining the placement of said components "U" and said signals "S" comprised in said printed circuit board or PCB " 3" for extracting said physical and topological data . Preferably, said sub-steps are carried out prior to executing the step of extracting physical and topological data of said printed circuit board or PCB 3 .

[0064] The present embodiment of the method allows acquiring images in which, in addition to locating the components "U", it is also possible to obtain physical and topological data about said traces or tracks "T" , or at least about some of them .

[0065] The sub-step of defining the pos itions of components "U" may be carried out either manually, by entering the data, or automatically, e . g . by means of a dedicated algorithm .

[0066] In a preferred embodiment of the method according to the present invention, said step of correlating said data is intended to create further data in which said schematic data and said physical and topological data are mutually coupled and associated .

[0067] In a preferred embodiment of the method according to the present invention, said database "D" is , for example , a non-volatile memory in a local or remote PC, or in a local or remote server , or in a smartphone , or in said digital visor or glasses "G" , e . g . connected to a network .

[0068] In a preferred embodiment of the method, the step of saving said data to a database "D" is followed by a decision-making step of executing the test on a printed circuit board or PCB . I f the decision made during such decision-making step is "Yes" , then the step of executing said augmented reality application "A" will be executed . Conversely, i f the decision made during such decisionmaking step is "No" , then the method will return to the step of extracting schematic data of said printed circuit board or PCB 3 from a first file "Fl", in particular in order to execute it on a new and different printed circuit board or PCB 3.

[0069] The present embodiment comprising said decision-making step allows saving to said database "D" a plurality of data relating to different printed circuit boards or PCBs 3, thus creating a data bank that can then be utilized by said augmented reality application "A", so that said test operator "0" will be able to test different printed circuit boards or PCBs 3, e.g. in succession.

[0070] In general, said augmented reality application "A" is adapted to control a suitable digital visor or digital glasses "G", the latter being a wearable device for better portability. Said digital visor or glasses "G" are preferably adapted to support files, e.g. OPENXR files, written in standard multi-platform formats for virtual and / or augmented reality creation, e.g. UNITY.

[0071] In a preferred embodiment of the method according to the present invention, between said step of saving to a database "D" and the step of executing said augmented reality application "A", or as a part of said step of executing said augmented reality application "A", there is a step of identifying a printed circuit board or PCB 3 being framed by test operator "0" by means of the digital visor or glasses "G".

[0072] In a preferred embodiment of the method according to the present invention, comprising the step of identifying a printed circuit board or PCB 3 being framed by test operator "0", the data extracted during the step of extracting physical and topological data of said printed circuit board or PCB 3 from a second file " F2" also include an identi fier of said printed circuit board or PCB 3 .

[0073] Preferably, said step of identi fying a printed circuit board or PCB 3 is designed in a manner such that said augmented reality application "A" will draw printed circuit board or PCB 3 being framed by the test operator "0" wearing said digital visor or glasses "G" . Said identi fication data of said printed circuit board or PCB 3 consist of , for example , visual references , such as QR codes on the PCB , a video recognition of printed circuit board or PCB 3 , or a definition of the geometrical boundaries of the physical board or PCB, e . g . performed by test operator "0" . In one possible embodiment of the method according to the present invention, said identi fication data of said printed circuit board or PCB 3 are obtained automatically from said second file " F2" , also when placement files are used .

[0074] In a preferred, but merely illustrative and nonlimiting, embodiment of the method according to the present invention, said step of identi fying a printed circuit board or PCB 3 comprises a sub-step of loading the data comprised in said database "D" and concerning identi fied printed circuit board or PCB 3 , so that such data can be used by said augmented reality application "A" . Said sub-step is , for example , incorporated into said augmented reality application "A" . Once printed circuit board or PCB 3 has been identi fied, augmented reality application "A" will retrieve all the data about said printed circuit board or PCB 3 from said database "D" .

[0075] In a preferred embodiment of the method according to the present invention, said step of identi fying a printed circuit board or PCB 3 includes an additional alignment sub-step, wherein the augmented reality application "A" will comprehend the arrangement and orientation and / or alignment of printed circuit board or PCB 3 relative to test operator "0" who is viewing printed circuit board or PCB 3 to be tested through said digital visor or glasses "G" , and will display in augmented reality, over said printed circuit board or PCB 3 , trace or track "T" to be tested in compliance with the orientation and / or alignment of printed circuit board or PCB 3 relative to test operator "0" .

[0076] Preferably, said augmented reality application "A" is so designed that , once printed circuit board or PCB 3 has been identi fied and its arrangement and orientation have been determined, said test operator "0" will be shown a menu for selecting signals "S" of interest , which will then be highlighted on printed circuit board or PCB 3 .

[0077] In a preferred embodiment of the method according to the present invention, said augmented reality application "A" is adapted to show to test operator "0" a circuit diagram defining said first file " Fl" of printed circuit board or PCB 3 , e . g . on a floating display visible through said digital visor or glasses "G" . This solution allows test operator "0" to obtain immediate information about the circuits on printed circuit board or PCB 3 being tested, thus speeding up the execution of the test operations on said printed circuit board or PCB 3 .

[0078] In a preferred embodiment of the method according to the present invention, said augmented reality application "A" is adapted to allow test operator "0" to select one or more points on the circuit diagram of printed circuit board or PCB 3, and such one or more selected points will be displayed over, e.g. superimposed on, printed circuit board or PCB 3. This solution speeds up the execution of the test procedure on a point of interest, and makes it possible to simultaneously test a plurality of parts of printed circuit board or PCB 3 or a plurality of components "U" and / or signals "S", e.g. correlated with each other, while avoiding the need for test operator "0" to remember multiple signals to be tested.

[0079] Said augmented reality application "A" can be executed by a processing unit, e.g. a microcontroller or a microprocessor, comprised in a computing device, e.g. a computer, a PC, a smartphone, or said digital visor or glasses "G".

[0080] In one possible embodiment, said augmented reality application "A" is executed on a computer or PC that comprises said database "D".

[0081] In an alternative embodiment, said augmented reality application "A" is executed by said digital visor or glasses "G", which comprise a processing unit and a memory unit into which the data comprised in said database "D" can be transferred. In one possible embodiment, said database "D" is comprised in said digital visor or glasses "G".

[0082] With reference to the annexed figures, the following will describe an example of implementation of the method and algorithm.

[0083] Figure 1 shows, by way of non-limiting example, a printed circuit board or PCB 3 comprising a plurality of components "U" and traces or tracks "T" whereto the method according to the present invention can be applied. Printed circuit board or PCB 3 shown in Figure 1 is merely illustrative , but useful to understand the steps of the method according to the present invention . In Figure 1 several types o f components "U" are visible , including connectors of various kinds compliant with di f ferent connection standards , integrated circuits for analyzing electronic signals and controlling the power supplied to said components "U" , as well as discrete components such as resistors , capacitors , LEDs , etc . Figure 1 also shows some traces or tracks "T" connecting components "U" to each other . In Figure 1 there are also some codes identi fying that speci fic printed circuit board or PCB 3 , as well as codes identi fying individual components "U" included in said printed circuit board or PCB 3 .

[0084] With reference to Figure 2A, there is shown a first portion of the circuit diagram, relating to that circuit part which concerns the input connectors available on printed circuit board or PCB 3 shown in Figure 1 . Figure 2A shows a graphic representation of said first file " Fl" relating to a first part of printed circuit board or PCB 3 . In particular, as aforementioned, Figure 2A shows components "U" consisting of connectors . The individual pins of each connector are associated with a signal "S" , i f present , and an identi fier or a name is assigned to each signal "S" and each component "U" .

[0085] Figure 2B shows a second portion of the circuit diagram, which concerns the integrated circuits that perform the functions of printed circuit board or PCB 3 shown in Figure 1 . Figure 2B is a graphic representation of said first file " Fl" relating to a second part o f printed circuit board or PCB 3 . In particular, as aforementioned, Figure 2B shows components "U" consisting of integrated circuits adapted to perform the functions of printed circuit board or PCB 3 . Furthermore , the individual pins of each integrated circuit "U" are associated with a s ignal "S" , i f present , and an identi fier or a name is ass igned to each signal "S" and each component "U" .

[0086] Figure 2C shows a third portion of the circuit diagram, which concerns the test connectors available on printed circuit board or PCB 3 shown in Figure 1 . Figure 2C is a graphic representation of said first fi le " Fl" relating to a third part of printed circuit board or PCB 3 . In particular, as aforementioned, Figure 2C shows test connectors provided on printed circuit board or PCB 3 , wherein the individual pins of each test connector "U" are associated with a signal "S" , i f present , and an identi fier or a name is assigned to each signal "S" and each component "U" .

[0087] Lastly, Figure 2D shows a fourth portion of the circuit diagram, which concerns the power supply for LED devices "U" and the power circuits that are present on printed circuit board or PCB 3 shown in Figure 1 . Figure 2D is a graphic representation of said first fi le " Fl" relating to a fourth part of printed circuit board or PCB 3 . In particular, as aforementioned, Figure 2D shows components "U" consisting of integrated circuits adapted to supply power to LED devices "U" and to power circuits "U" provided on printed circuit board or PCB 3 . Furthermore , the individual pins of each integrated circuit "U" are associated with a signal "S" , i f present , and an identi fier or a name is assigned to each signal "S" and each component "U" . In summary, Figures 2A, 2B, 2C and 2D are graphic representations of said first file " Fl" concerning dif ferent circuit diagrams pertaining to printed circuit board or PCB 3 of Figure 1 , showing all components "U" , all interconnections between said components "U" , and all signals "S" at said interconnections .

[0088] Figure 3 is a graphic representation of a second file " F2" relating to the placement o f components "U" , showing the physical and topological data of components "U" that are present on printed circuit board or PCB 3 shown in Figure 1 .

[0089] Figure 3 shows a second file " F2" relating to the placement of components "U" , wherein said component placement file provides no information about traces or tracks "T" carrying the signals and interconnecting components "U" . In Figure 3 one can also see that an identi fier or a name has been assigned to each component "U" to identi fy it , e . g . indicating where pin number 1 of each integrated circuit is located .

[0090] Another aspect of the present invention relates to an algorithm, implemented by means of a computer, a PC, or a generic device equipped with a memory and a process ing unit, for testing printed circuit boards or PCBs 3 through the use of augmented reality . Said algorithm according to the present invention is adapted to implement the method according to the present invention . Preferably, said algorithm is executed by a single local or remote computer or PC, or a generic device equipped with a memory and a processing unit , e . g . a smartphone or said digital visor or glasses "G" . In one possible embodiment , said computer or PC comprises said database "D" . As an alternative , said generic device is , for example , a mobile device , e . g . a smartphone or a digital visor or digital glasses "G" , comprising a processing unit and a memory unit into which the data contained in said database "D" can be trans ferred .

[0091] In a preferred embodiment of the algorithm according to the present invention, it also comprises the steps of : loading a first file " Fl" into a memory unit accessible to said device equipped with a memory and a processing unit ; loading a second file " F2" into a memory unit accessible to said device equipped with a memory and a processing unit .

[0092] Said steps comprised in the algorithm are executed before the respective steps of extracting .

[0093] Said algorithm is stored in a memory unit accessible to said device equipped with a memory and a process ing unit . For example , said memory unit may be a part of said database "D" or the memory of said device . In one possible embodiment , said database "D" is comprised in said device , e . g . said digital visor or glasses "G" .

[0094] In a preferred embodiment of the algorithm according to the present invention, the steps of extracting are carried out automatically, by automatically extracting the relevant information from said first file " Fl" and from said second file " F2" . Said steps being executed with the aid of a dedicated computer program .

[0095] In a preferred embodiment of the algorithm according to the present invention, said steps of : correlating; saving to a database "D" , and executing said augmented reality application "A" of the method according to the present invention are carried out automatically . Describing now in more detail the implementation of the method and algorithm according to the present invention, Figure 4 shows , by way of non-limiting example , a schematic image of a test operator "0" who is viewing, through a digital visor or digital glasses "G" , a trace or track "T" to be tested on printed circuit board or PCB 3 while executing the method according to the present invention .

[0096] From Figure 4 it can be understood that a test operator "0" can see in augmented reality, through digital visor or glasses "G" , trace or track "T" to be tested, superimposed on printed circuit board or PCB 3 . Said augmented reality image is visible through digital visor or glasses "G" controlled by augmented reality application "A" , the latter being adapted to extract from said database "D" the data about printed circuit board or PCB 3 being viewed by test operator "0" through digital visor or glasses "G" . Preferably, said database "D" is comprised in a device equipped with a memory and a processing unit , e . g . a computer, a PC, a smartphone , or digital visor or glasses "G" , comprising also a processing unit adapted to execute said augmented reality application "A" .

[0097] In this figure one can see that , on printed circuit board or PCB 3 , which comprises a plurality of components "U" , only a single trace or track "T" is visible , which is shown to test operator "0" highlighted in a colour di f ferent from that of printed circuit board or PCB 3 , so that test operator "0" can clearly see it while observing printed circuit board or PCB 3 through digital visor or glasses "G" . The highlighting of the single trace or track "T" to be tested, which is clearly visible to test operator "0" because it is shown in a colour other than that of the printed circuit board or PCB 3 , is apparent from a comparison with Figure 1 .

[0098] Another aspect of the present invention concerns an augmented reality application "A" . More particularly, said augmented reality application "A" is designed for testing printed circuit boards or PCBs 3 .

[0099] Said augmented reality application "A" is adapted to be executed by a processing unit , e . g . a microprocessor comprised in a PC , a computer, or a generic device equipped with a memory and a processing unit , e . g . a smartphone and / or said digital visor or glasses "G" .

[0100] Said augmented reality application "A" is adapted to control said digital visor or glasses "G" .

[0101] Augmented reality application "A" according to the present invention is adapted to execute the following steps , preferably in succession :

[0102] • identi fying said printed circuit board or PCB 3 being framed by said digital visor or glasses "G" being worn by a test operator "0" ;

[0103] • loading data comprised in a database "D" and concerning the identi fied printed circuit board or PCB 3 ;

[0104] • processing the data loaded from said database "D" and transmitting them to said digital visor or glas ses "G" , thus allowing said test operator "0" , who is wearing said digital visor or glasses "G" , to view in augmented reality, over said printed circuit board or PCB 3 , trace or track "T" to be tested .

[0105] In augmented reality application "A" according to the present invention, said database "D" contains the data obtained by executing the method according to the present invention .

[0106] The augmented reality application "A" according to the present invention makes it possible to trans form the data processed by means of the method and algorithm according to the present invention into an augmented reality image .

[0107] The steps of augmented reality application "A" listed above have already been described in the description of the method and algorithm according to the present invention; therefore , all of the above-described details should be considered as comprised also in said augmented reality application "A" and will not be described any further .

[0108] Preferably, said augmented reality application "A" is adapted to show to operator "0" a circuit diagram defining said first file " Fl" of printed circuit board or PCB 3 on a floating display visible through said digital visor or glasses "G" .

[0109] In a preferred, but merely illustrative and nonlimiting, embodiment of augmented reality application "A" according to the present invention, it comprises a graphical interface . Said graphical interface is at least adapted to allow test operator "0" to select a plurality of points on the circuit diagram of printed circuit board or PCB 3 , displaying such points over printed circuit board or PCB 3 .

[0110] Preferably, said graphical interface is designed to be intuitive , e . g . allowing test operator "0" to see further information useful for the test by showing at least one floating display, visible through said digital visor or glasses "G" . Such useful information may include , for example , signal "S" being measured by test operator "0" at that very instant , the theoretical value of that signal "S" , and / or the circuit diagram of that portion of printed circuit board or PCB 3 on which a test has to be carried out . Such useful information can be obtained from : said data stored in said database "D" ; one of said f irst file " Fl" and / or second file " F2" ; and / or measurement devices connected to a network, e . g . oscilloscopes connected to an Internet or Ethernet network .

[0111] More generally, said graphical interface is designed to allow test operator "0" to view also data and information other than the data obtained and processed by the method and algorithm according to the present invention . By way of example , through said graphical interface test operator "0" can display information retrieved from the Internet network, e . g . about a datasheet of one or more components "U" included in printed circuit board or PCB 3 , providing useful additional information to test operator "0" .

[0112] In a preferred, but merely illustrative and nonlimiting, embodiment of augmented reality application "A" according to the present invention, sel f-alignment of the augmented reality images with said printed circuit board or PCB 3 is implemented .

[0113] Said augmented reality application "A" is developed, for example , us ing multi-platform engines for virtual and / or augmented reality creation, such as , for example , UNITY .

[0114] The present invention assists test operators "0" in finding signals "S" and traces or tracks "T" on a printed circuit board or PCB 3 to be tested . Through said method and said algorithm, the present invention makes it possible to extract , preferably automatically, information about the various signal s "S" on a printed circuit board or PCB 3 starting from its files ( Fl , F2 ) , e . g . a circuit diagram and placement files or Gerber files and / or proj ect files . Afterwards , test operator "0" , equipped with a digital visor or digital glasses "G" for augmented reality, will be able to display traces or tracks "T" along with associated signals "S" to be tested, being also allowed to choose which signals "S" and traces or tracks "T" to display . Selected signals "S" and traces or tracks "T" will be highlighted on real printed circuit board or PCB 3 to make them easily identi fiable and to facilitate the execution of the tests , thereby minimi zing the probability of error .

[0115] The present invention makes for increased ef ficiency when testing printed circuit boards or PCBs 3 , which in turn translates into lower costs incurred by the company using such technology and a shorter time-to-market of new devices comprising a printed circuit board or PCB 3 .

[0116] Furthermore , augmented reality application "A" allows test operator "0" to select signals "S" to be tested or veri fied, and to display them over said printed circuit board or PCB 3 , even more than one at a time , e . g . through luminous and / or text indications superimposed on said printed circuit board or PCB 3 and on components "U" comprised in said printed circuit board or PCB 3 .

[0117] According to the present invention, test operator "0" can, by wearing a digital visor or digital glasses "G" and using automatic analysis , move from one laboratory to another, from one bench to another, and from one device to another, thus solving the problems that af fect the prior art . Indeed, the present invention ensures a more dynamic execution of the tests , since operators are not bound to speci fic laboratories and / or test benches .

[0118] The present invention allows a company to avoid having to manually encode every modi fication newly developed for a printed circuit board or PCB 3 , thus considerably reducing the number of required labour hours and reducing the number of errors .

[0119] The method, the algorithm, and augmented reality application "A" according to the present invention can be used for many purposes and / or at various development stages , from prototyping to validation of electronic products , although their main application i s testing printed circuit boards or PCBs 3 , in particular debugging and validation of circuits and test PCBs for microcontrollers and microproces sors , in order to simpli fy the task of test operators "0" .

[0120] Other implementations and embodiments of the present invention, which have not been explicitly described herein, but which can be easily inferred by a person skilled in the art in light o f the contents of the present patent application, should be considered to lie within the protection scope of the present invention .

[0121] REFERENCE NUMERALS :

[0122] Printed circuit board or PCB 3

[0123] Augmented reality application A

[0124] Database D First file Fl

[0125] Second file F2

[0126] Digital visor or glasses G

[0127] Test operator 0 Signals S

[0128] Traces or tracks T

[0129] Components U

[0130] Barzand & Zanardo S.p.A.

Claims

CLAIMS :

1. Method for testing a printed circuit board or PCB (3) through the use of augmented reality; said printed circuit board or PCB (3) comprising one or more components (U) , one or more traces or tracks (T) , and one or more signals (S) ; said method comprising the following steps: extracting schematic data of said printed circuit board or PCB (3) from a first data file (Fl) relating to said printed circuit board or PCB (3) , wherein said schematic data comprise the components (U) and the signals(S) of said printed circuit board or PCB (3) ; extracting physical and topological data of said printed circuit board or PCB (3) from a second data file (F2) relating to said printed circuit board or PCB (3) , wherein said physical or topological data concern said components (U) , and preferably also said traces or tracks(T) , of said printed circuit board or PCB (3) ; correlating said data concerning said signals (S) and said components (U) , extracted from said first file (Fl) , with said data concerning said components (U) , and preferably also said traces or tracks (T) , extracted from said second file (F2) ; saving to a database (D) said data obtained from the previous steps of the present method; the data contained in said database (D) being adapted to be used by an augmented reality application (A) ; said augmented reality application (A) being adapted to control a suitable digital visor or digital glasses (G) ; executing said augmented reality application (A) ; said augmented reality application (A) transmitting data to saiddigital visor or glasses (G) , thus allowing a test operator (0) , while wearing said digital visor or glasses (G) , to view in augmented reality, over said printed circuit board or PCB (3) , the trace or track (T) to be tested.

2. Method according to claim 1, wherein said first file (Fl) , used during the step of extracting the schematic data of the printed circuit board or PCB (3) , is a circuit diagram describing all components (U) , all interconnections between said components (U) , and, preferably, the signals (S) that are present at said interconnections.

3. Method according to claim 1 or 2, wherein said step of extracting the schematic data of the printed circuit board or PCB (3) comprises a sub-step of extracting a name of each component (U) and of each interconnection or connection between said components (U) .

4. Method according to claim 3, wherein said sub-step of extracting a name of each component (U) and of each interconnection or connection between said components (U) is carried out by means of a machine learning algorithm.

5. Method according to claim 1, wherein said second file (F2) , used during the step of extracting the physical and topological data of said the printed circuit board or PCB (3) , is a placement file concerning the components (U) , said placement file concerning the components (U) containing no information about the traces or tracks (T) that carry the signals (S) .

6. Method according to claim 5, wherein said step of correlating, or said step of extracting physical and topological data of said printed circuit board or PCB (3) from a second file (F2) , comprises a sub-step of extrapolating the physical and topological data of saidprinted circuit board or PCB (3) that concern said traces or tracks (T) .

7. Method according to claim 6 or 5, wherein said step of extracting the physical and topological data of said printed circuit board or PCB (3) comprises the following sub-steps :- acquiring said second file (F2) concerning the placement of the components (U) , wherein at least one image of the printed circuit board or PCB (3) is acquired by means of an image acquisition device;- defining the placement of said components (U) and said signals (S) comprised in said printed circuit board or PCB (3) for extracting said physical and topological data.

8. Method according to claim 1, wherein said second file (F2) , used during the step of extracting the physical and topological data of said printed circuit board or PCB (3) , is a project file.

9. Method according to claim 1, wherein between said step of saving to a database (D) and said step of executing said augmented reality application (A) , or as a part of said step of executing said augmented reality application (A) , there is a step of identifying a printed circuit board or PCB (3) being framed by the test operator (0) by means of said digital visor or glasses (G) .

10. Method according to the preceding claims, wherein said augmented reality application (A) is adapted to show to the test operator (0) a circuit diagram defining said first file (Fl) of the printed circuit board or PCB (3) on a floating display visible through said digital visor or glasses (G) .

11. Method according to claim 10, wherein the test operator (0) can select one or more points on the circuit diagram of the printed circuit board or PCB (3) , and such one or more selected points are displayed over the printed circuit board or PCB (3) .

12. Algorithm, implemented by means of a computer, a PC or a generic device equipped with a memory and a processing unit, for testing printed circuit boards or PCBs (3) , which uses augmented reality; said algorithm being adapted to implement the method according to claim 1.

13. Algorithm according to claim 12, wherein the steps of extracting are carried out automatically by automatically extracting all the relevant information from said first file (Fl) and from said second file (F2) .

14. Augmented reality application (A) for testing printed circuit boards or PCBs (3) ; said augmented reality application (A) being adapted to be executed by a processing unit; said augmented reality application (A) being adapted to control a suitable digital visor or digital glasses (G) ; said augmented reality application (A) being adapted to execute the following steps:• identifying said printed circuit board or PCB (3) being framed by said digital visor or glasses (G) being worn by a test operator (0) ;• loading data comprised in a database (D) and concerning the identified printed circuit board or PCB (3) ;• processing the data loaded from said database (D) and transmitting them to said digital visor or glasses (G) , thus allowing said test operator (0) wearing said digital visor or glasses (G) to view in augmented reality, oversaid printed circuit board or PCB (3) , the trace or track (T) to be tested; said augmented reality application (A) being characterized in that said database (D) contains data obtained by executing the method according to claim 1.

15. Augmented reality application (A) according to claim14, comprising a graphical interface and implementing selfalignment of augmented reality images with said printed circuit board or PCB (3) .

Images