Display device and method for driving same

Abstract

The present application discloses a variable refresh rate display device of the current-driven type in which display problems due to crosstalk caused by a voltage change on a data signal line does not occur in a low-speed drive mode. Provided is an organic EL display device having a high-speed drive mode and a low-speed drive mode, wherein, in the case of the low-speed drive mode, a pixel circuit is driven so that a hold time of a data signal with respect to a scan signal is not a length corresponding to the drive speed but instead is a length corresponding to a hold time in the high-speed drive mode, i.e., a configurable minimum hold time. With this arrangement, even if a power supply voltage in the vicinity of a pixel circuit that is to form a pixel of a long edge part of a black rectangular pattern long in the horizontal direction with white set as the background fluctuates due to being affected by the level change of the data signal to be written to said pixel circuit, the amount of fluctuation in said power supply voltage in the vicinity is remarkably smaller at the end point of the write period compared to the past.

Description

Display device and its driving method

[0001] The present disclosure relates to a display device, and more particularly, to a current-driven display device including a display element driven by current such as an organic EL (Electro Luminescence) display device and a driving method thereof.

[0002] In recent years, an organic EL display device including a pixel circuit including an organic EL element (also called an organic light emitting diode (OLED)) has been put into practical use. The pixel circuit of the organic EL display device includes, in addition to the organic EL element, a driving transistor, a writing control transistor, a holding capacitor, and the like. Thin film transistors are used for the driving transistor and the writing control transistor, a holding capacitor is connected to the gate terminal as the control terminal of the driving transistor, and a voltage corresponding to a video signal representing an image to be displayed (more specifically, a voltage indicating the gradation value of the pixel to be formed in the pixel circuit, hereinafter referred to as "data voltage") is applied to this holding capacitor via a data signal line from a driving circuit. The organic EL element is a self-emitting display element that emits light with a luminance corresponding to the current flowing through it. The driving transistor is provided in series with the organic EL element and controls the current flowing through the organic EL element according to the voltage held in the holding capacitor.

[0003] In such a display device, there is one configured to be able to change the refresh rate indicating the frequency of rewriting the image data for one screen composed of pixel data held in each pixel circuit in the display unit. Hereinafter, a display device having such a configuration is referred to as a variable refresh rate method (VRR method) display device. For example, there is an organic EL display device having a high-speed driving mode for displaying an image at a relatively high refresh rate and a low-speed driving mode for displaying an image at a relatively low refresh rate by changing the frequency of the clock signal of the driving circuit.

[0004] In addition, the following prior art documents are known in relation to this application. Japanese Patent Publication No. 2006-107566 discloses a configuration for achieving low power consumption and high-speed operation of a shift register in a driving circuit for a liquid crystal display device. Japanese Patent Publication No. 2022-105277 describes a display device having a high-speed driving mode and a low-speed driving mode, and explains that in this display device, if the video data is moving, it is driven in the high-speed driving mode, and if the image data is a still image, it is driven in the low-speed driving mode (see paragraph 0071 of the same document). Furthermore, Japanese Patent Publication No. 2023-170026 discloses a configuration for suppressing crosstalk in a liquid crystal display device caused by fluctuations in the common voltage within the panel resulting from parasitic capacitance between the source bus line as a video signal line (data signal line) and a common electrode.

[0005] Japanese Patent Publication No. 2006-107566, Japanese Patent Publication No. 2022-105277, Japanese Patent Publication No. 2023-170026

[0006] In current-driven display devices such as the variable refresh rate organic EL display devices described above, when a black rectangular pattern is displayed against a white background in low-speed drive mode, a display problem may occur in which bright and dark lines extending horizontally from the top and bottom edges of the rectangular pattern are visible, as shown in Figure 5(C). This is thought to be because the effects of crosstalk caused by the change in the voltage of the data signal line from the black display voltage to the white display voltage, or vice versa, are more easily visible in low-speed drive mode.

[0007] Therefore, in current-driven display devices with a variable refresh rate, it is desirable to eliminate display problems caused by crosstalk resulting from voltage changes in the data signal lines.

[0008] Some embodiments of the present disclosure are variable refresh rate display devices having a high-speed drive mode with a relatively high refresh rate and a low-speed drive mode with a refresh rate lower than the refresh rate of the high-speed drive mode, comprising: a display unit including a plurality of data signal lines, a plurality of scan signal lines intersecting the plurality of data signal lines, a plurality of pixel circuits arranged along the plurality of data signal lines and the plurality of scan signals, a first power line, and a second power line; a data signal line drive circuit that applies a plurality of data signals representing an image to be displayed to the plurality of data signal lines, respectively; a scan signal line drive circuit that applies a plurality of scan signals that become active sequentially for predetermined periods to the plurality of scan signal lines, respectively; and a display control circuit that controls the data signal line drive circuit and the scan signal line drive circuit, wherein each of the plurality of pixel circuits includes: a display element driven by current; a holding capacitor; a drive transistor having a gate terminal connected to the first power line via the holding capacitor, a source terminal connected to the first power line, and a drain terminal connected to the second power line via the display element, and controlling the amount of current supplied to the display element according to the voltage written to the holding capacitor, The display control circuit includes a write control switching element having a control terminal connected to one of the plurality of scan signal lines and controlling whether or not to write the voltage of one of the plurality of data signal lines as a data voltage to the holding capacitor, the first power line includes a power line arranged along the plurality of data signal lines, and the display control circuit controls the data signal line drive circuit and the scan signal line drive circuit in each of the plurality of pixel circuits such that the hold time that the data signal of one data signal line has with respect to the scan signal of one scan signal line in the low-speed drive mode is shorter than the hold time corresponding to the drive speed in the low-speed drive mode.

[0009] A driving method according to some embodiments of the present disclosure is a driving method for a variable refresh rate display device having a high-speed driving mode in which the refresh rate is relatively high and a low-speed driving mode in which the refresh rate is lower than the refresh rate of the high-speed driving mode, wherein the display device comprises a display unit including a plurality of data signal lines, a plurality of scan signal lines intersecting the plurality of data signal lines, a plurality of pixel circuits arranged along the plurality of data signal lines and the plurality of scan signals, a first power line, and a second power line, each of the plurality of pixel circuits includes a display element driven by current, a holding capacitor, a drive transistor having a gate terminal connected to the first power line via the holding capacitor, a source terminal connected to the first power line, and a drain terminal connected to the second power line via the display element, and controlling the amount of current supplied to the display element according to the voltage written to the holding capacitor, and a write control switching element having a control terminal connected to one of the plurality of scan signal lines, and controlling whether or not to write the voltage of one of the plurality of data signal lines as a data voltage to the holding capacitor. The first power line includes a power line arranged along the plurality of data signal lines, and the driving method includes a data signal line driving step of applying a plurality of data signals representing an image to be displayed to each of the plurality of data signal lines, a scan signal line driving step of applying a plurality of scan signals that become active sequentially for predetermined periods to each of the plurality of scan signal lines, and a display control step of controlling the data signal line driving step and the scan signal line driving step in each of the plurality of pixel circuits such that the hold time that the data signal of one data signal line has with respect to the scan signal of one scan signal line in the low-speed driving mode is shorter than the hold time corresponding to the driving speed in the low-speed driving mode.

[0010] In some embodiments of the present disclosure, when the voltage level of a data signal line to be written to the pixel circuit (holding capacitor in the display unit) changes significantly (especially when it changes from a white display voltage level to a black display voltage level or vice versa), the change in voltage level affects the voltage of the first power line through the parasitic capacitance between the data signal line and the first power line, causing the voltage of the first power line to fluctuate in the portion of the first power line near the pixel circuit where the voltage after the change in the data signal line should be written as the data voltage. In this way, while the voltage of the first power line is fluctuating (while the voltage level of the first power line is deviating from the original power supply voltage level), when the writing period for writing the voltage after the level change of the data signal line to the pixel circuit ends, that is, when the active period of the scanning signal of the scanning signal line connected to the pixel circuit ends, the voltage at the gate terminal of the drive transistor in the pixel circuit and other pixel circuits connected to the scanning signal line (gate voltage) is affected by the voltage fluctuation of the first power line via the holding capacitor, and fluctuates according to the amount of voltage fluctuation of the first power line at the end of the writing period (see, for example, the waveforms of VNelvdd, Vg(is,jb), Vg(is,jw) shown in Figure 6). Due to crosstalk caused by such voltage level changes of the data signal line (level changes of the data signal), conventional display devices sometimes had display problems in low-speed driving mode, such as the visibility of bright lines and dark lines that were not included in the original display image. However, in some embodiments of this disclosure, in each pixel circuit, the data signal line and the scan signal line are driven such that the hold time of the data signal line relative to the scan signal line in low-speed drive mode is shorter than the hold time corresponding to the drive speed in low-speed drive mode. As a result, the period from when the voltage level of the data signal line (level of the data signal) starts to change until the end of the write period is extended. Therefore, the amount of fluctuation of the first power line at the end of the write period is reduced, and as a result, the amount of fluctuation of the gate voltage of the drive transistor in the pixel circuit connected to the scan signal line is also reduced compared to conventional methods. As a result, display problems caused by crosstalk resulting from changes in the voltage level of the data signal line are eliminated or mitigated.

[0011] In some embodiments of the present disclosure, it is preferable that in each pixel circuit, the plurality of data signal lines and the plurality of scan signal lines are driven such that the hold time of the data signal on one data signal line with respect to the scan signal on one scan signal line in low-speed drive mode is substantially the same as the hold time of the data signal with respect to the scan signal in high-speed drive mode. In this way, display problems caused by crosstalk resulting from voltage level changes in the data signal lines are reliably eliminated or mitigated.

[0012] In some embodiments of the present disclosure, it is even more preferable that, in each pixel circuit, the plurality of data signal lines and the plurality of scan signal lines are driven such that the hold time of the data signal on one data signal line with respect to the scan signal on one scan signal line in low-speed drive mode is the minimum length that can be set in the display device. In this way, display problems caused by crosstalk resulting from voltage level changes in the data signal lines are more reliably eliminated or mitigated.

[0013] In some embodiments of the present disclosure, it is even more preferable that, in each pixel circuit, the plurality of data signal lines and the plurality of scan signal lines are driven such that the hold time of the data signal of one data signal line with respect to the scan signal of one scan signal line in low-speed drive mode is the minimum length required as the hold time of the data signal with respect to the scan signal. In this way, display problems caused by crosstalk resulting from voltage level changes of the data signal lines are more reliably eliminated or mitigated.

[0014] This is a block diagram showing the overall configuration of a display device according to one embodiment. This is a block diagram showing the configuration of the display panel of the display device according to the above embodiment. This is a timing chart for explaining the operation of the display panel of the display device according to the above embodiment. This is a circuit diagram showing the configuration of the pixel circuit in the above embodiment. These are diagrams (A, B, C) for explaining display problems that occur in the low-speed drive mode of a conventional display device. This is a signal waveform diagram for explaining a first example of operation of the pixel circuit in the low-speed drive mode of the conventional display device. This is a signal waveform diagram for explaining a first example of operation of the pixel circuit in the low-speed drive mode of the display device according to the above embodiment. This is a signal waveform diagram for explaining the driving and operation of the pixel circuit in the high-speed drive mode of the display device according to the above embodiment. This is a signal waveform diagram for explaining a second example of operation of the pixel circuit in the low-speed drive mode of the conventional display device. This is a signal waveform diagram for explaining a second example of operation of the pixel circuit in the low-speed drive mode of the display device according to the above embodiment.

[0015] Embodiments will be described below with reference to the attached drawings. In each transistor mentioned below, the gate terminal corresponds to the control terminal, one of the drain terminal and the source terminal corresponds to the first conduction terminal, and the other corresponds to the second conduction terminal. Furthermore, the transistors in the following embodiments are thin-film transistors having a channel layer formed of low-temperature polysilicon (hereinafter referred to as "LTPS-TFT"), but the present invention is not limited thereto, and some or all of the transistors used may be N-channel thin-film transistors having a channel layer formed of an oxide semiconductor containing indium, gallium, zinc, and oxygen (hereinafter referred to as "IGZO-TFT"). Moreover, in this specification, "connection" means "electrical connection" unless otherwise specified, and to the extent that it does not depart from the gist of the present invention, it includes not only direct connections but also indirect connections via other elements.

[0016] <1. Outline Configuration> Figure 1 is a block diagram showing the functional configuration of a display device according to one embodiment. This display device is a variable refresh rate (VRR) organic EL display device that uses organic EL elements (OLEDs) as display elements, and has two drive modes, a high-speed drive mode and a low-speed drive mode with different refresh rates, and is configured to be switchable between these two drive modes.

[0017] As shown in Figure 1, this organic EL display device comprises a display unit 10, a scanning-side drive circuit 20, a data signal line drive circuit (hereinafter also referred to as "data driver") 30 as a data-side drive circuit, and a display control circuit 40. In this embodiment, the scanning-side drive circuit 20 and the data signal line drive circuit 30 are included within the display panel having the display unit 10. The scanning-side drive circuit 20 is typically monolithic; that is, the scanning-side drive circuit 20 is directly formed on the substrate on which the pixel circuits in the display unit 10 are formed. The data signal line drive circuit 30 may also be monolithic or not. Furthermore, the data signal line drive circuit 30 may be directly provided on the display panel, or it may be composed of a circuit within an IC chip mounted on the display panel.

[0018] Figure 2 is a block diagram showing the configuration of the display panel of the organic EL display device according to this embodiment, and shows the connection relationship between the pixel circuit 15 and various drive signal lines. As shown in Figure 2, the display unit 10 is provided with m data signal lines D1, D2, ..., Dm (where m is an integer of 2 or more) and n scan signal lines SC1, SC2, ..., SCn (where n is an integer of 2 or more) that intersect these as write control lines. m × n pixel circuits 15 are provided arranged in a matrix along the m data signal lines D1 to Dm and the n scan signal lines SC1 to SCn. Each pixel circuit 15 corresponds to one of the m data signal lines D1 to Dm and one of the n scan signal lines SC1 to SCn (hereinafter, when distinguishing each pixel circuit 15, the pixel circuit corresponding to the i-th scan signal line SCi and the j-th data signal line Dj will be called the "i-th row j-th column pixel circuit" and will be indicated by the symbol "Pix(i,j)"). Furthermore, the display unit 10 is provided with n light emission control lines EM1, EM2, ..., EMn arranged along n scan signal lines SC1, SC2, ..., SCn, and n+1 initialization control lines DIS0, DIS1, DIS2, ..., DISn. The first initialization control line DIS0 is arranged along the first row of pixel circuits Pix(1,1) to Pix(1,m), the i-th initialization control line DISi of the n-1 initialization control lines DIS1 to DISn-1 is arranged along the i-th row of pixel circuits Pix(i,1) to Pix(i,m) and along the i+1-th row of pixel circuits Pix(i+1,1) to Pix(i+1,m) (i=1 to n-1), and the n-th initialization control line DISn is arranged along the n-th row of pixel circuits Pix(n,1) to Pix(n,m). Each pixel circuit 15 corresponds to one of the n light emission control lines EM1 to EMn, and also to one of the n initialization control lines DIS1 to DISn.

[0019] The display unit 10 is further equipped with power lines common to multiple pixel circuits. More specifically, it is equipped with a high-level power line Lelvdd that supplies a high-level power supply voltage ELVDD for driving the organic EL elements, a low-level power line Lelvss that supplies a low-level power supply voltage ELVSS for driving the organic EL elements, and an initialization voltage line Lini that supplies an initialization voltage Vini. In addition, the frame region of the display panel, which includes the display unit 10, where the scanning-side drive circuit 20 is located, is equipped with a gate high-level voltage line that supplies a gate high-level voltage VGH, which is a high-level fixed voltage, to the scanning-side drive circuit 20, and a gate low-level voltage line that supplies a gate low-level voltage VGL, which is a low-level fixed voltage, to the scanning-side drive circuit 20.

[0020] <2. General Operation> The display control circuit 40 receives an input signal Sin from outside the display device according to this embodiment, which includes image information representing the image to be displayed and timing control information for image display. Based on this input signal Sin, it generates a data-side control signal Scd, a digital video signal DV, and a scanning-side control signal Scs. It outputs the data-side control signal Scd and the digital video signal DV to the data signal line drive circuit 30, and outputs the scanning-side control signal Scs to the scanning-side drive circuit 20.

[0021] The data signal line drive circuit 30 drives the plurality of data signal lines based on the data-side control signal Scd and the digital video signal DV from the display control circuit 40. The scanning-side drive circuit 20 receives the scanning-side control signal Scs from the display control circuit 40. This scanning-side control signal Scs includes a drive control signal SCCTL for scanning signal lines consisting of a write control start pulse signal GSPa and write control clock signals GCK1a and GCK2a, a drive control signal DISCTL for initialization control lines consisting of an initialization control start pulse signal GSPb and initialization control clock signals GCK1b and GCK2b, and a drive control signal EMCTL for light emission control lines consisting of a light emission control start pulse signal ESP and light emission control clock signals ECK1 and ECK2. The scanning drive circuit 20 drives the plurality of initialization control lines based on the initialization control line drive control signal DISCTL, drives the plurality of scanning signal lines based on the scanning signal line drive control signal SCCTL, and drives the plurality of light emission control lines based on the light emission control line drive control signal EMCTL.

[0022] By driving the data signal lines, initialization control lines, scan signal lines, and light emission control lines as described above, a data voltage corresponding to the value of each pixel in the image represented by the digital video signal DV is written to the pixel circuit corresponding to that pixel, and each pixel circuit emits light with a brightness corresponding to the data voltage written thereto.

[0023] As described above, the display device according to this embodiment has a high-speed drive mode and a low-speed drive mode. In the low-speed drive mode, the frequencies of the clock signals supplied to the scanning drive circuit 20 (write control clock signals GCK1a, GCK2a, initialization control clock signals GCK1b, GCK2b, and light emission control clock signals ECK1, ECK2) and the frequencies of the clock signals supplied to the data signal line drive circuit 30 are lower by a predetermined percentage compared to the high-speed drive mode. Whether the display device operates in the low-speed drive mode or the high-speed drive mode is specified by mode information based on a predetermined operation by the user or by mode information included in an external input signal Sin. The display control circuit 40 switches the frequencies of the clock signals to be supplied to the scanning drive circuit 20 and the data signal line drive circuit 30 according to the specified drive mode, thereby switching the drive mode of the display device according to this embodiment between the high-speed drive mode and the low-speed drive mode.

[0024] <3. Operation of the Display Panel> Figure 3 is a timing chart for explaining the operation of the display panel according to this embodiment. The data signal lines D1 to Dm are driven by the application of data signals D(1) to D(m), which represent the image to be displayed, as shown in Figure 3, from the data signal line drive circuit 30. The scanning drive circuit 20 includes a DIS driver 211 as an initialization control circuit, an SC driver 212 as a scanning signal line drive circuit that functions as a write control circuit, and an EM driver (emission driver) 213 as a light emission control circuit. The initialization control lines DIS0 to DISn are driven by the application of initialization control signals DIS(0) to DIS(n), as shown in Figure 3, from the DIS driver 211, based on the initialization control start pulse signal GSPb and the initialization control clock signals GCK1b and GCK2b. The scanning signal lines SC1 to SCn are driven by the SC driver 212 applying scanning signals SC(1) to SC(n), which become active (low level) sequentially for predetermined periods as write control signals, based on the write control start pulse signal GSPa and write control clock signals GCK1a and GCK2a, as shown in Figure 3. The light emission control lines EM1 to EMn are driven by the EM driver 213 applying light emission control signals EM(1) to EM(n), which become inactive (high level) sequentially in conjunction with the scanning signals SC(1) to SC(n), as shown in Figure 3, based on the light emission control start pulse signal ESP and light emission control clock signals ECK1 and ECK2.

[0025] <4. Pixel Circuit Configuration> Figure 4 is a circuit diagram showing the configuration of the pixel circuit 15 in this embodiment. More specifically, it is a circuit diagram showing the configuration of the pixel circuit 15 corresponding to the i-th scan signal line SCi and the j-th data signal line Dj, i.e., the i-th row and j-th column pixel circuit Pix(i,j) (1≦i≦n, 1≦j≦m). This pixel circuit 15 includes one organic EL element OL as a display element, seven transistors T1 to T7 (hereinafter referred to as "first initialization transistor T1", "threshold compensation transistor T2", "write control transistor T3", "drive transistor T4", "power supply control transistor T5", "light emission control transistor T6", and "second initialization transistor T7"), and one retaining capacitor Cst. The retaining capacitor Cst is a capacitive element having two electrodes consisting of a first electrode and a second electrode. Transistors T1 to T7 are all P-channel type, thin-film transistors (LTPS-TFTs) having a channel layer formed, for example, from low-temperature polysilicon. Of these, transistors T1 and T2 are double-gate transistors. In the pixel circuit 15, transistors T1 to T3 and T5 to T7, other than the driving transistor T4, function as switching elements.

[0026] As shown in Figure 4, the pixel circuit Pix(i,j) is connected to the corresponding scan signal line SCi, the corresponding initialization control line DISi, the initialization control line immediately preceding the initialization control line DISi, i.e., the i-1th initialization control line DISi-1 (hereinafter, in explanations focusing on the pixel circuit, this will also be simply called the "previous initialization control line"), the corresponding light emission control line EMI, the corresponding data signal line Dj, the initialization voltage line Lini, the high-level power supply line Lelvdd, and the low-level power supply line Lelvss. In Figure 4, Cil represents the parasitic capacitance present between the data signal line Dj and the high-level power supply line Lelvdd (see Figure 5(A) described later).

[0027] The drive transistor T4 has a gate terminal connected to the high-level power line Lelvdd via a holding capacitor Cst and to the initialization voltage line Lini via a first initialization transistor T1; a source terminal connected to the data signal line Dj via a write control transistor T3 and to the high-level power line Lelvdd via a power supply control transistor T5; and a drain terminal connected to the gate terminal via a threshold compensation transistor T2 and to the anode of the organic EL element OL via a light emission control transistor T6. The anode of the organic EL element OL is connected to the initialization voltage line Lini via a second initialization transistor T7, and the cathode of the organic EL element OL is connected to the low-level power line Lelvss. The gate terminals of the write control transistor T3 and the threshold compensation transistor T2 are connected to the scan signal line SCi, the gate terminals of the power supply control transistor T5 and the light emission control transistor T6 are connected to the light emission control line EMI, the gate terminal of the first initialization transistor T1 is connected to the pre-initialization control line DISi-1, and the gate terminal of the second initialization transistor T7 is connected to the initialization control line DISi.

[0028] <5. Display Problems in Conventional Display Devices> Figure 5 is a diagram illustrating display problems that occur in the low-speed drive mode of a conventional organic EL display device (hereinafter referred to as "conventional example") having a low-speed drive mode and a high-speed drive mode. Figure 5(A) schematically shows the parasitic capacitance between the data signal line Dj and the high-level power line Lelvdd in the display unit 10. Figure 5(B) shows the change in the level of the data voltage Vdata and the voltage of the high-level power line Lelvdd (ELVDD) in the vertical direction (the direction in which the data signal line Dj extends) when three black rectangular patterns (three black rectangular patterns with different horizontal lengths) BR1, BR2, and BR3 are displayed horizontally (in the direction perpendicular to the data signal line Dj, i.e., along the scanning signal line SCi) against a white background, as shown in Figure 5(C). Figure 5(C) is a diagram illustrating the bright and dark lines that occur when these three black rectangular patterns BR1, BR2, and BR3 are displayed. The following explanation is the result of the inventor's diligent investigation into the causes of such bright and dark lines.

[0029] In the display unit 10, as can be seen from Figure 5(A), the high-level power line Lelvdd includes power lines arranged along data signal lines D1 to Dm and power lines arranged along scan signal lines SC1 to SCn, and the wiring pattern of the high-level power line Lelvdd has a pattern extending vertically and a pattern extending horizontally. This is the same in this embodiment as well. Of these patterns of the high-level power line Lelvdd, the pattern extending vertically is arranged along each data signal line Dj in the same layer. Therefore, if the wiring width of the high-level power line Lelvdd is widened to reduce the voltage drop due to the current flowing through the high-level power line Lelvdd, the distance between it and the data signal line Dj becomes narrower, and the capacitance value of the parasitic capacitance Cil between the data signal line Dj and the high-level power line Lelvdd increases.

[0030] As shown in Figure 5(C), when displaying black rectangular patterns BR1, BR2, and BR3 against a white background, the longer the rectangular pattern in the horizontal direction, the more data signal lines Dj there are at the long edge of the rectangular pattern, where the voltage level changes significantly. These changes in the voltage level of the data signal lines Dj affect the voltage level of the high-level power line Lelvdd via the parasitic capacitance Cil. As a result, as shown in Figure 5(C), on the display screen, bright lines appear extending horizontally from the long edges of the black rectangular patterns BR1, BR2, and BR3 where the transition from the white background color to the black rectangle occurs vertically (the upper long edge in the figure), and dark lines appear extending horizontally from the long edges where the transition from the black rectangle to the white background color occurs vertically (the lower long edge in the figure). The effect of this crosstalk between the data signal lines Dj and the high-level power line Lelvdd on the display increases as the horizontal length of the black rectangular pattern increases, as shown in Figure 5(C). However, if the length in the water direction becomes less than a predetermined value, as is the case with the rectangular pattern BR3, which has the shortest horizontal length among the three black rectangular patterns BR1, BR2, and BR3, the bright and dark lines will practically become invisible.

[0031] Figure 6 is a signal waveform diagram illustrating the operation of the pixel circuit 15 (hereinafter referred to as "first operation example"), more specifically the operation of the pixel circuit Pix(is,jb) in the is row and jb column, when a black rectangular pattern BR1, etc., is displayed on a white background in a conventional organic EL display device in low-speed drive mode as described above. Here, is indicates the row number of the pixel circuit 15 that forms a pixel in the upper long edge of the black rectangular pattern BR1, and jb indicates the column number of the pixel circuit 15 that forms a pixel in the black rectangular pattern BR1 (see Figure 5(C)). Note that jw represents the column numbers other than the column number of the pixel circuit 15 that forms a pixel in the black rectangular pattern BR1 (numbers of data signal lines that do not intersect with the black rectangular pattern BR1) (see Figure 5(C)), and the waveforms of the data signal D(jw) and the voltage Vg at the gate terminal of the drive transistor T4 in the pixel circuit Pix(is,jw) are also shown in Figure 6.

[0032] In Figure 6, the period during which the light emission control signal EM(is) is at a high level is the non-light emission period. Immediately before this non-light emission period, the data signal D(jb) is at the level of the voltage Vw indicating white display (hereinafter referred to as "white voltage"), and the initialization control signals DIS(is-1), DIS(is) and the scan signals SC(is-1), SC(is) are all at a high level.

[0033] In the pixel circuit Pix(is,jb), at time t01 during the non-emitting period, the initialization control signal DIS(is-1) of the previous initialization control line DIDis-1 (hereinafter referred to as the "previous initialization control signal") changes from a high level (H level) to a low level (L level), and during the initialization period Tini, the voltage Vg at the gate terminal of the drive transistor T4 (hereinafter simply referred to as the "gate voltage") is initialized to the initialization voltage Vini. In the following, when distinguishing the gate voltage Vg of the drive transistor T4 in one pixel circuit Pix(i,j) from the gate voltage Vg of the drive transistor T4 in another pixel circuit, the symbol "Vg(i,j)" will be used.

[0034] During the initialization period Tini described above, the scan signal SC(is-1) changes from a high level to a low level. After this, while the scan signal SC(is-1) is at the low level, the write control transistor T3 and the threshold compensation transistor T2 are ON in the pixel circuit Pix(is-1, jb), and the white voltage Vw is written as the data signal D(jb) to the holding capacitor Cst via the write control transistor T3, the drive transistor T4, and the threshold compensation transistor T2.

[0035] Subsequently, at time t02, the scanning signal SC(is-1) changes from L level to H level, and the writing period in the pixel circuit Pix(is-1, jb) ends. However, in order to ensure that the data signal D(jb) is written to the holding capacitor Cst, the level of the data signal D(jb) is maintained for a predetermined hold time ThVD even after time t02.

[0036] At time t03, which is the time after the hold time ThVD has elapsed from time t02, the data signal D(jb) changes from the level of the white voltage Vw towards the level of the voltage indicating black (hereinafter referred to as "black voltage") Vb. This change in the data signal D(jb) affects the voltage level of the high-level power line Lelvdd via the parasitic capacitance Cil between the data signal line Dj and the high-level power line Lelvdd, causing the voltage of the high-level power line Lelvdd near the pixel circuit Pix(is,jb) (hereinafter referred to as "nearby high-level power supply voltage," and indicated by the symbol "VNelvdd") to fluctuate as shown in Figure 6.

[0037] After the data signal D(jb) changes to the level of the black voltage Vb, at time t04 the scan signal SC(is) changes from the H level to the L level, and the write period Tw in the pixel circuit Pix(is,jb) begins. Subsequently, at time t05 the scan signal SC(is) changes from the L level to the H level, and the write period Tw ends.

[0038] On the other hand, the high-level power supply voltage VNelvdd in the vicinity of the pixel circuit Pix(is,jb) rises in accordance with the change in the data signal D(jb) from time t03 onward due to the parasitic capacitance Cil between the data signal line Dj and the high-level power supply line Lelvdd. As shown in Figure 6, the high-level power supply voltage VNelvdd rises to ELVDD + ΔVelvdd1 and then decreases toward the high-level power supply voltage ELVDD, but at time t05 when the writing period Tw ends, it is at a level ΔVelvdd2 higher than the high-level power supply voltage ELVDD. Therefore, the gate voltage Vg(is,jb) of the drive transistor T4 connected to the high-level power line Lelvdd via the holding capacitor Cst decreases after time t05 in accordance with the decrease in the nearby high-level power supply voltage VNelvdd. When the nearby high-level power supply voltage VNelvdd reaches the high-level power supply voltage ELVDD and stops decreasing, the gate voltage Vg(is,jb) also stops decreasing. Hereafter, time t06 will be defined as the point in time when the nearby high-level power supply voltage VNelvdd and the gate voltage Vg(is,jb) stop decreasing.

[0039] At this time t06, assuming that the gate voltage Vg(is, jb) changes by ΔVg (<0) from the level at time t05 when the writing period Tw ends, then, in the light emission period when the light emission control signal EM(is) is at the L level, the gate-source voltage Vgs (<0) of the driving transistor T4 in the pixel circuit Pix(is, jb) is given by the following equation. Vgs = Vb - |VthT4| - ELVDD + ΔVg …(1) ΔVg = -ΔVelvdd2 × Cst / ΣCg …(2) In the above equation (1), VthT4 (<0) represents the threshold voltage of the driving transistor T4, Cst represents the capacitance value of the holding capacitor Cst, and ΣCg represents the sum of the capacitance values of the capacitors (including parasitic capacitances) existing between the node including the gate terminal of the driving transistor T4 and other nodes.

[0040] In the pixel circuit Pix(is, jb), the P-channel driving transistor T4 operates in the saturation region during the light emission period, and the driving current Id supplied from this driving transistor T4 to the organic EL element OL is given by the following equation. Id = (μ・Cox / 2)(W / L)(Vgs - VthT4) ,

[0042] …(3) Here, μ, W, L, and Cox represent the mobility, gate width, gate length, and gate insulation film capacitance per unit area of the driving transistor T4, respectively.

[0041] Substituting equation (1) into equation (3) and arranging considering VthT4 < 0, the following equation is obtained. Id = (μ・Cox / 2)(W / L)(Vb + ΔVg - ELVDD) 2 …(4) Also, substituting equation (2) into equation (4), the following equation is obtained. Id = (μ・Cox / 2)(W / L)(Vb - ΔVelvdd2 × Cst / ΣCg - ELVDD) 2 …(5) From the above equation (5), the larger the variation amount ΔVelvdd2 (>0) of the near high-level power supply voltage VNelvdd at the end point (time t05) of the writing period Tw of the pixel circuit Pix(is, jb), the larger the driving current Id supplied to the organic EL element OL during the light emission period and the higher the luminance.

[0042] Here, the pixel circuit Pix(is,jb) is a pixel circuit that forms a black pixel in the upper long edge of the black rectangular pattern BR1. Next, we examine the brightness of the pixel circuit (is,jw) which is in the same row (row is) as the pixel circuit Pix(is,jb) and forms a pixel with a white background located on the extension of the upper long edge (see Figure 5(C)).

[0043] As shown in Figure 6, the jw-th data signal D(jw) supplied to the pixel circuit Pix(is,jw) is maintained at the level of the white voltage Vw, which indicates a white background. Therefore, the gate voltage Vg(is,jw) of the drive transistor T4 in the pixel circuit Pix(is,jw) becomes at a level corresponding to the white voltage Vw during the write period Tw after the initialization period Tini. The voltage level of the data signal line Djw corresponding to this pixel circuit Pix(is,jw) does not change, but the voltage level of the data signal line Djb corresponding to the pixel circuit Pix(is,jb) that forms the black rectangular pattern BR1 pixels in the same row (row is) changes as described above, and this change causes the high-level power line Lelvdd to fluctuate via the parasitic capacitance Cil between the data signal line Dj and the high-level power line Lelvdd. Furthermore, since this black rectangular pattern BR1 is long horizontally, there are a relatively large number of such pixel circuits Pix(is,jb). For this reason, the voltage of the high-level power line Lelvdd near the pixel circuit Pix(is,jw) that forms a pixel of the white background located on the extension of the upper long edge of the black rectangular pattern BR1 (hereinafter referred to as "pixel circuit on the extension of the upper long edge") fluctuates via the high-level power line Lelvdd provided along the pixel circuits Pix(is,1) to Pix(is,m) of the is row.

[0044] Therefore, even in the pixel circuit (is, jw) on the extension line of the upper long edge portion like this, the gate voltage Vg(is, jw) of the driving transistor T4 decreases according to the variation amount ΔVelvdd2 at the time t05 of the near high-level power supply voltage VNelvdd from the end point (time t05) of the writing period Tw, and the gate voltage Vg(is, jw) in the subsequent light emission period changes by ΔVgw (<0) from the gate voltage Vg(is, jw) at the time t05. For this reason, the gate-source voltage Vgs (<0) in the driving transistor T4 in the pixel circuit Pix(is, jb) during the light emission period is given by the following equation similar to the above-described equations (1) and (2). Vgs = Vw - |VthT4| - ELVDD + ΔVgw...(6) ΔVgw = -ΔVelvdd2 × Cst / ΣCg...(7) However, the black voltage Vb in the equation (1) is replaced by the white voltage Vw in the equation (6). Also, ΔVelvdd2 in the equation (6) is smaller than ΔVelvdd2 in the equation (2).

[0045] Substituting the equation (6) into the above-described equation (3) and arranging, the following equation similar to the equation (4) is obtained as the equation showing the drive current Id supplied from the P-channel driving transistor T4 to the organic EL element OL in the pixel circuit Pix(is, jw). Id = (μ・Cox / 2)(W / L)(Vw + ΔVgw - ELVDD) 2 ...(8) Also, substituting the equation (7) into the equation (8), the following equation is obtained. Id = (μ・Cox / 2)(W / L)(Vw - ΔVelvdd2 × Cst / ΣCg - ELVDD) 2…(9) From equations (8) and (9) above, the larger the fluctuation amount ΔVelvdd2 (>0) of the nearby high-level power supply voltage VNelvdd at the end of the writing period Tw of the pixel circuit Pix(is,jw) (time t05) (the larger the decrease amount |ΔVgw| of the gate voltage Vg(is,jw)), the greater the drive current Id supplied to the organic EL element OL during the light emission period, and the greater the brightness. In such a pixel circuit Pix(is,jw) on the extension of the upper long edge, the organic EL element OL emits light with a brightness that is greater than the brightness corresponding to the white voltage Vw, according to the decrease amount |ΔVgw| of the gate voltage Vg(is,jw). This is visible as a bright line extending horizontally from the upper long edge of the black rectangular pattern BT1, as shown in Figure 5(C).

[0046] Furthermore, as shown in Figure 5(C), the longer the horizontal length of the black rectangular patterns BR1 to BR3, the larger the fluctuation amount ΔVelvdd2 of the nearby high-level power supply voltage VNelvdd for the pixel circuit Pix(is, jw) on the extension of the upper long edge, making the bright lines extending horizontally from the upper long edge of the black rectangular patterns BR1 to BR3 more visible. On the other hand, if the horizontal length becomes shorter than a predetermined value, as in the rectangular pattern BR3, the bright lines become practically invisible.

[0047] <6. Driving and Operation of Pixel Circuits in Embodiments> In this embodiment, when a black rectangular pattern BR1 etc. is displayed against a white background in low-speed driving mode, the pixel circuit 15 is driven as follows in order to resolve the display problem in which bright lines extending horizontally from the upper long edge of the black rectangular pattern BR1 etc. are visible as described above.

[0048] <6.1 First Operation Example> Figure 7 is a signal waveform diagram illustrating a first operation example of the pixel circuit 15 in the low-speed drive mode in the display device according to this embodiment. In this operation example, as with the first operation example in the conventional example, as shown in Figure 5(C), it shows the operation of the pixel circuit Pix(is,jb) in the is row and jb column when displaying a black rectangular pattern BR1, etc., which has a long side extending horizontally against a white background. Figure 7 also shows the gate voltage Vg(is,jw) of the drive transistor T4 in the pixel circuit Pix(is,jw) on the extension of the upper long edge of the black rectangular pattern BR1, and the waveform of the data signal D(jw) supplied to the pixel circuit Pix(is,jw).

[0049] As can be seen by comparing Figure 7 with Figure 6, in this embodiment, the data signal D(jb), initialization control signals DIS(is-1), Dis(is), scanning signal SC(is), and light emission control signal EM(is) provided to drive the pixel circuit Pix(is,jb) are basically the same as in the conventional example. In the conventional example, the hold time ThVD of the data signal D(j) with respect to the scanning signal SC(i) is configured to be a length corresponding to the driving speed, and the hold time ThVD becomes longer as the driving speed decreases. However, in this embodiment, the display control circuit 40 controls the data signal line driving circuit 30 and the scanning side driving circuit 20 so that in the low-speed driving mode, the hold time ThVD of the data signal D(j) with respect to the scanning signal SC(i) is not a length corresponding to the driving speed, but a length corresponding to the configurable minimum hold time ThVD(min), which is the hold time ThVD in the high-speed driving mode.

[0050] Therefore, as shown in Figure 7, at time t02, the scanning signal SC(is-1) changes from L level to H level, and after the writing period in the pixel circuit Pix(is-1,jb) ends, the level of the data signal D(jb) is maintained for a minimum hold time ThVD(min). At time t03, which is the minimum hold time ThVD(min) elapsed from time t02, the data signal D(jb) changes from the level of the white voltage Vw to the level of the black voltage Vb. This change in the data signal D(jb) affects the voltage level of the high-level power line Lelvdd via the parasitic capacitance Cil between the data signal line Dj and the high-level power line Lelvdd, and as in the conventional example (see Figure 6), the voltage of the high-level power line Lelvdd near the pixel circuit Pix(is,jb) fluctuates as shown in Figure 7.

[0051] Furthermore, similar to the conventional example (see Figure 6), after the data signal D(jb) changes to the level of the black voltage Vb, at time t04 the scan signal SC(is) changes from the H level to the L level, and the writing period Tw of the pixel circuit Pix(is,jb) begins. Then, at time t05 the scan signal SC(is) changes from the L level to the H level, and the writing period Tw ends. As shown in Figure 7, in this embodiment, the hold time ThVD of the data signal D(jb) with respect to the scan signal SC(is-1) is the minimum hold time ThVD(min), which is shorter than the hold time ThVD in the conventional example. Therefore, the period TA (the period from time t03 to t05) from the end of the hold time ThVD to the end of the write period Tw is longer in this embodiment than in the conventional example. Consequently, the period from the end of the hold time ThVD and the start of the change in the data signal D(jb) from the white voltage Vw to the black voltage Vb until the end of the write period Tw is also longer in this embodiment than in the conventional example. As a result, the amount of fluctuation ΔVelvdd2 of the nearby high-level power supply voltage VNeldvv at the end of the write period Tw (time t05) is significantly smaller in this embodiment than in the conventional example. Consequently, the amount of decrease |ΔVg| of the gate voltage Vg(is,jb) of the drive transistor T4 in the pixel circuit Pix(is,jb) after the end of the write period Tw (time t05) is also significantly smaller in this embodiment than in the conventional example.

[0052] In this embodiment as well, the drive current Id supplied from the P-channel drive transistor T4 to the organic EL element OL in the pixel circuit Pix(is,jb) during the light emission period is given by equation (4) or (5) as described above, as in the conventional example. However, the fluctuation of the drive current Id due to the decrease in the gate voltage Vg(is,jb) |ΔVg| and the fluctuation in the nearby high-level power supply voltage VNelvdd ΔVelvdd2 (>0) is significantly smaller than in the conventional example. As a result, the increase in brightness of the organic EL element OL in the pixel circuit Pix(is,jb) is suppressed.

[0053] Furthermore, in the pixel circuit Pix(is,jw) on the extension of the upper long edge of the black rectangular pattern BR1 in this embodiment (see Figure 5(C)), since the hold time ThVD is the minimum hold time ThVD(min) and the period TA is longer than in the conventional example, the fluctuation amount ΔVelvdd2 (>0) of the nearby high-level power supply voltage VNelvdd is significantly smaller, as shown in Figure 7. As a result, the decrease amount |ΔVgw| of the gate voltage Vg(is,jw) of the drive transistor T4 in the pixel circuit Pix(is,jw) is also significantly smaller in this embodiment than in the conventional example. That is, the waveform of the data signal D(jw) supplied to the pixel circuit Pix(is,jw) and the gate voltage Vg(is,jw) is as shown in Figure 7.

[0054] In this embodiment, the drive current Id supplied from the P-channel drive transistor T4 to the organic EL element OL during the light emission period in the pixel circuit Pix(is, jw) is given by equation (8) or (9) described above, as in the conventional example. However, the amount of change in the drive current Id due to the decrease in the gate voltage Vg(is, jb) |ΔVg| and the amount of change in the nearby high-level power supply voltage VNelvdd ΔVelvdd2 (>0) is significantly smaller than in the conventional example. As a result, the increase in brightness of the organic EL element OL in the pixel circuit Pix(is, jw) is suppressed. Consequently, in this embodiment, even when a black rectangular pattern BR1 or the like is displayed, the bright lines extending horizontally from the upper long edge are not visible.

[0055] The driving and operation of the pixel circuit Pix(i,j) in the high-speed driving mode of the display device according to this embodiment is the same as the driving and operation of the pixel circuit (i,j) in the high-speed driving mode of the conventional example, and the hold time ThVD of the data signal D(j) with respect to the scan signal SC(i) in the high-speed driving mode is shorter than in the case of the low-speed driving mode of the conventional example. Figure 8 is a signal waveform diagram for explaining the driving and operation of the pixel circuit Pix(is,jb) in the is row jb column when displaying a black rectangular pattern BR1 etc. on a white background in the high-speed driving mode of the display device according to this embodiment, as shown in Figure 5(C). However, Figure 8 also shows the gate voltage Vg(is,jw) of the driving transistor T4 in the pixel circuit Pix(is,jw) on the extension of the upper long edge of the black rectangular pattern BR1 and the waveform of the data signal D(jw) supplied to the pixel circuit Pix(is,jw).

[0056] As can be seen by comparing Figure 8 with Figure 7, in the high-speed drive mode, the data signal D(jb), initialization control signals DIS(is-1), Dis(is), scan signal SC(is), and light emission control signal EM(is) that are given to drive the pixel circuit Pix(is,jb) are basically the same as in the low-speed drive mode. However, in the high-speed drive mode, the interval of the active period in the drive signal of the pixel circuit Pix(i,j), for example, the interval between the write period as the active period of the i-1th scan signal SC(i-1) and the write period as the active period of the ith scan signal SC(i), becomes shorter than in the low-speed drive mode.

[0057] Therefore, in this embodiment, in the high-speed drive mode, the hold time ThVD of the data signal D(j) with respect to the scan signal SC(i) is the minimum hold time ThVD(min), which is the same as in the low-speed drive mode (see Figure 7). However, as shown in Figure 8, the time interval between the write period of the is-1 scan signal SC(is-1) (the period from time t12 to t02) and the write period of the is scan signal SC(is) (the period from time 04 to t05) is shorter than in the low-speed drive mode. As a result, the period TA (the period from time t03 to t05) from the end of the hold time ThVD(min) to the end of the write period Tw is shorter than in the low-speed drive mode. Consequently, the period from when the data signal D(jb) starts changing from white voltage Vw to black voltage Vb until the end of the write period Tw is also shorter than in the low-speed drive mode. As a result, as shown in Figure 8, the fluctuation amount ΔVelvdd2 (>0) of the nearby high-level power supply voltage VNeldvv at the end of the writing period Tw (time t05) is larger than in the low-speed drive mode. However, unlike the low-speed drive mode, in the high-speed drive mode, moving images (especially fast-moving images) are displayed, and still images are not. Therefore, in the high-speed drive mode, bright and dark lines that are not included in the image to be displayed are not practically visible, and display problems like those in the low-speed drive mode (see Figure 5(C)), namely display problems due to crosstalk caused by voltage changes in the data signal line Dj, do not occur.

[0058] <6.2 Second Operation Example> Next, in the case of displaying a black rectangular pattern BR1, etc., with a long side extending horizontally against a white background, as shown in Figure 5(C), in low-speed drive mode, the operation of the pixel circuit Pix(ie+1, jb) that forms white pixels adjacent to the lower long edge of the rectangular pattern BR1 will be explained as a second operation example with reference to Figures 9 and 10. Here, ie indicates the row number of the pixel circuit 15 that forms pixels at the lower long edge of the black rectangular pattern BR1, and jb indicates the column number of the pixel circuit 15 that forms pixels in the black rectangular pattern BR1 (see Figure 5(C)). Furthermore, the column numbers other than the column numbers of the pixel circuit 15 that form pixels in the black rectangular pattern BR1 (the numbers of data signal lines that do not intersect with the black rectangular pattern BR1) are denoted by jw (see Figure 5(C)), and in addition to the signal waveform related to the pixel circuit Pix(ie+1, jb), the waveforms of the data signal D(jw) and the gate voltage Vg(ie+1, jw) of the drive transistor T4 within the pixel circuit Pix(ie+1, jw) are also shown in Figures 9 and 10.

[0059] Before describing a second example of operation in the low-speed drive mode in this embodiment, we will first describe a second example of operation in the low-speed drive mode in a conventional example. Figure 9 is a signal waveform diagram used to explain the operation of the pixel circuit Pix(ie+1, ib) as a second example of operation when a black rectangular pattern BR1 etc. is displayed on a white background with a white background as shown in Figure 5(C) in a conventional organic EL display device in low-speed drive mode.

[0060] In Figure 9, the period during which the light emission control signal EM(ie+1) is at the H level is the non-light emission period. Immediately before this non-light emission period, the data signal D(jb) is at the level of the black voltage Vb, and the initialization control signals DIS(ie), DIS(ie+1) and the scan signals SC(ie), SC(ie+1) are all at the H level.

[0061] In the pixel circuit Pix(ie+1, jb), at time t01 during the non-emitting period, the initialization control signal (previous initialization control signal) DIS(ie) of the previous initialization control line DIDie changes from a high level to a low level, and during the initialization period Tini, the gate voltage Vg of the drive transistor T4 is initialized to the initialization voltage Vini.

[0062] During the initialization period Tini described above, the scan signal SC(ie) changes from a high level to a low level. After this, while the scan signal SC(ie) is at the low level, the write control transistor T3 and the threshold compensation transistor T2 in the pixel circuit Pix(ie, jb) are turned on, and the black voltage Vb is written as the data signal D(jb) to the holding capacitor Cst via the write control transistor T3, the drive transistor T4, and the threshold compensation transistor T2.

[0063] Subsequently, at time t02, the scanning signal SC(ie) changes from L level to H level, and the writing period Tw in the pixel circuit Pix(ie,jb) ends. However, in order to ensure that the data signal D(jb) is written to the holding capacitor Cst, the level of the data signal D(jb) is maintained for a predetermined hold time ThVD even after time t02.

[0064] At time t03, which is after a hold time ThVD has elapsed from time t02, the data signal D(jb) changes from the level of the black voltage Vb to the level of the white voltage Vw. This change in the data signal D(jb) affects the voltage level of the high-level power line Lelvdd via the parasitic capacitance Cil between the data signal line Dj and the high-level power line Lelvdd, causing the voltage of the high-level power line Lelvdd near the pixel circuit Pix(ie+1,jb) (nearby high-level power supply voltage) VNelvdd to fluctuate as shown in Figure 9.

[0065] After the data signal D(jb) changes to the level of the white voltage Vw, at time t04 the scan signal SC(ie+1) changes from the H level to the L level, and the write period Tw in the pixel circuit Pix(ie+1, jb) begins. Subsequently, at time t05 the scan signal SC(ie+1) changes from the L level to the H level, and its write period Tw ends.

[0066] On the other hand, the high-level power supply voltage VNelvdd in the vicinity of the pixel circuit Pix(ie+1, jb) decreases from time t03 onward due to the parasitic capacitance Cil between the data signal line Dj and the high-level power supply line Lelvdd, as the data signal D(jb) changes. As shown in Figure 9, the high-level power supply voltage VNelvdd decreases to ELVDD - ΔVelvdd1 and then rises toward the high-level power supply voltage ELVDD, but at time t05 when the writing period Tw ends, it is at a level lower than the high-level power supply voltage ELVDD by ΔVelvdd2 (>0). Therefore, the gate voltage Vg(ie+1,jb), which is the voltage at the gate terminal of the drive transistor T4 connected to the high-level power line Lelvdd via the holding capacitor Cst, rises after time t05 in accordance with the rise of the nearby high-level power supply voltage VNelvdd. When the nearby high-level power supply voltage VNelvdd reaches the high-level power supply voltage ELVDD and stops rising, the gate voltage Vg(ie+1,jb) also stops rising. Hereafter, time t06 will be defined as the point in time when the nearby high-level power supply voltage VNelvdd and the gate voltage Vg(ie+1,jb) stop rising.

[0067] At time t06, assuming that the gate voltage Vg(ie+1, jb) changes by ΔVg (>0) from the level at time t05 when the writing period Tw ends, then during the subsequent light emission period when the light emission control signal EM(is) is at the L level, the gate-source voltage Vgs (<0) at the drive transistor T4 in the pixel circuit Pix(ie+1, jb) is given by the following equation: Vgs = Vw - |VthT4| - ELVDD + ΔVg ... (11) ΔVg = ΔVelvdd² × Cst / ΣCg ... (12) In equation (12) above, VthT4 (<0) represents the threshold voltage of the drive transistor T4, Cst represents the capacitance value of the holding capacitor Cst, and ΣCg represents the sum of the capacitance values ​​of the capacitors (including parasitic capacitance) existing between the node containing the gate terminal of the drive transistor T4 and other nodes.

[0068] In the pixel circuit Pix(ie+1, jb), the drive current Id supplied from the P-channel drive transistor T4 to the organic EL element OL is given by equation (3) described above.

[0069] Substituting equation (11) into equation (3) described above, and rearranging while considering VthT4 < 0, we obtain the following equation: Id = (μ・Cox / 2)(W / L)(Vw + ΔVg - ELVDD) 2 …(14) Substituting equation (12) into equation (14) yields the following equation: Id = (μ・Cox / 2)(W / L)(Vw + ΔVelvdd2 × Cst / ΣCg - ELVDD) 2 …(15) From equation (15) above, the larger the decrease in the nearby high-level power supply voltage VNelvdd ΔVelvdd2 (>0) at the end of the writing period Tw of the pixel circuit Pix(ie+1, jb) (time t05), the smaller the drive current Id supplied to the organic EL element OL during the light emission period, and the lower the brightness.

[0070] Here, the pixel circuit Pix(ie+1, jb) is a pixel circuit that forms a white pixel adjacent to a black pixel in the lower long edge of the black rectangular pattern BR1. Next, we examine the brightness of the pixel circuit (ie+1, jw) in the same row (row ie+1) as the pixel circuit Pix(ie+1, jb), which forms a white background pixel located on the extension of the lower long edge (see Figure 5(C)).

[0071] As shown in Figure 9, the jw-th data signal D(jw) supplied to the pixel circuit Pix(ie+1, jw) is maintained at the level of the white voltage Vw, which indicates a white background. Therefore, the gate voltage Vg(ie+1, jw) of the drive transistor T4 in the pixel circuit Pix(ie+1, jw) changes after the initialization period Tini, similar to the gate voltage Vg(ie+1, jb) of the drive transistor T4 in the pixel circuit Pix(ie+1, jb). The amount of variation ΔVgw of the gate voltage Vg(ie+1, jw) in the pixel circuit Pix(ie+1, jw) is given by the following equation, which is similar to the previously described equation (12) that shows the amount of variation ΔVg of the gate voltage Vg(ie+1, jb) in the pixel circuit Pix(ie+1, jb). ΔVgw = ΔVelvdd2 × Cst / ΣCg … (13) Therefore, the equation for the drive current Id supplied from the P-channel drive transistor T4 to the organic EL element OL in the pixel circuit Pix(ie+1, jw) is given by equation (14) or (15) described above, just as in the case of the pixel circuit Pix(ie+1, jb). Consequently, the larger the decrease in the nearby high-level power supply voltage VNelvdd ΔVelvdd2 (>0) and the decrease in the gate voltage Vg(ie+1, jw) ΔVgw (>0) at the end of the writing period Tw of the pixel circuit Pix(ie+1, jw) (time t05), the smaller the drive current Id supplied to the organic EL element OL during the light emission period, and the lower the brightness. This decrease in brightness in the pixel circuit Pix(ie+1, jw) is visible as a dark line extending horizontally from the lower long edge of the black rectangular pattern BT1, as shown in Figure 5(C).

[0072] Figure 10 is a signal waveform diagram illustrating a second example of operation of the pixel circuit 15 in the low-speed drive mode in the display device according to this embodiment. In this example, as with the second example of operation in the conventional example, as shown in Figure 5(C), it shows the operation of the pixel circuit Pix(ie+1,jb) in the row ie+1 and column jb when displaying a black rectangular pattern BR1 having a long side extending horizontally against a white background. Figure 10 also shows the waveforms of the gate voltage Vg(ie+1,jw) of the drive transistor T4 in the pixel circuit Pix(ie+1,jw) and the data signal D(jw) supplied to the pixel circuit Pix(ie+1,jw), where jw is used to indicate the column numbers other than the column number of the pixel circuit 15 that forms the pixels in the black rectangular pattern BR1.

[0073] As can be seen by comparing Figure 10 with Figure 9, in this embodiment, the data signal D(jb), initialization control signals DIS(ie), Dis(ie+1), scanning signal SC(ie+1), and light emission control signal EM(ie+1) provided to the pixel circuit Pix(ie+1,jb) in order to drive the pixel circuit Pix(ie+1,jb) are basically the same as in the conventional example. However, in this embodiment, the display control circuit 40 controls the data signal line drive circuit 30 and the scanning side drive circuit 20 so that, in the low-speed drive mode, the hold time ThVD of the data signal D(j) with respect to the scanning signal SC(i) is not a time length corresponding to the drive speed, but a time length corresponding to the configurable minimum hold time ThVD(min), which is the hold time ThVD in the high-speed drive mode.

[0074] Therefore, as shown in Figure 10, at time t02, the scanning signal SC(ie) changes from L level to H level, and after the writing period in the pixel circuit Pix(ie,jb) ends at time t02, the level of the data signal D(jb) is maintained for a minimum hold time ThVD(min). At time t03, which is after the minimum hold time ThVD(min) has elapsed from time t02, the data signal D(jb) changes from the level of the black voltage Vb to the level of the white voltage Vw. This change in the data signal D(jb) affects the voltage level of the high-level power line Lelvdd via the parasitic capacitance Cil between the data signal line Dj and the high-level power line Lelvdd, and as in the conventional example (see Figure 9), the voltage of the high-level power line Lelvdd near the pixel circuit Pix(ie+1,jb) fluctuates as shown in Figure 10.

[0075] However, in this embodiment, the hold time ThVD of the data signal D(jb) relative to the scan signal SC(ie) is the minimum hold time ThVD(min), which is shorter than the hold time ThVD in the conventional example. Therefore, the period TA (the period from time t03 to t05) from the end of the hold time ThVD(min) to the end of the write period Tw is longer in this embodiment than in the conventional example. Consequently, the period from the end of the hold time ThVD and the start of the change in the data signal D(jb) from the white voltage Vw to the black voltage Vb until the end of the write period Tw is also longer in this embodiment than in the conventional example. As a result, the amount of decrease ΔVelvdd2 (>0) of the nearby high-level power supply voltage VNeldvv at the end of the write period Tw (time t05) is significantly smaller in this embodiment than in the conventional example. As a result, the decrease in the gate voltage Vg(ie+1, jb) of the drive transistor T4 in the pixel circuit Pix(ie+1, jb) after the end of the writing period Tw (time t05), ΔVgw (>0), is significantly smaller in this embodiment than in the conventional example.

[0076] As described above, in this embodiment, even in the second operating example, the amount of fluctuation in the drive current Id due to the decrease in the gate voltage Vg(ie+1, jb) ΔVgw (>0) and the decrease in the nearby high-level power supply voltage VNelvdd ΔVelvdd2 (>0) in the pixel circuit Pix(ie+1, jb) is significantly smaller than in the conventional example. Therefore, the decrease in brightness of the organic EL element OL in the pixel circuit Pix(ie+1, jw) is suppressed. As a result, in this embodiment, even when a black rectangular pattern BR1 or the like is displayed, the dark line extending horizontally from the lower long edge is no longer visible.

[0077] <7. Effects> As described above, according to this embodiment, in an organic EL display device with a variable refresh rate having a high-speed drive mode and a low-speed drive mode, in the low-speed drive mode, as shown in Figures 7 and 10, the pixel circuit Pix(i,j) is driven so that the hold time ThVD of the data signal D(j) with respect to the scan signal SC(i) is not a time length corresponding to the drive speed, but rather a time corresponding to the hold time ThVD in the high-speed drive mode, i.e., the minimum hold time ThVD(min) that can be set in the display device. For this reason, the period TA (the period from time t03 to t05) from the end of the hold time ThVD to the end of the write period Tw is longer in this embodiment than in the conventional example. Therefore, even when the level of the data signal D(j) to be written to the pixel circuit Pix(i,j) changes from the level of the data signal D(j) to be written to the pixel circuit Pix(i-1,j) of the previous row, such as when the level changes from the white voltage Vw to the black voltage Vb as shown in Figure 7, or when the level changes from the black voltage Vb to the white voltage Vw as shown in Figure 10, the period from when the data signal D(j) starts to change until the end of the writing period Tw is shortened because the hold time ThVD is the minimum hold time ThVD(min). As a result, even if the nearby high-level power supply voltage VNelvdd fluctuates due to a change in the level of the data signal D(j) caused by the parasitic capacitance Cil between the data signal line Dj and the high-level power supply line Lelvdd, the amount of fluctuation ΔVelvdd2 (>0) at the end of the writing period Tw for the pixel circuit Pix(i,j) becomes significantly smaller than in the conventional example. As a result, even when displaying a black rectangular pattern BR1, etc., with a long side extending horizontally against a white background, in low-speed drive mode as shown in Figure 5(C), the increase or decrease in brightness due to fluctuations in the nearby high-level power supply voltage VNelvdd is significantly reduced compared to conventional methods, and display problems such as the visibility of bright or dark lines extending horizontally from the upper and lower long edges of the black rectangular pattern BR1, etc., are eliminated. More generally, according to this embodiment described above, display problems caused by crosstalk resulting from voltage changes in the data signal line Dj are eliminated or mitigated.

[0078] <8. Modifications> The present invention is not limited to the embodiments described above, and various modifications can be made without departing from the scope of the present invention. For example, the following modifications are possible.

[0079] The above embodiment targets a variable refresh rate display device having two drive modes consisting of a high-speed drive mode and a low-speed drive mode, but it may have three or more drive modes with different refresh rates. For a display device having three or more drive modes with different refresh rates, as shown in Figure 5(C), when a horizontally long black rectangular pattern BR1 is displayed against a white background, the configuration of the above embodiment can be applied by selecting a low-speed drive mode and a high-speed drive mode from among the three or more drive modes, depending on whether or not a display problem occurs in which bright or dark lines extending from the long edge of the rectangular pattern BR1 are visible. Generally, regardless of the number of drive modes provided in the display device, if there is a drive mode with a relatively high refresh rate that does not cause the above display problem, and a drive mode with a relatively low refresh rate that does cause the above display problem, the former can be designated as the high-speed drive mode and the latter as the low-speed drive mode, and the configuration of the above embodiment can be applied. More generally, the configuration of the above embodiment is applicable to any variable refresh rate display device having a high-speed drive mode with a relatively high refresh rate and a low-speed drive mode with a refresh rate lower than that of the high-speed drive mode. Furthermore, the hold time to be set in the low-speed drive mode is preferably equal to the minimum hold time ThVD(min) that can be set in the display device, or the minimum time required as the hold time ThVD for the scanning signal SC(i) of the data signal D(j) in the pixel circuit Pix(i,j). However, it is not necessarily the minimum hold time ThVD(min) that can be set or the minimum required time, and may be equal to the hold time ThVD of the high-speed drive mode, which is longer than these time lengths. To add further, if a hold time substantially shorter than the hold time corresponding to the drive speed in the low-speed drive mode is set, display problems due to crosstalk caused by voltage changes in the data signal line Dj, as shown in Figure 5(C), will be reduced.

[0080] In the above embodiment, the high-level power line Lelvdd in the display unit 10 includes power lines arranged along data signal lines D1 to Dm and power lines arranged along scan signal lines SC1 to SCn, as shown in Figure 5(A). However, the high-level power line Lelvdd may be configured to include power lines arranged along data signal lines D1 to Dm but not power lines arranged along scan signal lines SC1 to SCn. In this case, even if a black rectangular pattern BR1, etc., as shown in Figure 5(C) is displayed in the conventional example, no bright or dark lines are visible on the lines extending horizontally from the long edge of the rectangular pattern BR1, etc. However, a display problem may occur in which the brightness of the long edge of the rectangular pattern BR1, etc. decreases or increases compared to the original brightness (see the Vg(is,jb) and Vg(ie+1,jb) waveforms shown in Figures 6 and 9). However, according to this embodiment, as described above, the data signal line Dj and the scan signal line SCi are driven so that the hold time ThVD becomes the minimum hold time ThVD(min) (i=1 to n, j=1 to m), so the amount of fluctuation |ΔVg| of the gate voltage Vg(is, jb) and Vg(ie+1, jb) in the pixel circuits Pix(is, jb) and Pix(ie+1, jb) that form the pixels at the long edge of the black rectangular pattern BR1 becomes significantly smaller than in the conventional case (see Figures 7 and 10). Therefore, the above configuration regarding the hold time ThVD in the above embodiment is effective in solving the display problem in which the brightness at the long edge of the black rectangular pattern BR1, etc. decreases or increases compared to the original brightness, even when the high-level power line Lelvdd does not include power lines arranged along the scan signal lines SC1 to SCn.

[0081] In the above embodiment, the transistors T1 to T7 included in the pixel circuit 15 are all P-channel type transistors (e.g., LTPS), and an internal compensation method as shown in Figure 4 is employed, but is not limited to this. N-channel type transistors (e.g., IGZO-TFTs) may be used for all or some of the transistors included in the pixel circuit 15. Alternatively, a pixel circuit that does not include a configuration for internal compensation may be used instead of the pixel circuit 15 with the internal compensation method shown in Figure 4. In such a pixel circuit, initialization of the holding capacitor Cst (initialization of the gate voltage Vg) is not necessarily required, so the first initialization transistor T1 may be omitted. In this case, if the second initialization transistor T7 is controlled by the scanning signal line SCi, the DIS driver 211 as an initialization control circuit becomes unnecessary in the scanning-side drive circuit 20. Furthermore, even when using an internal compensation type pixel circuit 15 as shown in Figure 4, if the size of the display unit 10 is relatively small and the initialization of the holding capacitor Cst in the pixel circuit 15 does not require a large driving capability, the DIS driver 211 may be omitted, and the SC driver 212 may act as a scanning signal line driving circuit to drive both the scanning signal lines SC1 to SCn and the initialization control lines DIS0 to DISn.

[0082] In the above, embodiments have been described using an organic EL display device as an example, but the present invention is not limited to organic EL display devices, and can be applied to any display device using a display element driven by electric current. Examples of display elements that can be used here include organic EL elements, i.e., organic light-emitting diodes (OLEDs), as well as inorganic light-emitting diodes and quantum dot light-emitting diodes (QLEDs).

[0083] 10...Display unit 15...Pixel circuit 20...Scanning drive circuit 30...Data signal line drive circuit 40...Display control circuit 211...DIS driver (initialization control circuit) 212...SC driver (scanning signal line drive circuit) 213...EM driver (light emission control circuit) Pix(i,j)...Pixel circuit (i=1 to n, j=1 to m) OL...Organic EL element Cst...Holding capacitor T1...First initialization transistor T2...Threshold compensation transistor T3...Write control transistor T4...Drive transistor D1 to Dm...Data signal line SC1 to SCn...Scanning signal line DIS0 to DISn...Initialization control line Lelvdd...High-level power line Lelvss...Low-level power line ELVDD...High-level power voltage ELVSS...Low-level power voltage BR1 to BR3...Black rectangular pattern Tw...Write period

Claims

1. A variable refresh rate display device having a high-speed drive mode with a relatively high refresh rate and a low-speed drive mode with a refresh rate lower than the refresh rate of the high-speed drive mode, comprising: a display unit including a plurality of data signal lines, a plurality of scan signal lines intersecting the plurality of data signal lines, a plurality of pixel circuits arranged along the plurality of data signal lines and the plurality of scan signals, a first power line, and a second power line; a data signal line drive circuit that applies a plurality of data signals representing an image to be displayed to each of the plurality of data signal lines; a scan signal line drive circuit that applies a plurality of scan signals that become active sequentially for predetermined periods to each of the plurality of scan signal lines; and a display control circuit that controls the data signal line drive circuit and the scan signal line drive circuit, wherein each of the plurality of pixel circuits includes: a display element driven by current; a holding capacitor; a drive transistor having a gate terminal connected to the first power line via the holding capacitor, a source terminal connected to the first power line, and a drain terminal connected to the second power line via the display element, and controlling the amount of current supplied to the display element according to the voltage written to the holding capacitor, A display device comprising a write control switching element having a control terminal connected to one of the plurality of scan signal lines and controlling whether or not to write the voltage of one of the plurality of data signal lines as a data voltage to the holding capacitor, the first power line comprising a power line arranged along the plurality of data signal lines, and the display control circuit controlling the data signal line drive circuit and the scan signal line drive circuit in each of the plurality of pixel circuits such that the hold time that the data signal of one data signal line has with respect to the scan signal of one scan signal line in the low-speed drive mode is shorter than the hold time corresponding to the drive speed in the low-speed drive mode.

2. The display device according to claim 1, wherein the display control circuit controls the data signal line drive circuit and the scan signal line drive circuit in each of the plurality of pixel circuits such that the hold time of the data signal of one data signal line with respect to the scan signal of one scan signal line in the low-speed drive mode is substantially the same as the hold time of the data signal with respect to the scan signal in the high-speed drive mode.

3. The display device according to claim 1, wherein the display control circuit controls the data signal line drive circuit and the scan signal line drive circuit in each of the plurality of pixel circuits such that the hold time of the data signal of one data signal line with respect to the scan signal of one scan signal line in the low-speed drive mode is the minimum length that can be set in the display device.

4. The display device according to claim 1, wherein the display control circuit controls the data signal line drive circuit and the scan signal line drive circuit in each of the plurality of pixel circuits such that the hold time of the data signal of one data signal line with respect to the scan signal of one scan signal line in the low-speed drive mode is the minimum length required as the hold time of the data signal with respect to the scan signal.

5. The display device according to any one of claims 1 to 4, wherein the first power line further includes power lines arranged along the plurality of scanning signal lines.

6. The display unit further includes a light emission control circuit, wherein the display unit further includes a plurality of light emission control lines arranged along the plurality of scan signal lines and an initialization voltage line, the light emission control circuit applies a plurality of light emission control signals that are sequentially deactivated to each of the plurality of light emission control lines, the display control circuit controls the light emission control circuit so that the plurality of light emission control signals are applied to the plurality of light emission control lines in conjunction with the plurality of scan signals, each of the plurality of pixel circuits further includes a threshold compensation switching element having a control terminal connected to one of the scan signal lines, a first conductive terminal connected to the gate terminal of the drive transistor, and a second conductive terminal connected to the drain terminal of the drive transistor, a power supply control switching element having a control terminal connected to one of the plurality of light emission control lines, a light emission control switching element having a control terminal connected to one of the light emission control lines, and an initialization switching element for initializing the holding capacitor, the gate terminal of the drive transistor is connected to the initialization voltage line via the initialization switching element. The display device according to any one of claims 1 to 4, wherein the source terminal of the drive transistor is connected to the one data signal line via the write control switching element and to the first power line via the power supply control switching element, and the drain terminal of the drive transistor is connected to the display element via the light emission control switching element.

7. The display device according to any one of claims 1 to 6, wherein the drive transistor is of the P-channel type.

8. A method for driving a variable refresh rate display device having a high-speed drive mode in which the refresh rate is relatively high and a low-speed drive mode in which the refresh rate is lower than the refresh rate of the high-speed drive mode, wherein the display device comprises a display unit including a plurality of data signal lines, a plurality of scan signal lines intersecting the plurality of data signal lines, a plurality of pixel circuits arranged along the plurality of data signal lines and the plurality of scan signals, a first power line, and a second power line, each of the plurality of pixel circuits includes a display element driven by current, a holding capacitor, a drive transistor having a gate terminal connected to the first power line via the holding capacitor, a source terminal connected to the first power line, and a drain terminal connected to the second power line via the display element, and controlling the amount of current supplied to the display element according to the voltage written to the holding capacitor, and a write control switching element having a control terminal connected to one of the plurality of scan signal lines, and controlling whether or not to write the voltage of one of the plurality of data signal lines as a data voltage to the holding capacitor, the first power line includes a power line arranged along the plurality of data signal lines. The driving method includes: a data signal line driving step of applying a plurality of data signals representing an image to be displayed to a plurality of data signal lines; a scan signal line driving step of applying a plurality of scan signals that become active sequentially for a predetermined period to a plurality of scan signal lines; and a display control step of controlling the data signal line driving step and the scan signal line driving step in each of the plurality of pixel circuits such that the hold time that the data signal of one data signal line has with respect to the scan signal of one scan signal line in the low-speed driving mode is shorter than the hold time corresponding to the driving speed in the low-speed driving mode.

9. The driving method according to claim 8, wherein the display control step controls the data signal line driving step and the scan signal line driving step in each of the plurality of pixel circuits such that the hold time of the data signal of one data signal line with respect to the scan signal of one scan signal line in the low-speed driving mode is substantially the same as the hold time of the data signal with respect to the scan signal in the high-speed driving mode.

10. The driving method according to claim 8, wherein the display control step controls the data signal line driving step and the scan signal line driving step in each of the plurality of pixel circuits such that the hold time of the data signal of one data signal line with respect to the scan signal of one scan signal line in the low-speed driving mode is the minimum length that can be set in the display device.

11. The driving method according to claim 8, wherein the display control step controls the data signal line driving step and the scan signal line driving step in each of the plurality of pixel circuits such that the hold time of the data signal of one data signal line with respect to the scan signal of one scan signal line in the low-speed driving mode is the minimum length required as the hold time of the data signal with respect to the scan signal.

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