Current or voltage detection circuit

Abstract

This current or voltage detection circuit comprises: first wiring (10) that has a first wave shape that is formed by alternating first peak parts (11) and first valley parts (12); and second wiring (20) that has a second wave shape that is formed by alternating second valley parts (22) and second peak parts (21). The first wiring (10) and the second wiring (20) are electrically insulated by an insulating layer (103), and when viewed from a first direction from which the first wave shape and the second wave shape can be seen, the first wiring (10) and the second wiring (20) three-dimensionally intersect at a plurality of intersections (40). First regions (41) formed by the first peak parts (11) and the second valley parts (22) and second regions (42) formed by the second peak parts (21) and the first valley parts (12) alternate with the intersections (40) therebetween.

Description

Current or voltage detection circuit

[0001] The present disclosure relates to a current or voltage detection circuit.

[0002] For the purpose of, among other things, improving the accuracy of control of a power conversion device performed based on a detected value of current or voltage (hereinafter referred to as current or the like), it is required to accurately detect current or the like. As a method of detecting current, there is a method of detecting current by inserting a shunt resistor into a current path through which the current to be detected flows and detecting the voltage generated across this resistor. When detecting current by this method, the signal transmitted by the detection wiring connected to both ends of the resistor may be affected by external noise, and the accuracy of detecting current may decrease. In particular, when a main circuit, which is a high-power circuit through which a large current flows, and a detection circuit, which is a low-power circuit through which a weak signal for detecting current or voltage flows, are arranged close to each other, the detection wiring is likely to be affected by external noise generated by the main circuit, so it is necessary to reduce the influence of external noise.

[0003] As a technique for reducing the influence of external noise in a detection circuit that detects current using a shunt resistor, for example, in Patent Document 1, two sets of detection circuits each composed of a shunt resistor, two detection wirings, and a differential operation unit are provided on a printed circuit board, and when two sets of detection wirings connected to terminals of differential operation units having opposite polarities are arranged close to each other, external noise of opposite polarity is superimposed on the signals detected by each detection circuit. Therefore, a current detection circuit is disclosed in which these signals are added together to cancel out the external noise, and current can be detected without being affected by the external noise.

[0004] Japanese Patent Application Laid-Open No. 2017 - 28859

[0005] In the current detection circuit described above, in order to achieve close proximity of the two sets of detection wiring, the two sets of detection circuits are arranged symmetrically with respect to the printed circuit board. From this, it is clear that in order to reduce the influence of external noise, the two sets of detection wiring must be placed in close proximity. However, in cases where there is competition with power supply patterns and other wiring, or when it is necessary to reduce the coupling capacitance caused by the wiring, these two sets of detection wiring cannot be placed in close proximity, and the influence of external noise cannot be reduced using the above current detection circuit.

[0006] This disclosure is made to solve the above-mentioned problems and provides a current or voltage detection circuit that can detect current or voltage with high accuracy while reducing the influence of external noise, even when two sets of detection wiring cannot be placed close together.

[0007] The current or voltage detection circuit according to this disclosure is a current or voltage detection circuit installed alongside the current path of a power converter, comprising: a circuit board in which a first wiring layer and a second wiring layer are provided separated by an insulating layer; a detection resistor provided in the first wiring layer through which the current to be detected flows; a differential voltage detection unit provided in the first or second wiring layer for detecting the voltage across the detection resistor; a first wiring connected to one end of the detection resistor and the differential voltage detection unit, having a first waveform shape in which first peaks and first valleys are alternately formed, and arranged in at least one of the first wiring layer and the second wiring layer; and detection The other end of the resistor is connected to the differential voltage detection unit, and the device comprises a second wiring having a second waveform shape in which second valleys and second peaks are formed alternately, and a second wiring arranged on at least one of the first wiring layer and the second wiring layer, wherein the first wiring and the second wiring are electrically insulated by an insulating layer, and when viewed from a first direction in which the first waveform shape and the second waveform shape can be seen, there are multiple intersection points where the first wiring and the second wiring intersect three-dimensionally, and a first region formed by the first peaks and second valleys and a second region formed by the second peaks and first valleys are arranged alternately adjacent to each other with the intersection points in between.

[0008] The current or voltage detection circuit according to this disclosure has multiple intersection points where the first and second wirings connecting the detection resistor and the differential voltage detection unit, which are provided on the substrate, intersect three-dimensionally, even when the two sets of detection wirings cannot be placed close together. By arranging the first and second regions alternately adjacent to each other with respect to these intersection points, the current induced by electromagnetic noise linking the first region and the current induced by electromagnetic noise linking the second region are in opposite directions. As a result, the influence of external noise on the signals transmitted by the two detection wirings is canceled out, and the current or voltage can be detected with high accuracy.

[0009] This is a diagram showing an example of the configuration of a detection circuit according to Embodiment 1. This is a partially enlarged view of the detection circuit according to Embodiment 1. This is a partially enlarged view of the detection circuit according to Embodiment 1. This is a view of the detection circuit according to Embodiment 1 as seen from direction A shown in Figure 1. This is a diagram showing an example of the configuration of a detection circuit according to Embodiment 1. This is a partially enlarged view of the detection circuit according to Embodiment 1. This is an example of the configuration of a power converter and detection circuit according to Embodiment 1. This is an example of the configuration of a power converter and detection circuit according to Embodiment 1. This is a diagram showing an example of the configuration of a detection circuit according to Embodiment 2. This is a diagram showing an example of the configuration of a detection circuit according to Embodiment 2. This is a partially enlarged view of the detection circuit according to Embodiment 2. This is a partially enlarged view of the detection circuit according to Embodiment 2. This is a diagram showing an example of the configuration of a detection circuit according to Embodiment 34. This is a diagram showing an example of the configuration of a detection circuit according to Embodiment 5.

[0010] The embodiments will be described in detail below with reference to the drawings. Note that the embodiments described below are illustrative examples. Furthermore, each embodiment can be combined as appropriate.

[0011] Embodiment 1. The current or voltage detection circuit according to Embodiment 1 will be described with reference to Figures 1 to 8.

[0012] Figure 1 is a diagram showing an example of the configuration of a detection circuit according to Embodiment 1. The top view shown in Figure 1 is a view from the top side of the circuit board 100 on which the detection circuit is formed, and the first wiring 10 arranged on the second wiring layer 102 and the first wiring 10 and second wiring 20 arranged below the detection resistor 1 are shown by dashed lines. The B-B cross-sectional view shown in Figure 1 is a diagram showing the B-B cross-section of the top view, and for convenience, the first wiring 10 and the second wiring 20 are shown together. In the B-B cross-sectional view shown in Figure 1, wiring connected to via 30 located in the foreground is shown as connected to via 30, and wiring not connected to via 30 located in the foreground is shown as not connected to via 30.

[0013] The detection circuit is configured by mounting a detection resistor 1, a differential voltage detection unit 2, a first wiring 10, and a second wiring 20 on a circuit board 100.

[0014] The circuit board 100 comprises a first wiring layer 101, a second wiring layer 102, and an insulating layer 103. The insulating layer 103 is provided between the first wiring layer 101 and the second wiring layer 102, electrically insulating the first wiring layer 101 and the second wiring layer 102. Examples of the circuit board 100 include, but are not limited to, two-layer boards and multilayer boards.

[0015] As shown in the cross-sectional view B-B of Figure 1, for example, the detection circuit is mounted across the first wiring layer 101 and the second wiring layer 102 of the circuit board 100.

[0016] The detection resistor 1 is a resistor through which the current to be detected flows, and in Figure 1, the detection resistor 1 is provided on the first wiring layer 101. In order to allow the current to be detected to flow through the detection resistor 1, for example, as shown in the top view of Figure 1, the detection resistor 1 is connected to the first wiring pattern 104 and the second wiring pattern 105 through the first land 106 and the second land 107, through the first land 106 and the second land 107. Here, the first wiring pattern 104 and the second wiring pattern 105 are provided on the first wiring layer 101, the first land 106 is provided on the first wiring pattern 104, and the second land 107 is provided on the second wiring pattern 105.

[0017] The differential voltage detection unit 2 is connected to both ends of the detection resistor 1 by the first wiring 10 and the second wiring 20, and detects the voltage across the detection resistor 1. In Figure 1, the differential voltage detection unit 2 is provided on the first wiring layer 101. However, the wiring layer on which the differential voltage detection unit 2 is provided is not limited to the first wiring layer 101; the differential voltage detection unit 2 may also be provided on the second wiring layer 102, as long as it is connectable to both ends of the detection resistor 1 by the first wiring 10 and the second wiring 20.

[0018] The first wiring 10 connects one end of the detection resistor 1 to the differential voltage detection unit 2. The first wiring 10 has a first waveform shape in which first peaks 11 and first valleys 12 are formed alternately. In Figure 1, the portion of the first wiring 10 connecting from the point where it is connected to the first land 106 to via 30 is placed on the first wiring layer 101, and via 30 causes it to be transposed from the first wiring layer 101 to the second wiring layer 102, the portion connecting via 30 to via 30 is placed on the second wiring layer 102, via 30 causes it to be transposed from the second wiring layer 102 to the first wiring layer 101, and the portion connecting via 30 to the differential voltage detection unit 2 is placed on the first wiring layer 101.

[0019] The second wiring 20 connects the other end of the detection resistor 1 to the differential voltage detection unit 2. The second wiring 20 has a second waveform shape in which second valleys 22 and second peaks 21 are formed alternately. In Figure 1, the portion of the second wiring 20 connecting from the point where it is connected to the second land 107 to the differential voltage detection unit 2 is arranged on the first wiring layer 101.

[0020] Here, the top view of Figure 1 shows a first waveform shape for the first wiring 10 and a second waveform shape for the second wiring 20, in which the first peak 11, first valley 12, second peak 21, and second valley 22 each have flat portions. However, these are just examples, and the waveform shape may also be one in which the first peak 11, first valley 12, second peak 21, and second valley 22 do not have flat portions.

[0021] Note that the location where the via 30 is provided is not limited to the location shown in Figure 1. For example, if the first wiring 10 is arranged on the first wiring layer 101 and the second wiring 20 is arranged on the second wiring layer 102, the via 30 may be provided on the second wiring 20 in order to connect the detection resistor 1 and differential voltage detection unit 2 of the first wiring layer 101 to the second wiring 20 of the second wiring layer 102.

[0022] As shown in the top view of Figure 1, when viewing the detection circuit from the top side of the circuit board 100, the first waveform shape of the first wiring 10 and the second waveform shape of the second wiring 20 can be visually observed. In this case, a first direction from which the first and second waveform shapes can be visually observed is, for example, a direction perpendicular to the circuit board 100. However, the first direction from which the first and second waveform shapes can be visually observed is not limited to this, and any direction from which the top surface of the circuit board 100 can be viewed at an angle may also be used, as long as the first and second waveform shapes can be visually observed.

[0023] Figure 2 is an enlarged view of the first wiring 10 and the second wiring 20 within X1, which is enclosed by the dotted line in the top view of Figure 1.

[0024] In Figure 2, the first wiring 10 is located on the second wiring layer 102, and the second wiring 20 is located on the first wiring layer 101. In other words, the first wiring 10 and the second wiring 20 are located only on different wiring layers from the first wiring layer 101 and the second wiring layer 102.

[0025] The first wiring 10 and the second wiring 20 intersect three-dimensionally at multiple intersection points 40. Furthermore, the first wiring 10 and the second wiring 20 are arranged such that the first region 41, formed by the first peak 11 of the first wiring 10 and the second valley 22 of the second wiring 20, and the second region 42, formed by the second peak 21 of the second wiring 20 and the first valley 12 of the first wiring 10, alternately occupy adjacent spaces on either side of the intersection points 40.

[0026] In this way, by arranging the first wiring 10 and the second wiring 20 so that the first region 41 and the second region 42 are alternately adjacent to each other with the intersection point 40 in between, the current induced by the electromagnetic noise linking the first region 41 and the current induced by the electromagnetic noise linking the second region 42 are in opposite directions in the first wiring 10 and the second wiring 20, so that the influence of external noise on the signals transmitted by the two detection wirings is canceled out.

[0027] As a specific example, using the enlarged view of the first wiring 10 and the second wiring 20 shown in Figure 3, we will explain the case where electromagnetic noise occurs from the back of the page in Figure 3 towards the front. Due to this electromagnetic noise, current flows to the right in the first peak 11 and the second peak 21. Also, due to this electromagnetic noise, current flows to the left in the first valley 12 and the second valley 22. Therefore, the direction of the current flowing in the first peak 11 and the first valley 12 of the first wiring 10 is opposite, and these currents cancel each other out. Similarly, the direction of the current flowing in the second peak 21 and the second valley 22 of the second wiring 20 is opposite, and these currents cancel each other out. In this way, the currents flowing in the first wiring 10 and the second wiring 20 due to electromagnetic noise are canceled out within each wiring, and the influence of external noise on the signals transmitted by the two detection wirings is canceled out.

[0028] Furthermore, by arranging the first wiring 10 and the second wiring 20 so that there are three or more intersection points 40, at least one first region 41 and one second region 42 are formed between adjacent intersection points 40, thus further reducing the influence of external noise.

[0029] Furthermore, by arranging the first wiring 10 and the second wiring 20 so that there are an odd number of intersection points 40, the same number of first regions 41 and second regions 42 are formed, the currents generated in the first peaks 11 and the first valleys 12 cancel each other out, and the currents generated in the second peaks 21 and the second valleys 22 cancel each other out, thus further reducing the influence of external noise.

[0030] Furthermore, by arranging the first wiring 10 and the second wiring 20 such that the areas of the first region 41 and the second region 42 are equal when viewed from a first direction from which the first and second waveform shapes can be seen, the influence of external noise on each of the first region 41 and the second region 42 becomes equal, thus further reducing the influence of external noise.

[0031] Furthermore, by not only making the areas of the first region 41 and the second region 42 equal, but also by making the shapes of the first region 41 and the second region 42 the same, the influence of external noise is further reduced. As a specific example of making the shapes of the first region 41 and the second region 42 the same, for example, as shown in the top view of Figure 1, the first wiring 10 and the second wiring 20 are arranged such that the first peak 11 and the second valley 22 have portions that are parallel to each other, and the second peak 21 and the first valley 12 have portions that are parallel to each other. As a result, the first peak 11 and the second valley 22 are symmetrical with respect to the line connecting adjacent intersection points 40, and the second peak 21 and the first valley 12 are symmetrical with respect to the line connecting adjacent intersection points 40. As a result, the first region 41 and the second region 42, which are formed alternately, are formed to have similar shapes, and the influence of external noise is further reduced.

[0032] Furthermore, as shown in the top view of Figure 1, the first wiring 10 and the second wiring 20 are connected to the first land 106 and the second land 107 at the bottom of the detection resistor 1, and are arranged so that the wiring is drawn out toward the space between the first land 106 and the second land 107.

[0033] Figure 4 shows a view of the detection circuit from direction A as shown in the top view of Figure 1. The first land 106 is provided on the first wiring pattern 104 and connects one end of the detection resistor 1 to the first wiring pattern 104. The second land 107 is provided on the second wiring pattern 105 and connects the other end of the detection resistor 1 to the second wiring pattern 105. The first connection part 108 is provided below the detection resistor 1 and is connected to the portion of the first land 106 facing the second land 107. The second connection part 109 is provided below the detection resistor 1 and is connected to the portion of the second land 107 facing the first land 106. The first wiring 10 is connected to the first connection part 108, and the second wiring 20 is connected to the second connection part 109.

[0034] When the current to be detected flows from the first wiring pattern 104 to the second wiring pattern 105, the current flows in the following order: first wiring pattern 104, first land 106, detection resistor 1, second land 107, and second wiring pattern 105. Therefore, even if the first connection part 108 and the second connection part 109, which are provided between the first land 106 and the second land 107, are connected to the first wiring 10 and the second wiring 20, the current to be detected does not flow through the first wiring 10 and the second wiring 20. As a result, the differential voltage detection unit 2 connected to the first wiring 10 and the second wiring 20 detects only the voltage across the detection resistor 1, and can therefore detect current or voltage with high accuracy.

[0035] Furthermore, in the detection circuit shown in Figure 1, the first wiring 10 and the second wiring 20 are arranged only on different wiring layers from the first wiring layer 101 and the second wiring layer 102. In this case, in order to reduce the influence of external noise, the first wiring 10 and the second wiring 20 should be arranged on their respective wiring layers so that they intersect three-dimensionally, forming the first region 41 and the second region 42. Therefore, it is not necessary to provide a new via 30 to intersect the first wiring 10 and the second wiring 20 three-dimensionally, and the influence of external noise can be reduced without increasing the man-hours required for implementing the detection circuit. Moreover, since there is no need for a gap between the first wiring 10 and the second wiring 20 to provide a via 30, and the amplitude of the first waveform shape of the first wiring 10 and the second waveform shape of the second wiring 20 can be freely determined, by reducing this amplitude, the range in which the first wiring 10 and the second wiring 20 are arranged can be narrowed, thereby improving the design freedom of the circuit board 100 or other structures in the device in which the detection circuit is provided.

[0036] As described above, one embodiment of Embodiment 1 is the case in which the first wiring 10 and the second wiring 20 each have a wave shape that meanders in a plane on the circuit board 100. However, another embodiment is the case in which the first wiring 10 and the second wiring 20 have a wave shape that meanders in a direction perpendicular to the circuit board 100. Thus, as another embodiment of Embodiment 1, the first wiring 10 and the second wiring 20 may be arranged such that, when viewed from the top side of the circuit board 100, there are no intersection points 40, first region 41 and second region 42, but when viewed in cross-section of the circuit board 100, there are intersection points 40, first region 41 and second region 42.

[0037] Specific examples of other embodiments according to Embodiment 1 will be described with reference to Figure 5. The top view shown in Figure 5 is a view from the top side of the circuit board 100 on which the detection circuit is formed, and the first wiring 10 and second wiring 20 arranged in the second wiring layer 102 and the first wiring 10 and second wiring 20 arranged below the detection resistor 1 are shown by dashed lines. The C-C cross-sectional view shown in Figure 5 is a view of the C-C cross-section of the top view, and for convenience, the first wiring 10 and the second wiring 20 are shown together. In the C-C cross-sectional view shown in Figure 5, wiring connected to via 30 located in the foreground is shown as being connected to via 30, and wiring connected to via 30 located in the background is shown as not being connected to via 30.

[0038] In Figure 5, the first wiring 10 and the second wiring 20 are transposed between the first wiring layer 101 and the second wiring layer 102, respectively, by a plurality of vias 30. In the top view of Figure 5, the vias 30 on the first wiring 10 and the vias 30 on the second wiring 20 are positioned in the same location along the direction in which the first wiring 10 and the second wiring 20 are routed, and in the cross-sectional view C-C of Figure 5, these vias 30 are shown overlapping.

[0039] Figure 6 is an enlarged view of the first wiring 10 and the second wiring 20 within Y1, enclosed by the dotted line shown in the C-C cross-sectional view of Figure 5. As shown in the top view of Figure 5, the first wiring 10 and the second wiring 20 are straight wirings when viewed from the top side of the circuit board 100. On the other hand, as shown in Figure 6, when viewing the C-C cross-section of the detection circuit shown in the top view of Figure 5, the first wiring 10 has a first waveform shape, and the second wiring 20 has a second waveform shape. In this case, a first direction from which the first and second waveform shapes can be seen is, for example, a direction parallel to the circuit board 100 and perpendicular to the direction in which the first wiring 10 and the second wiring 20 are wired. Note that the first direction from which the first and second waveform shapes can be seen is not limited to this, and any direction from which the first and second waveform shapes can be seen may be a direction from which the side of the circuit board 100 is viewed at an angle.

[0040] As shown in Figure 6, the first wiring 10 and the second wiring 20 intersect three-dimensionally at multiple intersection points 40. Furthermore, the first wiring 10 and the second wiring 20 form a first region 41 and a second region 42 that are alternately adjacent to each other with the intersection points 40 in between.

[0041] Thus, in the detection circuit shown in Figure 5, the first wiring 10 and the second wiring 20 are arranged so that the first region 41 and the second region 42 are alternately adjacent to each other with the intersection point 40 in between. Therefore, similar to the detection circuit shown in Figure 1, the influence of external noise is reduced.

[0042] The positions in which the vias 30 on the first wiring 10 and the vias 30 on the second wiring 20 are arranged are not limited to the positions shown in Figure 5. The vias 30 should be arranged such that the first region 41 and the second region 42 are formed by the first wiring 10 and the second wiring 20, alternately adjacent to each other with the intersection point 40 in between.

[0043] By installing the aforementioned detection circuit alongside the current path flowing through the power converter and using it to detect current or voltage within the power converter, the influence of external noise can be reduced, current or voltage can be detected with high accuracy, and the control of the power converter can be made more precise.

[0044] As a power conversion device provided with a detection circuit, for example, an inverter for a compressor can be cited. A specific example of the detection circuit provided in the inverter for a compressor is shown in FIG. 7. As shown in FIG. 7, the inverter for a compressor is a circuit provided on a circuit board 100, which connects a power supply 111 and a compressor 112 and includes a converter circuit 113, an inverter circuit 114, and a control unit 115. In such an inverter for a compressor, for example, as shown in FIG. 7, a detection resistor 1 of the detection circuit is inserted into the current path connecting the converter circuit 113 and the inverter circuit 114, and a differential voltage detection unit 2 provided in the control unit 115 and the detection resistor 1 are connected by a first wiring 10 and a second wiring 20. Here, the inverter for a compressor and the detection circuit are provided on the same circuit board 100. By using such a detection circuit, the current or voltage of the current path in the inverter for a compressor can be detected with high accuracy, and based on this detection result, the control unit 115 can accurately control the inverter for a compressor.

[0045] Note that the position where the detection circuit is provided in the inverter for a compressor is not limited to the position shown in FIG. 7. Also, the power conversion device provided with the detection circuit is not limited to the inverter for a compressor.

[0046] Furthermore, as shown in FIG. 8, when the first wiring 10 and the second wiring 20 of the detection circuit are arranged along the current path of the current flowing through the power conversion device, electromagnetic noise is generated by the flow of current in this current path. Therefore, the levels of the electromagnetic noise linked to the first region 41 and the second region 42 become substantially equal, and the induced currents generated along with this electromagnetic noise also become substantially equal. As a result, these induced currents cancel each other out, and the influence received from external noise can be further reduced. Furthermore, since the first wiring 10 and the second wiring 20 can be arranged along the current path of the current flowing through the power conversion device without being affected by external noise in this way, the space required for installing the detection circuit is reduced, and the design freedom is improved.

[0047] As described above, the current or voltage detection circuit according to Embodiment 1 has a plurality of intersection points 40 where the first wiring 10 and the second wiring 20 intersect three-dimensionally, and the first region 41 and the second region 42 are alternately adjacent to each other with the intersection points 40 interposed therebetween. In this way, the first wiring 10 and the second wiring 20 are arranged. According to such a configuration, even when the first wiring 10 and the second wiring 20 cannot be arranged close to each other sufficiently, the influence of electromagnetic noise that links the first region 41 and the second region 42 is canceled out, so the influence received from external noise is reduced. As a result, the current or voltage can be detected with high accuracy.

[0048] Furthermore, in Embodiment 1, the first wiring 10 and the second wiring 20 are arranged only in different wiring layers among the first wiring layer 101 and the second wiring layer 102. According to such a configuration, since it is not necessary to provide vias 30 for intersecting the first wiring 10 and the second wiring 20 three-dimensionally, the influence received from external noise can be reduced without increasing the man-hours required for mounting the detection circuit. Further, the interval between the first wiring 10 and the second wiring 20 for providing the vias 30 becomes unnecessary, and the amplitudes of the first waveform shape of the first wiring 10 and the second waveform shape of the second wiring 20 can be freely determined, so the range in which the first wiring 10 and the second wiring 20 are arranged can be narrowed, and the degree of freedom in designing other structures on the circuit board 100 or in the device where the detection circuit is provided is improved.

[0049] Embodiment 2. The current or voltage detection circuit according to Embodiment 2 will be described with reference to FIGS. 9 to 11. In Embodiment 2, the same reference numerals are given to the same components as those in Embodiment 1 described above, and the configuration different from that of Embodiment 1 will be mainly described.

[0050] Figure 9 shows an example of the configuration of a detection circuit according to Embodiment 2. The top view shown in Figure 9 is a view from the top side of the circuit board 100 on which the detection circuit is formed, and the first wiring 10 arranged in the second wiring layer 102 and the first wiring 10 and second wiring 20 arranged below the detection resistor 1 are shown by dashed lines. The D-D cross-sectional view shown in Figure 9 shows the D-D cross-section of the top view, and for convenience, the first wiring 10 and the second wiring 20 are shown together. In the D-D cross-sectional view shown in Figure 9, wiring connected to the first via 31 or second via 32 located in the foreground is shown as being connected to the first via 31 or second via 32, and wiring connected to the first via 31 or second via 32 located in the background is shown as not being connected to the first via 31 or second via 32.

[0051] In the second embodiment, the detection circuit further includes a first via 31 and a second via 32.

[0052] The first via 31 is provided on the first wiring 10 and electrically connects the first wiring layer 101 and the second wiring layer 102. The first wiring 10 is transposed between the first wiring layer 101 and the second wiring layer 102 by the first via 31.

[0053] The second via 32 is provided on the second wiring 20 and electrically connects the first wiring layer 101 and the second wiring layer 102. The second wiring 20 is transposed between the first wiring layer 101 and the second wiring layer 102 by the second via 32.

[0054] In the top view of Figure 9, the first via 31 and the second via 32 are positioned at the same location along the direction in which the first wiring 10 and the second wiring 20 are routed, and in the cross-sectional view D-D of Figure 9, these first via 31 and second via 32 are shown overlapping.

[0055] In Figure 9, the first wiring 10 is transposed between the first wiring layer 101 and the second wiring layer 102 by a plurality of first vias 31, and the second wiring 20 is transposed between the first wiring layer 101 and the second wiring layer 102 by a plurality of second vias 32. As a result, the first wiring 10 and the second wiring 20 move back and forth between the two wiring layers, and the first wiring 10 and the second wiring 20 intersect three-dimensionally at the intersection point 40. Consequently, an enlarged view of the first wiring 10 and the second wiring 20 within X2 enclosed by the dotted line in the top view of Figure 9 is shown in the same way as in Figure 2, and an enlarged view of the first wiring 10 and the second wiring 20 within Y2 enclosed by the dotted line in the cross-sectional view D-D of Figure 9 is shown in the same way as in Figure 6. Therefore, when viewed from two different directions, one perpendicular to the circuit board 100 and the other parallel to the circuit board 100, the first wiring 10 has a first waveform shape, and the second wiring 20 has a second waveform shape. The first wiring 10 and the second wiring 20 intersect three-dimensionally at the intersection point 40, forming the first region 41 and the second region 42.

[0056] Here, the direction parallel to the circuit board 100 is, for example, the direction in which the detection circuit is viewed from the side of the circuit board 100, and the direction in which the detection circuit is seen as shown in the cross-sectional view D-D in Figure 9. The direction perpendicular to the circuit board 100 is, for example, the direction in which the detection circuit is viewed from the top of the circuit board 100, and the direction in which the detection circuit is seen as shown in the top view in Figure 9.

[0057] In this way, by arranging the first wiring 10 and the second wiring 20 such that the first region 41 and the second region 42 are alternately adjacent to each other across the intersection point 40 when viewed from two different directions: one perpendicular to the circuit board 100 and the other parallel to the circuit board 100, the current flowing through the first wiring 10 and the second wiring 20 can be canceled out not by either electromagnetic noise generated perpendicular to the circuit board 100 or electromagnetic noise generated parallel to the circuit board 100, but by both types of electromagnetic noise, thus further reducing the influence of external noise.

[0058] The positions in which the first via 31 and the second via 32 are provided are not limited to those shown in Figure 9, as long as the first region 41 and the second region 42 are formed so that they alternately align with each other across the intersection point 40 when the detection circuit is viewed from a direction parallel to the circuit board 100.

[0059] For example, the first via 31 and the second via 32 may be arranged as shown in Figure 10. The top view shown in Figure 10 is a view from the top side of the circuit board 100 on which the detection circuit is formed, and the first wiring 10 and the second wiring 20 arranged in the second wiring layer 102 and the first wiring 10 and the second wiring 20 arranged below the detection resistor 1 are shown by dashed lines. The E-E cross-sectional view shown in Figure 10 is a view of the E-E cross-section of the top view, and for convenience, the first wiring 10 and the second wiring 20 are shown together. In the E-E cross-sectional view of Figure 10, wiring that is connected to the first via 31 or the second via 32 located in front is shown as being connected to the first via 31 or the second via 32, and wiring that is not connected to the first via 31 or the second via 32 located in front is shown as not being connected to the first via 31 or the second via 32.

[0060] Figures 11A, 11B, and 11C are enlarged views of the first wiring 10 and the second wiring 20 within Y3, enclosed by the dotted line in the cross-sectional view E-E of Figure 10. Figure 11A shows only the first wiring 10, Figure 11B shows only the second wiring 20, and Figure 11C shows both the first wiring 10 and the second wiring 20.

[0061] As shown in Figure 11A, when viewed from a direction parallel to the circuit board 100, the first wiring 10 has a first waveform shape. Also, as shown in Figure 11B, when viewed from a direction parallel to the circuit board 100, the second wiring 20 has a second waveform shape. When the first wiring 10 and the second wiring 20, having these shapes, overlap when viewed from a direction parallel to the circuit board 100, a plurality of intersection points 40, a first region 41, and a second region 42 are formed, as shown in Figure 11C.

[0062] Thus, in the detection circuit shown in Figure 10, the influence of external noise is reduced by arranging the first wiring 10 and the second wiring 20 such that the first region 41 and the second region 42 are alternately adjacent to each other with the intersection point 40 in between, when viewed from two different directions: a direction perpendicular to the circuit board 100 and a direction parallel to the circuit board 100.

[0063] Next, we will compare the detection circuit shown in Figure 9 with the detection circuit shown in Figure 10.

[0064] Comparing the cross-sectional view D-D in Figure 9 with the cross-sectional view E-E in Figure 10, in the detection circuit shown in the cross-sectional view D-D in Figure 9, the first wiring 10 and the second wiring 20 are arranged in different wiring layers from the first wiring layer 101 and the second wiring layer 102. On the other hand, in the detection circuit shown in the cross-sectional view E-E in Figure 10, at the intersection point 40, both the first wiring 10 and the second wiring 20 are arranged in the first wiring layer 101, the first wiring 10 is arranged in the second wiring layer 102 between adjacent first vias 31, and the second wiring 20 is arranged in the second wiring layer 102 between adjacent second vias 32.

[0065] In the detection circuit shown in the E-E cross-sectional view of Figure 10, there are fewer first wirings 10 and second wirings 20 arranged on the second wiring layer 102 compared to the detection circuit shown in the D-D cross-sectional view of Figure 9. Having fewer wirings on the second wiring layer 102 increases the area on which other structures besides the detection circuit can be placed, improving design flexibility.

[0066] In this way, by arranging more than 50% of the first wiring 10 and the second wiring 20 on the same wiring layer, either the first wiring layer 101 or the second wiring layer 102, the design flexibility of the circuit board 100 is improved.

[0067] On the other hand, in the detection circuit shown in the cross-sectional view D-D of Figure 9, the distance between the first region 41 and the second region 42, which are alternately adjacent across the intersection 40, is shorter compared to the detection circuit shown in the cross-sectional view E-E of Figure 10. Because the distance between the first region 41 and the second region 42 is shorter, the electromagnetic noise linking the first region 41 and the second region 42 becomes similar, and the currents flowing through the first region 41 and the second region 42 due to the electromagnetic noise become similar and cancel each other out, thus further reducing the influence of external noise.

[0068] In this way, by arranging more than 50% of the first wiring 10 and the second wiring 20 in different wiring layers from the first wiring layer 101 or the second wiring layer 102, the influence of external noise can be further reduced.

[0069] Furthermore, as described above, by adjusting the positions of the first via 31 and the second via 32, the wiring layer on which the first wiring 10 and the second wiring are placed can be determined. Therefore, the detection circuit can be implemented on the circuit board 100 while considering both its relationship with other structures provided on the circuit board 100 and the degree of influence from external noise.

[0070] Furthermore, in the detection circuit shown in the D-D cross-sectional view of Figure 9, the first via 31 and the second via 32 are positioned at the same location along the direction in which the first wiring 10 and the second wiring 20 are routed, and when viewed from the side of the circuit board 100, the first via 31 and the second via 32 appear to overlap. When viewed from the side of the circuit board 100, the overlapping appearance of the first via 31 and the second via 32 makes the width of the intersection point 40 approximately the same as the width of the first via 31 and the second via 32. Here, the width of the intersection point 40 and the widths of the first via 31 and the second via 32 are the respective widths in the direction in which the first wiring 10 and the second wiring 20 are routed. As a result, the first region 41 and the second region 42 can be brought as close together as possible, further reducing the influence of external noise.

[0071] Regarding the positions where the first via 31 and the second via 32 are arranged, the same position along the direction in which the first wiring 10 and the second wiring 20 are routed means that when viewed from the side of the circuit board 100, the first via 31 and the second via 32 have overlapping portions, and they do not need to completely overlap.

[0072] In this way, the first wiring 10 and the second wiring 20 are arranged on different wiring layers from the first wiring layer 101 or the second wiring layer 102, and the first via 31 and the second via 32 are arranged at the same position along the direction in which the first wiring 10 and the second wiring 20 are routed, thereby further reducing the influence of external noise.

[0073] Furthermore, the first vias 31 may be arranged such that the spacing between adjacent first vias 31 is equal along the direction in which the first wiring 10 is routed. By arranging the adjacent first vias 31 at equal intervals, the first region 41 and the second region 42, as viewed from the side of the circuit board 100, are formed to have similar shapes, thereby further reducing the influence of external noise.

[0074] As described above, in the current or voltage detection circuit according to Embodiment 2, the first wiring 10 is transposed between the first wiring layer 101 and the second wiring layer 102 by a first via 31 provided on the first wiring 10, and the second wiring 20 is transposed between the first wiring layer 101 and the second wiring layer 102 by a second via 32 provided on the second wiring 20, so that the first wiring 10 and the second wiring 20 intersect three-dimensionally at the intersection point 40. With this configuration, the first wiring 10 and the second wiring 20 are arranged such that the first region 41 and the second region 42 are alternately adjacent to each other across the intersection point 40 when viewed from two different directions: a direction perpendicular to the circuit board 100 and a direction parallel to the circuit board 100. As a result, the effects of electromagnetic noise generated in the direction perpendicular to the circuit board 100 and electromagnetic noise generated in the direction parallel to the circuit board 100 can be canceled out, and the effects of external noise can be further reduced.

[0075] Furthermore, in the second embodiment, by adjusting the positions in which the first via 31 and the second via 32 are provided, 50% of the first wiring 10 and the second wiring 20 are arranged on the same wiring layer. This configuration expands the range in which other structures can be placed on the circuit board 100 on which the detection circuit is located, thereby improving the degree of design freedom.

[0076] Furthermore, in the second embodiment, by adjusting the positions in which the first via 31 and the second via 32 are provided, 50% of the first wiring 10 and the second wiring 20 are arranged on different wiring layers from the first wiring layer 101 or the second wiring layer 102. With this configuration, the distance between the first region 41 and the second region 42, which are alternately adjacent across the intersection point 40, is narrowed, and the influence of external noise can be further reduced.

[0077] Furthermore, in the second embodiment, the wiring layer on which the first wiring 10 and the second wiring 20 are arranged can be determined by adjusting the positions of the first via 31 and the second via 32. Therefore, the detection circuit can be implemented on the circuit board 100 while considering both its relationship with other structures provided on the circuit board 100 and the degree of influence from external noise.

[0078] Embodiment 3. The current or voltage detection circuit according to Embodiment 3 will be described with reference to Figures 12 and 13. In Embodiment 3, the same reference numerals are used for components that are the same as those in Embodiments 1 and 2, and the description will mainly focus on configurations that differ from Embodiments 1 and 2.

[0079] Figure 12 shows an example of the configuration of a detection circuit according to Embodiment 3. In Embodiment 2, the detection circuit includes a plurality of detection resistors 1. In Figure 12, the detection circuit includes three detection resistors 1, but the number of detection resistors 1 is not limited to this.

[0080] Multiple detection resistors 1 are connected in parallel, and the current to be detected flows through each detection resistor 1. In order to allow the current to be detected to flow through each detection resistor 1, for example, as shown in Figure 12, the detection resistors 1 are connected to the first wiring pattern 104 and the second wiring pattern 105 through which the current to be detected flows, via the first land 106 and the second land 107 provided for each detection resistor 1.

[0081] By arranging multiple detection resistors 1 in parallel and passing the current to be detected through each detection resistor 1, the current flowing through a single detection resistor 1 is reduced, thereby suppressing the heat generated by each detection resistor 1.

[0082] The first wiring 10 and the second wiring 20 connect, for example, both ends of one of the multiple detection resistors 1 to the differential voltage detection unit 2. In Figure 12, the first wiring 10 and the second wiring 20 are connected to the middle detection resistor 1 of the three detection resistors 1, but the detection resistor 1 to which the first wiring 10 and the second wiring 20 are connected is not limited to this.

[0083] The first wiring 10 and the second wiring 20, connected to the detection resistor 1, are led out from the connected first land 106 and second land 107 toward the differential voltage detection unit 2. At this time, the intersection point 40 where the first wiring 10 and the second wiring 20 intersect in three dimensions may be located outside the multiple detection resistors 1 when viewed from the top side of the circuit board 100, or it may be located below the multiple detection resistors 1.

[0084] For example, as shown in Figure 12, the first wiring 10 and the second wiring 20 may be arranged such that the intersection point 40 where the first wiring 10 and the second wiring 20 intersect in three dimensions is located outside of the multiple detection resistors 1. Alternatively, as shown in Figure 13, the first wiring 10 and the second wiring 20 may be arranged such that the intersection point 40 where the first wiring 10 and the second wiring 20 intersect in three dimensions is also located below the multiple detection resistors 1.

[0085] As described above, by connecting the first wiring 10 and the second wiring 20 to multiple detection resistors 1 connected in parallel, the detection circuit according to Embodiments 1 to 3 can be connected even when multiple detection resistors 1 are connected in parallel, thereby reducing the influence of external noise.

[0086] In Figures 12 and 13, one of the multiple detection resistors 1 is connected to the first wiring 10 and the second wiring 20, but this is not limited to this. For example, two or more of the multiple detection resistors 1 may be connected to the first wiring 10 and the second wiring 20, or all of the multiple detection resistors 1 may be connected to the first wiring 10 and the second wiring 20.

[0087] As described above, the current or voltage detection circuit according to Embodiment 3 connects the differential voltage detection unit 2 to both ends of one of the multiple detection resistors 1 connected in parallel by the first wiring 10 and the second wiring 20. With this configuration, the heat generated in the detection resistors 1 is suppressed by connecting the multiple detection resistors 1 in parallel, the influence of external noise is reduced, and the accuracy of current or voltage detection can be improved.

[0088] Embodiment 4. The current or voltage detection circuit according to Embodiment 4 will be described with reference to Figure 14. In Embodiment 4, the same reference numerals are used for components that are the same as those in Embodiments 1 to 3, and the description will mainly focus on configurations that differ from Embodiments 1 to 3.

[0089] Figure 14 shows an example of the configuration of a detection circuit according to Embodiment 4. In Embodiment 4, the detection circuit includes a guard pattern 110 and a third via 33.

[0090] The guard pattern 110 is provided on the first wiring layer 101 and the second wiring layer 102, and is arranged around the first wiring 10, the second wiring 20, and the differential voltage detection unit 2. As shown in Figure 14, the guard pattern 110 is connected to the second wiring pattern, for example, and is arranged to surround the first wiring 10, the second wiring 20, and the differential voltage detection unit 2.

[0091] The guard patterns 110 provided on the first wiring layer 101 and the second wiring layer 102 are preferably provided so as to be symmetrical with respect to the circuit board 100, for example, but they do not necessarily have to be symmetrical with respect to the circuit board 100 as long as they are formed to surround the first wiring 10, the second wiring 20 and the differential voltage detection unit 2.

[0092] The third via 33 is provided on the guard pattern 110 and electrically connects the first wiring layer 101 and the second wiring layer 102. By providing the third via 33 on the guard pattern 110, the guard pattern 110 provided on the first wiring layer 101 and the guard pattern 110 provided on the second wiring layer 102 are electrically connected.

[0093] It is sufficient to provide one or more third vias 33 on the guard pattern 110, and as shown in Figure 14, multiple third vias 33 may be provided.

[0094] A guard pattern 110 electrically connected by a third via 33 is provided on the first wiring layer 101 and the second wiring layer 102, and is arranged around the first wiring 10, the second wiring 20, and the differential voltage detection unit 2, thereby reducing the influence of external noise on the detection circuit.

[0095] As described above, the current or voltage detection circuit according to Embodiment 4 can further reduce the influence of external noise and improve the accuracy of current or voltage detection by arranging a guard pattern 110 around the first wiring 10, the second wiring 20 and the differential voltage detection unit 2 of the detection circuit, and by providing a third via 33 on the guard pattern 110.

[0096] Embodiment 5. The current or voltage detection circuit according to Embodiment 5 will be described with reference to Figure 15. In Embodiment 5, the same reference numerals are used for components that are the same as those in Embodiments 1 to 4, and the description will mainly focus on configurations that differ from Embodiments 1 to 4.

[0097] Figure 15 shows an example of the configuration of a detection circuit according to Embodiment 5. In Embodiment 5, a differential amplifier circuit 2a is used as an example of the differential voltage detection unit 2, but the configuration of the differential voltage detection unit 2 is not limited to this.

[0098] The differential amplifier circuit 2a amplifies and outputs the voltage across the first wiring 10 and second wiring 20 connected to both ends of the detection resistor 1. The differential amplifier circuit 2a includes, for example, resistors 201, 202, 203, 204, a capacitor 205, an operational amplifier 206, and diodes 207, 208, as shown in Figure 15. Here, the amplification factor is determined by the resistance values ​​of resistors 201, 202, 203, and 204. Note that the differential amplifier circuit 2a is not limited to the configuration shown in Figure 15.

[0099] The detection resistor 1, inserted into the current path to detect current or voltage, generally has a small resistance value, resulting in a small voltage across the detection resistor 1. Therefore, by amplifying and outputting the voltage across the resistor using a differential amplifier circuit 2a, current or voltage can be detected with high accuracy.

[0100] As described above, the current or voltage detection circuit according to Embodiment 5 uses a differential amplifier circuit 2a as the differential voltage detection unit 2, so even when the resistance value of the detection resistor 1 is small and the voltage across the detection resistor 1 is small, the current or voltage can be detected with high accuracy.

[0101] While this disclosure describes various exemplary embodiments and examples, the various features, aspects, and functions described in one or more embodiments are not limited to the application of a particular embodiment, but are applicable individually or in various combinations to the embodiments. Accordingly, countless variations not illustrated are envisioned within the scope of the art disclosed in this specification. For example, these include modifying, adding or omitting at least one component, or extracting at least one component and combining it with a component from another embodiment.

[0102] 1 Detection resistor, 2 Differential voltage detection unit, 2a Differential amplifier circuit, 10 First wiring, 11 First peak, 12 First valley, 20 Second wiring, 21 Second peak, 22 Second valley, 30 Via, 31 First via, 32 Second via, 33 Third via, 40 Intersection, 41 First region, 42 Second region, 100 Circuit board, 101 First wiring layer, 102 Second wiring layer, 103 Insulation layer, 104 First wiring pattern, 105 Second wiring pattern, 106 First land, 107 Second land, 108 First connection, 109 Second connection, 110 Guard pattern, 111 Power supply, 112 Compressor, 113 Converter circuit, 114 Inverter circuit, 115 Control unit, 201, 202, 203, 204 Resistors, 205 Capacitors, 206 Op-amp, 207, 208 diodes

Claims

1. A current or voltage detection circuit provided alongside the current path of a power converter, comprising: a circuit board having a first wiring layer and a second wiring layer separated by an insulating layer; a detection resistor provided in the first wiring layer through which the current to be detected flows; a differential voltage detection unit provided in the first or second wiring layer for detecting the voltage across the detection resistor; a first wiring connected to one end of the detection resistor and the differential voltage detection unit, having a first waveform shape with alternating first peaks and first valleys, and provided in at least one of the first and second wiring layers; and a second wiring connected to the other end of the detection resistor and the differential voltage detection unit, having a second waveform shape with alternating second valleys and second peaks, and provided in at least one of the first and second wiring layers. The first wiring and the second wiring are electrically insulated by the insulating layer, and the current or voltage detection circuit has multiple intersection points where the first wiring and the second wiring intersect three-dimensionally when viewed from a first direction from which the first waveform shape and the second waveform shape can be seen, and the first region formed by the first peak and the second valley and the second region formed by the second peak and the first valley are arranged alternately adjacent to each other with the intersection points in between.

2. The current or voltage detection circuit according to claim 1, wherein the first wiring and the second wiring are arranged along the path of the current flowing through the power converter.

3. The current or voltage detection circuit according to claim 1 or 2, wherein the first wiring and the second wiring are arranged to have three or more intersection points.

4. The current or voltage detection circuit according to claim 1 or 2, wherein the first wiring and the second wiring are arranged to have an odd number of intersection points.

5. The current or voltage detection circuit according to claim 1 or 2, wherein the first wiring and the second wiring are arranged such that the areas of the first region and the second region are equal when viewed from the first direction.

6. A current or voltage detection circuit according to claim 1 or 2, further comprising: a first wiring pattern provided on the first wiring layer through which the current to be detected flows; a second wiring pattern provided on the first wiring layer through which the current to be detected flows; a first land provided on the first wiring pattern connecting one end of the detection resistor to the first wiring pattern; a second land provided on the second wiring pattern connecting the other end of the detection resistor to the second wiring pattern; a first connection portion connected to the first land at the lower part of the detection resistor and connected to a portion of the first land facing the second land; and a second connection portion connected to the second land at the lower part of the detection resistor and connected to a portion of the second land facing the first land, wherein the first wiring is connected to the first connection portion and the second wiring is connected to the second connection portion.

7. The current or voltage detection circuit according to any one of claims 1 to 6, wherein the first wiring and the second wiring are arranged only in different wiring layers from the first wiring layer or the second wiring layer.

8. A current or voltage detection circuit according to any one of claims 1 to 6, comprising: a first via provided on the first wiring and electrically connecting the first wiring layer and the second wiring layer; and a second via provided on the second wiring and electrically connecting the first wiring layer and the second wiring layer, wherein the first wiring is transposed between the first wiring layer and the second wiring layer by the first via, and the second wiring is transposed between the first wiring layer and the second wiring layer by the second via, so that they intersect three-dimensionally at the intersection.

9. The current or voltage detection circuit according to claim 8, wherein 50% or more of the first and second wirings are arranged in the same wiring layer, either the first or second wiring layer.

10. The current or voltage detection circuit according to claim 8, wherein 50% or more of the first and second wirings are arranged in different wiring layers from the first wiring layer or the second wiring layer.

11. The current or voltage detection circuit according to claim 10, wherein the first wiring and the second wiring are arranged in different wiring layers from the first wiring layer and the second wiring layer, and the first via and the second via are arranged in the same position along the direction in which the first wiring and the second wiring are routed.

12. The current or voltage detection circuit according to claim 11, wherein the first vias are provided such that the spacing between adjacent first vias is equal along the direction in which the first wiring is routed.

13. A current or voltage detection circuit according to any one of claims 1 to 12, wherein a plurality of the detection resistors are connected in parallel, and the first wiring and the second wiring connect both ends of one of the plurality of detection resistors to the differential voltage detection unit.

14. A current or voltage detection circuit according to any one of claims 1 to 12, comprising: a guard pattern provided on the first wiring layer and the second wiring layer and arranged around the first wiring, the second wiring and the differential voltage detection unit; and a third via provided on the guard pattern and electrically connecting the first wiring layer and the second wiring layer.

15. The current or voltage detection circuit according to any one of claims 1 to 12, wherein the differential voltage detection unit is a differential amplifier circuit that amplifies and outputs the voltage across the terminals.

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