Light detection device

Abstract

The present disclosure relates to a light detection device that makes it possible to achieve a supply path for supplying a prescribed voltage with low resistance. This light detection device is provided with: a semiconductor substrate having a photoelectric conversion region for photoelectrically converting incident light; a light shielding film formed on a light incident surface side of the semiconductor substrate; and an electrode pad formed on a side opposite to the light incident surface side of the semiconductor substrate. The light detection device has: a pixel array part having pixels; and a pad region having the electrode pad, wherein the pad region includes a guard ring in which a metal material is embedded in a trench penetrating the semiconductor substrate. The light detection device is configured so that the guard ring extracts, to the light incident surface side of the semiconductor substrate, a prescribed voltage which is supplied to the electrode pad, and so that the prescribed voltage extracted to the light incident surface side of the semiconductor substrate by the guard ring is supplied to the pixels of the pixel array part through the light shielding film. The technology of the present disclosure can be applied to, for example, an electronic apparatus or the like that detects the distance to a subject.

Description

Optical detection device

[0001] The present disclosure relates to an optical detection device, and particularly to an optical detection device capable of realizing a supply path for supplying a predetermined voltage with low resistance.

[0002] A direct ToF (Time-of-Flight) type light receiving device measures the distance to a measured object by measuring the time from when light is irradiated until the reflected light reflected by the measured object is received. For example, a SPAD (Single Photon Avalanche Diode) is used as a photoelectric conversion element in the pixel of the direct ToF type light receiving device. The light receiving device includes a TDC that measures the time until the photoelectric conversion element detects light and reacts, and a histogram generation unit that generates a histogram based on the measured time.

[0003] Patent Document 1 discloses a configuration in an imaging device using SPAD pixels, in which a predetermined voltage applied to a pad electrode disposed outside a pixel array on the front surface side of a semiconductor substrate is taken out to the back surface side of the semiconductor substrate, which is the light incident surface side, through a contact layer formed of an impurity layer or the like, and supplied from the back surface side to each pixel in the pixel array.

[0004] International Publication No. 2018 / 174090

[0005] If a high-resistance portion is included in the path for supplying a predetermined voltage to each pixel in the pixel array, variations in characteristics due to IR drop or voltage fluctuations are a concern, so a configuration for supplying a predetermined voltage with low resistance is desired.

[0006] The present disclosure has been made in view of such a situation, and is to enable the realization of a supply path for supplying a predetermined voltage with low resistance.

[0007] A first aspect of the present disclosure of a photodetector comprises a semiconductor substrate having a photoelectric conversion region for photoelectric conversion of incident light, a light-shielding film formed on the light-incident surface side of the semiconductor substrate, and electrode pads formed on the side of the semiconductor substrate opposite to the light-incident surface, and further comprises a pixel array portion having pixels and a pad region having the electrode pads, wherein the pad region includes a guard ring in which a metal material is embedded in a trench penetrating the semiconductor substrate, the guard ring extracts a predetermined voltage supplied to the electrode pads to the light-incident surface side of the semiconductor substrate, and the predetermined voltage extracted to the light-incident surface side of the semiconductor substrate by the guard ring is supplied to the pixels of the pixel array portion via the light-shielding film.

[0008] In a first aspect of this disclosure, a semiconductor substrate having a photoelectric conversion region for photoelectric conversion of incident light, a light-shielding film formed on the light-incident surface side of the semiconductor substrate, and electrode pads formed on the side of the semiconductor substrate opposite to the light-incident surface are provided, and a pixel array portion having pixels and a pad region having the electrode pads are provided, the pad region includes a guard ring in which a metal material is embedded in a trench penetrating the semiconductor substrate, the guard ring extracts a predetermined voltage supplied to the electrode pads to the light-incident surface side of the semiconductor substrate, and the predetermined voltage extracted to the light-incident surface side of the semiconductor substrate by the guard ring is supplied to the pixels of the pixel array portion via the light-shielding film.

[0009] A photodetector in a second aspect of the present disclosure is configured by stacking a first substrate having a photoelectric conversion region for photoelectric conversion of incident light, a second substrate on which a transistor for reading the charge generated in the photoelectric conversion region is formed, and a third substrate having a logic circuit, wherein the second substrate has a semiconductor substrate, a wiring layer, and electrode pads for electrically connecting to the outside, and the electrode pads are provided at a depth position of the semiconductor substrate of the second substrate.

[0010] In a second aspect of this disclosure, the device is constructed by stacking a first substrate having a photoelectric conversion region for photoelectric conversion of incident light, a second substrate on which a transistor for reading the charge generated in the photoelectric conversion region is formed, and a third substrate having a logic circuit, wherein the second substrate is provided with a semiconductor substrate, a wiring layer, and electrode pads for electrically connecting to the outside, and the electrode pads are provided at a depth position of the semiconductor substrate of the second substrate.

[0011] The light detection device may be a standalone device or a module incorporated into another device.

[0012] This is a block diagram showing an example configuration of the electronic device of the present disclosure. This is a block diagram showing an example configuration of a pixel in the optical detection device of Figure 1. This is a diagram illustrating the detection signal output by the pixel. This is a plan view showing the pixel array region and the pad region. This is a cross-sectional view showing an example configuration of a pixel. This is a cross-sectional view showing an example configuration of the pad portion. This is a cross-sectional view showing the voltage supply path from the pad portion to the pixel. This is a plan view showing the anode voltage region. This is a plan view showing a first example configuration of the wiring structure that supplies the anode voltage. This is a plan view showing a second example configuration of the wiring structure that supplies the anode voltage. This is a plan view showing a third example configuration of the wiring structure that supplies the anode voltage. This is a plan view showing the arrangement of the anode voltage region in the wiring structure of the third example configuration. This is a plan view showing a modified example of the wiring structure that supplies the anode voltage. This is a plan view showing a modified example of the wiring structure that supplies the anode voltage. This is a cross-sectional view showing a first modified example of the voltage supply path from the pad portion to the pixel. This is a cross-sectional view showing a second modified example of the voltage supply path from the pad portion to the pixel. This is a plan view corresponding to the second modified example in Figure 16. This is a plan view showing another example of the arrangement of the anode voltage region. This is a cross-sectional view showing a first modified example of the pad portion. This is a cross-sectional view showing a second modified example of the pad portion. This is a cross-sectional view showing a third modified example of the pad portion. This is a cross-sectional view showing a fourth modified example of the pad section. This is a cross-sectional view showing a fifth modified example of the pad section. This is a cross-sectional view showing a sixth modified example of the pad section. This is a cross-sectional view showing a seventh modified example of the pad section. This is a cross-sectional view showing an eighth modified example of the pad section. This is a cross-sectional view showing an example of the pixel configuration in a three-layer stacked structure. This is a diagram illustrating the difference in the circuit arrangement of pixels in a two-layer stacked structure and a three-layer stacked structure. This is a cross-sectional view showing an example of the pad section configuration in a three-layer stacked structure. This is a cross-sectional view showing a first modified example of the pad section. This is a cross-sectional view showing a second modified example of the pad section. This is a cross-sectional view showing a third modified example of the pad section. This is a cross-sectional view showing a fourth modified example of the pad section. This is a cross-sectional view showing a fifth modified example of the pad section. This is a cross-sectional view showing a sixth modified example of the pad section. This is a plan view of the sixth modified example of the pad section. This is a cross-sectional view showing a seventh modified example of the pad section. This is a diagram illustrating the manufacturing method of the basic pad structure of Figure 29. This is a diagram illustrating the manufacturing method of the basic pad structure of Figure 29. This is a diagram illustrating the manufacturing method of the basic pad structure of Figure 29. This is a diagram illustrating the manufacturing method of the basic pad structure of Figure 29.This is a diagram illustrating the manufacturing method of the basic pad structure shown in Figure 29. This is a diagram illustrating the manufacturing method of the basic pad structure shown in Figure 29. This is a diagram illustrating the manufacturing method of the basic pad structure shown in Figure 29. This is a diagram illustrating the manufacturing method of the basic pad structure shown in Figure 29. This is a diagram illustrating the manufacturing method of the basic pad structure shown in Figure 29. This is a diagram illustrating the manufacturing method of the basic pad structure shown in Figure 29. This is a diagram illustrating the manufacturing method of the basic pad structure shown in Figure 29. This is a block diagram illustrating an example of the schematic configuration of a vehicle control system. This is an explanatory diagram showing an example of the installation positions of the external information detection unit and the imaging unit.

[0013] The following describes embodiments for carrying out the technology of this disclosure (hereinafter referred to as "embodiments") with reference to the attached drawings. In this specification and drawings, components having substantially the same functional configuration are denoted by the same reference numerals, and redundant explanations are omitted. The explanation will proceed in the following order: 1. Example of electronic device configuration 2. Block diagram of pixel configuration of photodetector 3. Plan view of photodetector 4. Example of pixel cross-sectional configuration 5. Example of pad section cross-sectional configuration 6. Example of configuration showing connection between pad section and pixel 7. Modified pad section 8. Summary of two-layer laminated structure 9. Example of pixel cross-sectional configuration in a three-layer laminated structure 10. Example of pad section cross-sectional configuration in a three-layer laminated structure 11. Modified pad section 12. Manufacturing method of three-layer laminated structure 13. Summary of three-layer laminated structure 14. Application example to a mobile body

[0014] <1. Example of Electronic Device Configuration> Figure 1 is a block diagram showing an example of the configuration of the electronic device of this disclosure.

[0015] The electronic device 1 shown in Figure 1 includes a distance measuring device 11 and an application unit 12. The distance measuring device 11 directly measures the distance to the object to be measured (object to be measured) 30 using the Time of Flight (ToF) method and outputs the distance information, which is the measurement result, to the application unit 12. The distance information consists of a depth image in which, for example, the depth value indicating the distance to the subject is stored as the pixel value of each pixel. The application unit 12 is realized, for example, by a program running on a CPU (Central Processing Unit), requests the distance measuring device 11 to perform distance measurement, and obtains the distance information, which is the measurement result, from the distance measuring device 11. The electronic device 1 is envisioned to be, for example, a smartphone, tablet, wearable device, or a camera such as an in-car camera, digital still camera, or digital video camera, or an on-board device mounted on a vehicle such as an automobile or a mobile device such as a drone.

[0016] The distance measuring device 11 includes a control unit 21, a light source device 22, and a light detection device 23. The control unit 21 includes a processor and control circuit such as a CPU, MPU (Micro Processing Unit), FPGA (Field Programmable Gate Array), and DSP (Digital Signal Processor), and controls the overall operation of the distance measuring device 11. For example, the control unit 21 generates a reference clock signal that serves as the reference for the clock signals used by each part of the distance measuring device 11 and supplies it to the light source device 22 and the light detection device 23. In addition, the control unit 21 instructs the light detection device 23 to perform distance measurement in response to a request for distance measurement from the application unit 12, acquires distance information, which is the distance measurement result, from the light detection device 23, and outputs it to the application unit 12.

[0017] The light source device 22 includes, for example, a light-emitting element that emits light in the infrared region and a drive circuit that drives the light-emitting element. As the light-emitting element that emits light in the infrared region, for example, an LED (Light Emitting Diode) can be used. The light-emitting element is not limited to this, and for example, a VCSEL (Vertical Cavity Surface Emitting Laser) in which multiple light-emitting elements are formed in an array can also be used. The light source device 22 outputs illumination light 31 based on the emission timing signal supplied from the photodetector device 23. The emission timing signal is, for example, a pulse signal modulated into a square wave with a predetermined duty cycle. Hereinafter, unless otherwise specified, "the light-emitting element of the light source device 22 emits light" will be described as "the light source device 22 emits light," etc.

[0018] The photodetector 23 includes, for example, a photoelectric conversion element capable of detecting light with wavelengths in the infrared region, and a signal processing circuit that outputs a signal corresponding to the light detected by the photoelectric conversion element. The photodetector 23 is equipped with a SPAD (Single Photon Avalanche Diode) capable of detecting a single photon as the photoelectric conversion element. Hereafter, unless otherwise specified, "the photoelectric conversion element of the photodetector 23 detects light" will be described as "the photodetector 23 receives light," etc.

[0019] The light detection device 23 performs distance measurement processing in response to an instruction to perform distance measurement from the control unit 21. For example, the light detection device 23 generates a light emission timing signal indicating the timing when the light source device 22 emits light and supplies it to the light source device 22. The light detection device 23 also performs a light receiving operation in synchronization with the light emission timing signal and measures a count value which is the basis for calculating the depth value. The count value is the value obtained by counting the time from when the light source device 22 outputs the irradiation light 31 until the light detection device 23 receives the reflected light 32 that has been reflected by the object 30. The light detection device 23 supplies the count value to the control unit 21 as distance information. Alternatively, the light detection device 23 may calculate the distance D to the object 30 from the count value and supply the depth image stored as the depth value to the control unit 21 as distance information. The processing of generating the depth image based on the count value may be performed by the control unit 21.

[0020] <2. Block Diagram of Pixel Configuration of Light Detection Device> Figure 2 is a block diagram showing an example of the pixel configuration of the light detection device 23.

[0021] The light detection device 23 has a pixel 40 having the configuration shown in Figure 2, for example. The pixel 40 is an SPAD pixel equipped with an avalanche photodiode (APD) and capable of detecting a single photon, and has a pixel sensor unit 51 and a pixel readout circuit 52. When the light detection device 23 is composed of a stacked structure of two substrates, the pixel sensor unit 51 and the pixel readout circuit 52 are formed on different substrates. The pixel sensor unit 51 is provided on the first substrate on the light incident surface side, and the pixel readout circuit 52 is provided on the second substrate opposite to the light incident surface side.

[0022] The pixel sensor unit 51 has a SPAD 61 which is a photoelectric conversion element. The pixel readout circuit 52 has a transistor 62, an inverter 63 (input amplifier), and a level down unit 64.

[0023] The cathode of SPAD 61 is connected to the drain of transistor 62 and also to the input terminal of inverter 63. The anode of SPAD 61 is connected to the power supply voltage VA (hereinafter also referred to as the anode voltage VA). When incident light is incident on SPAD 61, it performs avalanche amplification of the generated electrons and outputs a signal of cathode voltage VS.

[0024] The SPAD61 has the characteristic that when a large negative voltage that causes avalanche multiplication is applied to its cathode, electrons generated in response to the incidence of a single photon undergo avalanche multiplication, causing a large current to flow. By utilizing this characteristic of the SPAD61, the incidence of a single photon can be detected with high sensitivity. The power supply voltage VA supplied to the anode of the SPAD61 is a negative voltage corresponding to the breakdown voltage VBD, and is, for example, a negative bias of about -20V.

[0025] Transistor 62 is a constant current source operating in the saturation region and performs passive quenching by acting as a quenching resistor. The source of transistor 62 is connected to the power supply voltage VE, and its drain is connected to the cathode of SPAD 61 and the input terminal of inverter 63. This also supplies the power supply voltage VE to the cathode of SPAD 61. The gate of transistor 62 is supplied with the bias voltage BIAS.

[0026] To detect photons with sufficient efficiency, a voltage greater than the breakdown voltage VBD of SPAD 61 (hereinafter referred to as excess bias) is applied to SPAD 61. For example, if the breakdown voltage VBD of SPAD 61 is 20V, and a voltage 3V greater than that is applied, the power supply voltage VE supplied to the source of transistor 62 will be 3V.

[0027] The breakdown voltage VBD of SPAD 61 varies significantly depending on temperature and other factors. Therefore, the applied voltage to SPAD 61 is controlled (adjusted) in accordance with the change in breakdown voltage VBD. For example, if the power supply voltage VE is a fixed voltage, the anode voltage VA is controlled (adjusted).

[0028] The inverter 63 compares the cathode voltage VS signal from the SPAD 61 with a threshold voltage Vth and outputs an inverted detection signal PFout each time the threshold voltage Vth is exceeded. The inverter 63 is constructed using thick-film MOS transistors.

[0029] Figure 3 shows the relationship between the cathode voltage VS signal input from SPAD 61 to inverter 63 and the detection signal PFout output by inverter 63.

[0030] In the voltage drop due to avalanche multiplication in response to the incidence of photons on the SPAD 61, inverter 63 inverts the detection signal PFout at time t0 when the cathode voltage VS crosses the threshold voltage Vth. Next, the SPAD 61 is charged by the recharge operation and the cathode voltage VS rises. Inverter 63 inverts the detection signal PFout again at time t1 when this rising cathode voltage VS crosses the threshold voltage Vth. The time width between time t0 and time t1 becomes the output pulse corresponding to the incidence of photons on the SPAD 61. Inverter 63 shapes this output pulse and outputs it to the level-down unit 64.

[0031] Returning to Figure 2, the level-down unit 64 is a voltage conversion unit that converts the detection signal PFout input from the inverter 63 to a voltage level at which the subsequent TDC operates. For example, if the power supply voltage VE is 3V, the level-down unit 64 converts the detection signal PFout, which has a voltage amplitude of 0V to 3V, into a signal with a voltage amplitude of 0V to 1V.

[0032] <3. Plan view of the light detection device> Figure 4 is a plan view of the light detection device 23.

[0033] The light detection device 23 is composed of a semiconductor chip with a stacked structure formed by stacking multiple substrates, and has a pixel array region 71 in an inner rectangular area in plan view, and a pad region 72 located outside of that, on the outer periphery of the semiconductor chip. The pixel array region 71 is composed of a pixel array section 81 in which the pixels 40 shown in Figure 2 are arranged in a matrix in two dimensions, and a pixel array peripheral section 82 outside of it. The pixel array peripheral section 82 is positioned between the pixel array section 81 and the pad region 72. The pixels 40 arranged in the pixel array section 81 include effective pixels that detect incident light and OPB pixels whose light incident surface is shielded by an OPB light-shielding film. In the pad region 72, multiple pad sections 92, including electrode pads 91, are arranged in a row along at least one side of the rectangular semiconductor chip. The example in Figure 4 shows an example in which multiple pad sections 92 are arranged along three predetermined sides of the four sides of the rectangle.

[0034] <4. Example of Pixel Cross-Sectional Configuration> Figure 5 is a cross-sectional view showing an example of the configuration of a pixel 40.

[0035] The pixels 40 of the light detection device 23 have a laminated structure formed by stacking a first substrate 101 and a second substrate 102. In Figure 5, the first substrate 101 and the second substrate 102 are bonded together at a bonding surface indicated by a dashed line. The first substrate 101 has a semiconductor substrate 121 made of a silicon substrate or the like, and a wiring layer 122. Hereinafter, to facilitate distinction from the second substrate 102, the semiconductor substrate 121 will be referred to as the first semiconductor substrate 121. Of the upper and lower surfaces of the first semiconductor substrate 121, the surface on which the wiring layer 122 is formed is the front surface, and in the figure, the upper surface on which the on-chip lens 148 is formed is the back surface of the first semiconductor substrate 121, which is the light incident surface to which reflected light is incident. The second substrate 102 has a semiconductor substrate made of a silicon substrate or the like, and a wiring layer 161, but the semiconductor substrate is not shown in Figure 5, and only the portion of the wiring layer 161 close to the bonding surface is shown. The semiconductor substrate of the second substrate 102 is referred to as the second semiconductor substrate.

[0036] In the description of the cross-sectional diagrams in this specification, for convenience, the side of the first semiconductor substrate 121 facing the incident light may be referred to as "top," "upper side," "upper," or "upper layer," while the side opposite to the incident light may be referred to as "bottom," "lower side," "downward," or "lower layer."

[0037] Each pixel 40 has an inter-pixel isolation portion 141 at the boundary with an adjacent pixel, and the photoelectric conversion region that converts incident light into photoelectric energy is separated on a pixel-by-pixel basis by the inter-pixel isolation portion 141. The inter-pixel isolation portion 141 is constructed by embedding a fixed charge film 142, an insulating film 143, and a metal material 144 inside a trench that penetrates the first semiconductor substrate 121. The insulating film 143 is formed inside the fixed charge film 142 formed on the side surface of the trench, and the metal material 144 is formed in the central part inside the insulating film 143. The fixed charge film 142 and the insulating film 143 are also formed on the light incident surface side of the first semiconductor substrate 121 so as to surround the photoelectric conversion region of each pixel. The inter-pixel isolation portion 141 is connected to a contact electrode 182 on the lower surface side of the first semiconductor substrate 121 and to an inter-pixel light-shielding film 146 on the upper surface side. The fixed charge film 142 is a film having a negative fixed charge and has the effect of suppressing dark current generation and anti-reflection. For the material of the fixed charge film 142, for example, hafnium oxide (HfO2), zirconium dioxide (ZrO2), tantalum oxide (Ta2O5), etc. can be used. For the material of the insulating film 143, for example, SiO2, or a composite material mainly composed of SiO2 (SiON, SiOC, etc.) can be used. For the metal material 144, for example, tungsten (W), aluminum (Al), copper (Cu), etc. can be used. The inter-pixel light-shielding film 146 is formed in a grid pattern in plan view on the light incident surface side of the first semiconductor substrate 121, on the upper layer of the inter-pixel separation portion 141. The material of the inter-pixel light-shielding film 146 is the same as the material of the metal material 144. A barrier metal may be formed in the lower layer of the metal material 144 and the inter-pixel light-shielding film 146 to improve adhesion with the substrate. The barrier metal material can be, for example, titanium (Ti), tantalum (Ta), tungsten (W), cobalt (Co), molybdenum (Mo), or alloys, nitrides, oxides, or carbides thereof. The contact electrode 182 is made of, for example, polysilicon.

[0038] On the light incident surface side of the first semiconductor substrate 121, a planarization film 147 is formed to fill the step in the interpixel light-shielding film 146. The planarization film 147 is composed of an oxide film such as TEOS, PSG, BPSG, or SOG. An on-chip lens 148 is formed on the upper side of the planarization film 147 for each pixel. The on-chip lens 148 is formed of a resin material such as a styrene resin, acrylic resin, styrene-acrylic copolymer resin, or siloxane resin. Alternatively, it can be constructed by dispersing titanium oxide particles in the above-mentioned organic material or polyimide resin. It may also be constructed of an inorganic material such as silicon nitride (SiN) or silicon oxynitride (SiON). The on-chip lens 148 focuses the incident light and efficiently directs it into the photoelectric conversion region of the first semiconductor substrate 121. Furthermore, a color filter layer may be provided between the planarization film 147 and the on-chip lens 148, in which, for example, R (Red), G (Green), and B (Blue) are arranged in a predetermined arrangement such as a Bayer array.

[0039] The photoelectric conversion region of the first semiconductor substrate 121, separated into pixel units by the inter-pixel separation section 141, includes an N-well 151, a P-type diffusion layer 152, an N-type diffusion layer 153, a hole accumulation layer 154, and a high-concentration P-type diffusion layer 155. An avalanche multiplication region 156 is formed by a depletion layer formed in the region where the P-type diffusion layer 152 and the N-type diffusion layer 153 are connected.

[0040] The N-well 151 is formed by controlling the impurity concentration of the first semiconductor substrate 121 to an n-type, and forms an electric field that transfers electrons generated by photoelectric conversion in the pixel 40 to the avalanche multiplication region 156. Alternatively, instead of the N-well 151, a P-well may be formed by controlling the impurity concentration of the first semiconductor substrate 121 to a p-type.

[0041] The P-type diffusion layer 152 is a heavily doped P-type (P+) impurity region formed so as to extend over substantially the entire pixel region in the planar direction. The N-type diffusion layer 153 is a heavily doped N-type (N+) impurity region formed so as to extend over substantially the entire pixel region near the surface of the first semiconductor substrate 121, similar to the P-type diffusion layer 152. The N-type diffusion layer 153 is a contact layer connected to the contact electrode 181 serving as a cathode electrode for supplying a negative voltage for forming the avalanche multiplication region 156, and a part thereof has a convex shape formed up to the contact electrode 181 on the surface of the first semiconductor substrate 121.

[0042] The hole accumulation layer 154 is a P-type (P) diffusion layer formed so as to surround the side surface of the N-well 151 and accumulates holes. The hole accumulation layer 154 is also connected to a high-concentration P-type diffusion layer 155 that is electrically connected to the contact electrode 182 serving as the anode electrode of the SPAD 61.

[0043] The high-concentration P-type diffusion layer 155 is a heavily doped P-type (P++) impurity region formed so as to surround the outer periphery of the N-well 151 near the front surface of the first semiconductor substrate 121, and constitutes a contact layer for electrically connecting the hole accumulation layer 154 to the contact electrode 182 of the SPAD 61.

[0044] In addition to the contact electrodes 181 and 182, a plurality of layers of metal wirings 183, wiring vias 184 for connecting the metal wirings 183 of each layer, and bonding electrodes 185 are formed in the interlayer insulating film 191 in the wiring layer 122. In FIG. 5, two layers of metal wirings 183 are formed, but the number of stacked layers of the metal wirings 183 is not limited. The contact electrodes 181 and 182, the metal wirings 183, and the wiring vias 184 are made of, for example, tungsten (W), aluminum (Al), copper (Cu), etc. The interlayer insulating film 191 is made of, for example, a single layer or a stack of SiO2, SiN, SiON, etc. A barrier metal may be formed on the metal wirings 183, the wiring vias 184, and the bonding electrodes 185.

[0045] The contact electrode 181 connects the N-type diffusion layer 153 and the metal wiring 183. The contact electrode 181 is connected to the junction electrode 185 via multiple layers of metal wiring 183 and wiring vias 184. Since the junction electrode 185 is connected to the junction electrode 201 of the wiring layer 161 of the second substrate 102, the power supply voltage VE supplied from the second substrate 102 is supplied to the contact electrode 181 as a cathode electrode via multiple layers of metal wiring 183 and wiring vias 184. The junction electrode 185 is formed of a metallic material such as Cu (copper) or Al (aluminum), and is an electrode that is electrically connected by a metal junction such as Cu-Cu. The junction electrode 185 is used for the electrical connection between the first substrate 101 and the second substrate 102, and for bonding the first substrate 101 and the second substrate 102.

[0046] The wiring layer 161 of the second substrate 102 has a bonding electrode 201, wiring vias 202, pad wiring 203, and an interlayer insulating film 211. The wiring layer 161 has multiple layers of metal wiring, including areas not shown. The bonding electrode 201 is electrically connected to the bonding electrode 185 of the first substrate 101 by a metal bond such as Cu-Cu. The pad wiring 203 is a metal wiring formed simultaneously with the electrode pad 91 of the pad region 72, which will be described later in Figure 6, etc. The pad wiring 203 is formed of the same material as the electrode pad 91, such as AlCu, and has the same film thickness. The materials of the bonding electrode 201, wiring vias 202, and interlayer insulating film 211 of the wiring layer 161 can be the same materials as those used for the bonding electrode 185, wiring vias 184, and interlayer insulating film 191 of the wiring layer 161.

[0047] The pixel 40 of the photodetection device 23 is configured as described above. The power supply voltage VE supplied to the cathode of the SPAD 61 is supplied from the second substrate 102 side, and is supplied to the contact electrode 181 as the cathode electrode via the plurality of metal wirings 183 and the wiring via 184, and is applied to the N-type diffusion layer 153. The anode voltage VA supplied to the anode of the SPAD 61 is taken out from the electrode pad 91 in the pad region 72 to be described later in FIG. 6 and the like from the back side of the first semiconductor substrate 121, and is supplied to the contact electrode 182 via the inter-pixel light shielding film 146 and the metal material 144 of the inter-pixel separation portion 141 arranged in a grid pattern in the pixel array portion 81, and is applied to the high-concentration P-type diffusion layer 155.

[0048] <5. Cross-sectional configuration example of pad portion> FIG. 6 is a cross-sectional view showing a configuration example of a pad portion 92 including one electrode pad 91 in the pad region 72.

[0049] Note that the pad portion 92 in FIG. 6 shows a configuration example of the pad portion 92 having the electrode pad 91 to which the anode voltage VA supplied to the anode of the SPAD 61 is input from the outside.

[0050] In FIG. 6, the same reference numerals are given to the portions corresponding to the pixel 40 shown in FIG. 5, and the description of those portions will be omitted as appropriate.

[0051] The pad portion 92 in FIG. 6 has the electrode pad 91 in the wiring layer 161 of the second substrate 102. This electrode pad 91 is located in the same layer as the pad wiring 203 of the pixel 40 shown in FIG. 5. An opening 251 is provided above the electrode pad 91, and the anode voltage VA is supplied to the electrode pad 91 from the outside by wire bonding or the like.

[0052] A guard ring 271 is formed on the outside of the opening 251. The guard ring 271 is formed in a rectangular shape so as to surround the outside of the opening 251 in a plan view. The guard ring 271 is formed in the same process as the inter-pixel separation portion 141 of the pixel 40, and therefore has the same structure as the inter-pixel separation portion 141. That is, the guard ring 271 is constructed by embedding a fixed charge film 142, an insulating film 143, and a metal material 144 inside a trench that penetrates the first semiconductor substrate 121. An OPB light-shielding film 272 is placed on the light incident surface side of the first semiconductor substrate 121 of the guard ring 271 and is connected to the metal material 144 embedded inside the guard ring 271. The OPB light-shielding film 272 is formed simultaneously with the inter-pixel light-shielding film 146 of the pixel array portion 81, and is therefore formed integrally with the inter-pixel light-shielding film 146. The on-chip lens material 148P on top of the planarization film 147 is made of the same material as the on-chip lens 148, but in the pad region 72 it has a flat shape rather than a lens shape.

[0053] In the pad portion 92 of the pad region 72 configured as described above, the anode voltage VA is supplied to the electrode pad 91 from the outside by wire bonding or the like. The anode voltage VA supplied to the electrode pad 91 is applied from the contact electrode 181 to the high-concentration P-type diffusion layer 155 via the wiring via 202, junction electrode 201, junction electrode 185, wiring via 184, and metal wiring 183. Furthermore, the anode voltage VA is supplied from the high-concentration P-type diffusion layer 155 to the OPB light-shielding film 272 via the contact electrode 182 and the metal material 144 in the guard ring 271, and is extracted to the back side of the first semiconductor substrate 121.

[0054] <6. Example of configuration showing connection between pad portion and pixel> <Cross-sectional view> Figure 7 is a cross-sectional view showing the voltage supply path from the pad portion 92 of the pad area 72 to the pixel 40 of the pixel array portion 81.

[0055] In Figure 7, the detailed reference numerals for the pad portion 92 and the pixels 40 have been omitted as appropriate.

[0056] The OPB light-shielding film 272 is connected to a metal material 144 embedded inside the guard ring 271 in the pad portion 92 of the pad region 72, and is connected to the inter-pixel light-shielding film 146 in the pixel array portion 81. As a result, the anode voltage VA extracted from the back side of the first semiconductor substrate 121 in the pad portion 92 of the pad region 72 is supplied to the metal material 144 of the inter-pixel separation portion 141 via the OPB light-shielding film 272 in the pixel array peripheral portion 82 and the inter-pixel light-shielding film 146 in the pixel array portion 81, and further supplied to the contact electrode 182 and applied to the high-concentration P-type diffusion layer 155. Therefore, in the pixel array portion 81 and the pixel array peripheral portion 82, the metal wiring that supplies the anode voltage VA is routed on the back side of the first semiconductor substrate 121. As a result, there is no need to arrange the wiring that supplies the anode voltage VA in the region 301 of the wiring layer 122 and wiring layer 161 below the first semiconductor substrate 121 in the pixel array peripheral portion 82. Because the anode voltage VA is a high voltage, it needs to be kept at a large distance from other voltage supply lines or signal wiring, which imposes design constraints. However, by routing the metal wiring that supplies the anode voltage VA on the back side of the first semiconductor substrate 121, the degree of freedom for the layout of other wiring can be increased.

[0057] Pixels 40B located near the periphery 82 of the pixel array within the pixel array section 81 are OPB pixels, with the light incident surface side shielded by an OPB light-shielding film 272. The first semiconductor substrate 121 of the periphery 82 of the pixel array is formed of the same P-type diffusion layer as the hole accumulation layer 154 of the pixel 40, and has an anode voltage region 311 to which an anode voltage VA is applied and a ground region 312 to which ground is applied. One or more guard rings 313 are formed between the anode voltage region 311 and the ground region 312. The guard rings 313 have the same structure as the inter-pixel separation section 141 and the guard ring 271, and have the anode voltage VA applied to them.

[0058] <Plan View> Figure 8 is a plan view showing the anode voltage region 311.

[0059] As shown in Figure 8, the anode voltage region 311 is formed within the pixel array peripheral region 82 so as to surround the outer periphery of the pixel array portion 81. The electrode pad 91 to which the anode voltage VA described in Figures 6 and 7 is applied is the electrode pad 91 with hatching in Figure 8.

[0060] Figure 9 is a plan view showing a first example of a wiring structure that supplies an anode voltage VA from a hatched electrode pad 91 to each pixel 40 in the pixel array 81.

[0061] In the first configuration example shown in Figure 9, the anode voltage VA extracted from the pad portion 92 of the pad region 72 on the back side of the first semiconductor substrate 121 is supplied to each pixel 40 by the OPB light-shielding film 272 formed as a solid pattern.

[0062] More specifically, the OPB light-shielding film 272 is formed in a solid pattern in the peripheral portion 82 of the pixel array and supplies the anode voltage VA to the inter-pixel light-shielding film 146 in the pixel array portion 81. The OPB light-shielding film 272 is connected to the inter-pixel light-shielding film 146 which is formed in a grid pattern in the pixel array portion 81. By forming the OPB light-shielding film 272 in a solid pattern in the peripheral portion 82 of the pixel array and connecting the metal material 144 of the guard ring 271 of the pad portion 92 to the metal material 144 of the inter-pixel separation portion 141 in the pixel array portion 81, a low-resistance voltage supply path is realized, and the anode voltage VA can be supplied to each pixel 40.

[0063] Figure 10 is a plan view showing a second example of a wiring structure that supplies the anode voltage VA from the electrode pad 91 to each pixel 40 in the pixel array 81.

[0064] In the second configuration example shown in Figure 10, the pattern width of the OPB light-shielding film 272, which is formed as a solid pattern, is formed to gradually narrow as it approaches the electrode pad 91 from the pixel array portion 81. This makes it possible to mitigate the electric field, in other words, to mitigate electromigration (EM) and stress migration (SM).

[0065] Figure 11 is a plan view showing a third example of a wiring structure that supplies the anode voltage VA from the electrode pad 91 to each pixel 40 in the pixel array 81.

[0066] In the third configuration example shown in Figure 11, the OPB light-shielding film 272 is arranged on the back side of the first semiconductor substrate 121 with a predetermined width, similar to the anode voltage region 311, so as to surround the outer periphery of the pixel array portion 81. Meanwhile, within the first semiconductor substrate 121 of the pixel array peripheral portion 82, a grid-like through-trench 331 is formed so as to connect to the electrode pad 91 to which the anode voltage VA is applied. The grid-like through-trench 331 has the same structure as the inter-pixel separation portion 141 of the pixel array portion 81 and is formed at the same time as the inter-pixel separation portion 141. In other words, the inter-pixel separation portion 141 of the pixel array portion 81 is extended as the grid-like through-trench 331 until it connects to the electrode pad 91 to which the anode voltage VA is applied. The width DS of the plane in which the grid-like through trenches 331 are formed in a direction perpendicular to the direction toward the pixel array portion 81 from the electrode pad 91 to which the anode voltage VA is applied is formed to a maximum of, for example, 1 mm or more, and is formed to gradually narrow as it approaches the electrode pad 91 from the pixel array portion 81. A grid-like OPB light-shielding film 272 may be formed on the light incident surface side of the upper layer of the grid-like through trenches 331 in the pixel array peripheral portion 82. In other words, a grid-like pattern may be formed in the pixel array peripheral portion 82 by the grid-like through trenches 331 and the OPB light-shielding film 272.

[0067] The metal material 144 of the guard ring 271 of the pad portion 92 and the metal material 144 of the inter-pixel separation portion 141 in the pixel array portion 81 are connected by a grid-shaped through-trench 331 that penetrates the first semiconductor substrate 121 in cross-sectional view and is formed in a grid shape in plan view. As a result, the anode voltage VA is supplied from the guard ring 271 to the inter-pixel separation portion 141 in the pixel array portion 81 via the grid-shaped through-trench 331. This makes it possible to realize a low-resistance voltage supply path that supplies the anode voltage VA to each pixel 40. The anode voltage VA flows from the electrode pad 91 of the pad portion 92 to the low-resistance portion of the grid-shaped through-trench 331 that extends in the planar direction and in the substrate depth direction.

[0068] Figure 12 is a plan view showing the arrangement of the anode voltage region 311 in the wiring structure of the third configuration example shown in Figure 11.

[0069] When the pad portion 92 and the inter-pixel separation portion 141 within the pixel array portion 81 are connected by a grid-like through-trench 331, the anode voltage region 311 may be omitted from the four sides surrounding the pixel array portion 81 where the grid-like through-trench 331 is formed, as shown in Figure 12.

[0070] Figures 13 and 14 are plan views showing modified wiring structures that supply the anode voltage VA from the electrode pad 91 to each pixel 40 in the pixel array 81.

[0071] In the example described in Figures 8 to 12, the anode voltage VA is supplied to each pixel 40 from the electrode pad 91 of one pad section 92, but it may also be supplied to each pixel 40 from multiple pad sections 92.

[0072] Figure 13 shows an example in which the anode voltage VA is supplied from two pad sections 92 to each pixel 40.

[0073] In Figure 13, the grid-like through-trench 331 is formed extending from two predetermined sides of the rectangular pixel array 81 to predetermined pad portions 92 of the pad region 72, and is connected to the electrode pads 91 of the two pad portions 92. The two predetermined sides of the pixel array 81 formed by the extension of the grid-like through-trench 331 are, for example, opposing sides. The arrangement of the two pad portions 92 is, for example, at positions facing each other with respect to the rectangular pixel array 81. As explained in Figure 12, the anode voltage region 311 may be omitted for the sides formed by the extension of the grid-like through-trench 331.

[0074] Figure 14 shows an example in which the anode voltage VA is supplied from three pad sections 92 to each pixel 40.

[0075] In Figure 14, the grid-like through-trench 331 is formed extending from three predetermined sides of the rectangular pixel array 81 to predetermined pad portions 92 of the pad region 72, and is connected to the electrode pads 91 of the three pad portions 92. The three predetermined sides of the pixel array 81 formed by the extension of the grid-like through-trench 331 are, for example, the three sides of the rectangular pixel array 81 that have the shortest distance from the pixel array 81 to the pad portions 92. As explained in Figure 12, the anode voltage region 311 may be omitted for the sides formed by the extension of the grid-like through-trench 331.

[0076] In Figures 13 and 14, the OPB light-shielding film 272 is shown using the third configuration example shown in Figure 11, but it may also be combined with the first configuration example in Figure 9 or the second configuration example in Figure 10. In other words, any combination of the configuration of the OPB light-shielding film 272 in Figures 9 to 11 and the configuration of the grid-like through-trench 331 in Figures 11 to 14 is possible. Also, the number of pad sections 92 that supply the anode voltage VA to each pixel 40 of the pixel array section 81 may be one or multiple.

[0077] Figure 15 is a cross-sectional view showing a first modified example of the voltage supply path from the pad portion 92 of the pad region 72 to the pixels 40 of the pixel array portion 81.

[0078] Comparing the first modified example shown in Figure 15 with the configuration example shown in Figure 7 (hereinafter referred to as the basic structure), a through-trench 351 penetrating the first semiconductor substrate 121 is added to the boundary between the pixel array region 71 and the pad region 72. The material 361 embedded inside the through-trench 351 is the same material as the insulating film 143, for example, SiO2, or a composite material mainly composed of SiO2 (SiON, SiOC, etc.). In addition, the guard ring 313 formed between the anode voltage region 311 and the ground region 312 has been changed to a guard ring 313' in which the material inside the through-trench has been changed. The guard ring 313 in the configuration example shown in Figure 7 was formed with the same structure as the inter-pixel separation portion 141 of the pixel array portion 81. In contrast, the material 362 embedded in the guard ring 313' of the first modified example is the same material as the insulating film 143.

[0079] In the basic structure shown in Figure 7, the thickness of the insulating film 143 on the side walls of the interpixel separation portion 141 and the guard ring 271 is set to a thickness that can withstand the large voltage (anode voltage VA) applied to the hole accumulation layer 154. Similarly, the thickness of the insulating film 143 formed on the upper surface of the substrate on the back side of the first semiconductor substrate 121 is also set to a thickness that can withstand the large voltage (anode voltage VA) applied to the OPB light-shielding film 272. It is desirable that the thickness of the insulating film 143 that can withstand the anode voltage VA be, for example, 80 nm or more.

[0080] However, if the thickness of the insulating film 143 cannot be formed to a thickness that can withstand the large anode voltage VA, the configuration example shown in Figure 15 can be used as a leakage countermeasure. That is, Figure 15 is an example of a configuration in which the thickness of the insulating film 143 is formed to be thinner than the thickness that can withstand the large anode voltage VA.

[0081] In the first modified example shown in Figure 15, a through trench 351 is additionally provided at the boundary between the pixel array region 71 and the pad region 72, and the guard ring 313 between the anode voltage region 311 and the ground region 312 is changed to a guard ring 313' in which the same material 362 as the insulating film 143 is embedded. Furthermore, the insulating film 143' formed on the upper surface of the substrate on the back side of the first semiconductor substrate 121 has a thicker film thickness than the insulating film 143 of the basic structure shown in Figure 7. The insulating film 143' is formed simultaneously with the insulating film 143 of the side walls of the inter-pixel separation portion 141 and the guard ring 271, and therefore has the same film thickness. However, by adding an additional film, it is made to have a thicker film thickness than the insulating film 143 of the side walls. In terms of the manufacturing process, before forming the insulating film 143 of the side walls, an oxide film of the same material as the insulating film 143 can be formed on the back side of the first semiconductor substrate 121 to a predetermined thickness.

[0082] Figure 16 is a cross-sectional view showing a second modified example of the voltage supply path from the pad portion 92 of the pad region 72 to the pixels 40 of the pixel array portion 81.

[0083] The second modified example shown in Figure 16 is also an example of a configuration in which the thickness of the insulating film 143 is formed to be thinner than the thickness that can withstand a large anode voltage VA.

[0084] Figure 17 is a plan view corresponding to the second modified example of Figure 16.

[0085] In the second modification shown in Figures 16 and 17, the anode voltage region 311 is extended to the electrode pad 91 to which the anode voltage VA is applied. The anode voltage region 311 is surrounded by a through trench 371 embedded with the same material 372 as the insulating film 143. One or more guard rings 313, which were provided to separate the anode voltage region 311 from the ground region 312, may be omitted.

[0086] Figure 18 is a plan view showing another arrangement example of the anode voltage region 311 shown in Figures 16 and 17.

[0087] As shown in Figure 18, the well region of the anode voltage region 311 may be further extended. In Figure 18, the entire substrate region of the chip outside the grid-like through-trench 331 that supplies the anode voltage VA from the pad portion 92 is defined as the anode voltage region 311. In this case, the through-trench 371 of the insulating film surrounding the anode voltage region 311 may be omitted.

[0088] As shown in Figures 17 and 18, by making the substrate region (well region of the first semiconductor substrate 121) surrounding the electrode pad 91 to which the anode voltage VA is applied the anode voltage region 311, the potential difference between the guard ring 271, the metal material 144 of the inter-pixel separation portion 141 and the substrate region can be eliminated, thereby resolving concerns about voltage resistance.

[0089] In the example described above, the grid pattern of the grid-like through-trench 331 between the pad portion 92 and the pixel array portion 81 was the same as the grid pattern of the inter-pixel separation portion 141 of the pixel array portion 81. However, a different grid pattern may be used. For example, the grid pattern of the grid-like through-trench 331 may have a grid pitch that is two or three times, or a grid width that is different from that of the inter-pixel separation portion 141.

[0090] <7. Modified Pad Section> Next, a modified version of the pad section 92 shown in Figure 6 will be described with reference to Figures 19 to 26. In the following description, the example configuration of the pad section 92 shown in Figure 6 will be referred to as the basic pad structure.

[0091] <First modified example of the pad portion> Figure 19 is a cross-sectional view showing a first modified example of the pad portion 92.

[0092] Comparing the first modified example in Figure 19 with the basic pad structure shown in Figure 6, an air gap (air layer) 145 is provided inside the guard ring 271. The guard ring 271 of the basic pad structure shown in Figure 6 is constructed by embedding a fixed charge film 142, an insulating film 143, and a metal material 144 inside a trench that penetrates the first semiconductor substrate 121. Polysilicon may be embedded instead of the metal material 144. In the guard ring 271 of the first modified example in Figure 19, an air gap 145 is further formed inside the metal material 144.

[0093] <Second modified example of the pad portion> Figure 20 is a cross-sectional view showing a second modified example of the pad portion 92.

[0094] In the second modified example shown in Figure 20, the position of the electrode pad 91 in the substrate depth direction is changed from the basic pad structure shown in Figure 6. In the basic pad structure shown in Figure 6, the electrode pad 91 was located below the bonding surface between the first substrate 101 and the second substrate 102, within the wiring layer 161 on the second semiconductor substrate side. In the second modified example shown in Figure 20, the electrode pad 91 is located above the bonding surface between the first substrate 101 and the second substrate 102, within the wiring layer 122 on the first semiconductor substrate 121 side. Specifically, the electrode pad 91 is positioned between the bonding electrode 185 and the bottommost metal wiring 183. Of the multiple layers of metal wiring 183 in the wiring layer 122, the lower layer or lower side represents the direction away from the first semiconductor substrate 121 and closer to the second substrate 102, while the upper layer or upper side represents the direction closer to the first semiconductor substrate 121 and further away from the second substrate 102. Furthermore, the electrode pad 91 may be placed not between the bonding electrode 185 and the bottommost metal wiring 183, but between any two metal wirings 183 of the multiple layers of metal wiring 183. In other words, the position of the electrode pad 91 in the depth direction of the substrate may be placed at any position between the bonding electrode 185 and the topmost metal wiring 183.

[0095] <Third Modified Example of Pad Section> Figure 21 is a cross-sectional view showing a third modified example of the pad section 92.

[0096] In the third modified example shown in Figure 21, the position of the electrode pad 91 in the depth direction of the substrate is also changed from the basic pad structure shown in Figure 6. In the basic pad structure shown in Figure 6, the electrode pad 91 was located below the bonding surface between the first substrate 101 and the second substrate 102, and was provided within the wiring layer 161 of the second substrate 102. In the third modified example shown in Figure 21, the electrode pad 91 is located above the bonding surface between the first substrate 101 and the second substrate 102, and is provided within the wiring layer 122 of the first substrate 101. The electrode pad 91 is connected to a plurality of wiring vias 184 on its lower surface.

[0097] The anode voltage VA supplied to the electrode pad 91 is supplied to the lower junction electrode 185 via the wiring via 184, and then supplied to the junction electrode 185 of the wiring layer 122 of the first substrate 101, which is connected to the guard ring 271, via the metal wiring in the wiring layer 161 of the second substrate 102. Furthermore, the anode voltage VA is supplied to the high-concentration P-type diffusion layer 155 via the wiring via 184, the metal wiring 183, and the contact electrode 181. Further, the anode voltage VA is transmitted from the high-concentration P-type diffusion layer 155 to the OPB light-shielding film 272 via the contact electrode 182 and the metal material 144 in the guard ring 271, and is extracted to the back side of the first semiconductor substrate 121.

[0098] The second modification in Figure 20 and the third modification in Figure 21 are similar in that the electrode pad 91 is located above the bonding surface of the first substrate 101 and the second substrate 102, and is provided within the wiring layer 122 of the first substrate 101. On the other hand, the second modification in Figure 20 supplies the anode voltage VA to the metal material 144 in the guard ring 271 without going through the metal wiring in the wiring layer 161 of the second substrate 102, whereas the third modification in Figure 21 supplies the anode voltage VA to the metal material 144 in the guard ring 271 via the metal wiring in the wiring layer 161 of the second substrate 102. In the third modification as well, the position of the electrode pad 91 in the substrate depth direction may be placed at any position between the bonding electrode 185 and the uppermost metal wiring 183.

[0099] <Fourth Modified Example of the Pad Section> Figure 22 is a cross-sectional view showing a fourth modified example of the pad section 92.

[0100] In the fourth modified example shown in Figure 22, the electrode pad 91 is located on the back side (light incident side) of the first semiconductor substrate 121, rather than on the front side, which is different from the basic pad structure shown in Figure 6. The electrode pad 91 is provided on the back side of the first semiconductor substrate 121 and is directly connected to the OPB light-shielding film 272. The anode voltage VA supplied to the electrode pad 91 is supplied to the inter-pixel separation section 141 in the pixel array section 81 via the OPB light-shielding film 272 which extends in the planar direction, or via the grid-like through-trench 331 which extends in the planar direction and the substrate depth direction.

[0101] <Fifth Modified Example of Pad Section> Figure 23 is a cross-sectional view showing a fifth modified example of the pad section 92.

[0102] In the fifth modified example shown in Figure 23, the position of the high-concentration P-type diffusion layer 155 has been changed from the basic pad structure shown in Figure 6. In the basic pad structure shown in Figure 6, the high-concentration P-type diffusion layer 155 was located inside the guard ring 271 (on the side of the opening 251). In the fifth modified example shown in Figure 23, the high-concentration P-type diffusion layer 155 is located outside the guard ring 271 (on the opposite side of the opening 251). Furthermore, a second guard ring 411 is located even further outside the guard ring 271 and the high-concentration P-type diffusion layer 155. An insulating film 412 made of the same material as the insulating film 143 formed on the back side of the first semiconductor substrate 121 is embedded inside the second guard ring 411. The second guard ring 411, like the guard ring 271, is formed in a rectangular shape in a plan view so as to surround the opening 251.

[0103] <Sixth Modified Example of the Pad Section> Figure 24 is a cross-sectional view showing the sixth modified example of the pad section 92.

[0104] In the sixth modified example shown in Figure 24, the high-concentration P-type diffusion layer 155 is omitted from the basic pad structure shown in Figure 6, and the contact electrode 181 is directly connected to a contact electrode 182 made of, for example, polysilicon.

[0105] <Seventh Modified Example of the Pad Section> Figure 25 is a cross-sectional view showing the seventh modified example of the pad section 92.

[0106] In the seventh modified example shown in Figure 25, the high-concentration P-type diffusion layer 155 and contact electrode 182 are omitted from the basic pad structure shown in Figure 6, and the metal material 144 of the guard ring 271 is directly connected to the metal wiring 183 of the wiring layer 122 of the first semiconductor substrate 121. The trench of the guard ring 271 is dug out until it reaches the metal wiring 183 of the wiring layer 122, and the fixed charge film 142, insulating film 143, and metal material 144 are embedded inside the trench. The hole accumulation layer 154 of the pad portion 92 may be omitted.

[0107] <Eighth modified example of the pad portion> Figure 26 is a cross-sectional view showing the eighth modified example of the pad portion 92.

[0108] In the eighth modified example shown in Figure 26, the high-concentration P-type diffusion layer 155, contact electrode 182, metal wiring 183, wiring via 184, etc., are omitted from the basic pad structure shown in Figure 6, and the metal material 144 of the guard ring 271 is directly connected to the electrode pad 91 of the wiring layer 161 of the second substrate 102. The guard ring 271 is formed by excavating a trench for the guard ring 271 that penetrates the wiring layer 122 of the first substrate 101 and reaches the electrode pad 91, and then embedding a fixed charge film 142, an insulating film 143, and the metal material 144 inside the trench. The hole accumulation layer 154 of the pad portion 92 may be omitted.

[0109] <Combination of Basic Pad Structure and Modified Examples> The basic pad structure shown in Figure 6 and the various modified structures shown in Figures 19 to 26 may be combined as appropriate to form a pad structure. For example, the second guard ring 411 of the fifth modified example in Figure 23 may be combined with the pad structure of another modified example. Also, for example, the arrangement of the electrode pad 91 of the second modified example in Figure 20 may be adopted in the structures of the fifth modified example in Figure 23 to the eighth modified example in Figure 26.

[0110] In the basic pad structure shown in Figure 6 and the various modifications shown in Figures 19 to 26, the anode voltage VA supplied to the electrode pad 91 can be taken out to the back side of the first semiconductor substrate 121 and supplied to the inter-pixel separation section 141 in the pixel array section 81 via the OPB light-shielding film 272 that extends in the planar direction, or the grid-like through-trench 331 that extends in the planar direction and the substrate depth direction. This realizes a low-resistance voltage supply path and allows the anode voltage VA to be supplied to each pixel 40.

[0111] <8.2 Summary of the Laminated Structure> The photodetector 23 comprises a first semiconductor substrate 121 having a photoelectric conversion region for photoelectric conversion of incident light, a light-shielding film (inter-pixel light-shielding film 146, OPB light-shielding film 272) formed on the light-incident surface side of the first semiconductor substrate 121, and an electrode pad 91 formed on the side opposite to the light-incident surface side of the first semiconductor substrate 121, and has a pixel array section 81 having pixels 40 and a pad section 72 having the electrode pad 91. The pad section 72 includes a guard ring 271 in which a metal material 144 is embedded in a trench penetrating the first semiconductor substrate 121. The guard ring 271 is configured to extract a predetermined voltage (e.g., anode voltage VA) supplied to the electrode pad 91 to the light-incident surface side of the first semiconductor substrate 121, and the predetermined voltage extracted to the light-incident surface side of the first semiconductor substrate 121 by the guard ring 271 is supplied to the pixels 40 of the pixel array section 81 by the light-shielding film. The guard ring 271 and light-shielding films (inter-pixel light-shielding film 146, OPB light-shielding film 272) enable a low-resistance voltage supply path, allowing a predetermined voltage to be supplied to each pixel 40 with low resistance. The predetermined voltage supplied to the electrode pad 91 (e.g., anode voltage VA) flows from the electrode pad 91 of the pad section 92, selecting the low-resistance portions of the OPB light-shielding film 272 and the grid-shaped through-trench 331, in the planar direction and the substrate depth direction.

[0112] When a highly concentrated diffusion layer (impurity region) is used as a voltage supply path to supply a predetermined voltage from the front surface to the back surface of the first semiconductor substrate 121, its resistivity is approximately ~0.1 [Ω・cm]. On the other hand, when the supply path is formed via the guard ring 271 or the metal material 144 of the inter-pixel separation section 141 of this disclosure, for example, if the metal material 144 is tungsten, its resistivity becomes approximately 7.3e-6 [Ω・cm], which is several orders of magnitude lower, thus enabling low resistance and being advantageous for IR drop, etc.

[0113] Furthermore, by providing a grid-like through-trench 331 in the pixel array peripheral portion 82 between the pad portion 92 and the pixel array portion 81, and allowing the current to flow through low-resistance areas in the planar direction and substrate depth direction, the resistance can be reduced by about 20 times, depending on conditions such as film thickness. Therefore, this is advantageous for reducing IR drop and can contribute to reducing power consumption.

[0114] In the example described above, the anode voltage VA is supplied to the electrode pad 91 of the pad portion 92 from an external source. However, the structure of this disclosure is also applicable to electrode pads 91 to which voltages or signals other than the anode voltage VA are input and output.

[0115] <9.3 Example of Pixel Cross-Sectional Configuration in a Stacked Structure> In the example described above, the photodetector 23 was described as having a stacked structure in which two substrates, a first substrate 101 and a second substrate 102, are stacked. The photodetector 23 can also be configured as a stacked structure in which three substrates are stacked. Below, the structure of the pixel 40 and pad portion 92 when configured as a stacked structure in which three substrates are stacked will be described.

[0116] Figure 27 is a cross-sectional view showing an example of the configuration of a pixel 40 in a three-layer stacked structure.

[0117] The pixel 40 shown in Figure 27 has a laminated structure in which a first substrate 101, a second substrate 502, and a third substrate 503 are stacked. The first substrate 101, the second substrate 502, and the third substrate 503 are stacked in that order, with the second substrate 502 positioned between the first substrate 101 and the third substrate 503. In Figure 27, the bonding surfaces of the first substrate 101 and the second substrate 502, and the bonding surfaces of the second substrate 502 and the third substrate 503 are shown by dashed lines. The first substrate 101 on which the on-chip lens 148 is formed is the substrate on the side of the object 30 (Figure 1) to be measured.

[0118] The three-layered structure in Figure 27 is the same as the two-layered structure in Figure 5, but with the second substrate 102 replaced by the second substrate 502 and the third substrate 503. The explanation of the first substrate 101, which is common to both Figure 5 and Figure 27, will be omitted as appropriate.

[0119] The second substrate 502 has a semiconductor substrate 511, a wiring layer 512, and an insulating layer 513. The third substrate 503 has a semiconductor substrate (not shown) and a wiring layer 514.

[0120] On the second substrate 502, an insulating layer 513 is formed on the back side of the semiconductor substrate 511, and a wiring layer 512 is formed on the front side of the semiconductor substrate 511. The insulating layer 513 formed on the back side of the semiconductor substrate 511 is bonded to the wiring layer 122 of the first substrate 101, and the wiring layer 512 formed on the front side of the semiconductor substrate 511 is bonded to the wiring layer 514 of the third substrate 503. Hereinafter, the semiconductor substrate 511 of the second substrate 502 will be referred to as the second semiconductor substrate 511, and the semiconductor substrate not shown on the third substrate 503 will be referred to as the third semiconductor substrate.

[0121] Multiple pixel transistors Tr, including pixel transistors Tr1 and Tr2, are formed on the second substrate 502. Pixel transistor Tr1 is an N-type MOS transistor whose source and drain regions are formed in the substrate region 521 of the second semiconductor substrate 511 using N-type impurity regions. Pixel transistor Tr2 is a P-type MOS transistor whose source and drain regions are formed in the substrate region 521 of the second semiconductor substrate 511 using P-type impurity regions. An insulating film 522 is embedded in the region of the second semiconductor substrate 511 other than the region where the pixel transistors Tr are formed.

[0122] The wiring layer 512 of the second substrate 502 has multiple layers of metal wiring 531 and an interlayer insulating film 532. In Figure 27, three layers of metal wiring 531 are formed, but the number of layers of metal wiring 531 is not limited. The multiple layers of metal wiring 531 are connected to the upper and lower metal wiring 531 at required locations by wiring vias 533. The gate electrodes, source regions, and drain regions of the pixel transistors Tr1 and Tr2 are connected to predetermined metal wiring 531 via contact vias 541. The metal wiring 531, wiring vias 533, and contact vias 541 are made of, for example, tungsten (W), aluminum (Al), copper (Cu), etc. The interlayer insulating film 532 is made of, for example, a single layer or multiple layers of SiO2, SiN, SiON, etc. The wiring layer 512 further has multiple junction electrodes 534 at the junction surface with the wiring layer 514 of the third substrate 503. The bonding electrodes 534 are formed from a metallic material such as Cu (copper) or Al (aluminum). Each bonding electrode 534 is used for electrical connection between the second substrate 502 and the third substrate 503, and for bonding the second substrate 502 and the third substrate 503. Barrier metal may be formed on the metal wiring 531, wiring vias 533, and bonding electrodes 534.

[0123] The third substrate 503 has a semiconductor substrate (not shown), which is a third semiconductor substrate, and a wiring layer 514, and is bonded to the second substrate 502 with the front surface of the third semiconductor substrate facing the front surface of the second substrate 502. In other words, the third substrate 503 is bonded to the second substrate 502 face to face. Logic circuits such as a TDC for measuring time and a histogram generation unit for generating a histogram based on the measured time are formed on the third semiconductor substrate (not shown) of the third substrate 503.

[0124] The wiring layer 514 of the third substrate 503 has multiple layers of metal wiring 551 and an interlayer insulating film 552. The number of layers of metal wiring 551 is not limited. The multiple layers of metal wiring 551 are connected to the upper and lower metal wiring 551 at required locations by wiring vias 553. The metal wiring 551 is made of, for example, tungsten (W), aluminum (Al), copper (Cu), etc. The interlayer insulating film 552 is made of, for example, a single layer or multiple layers of SiO2, SiN, SiON, etc. The wiring layer 514 further has multiple bonding electrodes 554 at the bonding surface with the wiring layer 512 of the second substrate 502. The bonding electrodes 554 are made of, for example, a metallic material such as copper (Cu) or aluminum (Al). Each bonding electrode 554 is used for electrical connection between the second substrate 502 and the third substrate 503 and for bonding the second substrate 502 and the third substrate 503.

[0125] If the light detection device 23 is composed of a stacked structure of three substrates, the pixels 40 can be configured as described above. With a three-layer stacked structure for the pixels 40, even if the number of pixels or pixel circuits increases, the light detection device 23 can be formed with the same chip size as before. Alternatively, if the number of pixels or pixel circuits remains the same as before, a light detection device 23 with an even smaller chip size can be provided.

[0126] Figure 28 illustrates the difference in pixel circuit arrangement between a two-layer stacked structure and a three-layer stacked structure.

[0127] Figure 28A shows the correspondence between the cross-sectional view of a two-layer laminated structure and the circuit layout, and Figure 28B shows the correspondence between the cross-sectional view of a three-layer laminated structure and the circuit layout.

[0128] As shown in Figure 28A, when the pixel 40 is configured in a two-layer stacked structure, the pixel sensor section 51 including the SPAD 61 is formed on the first substrate 101, and the pixel readout circuit 52 including a transistor 62 and an inverter 63, which are constant current sources, is formed on the second substrate 102. In this case, there is a concern that the wiring distance connecting the SPAD 61, the transistor 62 and the inverter 63 will be long, and the parasitic capacitance will increase.

[0129] As shown in Figure 28B, when the pixel 40 is configured in a three-layer stacked structure, the pixel readout circuit 52, which includes a transistor 62 and an inverter 63 that are constant current sources, can be formed on the second substrate 502. This reduces parasitic capacitance. In addition, the area where logic circuits can be placed increases to the second substrate 502 and the third substrate 503, thus increasing the circuit area.

[0130] <10.3 Example of Cross-Sectional Configuration of Pad Section in a Laminated Structure> Figure 29 is a cross-sectional view showing an example of the configuration of one pad section 92 of the pad region 72 in a laminated structure.

[0131] In Figure 29, parts common to Figure 27 are denoted by the same reference numerals, and redundant explanations are omitted as appropriate.

[0132] As in the example described above, the pad portion 92 in Figure 29 will be described as the pad portion 92 of the electrode pad 91 to which the anode voltage VA supplied to the anode of the SPAD 61 is input from an external source. However, the pad portion 92 in Figure 29 differs from the example described above in that the electrode pad 91 and the guard ring 271 are not electrically connected. In the example of the three-layer stacked structure described below, as will be explained in detail later, the anode voltage VA supplied to the electrode pad 91 is supplied to each pixel 40 of the pixel array portion 81 using the wiring layer 512 of the second substrate 502 or the wiring layer 514 of the third substrate 503, which are located below the first semiconductor substrate 121. At each pixel 40, for example, the anode voltage VA is supplied to the contact electrode 182 from a contact via connected to the contact electrode 182 in an area not shown in Figure 27. Of course, as with the two-layer laminated structure described above, the electrode pad 91 and the guard ring 271 may be electrically connected, and a metal wiring supplying the anode voltage VA may be routed on the back side of the first semiconductor substrate 121.

[0133] The pad portion 92 in Figure 29 has electrode pads 91 at the same layer position as the second semiconductor substrate 511. Therefore, when the pad portion 92 is configured as a three-layer laminated structure, the electrode pads 91 are placed on the second substrate 502, not the third substrate 503. An opening 251 is provided above the electrode pads 91, and an anode voltage VA is supplied to the electrode pads 91 from the outside by wire bonding or the like. The electrode pads 91 are electrically connected to the first substrate 101 via the wiring layer 514 of the third substrate 503.

[0134] More specifically, the electrode pad 91 is connected to the underlying metal wiring 531 via contact via 542, and further electrically connected to the wiring layer 514 of the third substrate 503 via multiple layers of metal wiring 531, wiring via 533, and bonding electrodes 534, 554. The anode voltage VA supplied to the electrode pad 91 is supplied to each pixel 40 of the pixel array 81 via the wiring layer 514 of the third substrate 503.

[0135] A guard ring 571 is formed around the electrode pad 91 placed on the second substrate 502. In a plan view, the guard ring 571 is formed in a rectangular shape that surrounds the electrode pad 91. The guard ring 571 is formed by embedding the same metal material as the contact via 542 in a trench that penetrates the second semiconductor substrate 511.

[0136] The contact via 542 connected to the electrode pad 91 is a via formed at the same time as the contact via 541 connected to the pixel transistor Tr formed on the second substrate 502 in each pixel 40 of the pixel array 81. The guard ring 571 is also formed at the same time as the contact via 541.

[0137] In the pad portion 92 of the pad region 72 configured as described above, the electrode pad 91 is positioned at a depth of the second semiconductor substrate 511 of the second substrate 502, which is placed between the first substrate 101 and the third substrate 503. As a result, the pad depth DP, which is the depth from the opening 251 to the electrode pad 91, can be made shallower (shorter) compared to when it is placed on the third substrate 503, thus facilitating bonding.

[0138] <11. Modified Pad Section> Next, a modified version of the pad section 92 shown in Figure 29 will be described with reference to Figures 30 to 37. In the following description, the example configuration of the pad section 92 shown in Figure 29 will be referred to as the basic pad structure.

[0139] <First modified example of the pad portion> Figure 30 is a cross-sectional view showing a first modified example of the pad portion 92.

[0140] Comparing the first modified example in Figure 30 with the basic pad structure shown in Figure 29, the method of connecting the lower layer of the electrode pad 91 is different. In the basic pad structure shown in Figure 29, the electrode pad 91 was connected to the first layer of metal wiring 531 via a contact via 542. In contrast, in the first modified example in Figure 30, the contact via 542 is omitted, and the electrode pad 91 is directly connected to the first layer of metal wiring 531 in the wiring layer 512. Note that the first, second, and third layers of metal wiring 531 in the wiring layer 512 refer to the order of the layers counted from the first substrate 101 side.

[0141] <Second modified example of the pad portion> Figure 31 is a cross-sectional view showing a second modified example of the pad portion 92.

[0142] In the second modified example shown in Figure 31, compared to the basic pad structure shown in Figure 29, the contact via 542 and the first layer of metal wiring 531 are omitted, and the electrode pad 91 is directly connected to the wiring via 533 between the first and second layers of metal wiring 531.

[0143] <Third Modification of the Pad Section> Figure 32 is a cross-sectional view showing a third modification of the pad section 92.

[0144] In the third modified example shown in Figure 32, compared to the basic pad structure shown in Figure 29, the contact via 542 to the second layer of metal wiring 531 is omitted, and the electrode pad 91 is directly connected to the wiring via 533 between the second and third layers of metal wiring 531.

[0145] <Fourth Modified Example of the Pad Section> Figure 33 is a cross-sectional view showing a fourth modified example of the pad section 92.

[0146] In the fourth modified example shown in Figure 33, compared to the basic pad structure shown in Figure 29, the contact via 542 to the third layer of metal wiring 531 is omitted, and the electrode pad 91 is directly connected to the wiring via 533 connected to the bonding electrode 534.

[0147] The first modified example in Figure 30 to the fourth modified example in Figure 33 are merely examples, and the connection of the electrode pads 91, which are positioned at least at the depth of the second semiconductor substrate 511 on the second substrate 502, to any metal wiring 531 or wiring via 533 in the wiring layer 512 of the second substrate 502 may be determined as appropriate.

[0148] <Fifth Modified Example of Pad Section> Figure 34 is a cross-sectional view showing a fifth modified example of the pad section 92.

[0149] In the fifth modified example shown in Figure 34, the electrode pad 91 has the structure of the fourth modified example shown in Figure 33 and is directly connected to the wiring via 533 connected to the bonding electrode 601. In the fourth modified example shown in Figure 33, the anode voltage VA supplied to the electrode pad 91 was configured to pass through the wiring layer 514 of the third substrate 503 and then be supplied from the third substrate 503 to the second substrate 502 and the first substrate 101 in the pixel array section 81.

[0150] In contrast, in the fifth modified example shown in Figure 34, the anode voltage VA supplied to the electrode pad 91 is supplied to the pixel array section 81 by bonding electrodes 601 and 602 formed in a wiring-like manner at the bonding surface of the second substrate 502 and the third substrate 503. Bonding electrode 601 is the bonding electrode on the wiring layer 512 side of the second substrate 502, and bonding electrode 602 is the bonding electrode on the wiring layer 514 side of the third substrate 503. Bonding electrodes 601 and 602 have the functions of electrical connection between the second substrate 502 and the third substrate 503, bonding the second substrate 502 and the third substrate 503, and supplying the anode voltage VA from the pad section 92 to the pixel array section 81. The anode voltage VA supplied from the pad section 92 to the pixel array section 81 is supplied to the first substrate 101 side within the pixels 40 of the pixel array section 81 via the metal wiring 531 and wiring via 533 of the wiring layer 512 of the second substrate 502, and also to the third substrate 503 side via the wiring via 553 and metal wiring 551 of the wiring layer 514 of the third substrate 503.

[0151] <Sixth Modified Example of the Pad Section> Figure 35 is a cross-sectional view showing the sixth modified example of the pad section 92.

[0152] In the sixth modified example shown in Figure 35, a metal wiring 621 directly connected to the electrode pad 91 is routed from the pad portion 92 to the pixel array portion 81. As a result, the anode voltage VA supplied to the electrode pad 91 is supplied to the pixel array portion 81 via the metal wiring 621. The anode voltage VA supplied from the pad portion 92 to the pixel array portion 81 via the metal wiring 621 is supplied to the first substrate 101 side within the pixels 40 of the pixel array portion 81 via the metal wiring 531 and wiring via 533 of the wiring layer 512 of the second substrate 502, and also to the third substrate 503 side via the bonding electrodes 534, 554, wiring via 553 and metal wiring 551. Therefore, the electrode pad 91 is electrically connected to the first substrate 101 and the third substrate 503 in the pixel array portion 81 via the metal wiring 621.

[0153] Figure 36 is a plan view showing the arrangement of the electrode pad 91 and metal wiring 621 in Figure 35. Figure 36 is a view of the electrode pad 91 and metal wiring 621 from the third substrate 503 side.

[0154] The metal wiring 531 connected to the lower layer of the guard ring 571 is not formed on a predetermined side of the rectangular electrode pad 91, but is open. The metal wiring 621 connected to the side of the electrode pad 91 opposite to the bonding surface is led out from the open side to the outside of the electrode pad 91. The metal wiring 621 led out to the outside of the electrode pad 91 is routed to the pixel array section 81.

[0155] As described above, by routing the metal wiring 621 on the wiring layer 512 side of the second substrate 502 from the pad portion 92 to the pixel array portion 81 without using bonding electrodes 601 and 602, it is possible to configure the system to supply the anode voltage VA supplied to the electrode pad 91 from the pad portion 92 to the pixel array portion 81.

[0156] In the sixth modified example shown in Figure 35, the metal wiring 621 is formed in the same position as the second layer of metal wiring 531 among the three layers of metal wiring 531 in the wiring layer 512 of the second substrate 502, but it may also be placed in the position of the metal wiring 531 in any of the other layers. In other words, the metal wiring 621 that connects to the electrode pad 91 and wires from the pad portion 92 to the pixel array portion 81 may be placed in any of the multiple layers of metal wiring 531 in the wiring layer 512 of the second substrate 502.

[0157] <Seventh Modified Example of the Pad Section> Figure 37 is a cross-sectional view showing the seventh modified example of the pad section 92.

[0158] The seventh modified example shown in Figure 37 is a structure adopted when the anode voltage VA supplied to the electrode pad 91 is required only on the first substrate 101 and the second substrate 502, and not on the third substrate 503.

[0159] In the seventh modified example shown in Figure 37, a metal wiring 641 connected to the electrode pad 91 via a wiring via 533 is routed from the pad portion 92 to the pixel array portion 81. As a result, the anode voltage VA supplied to the electrode pad 91 is supplied from the pad portion 92 to the pixel array portion 81. The anode voltage VA supplied to the pixel array portion 81 is then supplied to the first substrate 101 side at the pixels 40 of the pixel array portion 81 via the metal wiring 531, wiring via 533, etc., of the wiring layer 512 of the second substrate 502. On the other hand, with respect to the third substrate 503 side, the metal wiring 641 is not directly or indirectly connected to the junction electrode 554, wiring via 553, or metal wiring 551 of the wiring layer 514 of the third substrate 503, and therefore the anode voltage VA supplied to the electrode pad 91 is not supplied to the third substrate 503 side.

[0160] <Combination of basic pad structure and modified examples> The basic pad structure shown in Figure 29 and the various modified structures shown in Figures 30 to 37 may be combined as appropriate to form a pad structure.

[0161] In the basic pad structure shown in Figure 29 and the various modified examples shown in Figures 30 to 37, the pad depth DP can be made shallower by placing the electrode pad 91 at least at the depth of the second semiconductor substrate 511 on the second substrate 502 in the three-layer stacked structure. Since the area of ​​the electrode pad 91 can be made smaller compared to when it is placed on the third substrate 503, the area efficiency can be improved.

[0162] <12.3-Layer Stacked Structure Manufacturing Method> Next, the manufacturing method for the pad basic structure shown in Figure 29 will be described with reference to Figures 38 to 50. In Figures 38 to 50, the right side, separated by a space, shows a cross-sectional view of the region where the pixel transistor Tr of the pixel 40 is formed, and the left side shows a cross-sectional view of the region of the pad portion 92. Also, in Figures 38 to 50, the cross-sectional views shown in Figures 27 and 29 are inverted vertically during manufacturing, so the second substrate 502 side of the first semiconductor substrate 121 is at the top of the drawing, and the light incident surface side is at the bottom of the drawing.

[0163] First, as shown in Figure 38, a first semiconductor substrate 101, on which a P-type diffusion layer 152 and an N-type diffusion layer 153 forming an avalanche multiplication region 156 in the pixel region of the first semiconductor substrate 121, and a hole accumulation layer 154 formed near the inter-pixel separation portion 141, are bonded together by plasma bonding or the like with a second semiconductor substrate 511 on which pixel transistors Tr(Tr1,Tr2) are formed. The hole accumulation layer 154 and the high-density P-type diffusion layer 155 are also formed in the pad portion 92, similar to the region of the pixel 40. An insulating film 701, such as silicon nitride (SiN), is formed on the upper surface of the second semiconductor substrate 511 on which the pixel transistors Tr are formed. In the second semiconductor substrate 511 of the second substrate 502, the substrate region 521 remains only in the region where the pixel transistors Tr in the pixel region are formed and in the region where the electrode pads 91 of the pad portion 92 are formed, and the insulating film 522 is embedded in the other regions.

[0164] Next, as shown in Figure 39, a resist 702 is deposited on the upper layer of the insulating film 701 of the second semiconductor substrate 511, and then patterned. During the patterning of the resist 702, openings 703 are formed in the region where the electrode pads 91 are formed.

[0165] Next, as shown in Figure 40, the second semiconductor substrate 511 is etched using the patterned resist 702 as a mask. This removes the substrate region 521 of the second semiconductor substrate 511, and an opening 704 is formed in the second semiconductor substrate 511.

[0166] Next, as shown in Figure 41, after the resist 702 is removed, an insulating film 711 such as SiO2 is formed on the upper surface of the opening 704 of the second semiconductor substrate 511 and on the upper layer of the insulating film 701.

[0167] Next, as shown in Figure 42, a metal material 712 for forming electrode pads 91 is deposited on the entire upper surface of the insulating film 711. This embeds the metal material 712 inside the opening 704 of the second semiconductor substrate 511. For example, AlCu is used as the metal material 712. A resist 713 is formed on top of the metal material 712 embedded in the opening 704.

[0168] Next, as shown in Figure 43, the insulating film 711, the metal material 712, and the resist 713 above the insulating film 701 on the second semiconductor substrate 511 are etched. This forms electrode pads 91 on the pad portion 92.

[0169] Next, as shown in Figure 44, interlayer insulating films 721 and 722 are sequentially laminated and planarized on the upper layer of the electrode pad 91 of the pad portion 92 and on the upper layer of the pixel transistor Tr in the pixel region. The interlayer insulating films 721 and 722 may be different types of insulating films or the same type of insulating film. For example, the interlayer insulating film 721 may be an SiO2 film and the interlayer insulating film 722 may be a TEOS film.

[0170] Next, as shown in Figure 45, trenches 731 and 732 are formed in the pad portion 92 and trenches 733 and 734 are formed in the pixel region by etching the interlayer insulating films 721 and 722, etc. Trenches 731 and 732 are formed in the positions where the contact vias 542 and guard rings 571 of the pad portion 92 are formed. Trench 733 is formed in the gate electrode, source region, and drain region of the pixel transistor Tr. Trench 734 is formed in the high-density P-type diffusion layer 155 of the inter-pixel isolation portion 141.

[0171] Next, as shown in Figure 46, a predetermined metal material is embedded in the trenches 731 and 732 of the pad portion 92 and the trenches 733 and 734 of the pixel region to form the contact via 542 of the pad portion 92, the guard ring 571, and the contact vias 541 and 543 of the pixel region. The trenches 731 to 734 can be formed simultaneously in the same process, and the process of embedding the metal material can also be carried out simultaneously. For example, tungsten can be used as the metal material to be embedded. A barrier metal may be formed as a base before embedding the metal material. The contact via 543 of the pixel region is wiring for supplying the anode voltage VA to the high-density P-type diffusion layer 155 of the pixel 40.

[0172] Next, as shown in Figure 47, a wiring layer 512 including multiple layers of metal wiring 531 and interlayer insulating film 532 is formed by sequentially repeating the process of forming multiple layers of metal wiring 531, wiring vias 533 connecting each layer of metal wiring 531, and interlayer insulating film 532 on the upper layer of contact vias 541 to 543, guard ring 571, and interlayer insulating film 722 using a damascene method or the like. Barrier metal may be formed as a base before embedding the metal wiring 531. The interlayer insulating film 532 is composed of insulating film 701, interlayer insulating films 721 and 722, and an interlayer insulating film stacked on top of them. The insulating film 701, interlayer insulating films 721 and 722, and the upper layer of interlayer insulating film are composed of single or multilayer layers of, for example, SiO2, SiN, or SiON.

[0173] Next, as shown in Figure 48, a trench 751 is formed at the location where the bonding electrode 534 will be formed on the upper surface of the wiring layer 512 of the second substrate 502, which will be the bonding surface with the third substrate 503. Furthermore, as shown in Figure 49, multiple trenches 761 are formed in a predetermined area of ​​the trench 751 by dry etching or the like until the uppermost layer of metal wiring 531 is reached. Then, by embedding a metal material such as copper (Cu) inside the multiple trenches 751 and 761 that have been formed, wiring vias 533 and bonding electrodes 534 are formed, as shown in Figure 50.

[0174] Through the above process, a second semiconductor substrate 511 including electrode pads 91, pixel transistors Tr, etc., and a second substrate 502 including wiring layers 512 are completed.

[0175] In the subsequent steps, the wiring layer 512 of the second substrate 502 and the wiring layer 514 of the third substrate 503 are bonded together, then the substrate is inverted so that the first substrate 501 is on top, and the first semiconductor substrate 121 is thinned. After forming the inter-pixel separation section 141 and the like on the first semiconductor substrate 121, the inter-pixel light-shielding film 146, OPB light-shielding film 272, planarization film 147, on-chip lens 148, and the like are sequentially formed to complete the three-layer stacked photodetector 23.

[0176] By aligning the height of the connection surface of the electrode pad 91 to which the contact via 542 is connected in the pad portion 92 with the height of the connection surface of the pixel transistor Tr to which the contact via 541 is connected in the pixel region, the contact vias 541, 542 and the guard ring 571 can be formed simultaneously, thereby reducing the number of steps required for contact via formation.

[0177] <13. Summary of the 3-Layer Laminated Structure> The photodetector 23 is constructed by laminating a first substrate 101 having a photoelectric conversion region for converting incident light into photoelectric energy, a second substrate 502 on which pixel transistors Tr for reading out the charge generated in the photoelectric conversion region are formed, and a third substrate 503 having a logic circuit. The second substrate 502 has a semiconductor substrate 511, a wiring layer 512, and electrode pads 91 for electrically connecting to the outside. The electrode pads 91 are provided at the same depth as the second semiconductor substrate 511 of the second substrate 502, which is positioned between the first substrate 101 and the third substrate 503. As the electrode pads 91 are provided at the same depth as the second semiconductor substrate 511 of the second substrate 502, which is positioned between the first substrate 101 and the third substrate 503, the pad depth DP from the opening 251 to the electrode pads 91 can be made shallower (shorter) compared to when they are positioned on the third substrate 503, thus facilitating bonding. By making the pad depth DP shallower, the area of ​​the electrode pads 91 can be reduced, thereby improving area efficiency.

[0178] In the above example, the configuration of the pad portion 92 of the pad area 72 and the pixels 40 of the pixel array area 71 was described, and an example was described in which the electrode pad 91 of the pad portion 92 is supplied with an anode voltage VA from an external source. However, the structure of this disclosure can also be applied to electrode pads 91 to which voltages or signals other than the anode voltage VA are input and output.

[0179] <14. Examples of Application to Mobile Devices> The technology relating to this disclosure (this technology) can be applied to various products. For example, the technology relating to this disclosure may be implemented as a device mounted on any type of mobile device such as automobiles, electric vehicles, hybrid electric vehicles, motorcycles, bicycles, personal mobility devices, airplanes, drones, ships, and robots.

[0180] Figure 51 is a block diagram showing a schematic configuration example of a vehicle control system, which is an example of a mobile control system to which the technology described herein may be applied.

[0181] The vehicle control system 12000 comprises a plurality of electronic control units connected via a communication network 12001. In the example shown in Figure 51, the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an external information detection unit 12030, an internal information detection unit 12040, and an integrated control unit 12050. The functional configuration of the integrated control unit 12050 is shown in the figure, which includes a microcomputer 12051, an audio / image output unit 12052, and an in-vehicle network interface 12053.

[0182] The drivetrain control unit 12010 controls the operation of devices related to the vehicle's drivetrain according to various programs. For example, the drivetrain control unit 12010 functions as a control device for a drivetrain generating device that generates driving force for the vehicle, such as an internal combustion engine or a drive motor; a drivetrain transmission mechanism that transmits driving force to the wheels; a steering mechanism that adjusts the steering angle of the vehicle; and a braking device that generates braking force for the vehicle.

[0183] The body system control unit 12020 controls the operation of various devices mounted on the vehicle body according to various programs. For example, the body system control unit 12020 functions as a control device for a keyless entry system, a smart key system, a power window system, or various lamps such as headlights, reverse lights, brake lights, turn signals, or fog lights. In this case, the body system control unit 12020 may receive radio waves transmitted from a portable device that replaces a key or signals from various switches. The body system control unit 12020 receives these radio waves or signals and controls the vehicle's door lock system, power window system, lamps, etc.

[0184] The external information detection unit 12030 detects information from outside the vehicle equipped with the vehicle control system 12000. For example, an imaging unit 12031 is connected to the external information detection unit 12030. The external information detection unit 12030 causes the imaging unit 12031 to capture images of the outside of the vehicle and receives the captured images. Based on the received images, the external information detection unit 12030 may perform object detection processing such as detecting people, cars, obstacles, signs, or characters on the road surface, or distance detection processing.

[0185] The imaging unit 12031 is a light sensor that receives light and outputs an electrical signal corresponding to the amount of light received. The imaging unit 12031 can output the electrical signal as an image or as distance measurement information. The light received by the imaging unit 12031 may be visible light or invisible light such as infrared light.

[0186] The in-vehicle information detection unit 12040 detects information inside the vehicle. The in-vehicle information detection unit 12040 is connected to, for example, a driver status detection unit 12041 that detects the driver's state. The driver status detection unit 12041 includes, for example, a camera that captures images of the driver, and the in-vehicle information detection unit 12040 may calculate the driver's level of fatigue or concentration, or determine whether the driver is drowsy, based on the detection information input from the driver status detection unit 12041.

[0187] The microcomputer 12051 can calculate control target values ​​for the drive force generator, steering mechanism, or braking device based on information inside and outside the vehicle acquired by the external information detection unit 12030 or the internal information detection unit 12040, and output control commands to the drive system control unit 12010. For example, the microcomputer 12051 can perform cooperative control aimed at realizing ADAS (Advanced Driver Assistance System) functions, including collision avoidance or impact mitigation, following driving based on distance between vehicles, maintaining vehicle speed, vehicle collision warning, or vehicle lane departure warning.

[0188] Furthermore, the microcomputer 12051 can perform cooperative control for purposes such as autonomous driving, where the vehicle drives autonomously without driver intervention, by controlling the drive force generating device, steering mechanism, or braking device, etc., based on information about the vehicle's surroundings acquired by the external information detection unit 12030 or the internal information detection unit 12040.

[0189] Furthermore, the microcomputer 12051 can output control commands to the body system control unit 12020 based on external information acquired by the external information detection unit 12030. For example, the microcomputer 12051 can control the headlights according to the position of a preceding or oncoming vehicle detected by the external information detection unit 12030, and perform coordinated control aimed at reducing glare, such as switching from high beams to low beams.

[0190] The audio-image output unit 12052 transmits at least one of audio and image output signals to an output device capable of visually or audibly notifying information to the vehicle's occupants or to those outside the vehicle. In the example shown in Figure 51, the output devices include an audio speaker 12061, a display unit 12062, and an instrument panel 12063. The display unit 12062 may include, for example, at least one of an onboard display and a head-up display.

[0191] Figure 52 shows an example of the installation position of the imaging unit 12031.

[0192] In Figure 52, the imaging unit 12031 includes imaging units 12101, 12102, 12103, 12104, and 12105.

[0193] The imaging units 12101, 12102, 12103, 12104, and 12105 are installed, for example, on the front nose, side mirrors, rear bumper, back door, and the upper part of the windshield inside the vehicle 12100. The imaging unit 12101 installed on the front nose and the imaging unit 12105 installed on the upper part of the windshield inside the vehicle mainly acquire images of the front of the vehicle 12100. The imaging units 12102 and 12103 installed on the side mirrors mainly acquire images of the sides of the vehicle 12100. The imaging unit 12104 installed on the rear bumper or back door mainly acquires images of the rear of the vehicle 12100. The imaging unit 12105 installed on the upper part of the windshield inside the vehicle is mainly used for detecting preceding vehicles, pedestrians, obstacles, traffic lights, traffic signs, or lanes.

[0194] Figure 52 shows an example of the imaging ranges of imaging units 12101 to 12104. Imaging range 12111 indicates the imaging range of imaging unit 12101 located on the front nose, imaging ranges 12112 and 12113 indicate the imaging ranges of imaging units 12102 and 12103 located on the side mirrors, respectively, and imaging range 12114 indicates the imaging range of imaging unit 12104 located on the rear bumper or back door. For example, by superimposing the image data captured by imaging units 12101 to 12104, an overhead view image of the vehicle 12100 can be obtained.

[0195] At least one of the imaging units 12101 to 12104 may have a function for acquiring distance information. For example, at least one of the imaging units 12101 to 12104 may be a stereo camera consisting of multiple image sensors, or an image sensor having pixels for phase difference detection.

[0196] For example, the microcomputer 12051, based on distance information obtained from imaging units 12101 to 12104, can determine the distance to each object within the imaging range 12111 to 12114 and the temporal change of this distance (relative speed to the vehicle 12100). In particular, it can extract the closest object on the vehicle 12100's path that is traveling in approximately the same direction as the vehicle 12100 at a predetermined speed (e.g., 0 km / h or more) as the preceding vehicle. Furthermore, the microcomputer 12051 can set a predetermined distance to be maintained before the preceding vehicle and perform automatic braking control (including follow-and-stop control) and automatic acceleration control (including follow-and-start control), etc. In this way, cooperative control aimed at autonomous driving, where the vehicle drives autonomously without driver intervention, can be performed.

[0197] For example, the microcomputer 12051 can use distance information obtained from imaging units 12101 to 12104 to classify and extract three-dimensional object data related to three-dimensional objects, such as motorcycles, passenger cars, large vehicles, pedestrians, utility poles, and other three-dimensional objects, and use this data for automatic obstacle avoidance. For example, the microcomputer 12051 identifies obstacles around the vehicle 12100 into obstacles that are visible to the driver of the vehicle 12100 and obstacles that are difficult to see. The microcomputer 12051 then determines the collision risk, which indicates the degree of risk of collision with each obstacle. If the collision risk is above a set value and there is a possibility of collision, the microcomputer 12051 can provide driving assistance to avoid collisions by outputting a warning to the driver via the audio speaker 12061 or the display unit 12062, or by performing forced deceleration or evasive steering via the drive system control unit 12010.

[0198] At least one of the imaging units 12101 to 12104 may be an infrared camera that detects infrared light. For example, the microcomputer 12051 can recognize pedestrians by determining whether or not pedestrians are present in the images captured by the imaging units 12101 to 12104. Such pedestrian recognition is performed, for example, by a procedure to extract feature points from the images captured by the imaging units 12101 to 12104 as infrared cameras, and a procedure to perform pattern matching on a series of feature points that indicate the contour of an object to determine whether or not it is a pedestrian. When the microcomputer 12051 determines that a pedestrian is present in the images captured by the imaging units 12101 to 12104 and recognizes a pedestrian, the audio-image output unit 12052 controls the display unit 12062 to superimpose a rectangular contour line for emphasis on the recognized pedestrian. The audio-image output unit 12052 may also control the display unit 12062 to display an icon indicating a pedestrian at a desired position.

[0199] The above describes an example of a vehicle control system to which the technology of this disclosure may be applied. The technology of this disclosure can be applied to the imaging unit 12031, etc., among the configurations described above. Specifically, the imaging unit 12031 can be the electronic device 1 or the distance measuring device 11 shown in Figure 1. The imaging unit 12031 is, for example, a LIDAR and is used to detect objects around the vehicle 12100 and the distance to those objects. By applying the technology of this disclosure to the imaging unit 12031, the detection accuracy of objects around the vehicle 12100 and the distance to those objects is improved. As a result, for example, collision warnings for the vehicle can be issued at an appropriate time, making it possible to prevent traffic accidents.

[0200] In this specification, a system refers to a collection of multiple components (devices, modules (parts), etc.), regardless of whether all components are located in the same enclosure. Therefore, multiple devices housed in separate enclosures and connected via a network, and a single device containing multiple modules within a single enclosure, are both considered systems.

[0201] The embodiments of the technology described herein are not limited to those described above, and various modifications are possible without departing from the spirit of the technology described herein.

[0202] In the example described above, a pixel cross-sectional structure in which electrons are used as signal charges was explained with the first conductivity type being P-type and the second conductivity type being N-type. However, this disclosure can also be applied to a pixel cross-sectional structure in which holes are used as signal charges. That is, by setting the first conductivity type to N-type and the second conductivity type to P-type, each of the aforementioned semiconductor regions can be composed of semiconductor regions of the opposite conductivity type.

[0203] The effects described herein are merely illustrative and not limiting; other effects may also occur.

[0204] The technology of this disclosure may adopt the following configurations: (1) A photodetector comprising: a semiconductor substrate having a photoelectric conversion region for photoelectric conversion of incident light; a light-shielding film formed on the light incident surface side of the semiconductor substrate; and an electrode pad formed on the side opposite to the light incident surface side of the semiconductor substrate, wherein the photodetector comprises a pixel array portion having pixels and a pad region having the electrode pad, the pad region includes a guard ring in which a metal material is embedded in a trench penetrating the semiconductor substrate, the guard ring extracts a predetermined voltage supplied to the electrode pad to the light incident surface side of the semiconductor substrate, and the predetermined voltage extracted to the light incident surface side of the semiconductor substrate by the guard ring is supplied to the pixels of the pixel array portion via the light-shielding film. (2) The photodetector according to (1), wherein the pixels are SPAD pixels capable of detecting a single photon, and the predetermined voltage supplied to the electrode pad is a voltage applied to form an avalanche multiplication region in the photoelectric conversion region of the pixel. (3) The photodetector according to (1) or (2), wherein, in a plan view, the photodetector has a pixel array peripheral portion between the pixel array portion and the pad region, and the light-shielding film has a solid pattern or a grid pattern in the pixel array peripheral portion. (4) The photodetector according to (3), wherein the light-shielding film in the pixel array peripheral portion is connected to the metal material embedded in the guard ring in the pad region and connected to the inter-pixel light-shielding film formed on the light incident surface side of the semiconductor substrate in the pixel array portion. (5) The photodetector according to any one of (3) to (4), wherein the light-shielding film has the solid pattern in the pixel array peripheral portion. (6) The photodetector according to (5), wherein the pattern width of the solid pattern of the light-shielding film is formed to gradually narrow as it approaches the electrode pad from the pixel array portion. (7) The photodetector according to (3), wherein the light-shielding film has the grid pattern in the pixel array peripheral portion.(8) The light detection device according to any one of (1) to (7), wherein, in a plan view, the pixel array peripheral portion is located between the pixel array portion and the pad region, the pixel array peripheral portion has a grid-like through trench in which a metal material is embedded inside a grid-like trench that penetrates the semiconductor substrate, and the predetermined voltage extracted to the light incident surface side of the semiconductor substrate by the guard ring is supplied to the pixels of the pixel array portion through the grid-like through trench. (9) The light detection device according to (8), wherein the width of the plane of the grid-like through trench in a direction perpendicular to the direction from the electrode pad toward the pixel array portion is formed to gradually narrow as it approaches the electrode pad. (10) The light-shielding film is formed in a grid shape in the pixel array portion, and the grid-like through trench in the pixel array peripheral portion is formed in the same grid shape as the grid shape of the pixel array portion. (11) The light-shielding film is formed in a grid pattern in the pixel array portion, and the grid-like through trenches in the peripheral portion of the pixel array are formed in a grid pattern different from the grid pattern of the pixel array portion, as described in any of (8) to (9). (12) The light-detecting device according to any of (8) to (11), having a first voltage region in plan view where the predetermined voltage is applied to the outer periphery of the grid-like through trenches and the electrode pads. (13) The light-detecting device according to (12), having through trenches in which an insulating film is embedded in the outer periphery of the first voltage region, as described in plan view. (14) The light-detecting device according to any of (12) to (13), wherein in plan view, the substrate region from the outer periphery of the grid-like through trenches and the electrode pads to the end face of the chip is the first voltage region to which the predetermined voltage is applied.(15) The optical detection device according to any one of (1) to (14), wherein, in a plan view, a pixel array peripheral portion is located between the pixel array portion and the pad region, the pixel array peripheral portion having a first voltage region to which the predetermined voltage is applied, a second voltage region to which ground is applied, and a second guard ring between the first voltage region and the second voltage region, and the second guard ring is configured by embedding at least an insulating film and a metal material in a trench penetrating the semiconductor substrate. (16) The optical detection device according to any one of (1) to (14), wherein, in a plan view, a pixel array peripheral portion is located between the pixel array portion and the pad region, the pixel array peripheral portion having a first voltage region to which the predetermined voltage is applied, a second voltage region to which ground is applied, and a second guard ring between the first voltage region and the second voltage region, and the second guard ring is configured by embedding an insulating film in a trench penetrating the semiconductor substrate. (17) A photodetector according to any one of (1) to (16), wherein, in a plan view, the photodetector has a pixel array peripheral portion between the pixel array portion and the pad region, the pixel array peripheral portion has a first voltage region to which the predetermined voltage is applied, a second voltage region to which ground is applied, and a third guard ring between the second voltage region and the guard ring, and the third guard ring is configured by embedding an insulating film in a trench penetrating the semiconductor substrate. (18) A photodetector according to any one of (1) to (17), wherein the photodetector has an insulating film between the light-shielding film on the light incident surface side of the semiconductor substrate and the semiconductor substrate, the thickness of the insulating film is thicker than the thickness of the insulating film on the side wall of the guard ring. (19) A photodetector according to any one of (1) to (18), wherein the predetermined voltage is supplied to a plurality of electrode pads in the pad region, and the predetermined voltage is supplied from the plurality of electrode pads to the pixels in the pixel array portion. (20) The photodetector according to any one of (1) to (19), wherein the photodetector is configured in a laminated structure of the semiconductor substrate and the second semiconductor substrate, and the electrode pad is provided on the second semiconductor substrate side of the bonding surface between the semiconductor substrate and the second semiconductor substrate.(21) The photodetector according to any one of (1) to (19), comprising a laminated structure of the semiconductor substrate and a second semiconductor substrate, wherein the electrode pad is provided on the semiconductor substrate side from the junction surface between the semiconductor substrate and the second semiconductor substrate. (22) The photodetector according to any one of (1) to (19), comprising a laminated structure of the semiconductor substrate and a second semiconductor substrate, wherein the electrode pad is provided on the light incident surface side of the semiconductor substrate. (23) The photodetector comprising a first substrate having a photoelectric conversion region for photoelectric conversion of incident light, a second substrate having a transistor for reading the charge generated in the photoelectric conversion region, and a third substrate having a logic circuit, wherein the second substrate has a semiconductor substrate, a wiring layer, and an electrode pad for electrically connecting to the outside, and the electrode pad is provided at the same depth position as the semiconductor substrate. (24) The photodetector according to (23), wherein the wiring layer of the second substrate and the wiring layer of the third substrate are electrically connected, and the electrode pad is electrically connected to the first substrate via the wiring layer of the third substrate. (25) The photodetector according to (24), wherein the wiring layer of the second substrate has a plurality of layers of metal wiring, wiring vias connecting the metal wiring of different layers to each other, a bonding electrode joining the wiring layer of the second substrate and the wiring layer of the third substrate, and an interlayer insulating film, and the electrode pad is electrically connected to the wiring layer of the third substrate via at least one of the metal wiring or the wiring via and the bonding electrode. (26) The photodetector according to (25), wherein the electrode pad is electrically connected to the wiring layer of the third substrate via a contact via connecting the electrode pad to the metal wiring, at least one of the metal wiring or the wiring via and the bonding electrode. (27) The photodetector according to any one of (25) to (26), wherein the junction electrode electrically connected to the electrode pad is formed in a wiring manner to the pixel array portion having the photoelectric conversion region.(28) The photodetector according to any one of (23) to (27), wherein the wiring layer of the second substrate has a plurality of layers of metal wiring, wiring vias connecting the metal wiring of different layers to each other, a bonding electrode joining the wiring layer of the second substrate and the wiring layer of the third substrate, and the electrode pad is connected to a predetermined metal wiring among the plurality of layers of metal wiring of the wiring layer of the second substrate, and the predetermined metal wiring connected to the electrode pad is wired to the pixel array section having the photoelectric conversion region and is electrically connected to the first substrate. (29) The photodetector according to (28), wherein the predetermined metal wiring connected to the electrode pad is electrically connected to the wiring layer of the third substrate in the pixel array section via at least one of the metal wiring or the wiring via and the bonding electrode. (30) The photodetector according to any one of (28) to (29), wherein the predetermined metal wiring connected to the electrode pad has guard rings on the outside of the three sides surrounding the electrode pad, and the predetermined metal wiring connected to the electrode pad is drawn out from the side without the guard ring to the outside of the electrode pad and wired to the pixel array section. (31) The photodetector according to any one of (28) to (29), wherein the predetermined metal wiring connected to the electrode pad is configured not to be electrically connected to the third substrate.

[0205] 1 Electronic device, 11 Distance measuring device, 12 Application unit, 22 Light source device, 23 Light detection device, 30 Object, 31 Irradiated light, 32 Reflected light, 40, 40B Pixel, 51 Pixel sensor unit, 52 Pixel readout circuit, 62 Transistor, 63 Inverter, 71 Pixel array area, 72 Pad area, 81 Pixel array unit, 82 Pixel array peripheral unit, 91 Electrode pad, 92 Pad unit, 101 First substrate, 102 Second substrate, 121 Semiconductor substrate (First semiconductor substrate), 122 Wiring layer, 141 Inter-pixel separation unit, 142 Fixed charge film, 143, 143' Insulating film, 144 Metal material, 145 Air gap, 146 Inter-pixel light shielding film, 147 Planarization film, 148 On-chip lens, 151 N-well, 152 P-type diffusion layer, 153 N-type diffusion layer, 154 Hole accumulation layer, 155 High-concentration P-type diffusion layer, 156 Avalanche multiplication region, 161 Wiring layer, 181 Contact electrode, 182 Contact electrode, 183 Metal wiring, 184 Wiring via, 185 Junction electrode, 191 Interlayer insulating film, 201 Junction electrode, 202 Wiring via, 203 Pad wiring, 211 Interlayer insulating film, 251 Aperture, 271 Guard ring, 272 OPB light-shielding film, 282 Interlayer insulating film, 311 Anode voltage region, 312 Ground region, 313,313' Guard ring, 331 Grid-like through trench, 351 Through trench 371 Through trench, 411 Second guard ring, 412 Insulating film, 501 First substrate, 502 Second substrate, 503 Third substrate, 511 Semiconductor substrate (Second semiconductor substrate), 512 Wiring layer, 513 Insulating layer, 514 Wiring layer, 521 Substrate region, 522 Insulating film, 531 Metal wiring, 532 Interlayer insulating film, 533 Wiring via, 534 Junction electrode, 541 Contact via, 542 Contact via, 543 Contact via, 551 Metal wiring, 552 Interlayer insulating film, 553 Wiring via, 554 Junction electrode, 571 Guard ring, 601 Junction electrode, 602 Junction electrode, 621, 641 Metal wiring, DP Pad depth, Tr1, Tr2 Pixel transistors

Claims

A semiconductor substrate having a photoelectric conversion region that converts incident light into photoelectric energy, A light-shielding film formed on the light incident surface side of the semiconductor substrate, An electrode pad formed on the side opposite to the light incident surface of the semiconductor substrate and Equipped with, It comprises a pixel array portion having pixels and a pad region having the electrode pads, The pad region includes a guard ring in which a metal material is embedded in a trench penetrating the semiconductor substrate. The guard ring extracts a predetermined voltage supplied to the electrode pad and places it on the light incident surface side of the semiconductor substrate. The predetermined voltage, extracted to the light incident surface side of the semiconductor substrate by the guard ring, is supplied to the pixels of the pixel array portion via the light-shielding film. Light detection device. 　 The aforementioned pixel is a SPAD pixel capable of detecting a single photon, The predetermined voltage supplied to the electrode pad is a voltage applied to form an avalanche multiplication region in the photoelectric conversion region of the pixel. The light detection device according to claim 1. 　 In a plan view, the pixel array peripheral portion is located between the pixel array portion and the pad region. The light-shielding film has a solid pattern or a grid pattern in the peripheral portion of the pixel array. The light detection device according to claim 1. 　 The light-shielding film in the peripheral portion of the pixel array is connected to the metal material embedded in the guard ring in the pad region and to the inter-pixel light-shielding film formed on the light-incident surface side of the semiconductor substrate in the pixel array portion. The light detection device according to claim 3. 　 The light-shielding film has the solid pattern in the peripheral portion of the pixel array. The light detection device according to claim 3. 　 The pattern width of the solid pattern of the light-shielding film is formed to gradually narrow as it approaches the electrode pad from the pixel array portion. The light detection device according to claim 5. 　 The light-shielding film has the grid pattern in the peripheral portion of the pixel array. The light detection device according to claim 3. 　 In a plan view, the pixel array peripheral portion is located between the pixel array portion and the pad region. The peripheral portion of the pixel array has grid-like through trenches in which a metal material is embedded inside grid-like trenches that penetrate the semiconductor substrate. The predetermined voltage, extracted to the light incident surface side of the semiconductor substrate by the guard ring, is supplied to the pixels of the pixel array through the grid-like through-trenches. The light detection device according to claim 1. 　 The width of the grid-like through trench in the direction perpendicular to the direction from the electrode pad toward the pixel array is formed to gradually narrow as it approaches the electrode pad. The light detection device according to claim 8. 　 The light-shielding film is formed in a grid pattern in the pixel array portion, The grid-like through trenches in the peripheral portion of the pixel array are formed in the same grid pattern as the grid pattern of the pixel array portion. The light detection device according to claim 8. 　 The light-shielding film is formed in a grid pattern in the pixel array portion, The grid-like through trenches in the peripheral portion of the pixel array are formed with a grid pattern different from that of the pixel array portion. The light detection device according to claim 8. 　 In a plan view, the grid-like through trench and the outer circumference of the electrode pad have a first voltage region to which the predetermined voltage is applied. The light detection device according to claim 8. 　 In a plan view, the first voltage region has a through trench with an insulating film embedded in its outer periphery. The light detection device according to claim 12. 　 In a plan view, the substrate region from the outer periphery of the grid-like through trench and the electrode pad to the end face of the chip is defined as the first voltage region to which the predetermined voltage is applied. The light detection device according to claim 12. 　 In a plan view, the pixel array peripheral portion is located between the pixel array portion and the pad region. The periphery of the pixel array has a first voltage region to which the predetermined voltage is applied, a second voltage region to which ground is applied, and a second guard ring between the first voltage region and the second voltage region. The second guard ring is constructed by embedding at least an insulating film and a metal material in a trench that penetrates the semiconductor substrate. The light detection device according to claim 1. 　 In a plan view, the pixel array peripheral portion is located between the pixel array portion and the pad region. The periphery of the pixel array has a first voltage region to which the predetermined voltage is applied, a second voltage region to which ground is applied, and a second guard ring between the first voltage region and the second voltage region. The second guard ring is constructed by embedding an insulating film in a trench that penetrates the semiconductor substrate. The light detection device according to claim 1. 　 In a plan view, the pixel array peripheral portion is located between the pixel array portion and the pad region. The periphery of the pixel array has a first voltage region to which the predetermined voltage is applied, a second voltage region to which ground is applied, and a third guard ring between the second voltage region and the guard ring. The third guard ring is constructed by embedding an insulating film in a trench that penetrates the semiconductor substrate. The light detection device according to claim 1. 　 An insulating film is provided between the light-shielding film on the light incident surface side of the semiconductor substrate and the semiconductor substrate, The thickness of the insulating film is set to be thicker than the insulating film on the side wall of the guard ring. The light detection device according to claim 1. 　 The predetermined voltage is supplied to the plurality of electrode pads in the pad area. Multiple electrode pads are configured to supply the predetermined voltage to the pixels of the pixel array. The light detection device according to claim 1. 　 It is composed of a laminated structure of the aforementioned semiconductor substrate and a second semiconductor substrate, The electrode pad is provided on the side of the second semiconductor substrate from the bonding surface between the semiconductor substrate and the second semiconductor substrate. The light detection device according to claim 1. 　 It is composed of a laminated structure of the aforementioned semiconductor substrate and a second semiconductor substrate, The electrode pad is provided on the semiconductor substrate side of the bonding surface between the semiconductor substrate and the second semiconductor substrate. The light detection device according to claim 1. 　 It is composed of a laminated structure of the aforementioned semiconductor substrate and a second semiconductor substrate, The electrode pad is provided on the light incident surface side of the semiconductor substrate. The light detection device according to claim 1. 　 A first substrate having a photoelectric conversion region that converts incident light into photoelectric energy, A second substrate on which a transistor for reading the charge generated in the photoelectric conversion region is formed, A third board having a logic circuit and It is constructed by stacking these, The second substrate comprises a semiconductor substrate, a wiring layer, and electrode pads for electrical connection to the outside. The electrode pad is provided at the same depth as the semiconductor substrate. Light detection device. 　 The wiring layer of the second substrate and the wiring layer of the third substrate are electrically connected. The electrode pad is electrically connected to the first substrate via the wiring layer of the third substrate. The light detection device according to claim 23. 　 The wiring layer of the second substrate comprises multiple layers of metal wiring, wiring vias connecting the metal wiring of different layers, bonding electrodes joining the wiring layer of the second substrate and the wiring layer of the third substrate, and an interlayer insulating film. The electrode pad is electrically connected to the wiring layer of the third substrate via at least one of the metal wirings or wiring vias and the bonding electrode. The light detection device according to claim 24. 　 The electrode pad is electrically connected to the wiring layer of the third substrate via a contact via connecting the electrode pad to the metal wiring, at least one of the metal wiring or the wiring via, and the bonding electrode. The light detection device according to claim 25. 　 The bonding electrode, electrically connected to the electrode pad, is formed in a wiring-like manner to the pixel array portion having the photoelectric conversion region. The light detection device according to claim 25. 　 The wiring layer of the second substrate comprises multiple layers of metal wiring, wiring vias connecting the metal wiring of different layers, bonding electrodes joining the wiring layer of the second substrate and the wiring layer of the third substrate, and an interlayer insulating film. The electrode pad is connected to a predetermined metal wiring among the multiple layers of metal wiring in the wiring layer of the second substrate. The predetermined metal wiring connected to the electrode pad is routed to the pixel array section having the photoelectric conversion region and is electrically connected to the first substrate. The light detection device according to claim 23. 　 The predetermined metal wiring connected to the electrode pad is electrically connected in the pixel array portion to the wiring layer of the third substrate via at least one of the metal wiring or the wiring via and the bonding electrode. The light detection device according to claim 28. 　 The electrode pad has a guard ring on the outside of the three sides surrounding it. The predetermined metal wiring connected to the electrode pad is routed out from one side without the guard ring to the outside of the electrode pad and to the pixel array section. The light detection device according to claim 28. 　 The predetermined metal wiring connected to the electrode pad is configured not to be electrically connected to the third substrate. The light detection device according to claim 28.

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