Semiconductor module and semiconductor module manufacturing method

Abstract

The present invention provides a semiconductor module manufacturing method and a semiconductor module capable of significantly reducing the thermal resistance of the semiconductor module. This semiconductor module comprises a semiconductor chip (12), a joining layer (11), and a metal plate (101) in this order. The joining layer (11) includes at least one type of substance selected from the group consisting of gold, silver, a gold alloy, and a silver alloy. The main surface, of the metal plate (101), on the joining layer (11) side includes a polycrystalline structure of copper and / or a copper alloy. The metal plate (101) has, on the main surface (101a), a texture in which the maximum value of the degree of integration of the <111> axis during a polar analysis using X-ray diffraction is greater than 20.

Description

Semiconductor module and method for manufacturing a semiconductor module

[0001] This disclosure relates to semiconductor modules and methods for manufacturing semiconductor modules.

[0002] In electronic components using semiconductor elements that generate significant heat, such as LED lighting devices, semiconductor computing devices, semiconductor memory, and automotive power modules, efficiently dissipating the heat generated during use is a challenge. To address this challenge, methods such as increasing the thermal conductivity of the insulating layer of the printed circuit board on which the electronic components are mounted, or dissipating heat from the electronic components or printed circuit board to a heatsink via thermal interface materials or solder, have been employed.

[0003] For example, Patent Document 1 discloses a semiconductor structure that improves heat dissipation by incorporating a conductive material with a different coefficient of thermal expansion from a crystalline oxide semiconductor as the main component in a support layer.

[0004] Furthermore, Patent Document 2 discloses a bonding wire for use in a semiconductor device having 1.0 to 4.0 mass% of Pd and a total of 50 mass ppm or less of group S elements (5.0 to 12.0 mass ppm of S, 5.0 to 20.0 mass ppm of Se, or 15.0 to 50 mass ppm of Te). Patent Document 2 also discloses that the <100> orientation ratio in the crystal plane of the cross-section of this wire is 15% or more and the <111> orientation ratio is 50% or less.

[0005] Japanese Patent Publication No. 2016-81946, International Publication No. 2020 / 183748

[0006] The problem to be solved by the present invention will be described by taking a power semiconductor module as an example. In the following description, the power semiconductor module may be described as a power module. The conventional power module had the following problems. FIG. 20 shows a schematic view of a power module 2. The power module 2 includes a metal plate 201 disposed on the front side of a ceramic plate 200 and a metal plate 202 disposed on the back side thereof, and an insulating substrate 20 is formed. A semiconductor chip 21 is joined to the metal plate 201 by solder 22. In this configuration, the heat generated by the semiconductor chip 21 is dissipated by a cooler (not shown) via the solder 22 and the insulating substrate 20. FIG. 21 shows the breakdown of the power module thermal resistance (semiconductor module thermal resistance) R ｔｈ＿ｊｃ from the front surface of the semiconductor chip 21 to the back surface of the metal plate 202. Thermal resistance R ｔｈ＿ｊｃ is composed of chip thermal resistance R ｔｈ＿ｃｈｉｐ 30, solder thermal resistance R ｔｈ＿ｓｏｌｄｅｒ 31, copper thermal resistance R ｔｈ＿Ｃｕ 32, ceramics thermal resistance R ｔｈ＿ｃｅｒａｍｉｃ 33, and copper thermal resistance R ｔｈ＿Ｃｕ 34. Each thermal resistance R ｔｈ is basically calculated by the following formula (1). Thermal resistance R ｔｈ = thickness t / thermal conductivity λ × heat transfer area A... (1)

[0007] Among these, the thermal resistance R ｔｈ＿ｓｏｌｄｅｒ 31 of the solder 22 has a small heat transfer area that is the same as that of the semiconductor chip 21, so the proportion of the power module thermal resistance R ｔｈ＿ｊｃ 3 is as large as about 40%, which is a problem for improving heat dissipation performance.

[0008] Such a problem is not limited to the power semiconductor module, but is a common problem in semiconductor modules in which a high-heat-generating semiconductor chip is joined to a metal plate such as copper. The large thermal resistance of the solder used for joining is a problem for improving heat dissipation performance. Therefore, in view of the above problems, the present disclosure aims to provide a semiconductor module and a method for manufacturing the semiconductor module capable of significantly reducing the semiconductor module thermal resistance.

[0009] One aspect of the present disclosure is a semiconductor module comprising, in this order, a semiconductor chip, a bonding layer, and a metal plate, wherein the bonding layer includes at least one selected from the group consisting of gold, silver, gold alloys, and silver alloys, the main surface of the metal plate on the bonding layer side includes a polycrystalline structure of at least one of copper and copper alloys, and the main surface of the metal plate has a texture in which the maximum value of the <111> axis integration exceeds 20 in pole analysis using X-ray diffraction.

[0010] Another aspect of the present disclosure is a method for manufacturing a semiconductor module comprising the steps of: placing a semiconductor chip having a first metal layer on at least a portion of its surface and a metal plate having a second metal layer on at least a portion of its main surface such that the first metal layer and the second metal layer face each other; and joining the first metal layer and the second metal layer to form a bonding layer, wherein the first metal layer includes at least one selected from the group consisting of gold, silver, gold alloys, and silver alloys; the second metal layer includes at least one selected from the group consisting of gold, silver, gold alloys, and silver alloys; the main surface of the metal plate on the side of the second metal layer includes a polycrystalline structure of at least one of copper and copper alloys; and the main surface of the metal plate has a texture on its main surface such that the maximum value of the <111> axis integration exceeds 20 in pole analysis using X-ray diffraction.

[0011] According to this disclosure, it is possible to provide a semiconductor module capable of significantly reducing the thermal resistance of the semiconductor module, and a method for manufacturing the semiconductor module.

[0012] This is a schematic diagram showing a power module according to one embodiment of the present disclosure. This is a schematic diagram showing twinned crystal grains. This is a schematic diagram showing the surface layer of a copper plate where only the {111} twinned plane is exposed on the surface. This is a schematic diagram showing the surface layer of a copper plate in which two twinned crystal grains, twinned crystal grain A and twinned crystal grain B, have a twinned structure with the {111} plane as the grain interface. This is a schematic diagram showing the case where each twinned crystal grain consists of a single crystal in the surface layer of a copper plate in which two twinned crystal grains, twinned crystal grain A and twinned crystal grain B, have a twinned structure with the {111} plane as the grain interface. This is a scanning electron microscope image showing a cross-section when the bonding layer is a bonded body of two or more metal layers. This is a scanning electron microscope image showing a cross-section when the bonding layer is a bonded body of two or more metal layers, and the thickness of the metal layer is greater than that in Figure 6. This is a schematic diagram showing a modified example of a power module according to one embodiment of the present disclosure. This is a schematic diagram for explaining the crystal axis orientation used in pole analysis using X-ray diffraction. This is a schematic diagram of a pole figure used to explain pole analysis using X-ray diffraction. This is a pole figure showing the results of pole analysis for a copper plate in Manufacturing Example 1. This is a pole figure showing the results of pole analysis for a copper plate in Manufacturing Example 1. This is a pole figure showing the results of pole analysis for a copper plate in Manufacturing Example 2. This is a pole figure showing the results of pole analysis for a copper plate in Manufacturing Example 2. This is a pole figure showing the results of pole analysis for a copper plate in Manufacturing Example 3. This is a pole figure showing the results of pole analysis for a copper plate in Manufacturing Example 3. This is a graph showing the results of thermal stability evaluation for copper plates in Examples 1-2 and Comparative Example 1. This is a graph showing the results of thermal stability evaluation for copper plates in Examples 1-2 and Comparative Example 1. This is a schematic diagram showing a conventional power module. This is an explanatory diagram showing the breakdown of thermal resistance in a conventional power module.

[0013] An embodiment of this disclosure will be described below with reference to the drawings. However, the drawings are schematic, and the relationship between thickness and planar dimensions, the ratio of the thickness of each layer, etc., may differ from the actual ones. Furthermore, there may be differences in dimensional relationships and ratios between the drawings. In addition, the embodiment shown below is an example of an apparatus or method for realizing the technical idea of ​​the present invention, and the technical idea of ​​the present invention is not limited to the material, shape, structure, arrangement, etc. of the components described below.

[0014] Furthermore, the definitions of directions such as up and down in the following explanation are merely for explanatory convenience and do not limit the technical concept of the present invention. For example, it is obvious that if an object is rotated 90° and observed, up and down will be converted to left and right and read accordingly, and if it is rotated 180° and observed, up and down will be inverted and read accordingly.

[0015] <Semiconductor Module> In one embodiment of this disclosure, as an example, a case in which the semiconductor module is a power semiconductor module (power module) will be described. As shown in Figure 1, the power module 1 according to this embodiment comprises a semiconductor chip 12, a bonding layer 11, and an insulating substrate 10 in this order. The insulating substrate 10 has a metal plate 101 on the front side of a ceramic plate 100 and a metal plate 102 on the back side. In other words, the power module 1 comprises a semiconductor chip 12, a bonding layer 11, and a metal plate 101 in this order. The insulating substrate 10 is bonded to the semiconductor chip 12 via the bonding layer 11. The bonding layer 11 consists of a second metal layer 110 provided on at least a part of the main surface 101a of the metal plate 101, and a first metal layer 111 provided on the metal plate 101 side of the semiconductor chip 12. The second metal layer 110 may be provided on the entire surface of the main surface 101a of the metal plate 101. The bonding layer 11 is formed by bonding the second metal layer 110 and the first metal layer 111. The bonding of the second metal layer 110 and the first metal layer 111 may be performed, for example, by atomic diffusion bonding.

[0016] The main surface 101a of the metal plate 101 on the bonding layer 110 side is preferably a polycrystalline structure of copper. The metal plate 101 may be, for example, a copper plate, a polycrystalline body made up of crystal grains of copper or the like, or a microcrystalline copper plate.

[0017] The metal plate 101 has a texture on at least the main surface 101a on the side on which the semiconductor chip 12 is mounted, where the maximum value of the density of the <111> axis exceeds 20 in pole analysis using X-ray diffraction. Hereinafter, the density of the density of the main surface 101a of the metal plate 101, as determined by pole analysis using X-ray diffraction, will also be simply referred to as density. The density of the density is obtained by pole analysis using X-ray analysis, for example, by analyzing the orientation distribution function based on the pole diagram on the {111} plane. A metal plate 101 with a texture of density in this range means that it has been prepared so that the grain boundary energy between the crystal grains of the metal constituting the metal plate is low. In a metal plate 101 prepared so that the grain boundary energy is low, even if it is exposed to heat treatment (reflow treatment) during the manufacturing process of the device or heat during device operation, the increase in surface roughness on the main surface of the metal plate is suppressed due to recrystallization caused by grain boundary diffusion. As a result, even when the bonding layer 11 is formed thinly, delamination between members is suppressed, and the device manufactured using the predetermined metal plate 101 can exhibit excellent reliability.

[0018] In this embodiment, the bonding layer 11 formed by bonding the second metal layer 110 and the first metal layer 111 by atomic diffusion bonding or the like can significantly reduce the thermal resistance of the bonding layer compared to the case where solder is used to bond the semiconductor chip 12 and the metal plate 101 (i.e., when the bonding layer is solder). However, the bonding layer 11 formed by the second metal layer 110 and the first metal layer 111 needs to maintain close contact between the metal plate 101 and the second metal layer 110, and for this purpose it is necessary to suppress the increase in surface roughness on the main surface 101a of the metal plate 101. In the power module 1 according to this embodiment, by setting the integration density of the metal plate 101 within the above range, the increase in surface roughness is suppressed, and the bonding layer 11 can be stably formed by the second metal layer 110 and the first metal layer 111. This makes it possible to significantly reduce the thermal resistance of the power module.

[0019] The following explanation uses the case where the metal plate 101 is composed solely of copper as an example. The same explanation applies even when the metal plate 101 is a copper alloy. In a polycrystalline copper material, the properties of the polycrystalline material differ greatly depending on the relative crystal orientations of adjacent crystal grains at the grain boundaries. When using a general polycrystalline copper material (copper plate) that has not undergone any special treatment, if the copper plate is subjected to heat treatment during the manufacturing of a power module or device incorporating this copper plate, recrystallization may occur between crystal grains in the copper plate so that the interfacial energy (grain boundary energy) at the grain boundaries of adjacent copper crystal grains becomes lower. This can change the relationship of crystal orientations between adjacent crystal grains. For example, a similar state can occur in annealed twins. More specifically, at symmetric tilted grain boundaries with a common rotation axis <110> that includes a twin boundary, the grain boundary energy of the twin structure where the {111} plane or {113} plane becomes the grain interface is low, making it easier for a twin structure to form during the heating process.

[0020] On the other hand, it was found that by pre-treating the copper plate with heat or other methods to create a structure in which the grain boundary energy near the main surface of the copper plate is low, the occurrence of recrystallization on the main surface of the copper plate due to changes in temperature can be suppressed. As a result, the increase in surface roughness on the main surface of the metal plate was suppressed. A structure that results in low grain boundary energy is, for example, a texture in which the crystal orientations of multiple copper crystal grains are aligned in a certain direction.

[0021] Copper has an fcc crystal structure, and among annealed twins, the twin structure where the {111} plane is the grain interface has the lowest grain boundary energy, and grain boundaries with such grain boundary energy are stable to heating. Within a copper crystal, there are four equivalent {111} planes and four <111> axes perpendicular to the {111} planes. Any of the four {111} planes can form a twin structure with it as the grain interface. The grain interface (crystal plane) that forms the twin structure is called the twin plane.

[0022] As shown in Figure 2, a structure in which twins are repeatedly formed with the <111> direction as the axis and the {111} plane perpendicular to that axis as the twinning plane is a stable structure that is easily obtained by recrystallization during the high-temperature heating process of forming copper plates, and is generally present inside the crystal grains of copper. The temperature of the heating process that forms the copper plate is much higher than the temperature of the heat treatment in the manufacturing of power modules and devices into which this copper plate is incorporated. Therefore, the twin structure shown in Figure 2 is stable at the heating temperature in the manufacturing of power modules and devices into which this copper plate is incorporated.

[0023] In Figure 2, the structure is formed by two or more crystals integrating with the {111} plane as a twinning plane, using the <111> axis as a common axis. This entire structure is considered a single crystal grain and is called a twinned crystal grain. In this case, the <111> axis perpendicular to the {111} plane, which is the twinning plane, is sometimes called the twinning axis. A twinned crystal grain is one of the textures with this <111> direction as the axis.

[0024] A twinned crystal grain is composed of two types of crystals: crystal (a) and crystal (b). Both crystal (a) and crystal (b) have the same fcc structure, but the stacking order of atoms in the {111} plane along the <111> axis direction is different. In Figure 2, crystals (a-1), (a-2), and (a-3) are crystal (a), and crystals (b-1) and (b-2) are crystal (b). The number of crystals constituting a twinned crystal grain can be any number. Note that the crystals constituting a twinned crystal grain have three <111> axes in addition to the <111> axis which is the twinning axis of the twinned crystal grain, but Figure 2 only shows the <111> axis which is the twinning axis of the twinned crystal grain. The orientations of these three <111> axes differ by 60° between crystal (a) and crystal (b) within the {111} plane, which is the twinning plane. However, in both crystal (a) and crystal (b), the three-dimensional angles between the four <111> axes, including the <111> twinning axis, are 70.5° or 109.5°. In other words, the relationship of the angles of the <111> axes of the crystals constituting the twinned crystal grains allows us to determine that they are twinned crystal grains.

[0025] Here, as shown in Figure 3, the surface of the microcrystalline copper plate is oriented such that the <111> axis (twin axis) is oriented from the normal to the copper plate Pｓｉ If it is composed of a single tilted twin crystal grain, only the {111} twin plane that is stable against heat is exposed on the surface, so a surface that is stable against temperature rise can be obtained. And the inventors have conceived that by using such a structure, it is possible to suppress the slight surface fluctuations that occur on the surface of the copper plate during the heat treatment (reflow treatment) in the manufacturing process of the device and at the temperature during device operation. At this time, P ｓｉ can be done any number of times.

[0026] Also, the surface of the copper plate may be composed of a microstructure composed of two twin crystal grains as shown in FIG. 4. FIG. 4 is a schematic diagram showing the surface of a copper plate having a twin structure with the {111} planes of crystal P and crystal Q in the crystals constituting each of the two twin crystal grains, twin crystal grain A and twin crystal grain B, as twin planes (grain boundaries). The {111} plane described here may be any of the other three {111} planes excluding the {111} plane perpendicular to the <111> twin axis of the twin crystal grain, and is defined as twin plane S in FIG. 4.

[0027] In the structure as shown in FIG. 4, twin plane S is stable against heat together with the twin planes inside twin crystal grain A and twin crystal grain B. Therefore, by forming such a structure on at least a part of the main surface of the copper plate, it is possible to suppress surface fluctuations against temperature rise compared to a copper plate that does not have such a microstructure. In such a structure, the three-dimensional angle formed by the <111> twin axis of twin crystal grain A and the <111> twin axis of twin crystal grain B is 70.5° or 109.5° (the supplementary angle of 70.5° from 180°). That is, although the orientations of the <111> twin axes of twin crystal grain A and twin crystal grain B are different, it can be said that they form one microstructure. Here, if such a microstructure is formed, the angle P from the film normal of the <111> twin axis of twin crystal grain A in FIG. 4 ｓｉ（Ａ） and the angle P from the plane normal of the <111> twin axis of twin crystal grain B ｓｉ（Ｂ）The sizes do not have to be the same. Furthermore, twinned crystal grains A and B each have a <111> axis different from the <111> twinning axis shown in Figure 4, but as explained in Figure 2, the three-dimensional angle between these <111> axes is 70.5° or 109.5°. In other words, the relationship between the angles of the <111> twinning axes of twinned crystal grains A and B indicates that a twinned grain boundary is formed.

[0028] Although only a partial structure is shown in Figure 4, the above-described structure may be continuously formed over many more crystal grains in addition to twinned crystal grains A and B. In that case, the grain boundaries appearing on the copper plate surface will consist only of stable grain boundaries with the {111} plane as the twinning plane, thus further suppressing the increase in surface roughness on the main surface when subjected to heat treatment. Even in this case, the three-dimensional angle formed by the <111> axis (twin axis) of each twinned crystal grain will be 70.5° or 109.5°, forming a texture with aligned <111> axes. At that time, the higher the degree of accumulation, the more stable the structure of the grain boundaries becomes, further enhancing the effect of suppressing surface fluctuations with respect to temperature rise.

[0029] Furthermore, the number of crystals constituting each twinned crystal grain can be any number; for example, as shown in Figure 5, there may be as few as one. Even in this case, the two crystal grains have a twinned structure via a thermally stable twinning plane S, and since only the heat-stable {111} twinning plane is exposed on the surface of the copper plate, a surface that is stable against temperature increases can be obtained. Even in this case, the three-dimensional angle formed by the <111> axis (twinning axis) of each crystal grain will be 70.5° or 109.5°, and a texture with aligned <111> axes will be formed. At that time, the higher the degree of accumulation, the more stable the grain boundary structure becomes, and the effect of suppressing surface fluctuations with respect to temperature increases is further enhanced.

[0030] Furthermore, in the structure as shown in FIGS. 4 and 5, a plurality of twin-structured grains may form a twin structure with a crystal plane other than the {111} plane as the grain boundary. For example, a twin structure with the {113} plane as the grain boundary also has a low grain boundary energy and is stable against heat. If the grain boundary appearing on the surface of the copper plate is a grain boundary stable against heat, an increase in surface roughness due to a temperature rise can be suppressed. In FIG. 4, the three-dimensional angle formed by the <111> axis of twin-structured grain A and the <111> axis of twin-structured grain B has a specific angle depending on the crystal plane serving as the grain boundary. This is the same for the three-dimensional angle formed by the <111> axis of grain A and the <111> axis of grain B in FIG. 5. Therefore, by examining the angular relationship of the <111> axes, it is possible to know that a grain boundary in a twin relationship is formed. Also, as the integration degree is higher, the grain boundary becomes a more stable structure, so the effect of suppressing surface fluctuations due to a temperature rise is further enhanced.

[0031] The copper plate having such a surface structure may be, for example, a copper plate obtained by a heat treatment such as hot pressing or rolling, or a copper plate obtained by further cutting, machining, polishing, etc. of the copper plate obtained by the heat treatment. When joining a metal plate and a semiconductor chip by the atomic diffusion bonding method, from the viewpoint of making the surface roughness of the copper plate surface smaller, a mirror-polished copper plate is preferable.

[0032] The texture on the main surface 101a of the metal plate 101 has a maximum value of the integration degree of the <111> axis exceeding 20 in the pole figure analysis using X-ray diffraction. However, the maximum value of the integration degree of the <111> axis may be, for example, 23 or more, 25 or more, 26 or more, 28 or more, or 30 or more. The lower limit value of the integration degree of the <111> axis being within the above range means that the stability on the main surface of the metal plate 101 is higher, so an increase in surface roughness caused by being exposed to heat during the manufacturing process and use of the device is suppressed. Also, by making the maximum value of the integration degree of the <111> axis larger, the thermal stability can be further enhanced.

[0033] In the power semiconductor module, the thickness of the metal plate 101 may be, for example, 0.1 mm or more and 1.0 mm or less.

[0034] In this embodiment, the thickness of the metal plate 101, etc., is measured along a direction perpendicular to the main surface of the metal plate 101, etc., that is to be measured. If the thickness of the metal plate 101, etc., is not constant, the thickness can be measured at any 10 locations, and the arithmetic mean of these measurements must fall within the specified range for each thickness.

[0035] The metal plate 101 may be a single-layer metal sheet, or it may be a laminate of two or more layers of metal sheets. When the metal plate 101 is a laminate of metal sheets, it is easier to adjust the thickness of the metal plate 101. Furthermore, since the metal sheet may be a thin film, it is easy to adjust the crystal structure, and it is easy to prepare a metal plate having a texture with an integration density within the above-mentioned range. Also, when preparing the metal plate 101 by laminating the above-mentioned metal sheets, it becomes possible to prepare a more homogeneous metal plate 101. The number of metal sheets constituting the laminate may be, for example, two to five sheets, or two to three sheets.

[0036] The bonding layer 11 includes at least one selected from the group consisting of gold, silver, gold alloys, and silver alloys, but from the viewpoint of corrosion, it is preferably gold or a gold alloy, and more preferably gold.

[0037] The bonding layer 11 may be a bond of two or more metal layers. In the example in Figure 1, the bonding layer 11 is shown as a bond formed by bonding a first metal layer 110 provided on a part of the main surface 101a of the metal plate 101 and a second metal layer 111 provided on the metal plate 101 side of the semiconductor chip 12. The fact that the bonding layer 11 is a bond can be confirmed by cross-sectional observation of the bonding layer. For reference, Figure 6 shows a scanning electron microscope image of a cross-section when the bonding layer is a bond of two or more metal layers. Figure 6 is a cross-section of a laminated structure obtained by bonding two silicon wafers, each having a metal layer made of gold with a thickness of 50 nm on its main surface, by atomic diffusion bonding. As shown in Figure 6, although the bonding layer is a single layer with a thickness of 100 nm, the contrast due to the difference in crystal orientation allows observation of a pseudo-interface corresponding to the surface of the metal layer before bonding, confirming that the bonding layer is a bond of two metal layers.

[0038] Furthermore, the thickness of the bonding layer 11 may be thicker or thinner than the 100 nm shown in Figure 6. For reference, Figure 7 shows a scanning electron microscope image of a cross-section of a stacked structure obtained by bonding two silicon wafers, each having a metal layer made of gold with a thickness of 300 nm on its main surface, by atomic diffusion bonding. As shown in Figure 7, although the bonding layer is a single layer with a thickness of 600 nm, similar to Figure 6, it is possible to observe a pseudo-interface corresponding to the surface of the metal layer before bonding from the contrast due to the difference in crystal orientation, and it can be confirmed that the bonding layer is a bonded body of two metal layers.

[0039] The upper limit of the thickness of the bonding layer 11 may be, for example, 2000 nm or less, 1000 nm or less, 500 nm or less, 300 nm or less, 150 nm or less, or 100 nm or less. The lower limit of the thickness of the bonding layer 11 may be, for example, 5 nm or more, 10 nm or more, 15 nm or more, 30 nm or more, or 50 nm or more.

[0040] The power module 1 may further include an underlayment (not shown) on at least one of the main surface of the bonding layer 11 facing the semiconductor chip 12 and the main surface of the bonding layer 11 facing the metal plate. Alternatively, the power module 1 may include an underlayment on both the main surface of the bonding layer 11 facing the semiconductor chip 12 and the main surface of the bonding layer 11 facing the metal plate 101. By including such an underlayment, the adhesive strength between the bonding layer 11 and the semiconductor chip 12 and the metal plate 101 can be further improved.

[0041] The base layer provided in the bonding layer 11 is, for example, at least one selected from the group consisting of Ti (titanium), V (vanadium), Cr (chromium), Ni (nickel), Zr (zirconium), Nb (niobium), Mo (molybdenum), Hf (hafnium), Ta (tantalum), W (tungsten), and alloys of two or more of these elements.

[0042] The ceramic plate 100 may be, for example, a nitride sintered plate. The nitride sintered plate may be, for example, a boron nitride sintered plate, an aluminum nitride sintered plate, or a silicon nitride sintered plate. The thickness of the ceramic plate 100 may be, for example, 0.1 mm or more and 2.0 mm or less.

[0043] The metal plate 102 (second metal plate) may be the same as or different from the metal plate 101. The metal plate 102 may be a metal sheet or a metal foil. Examples of materials for the metal sheet and metal foil include aluminum and copper.

[0044] <Method for Manufacturing Semiconductor Modules> In the method for manufacturing semiconductor modules according to this embodiment, first, a semiconductor chip 12 having a first metal layer 111 on at least a part of its surface and a metal plate 101 having a second metal layer 110 on at least a part of its main surface 101a are placed on the metal plate 101 such that the second metal layer 110 and the first metal layer 111 face each other (placement step). Next, the second metal layer 110 and the first metal layer 111 are joined to form a bonding layer 11 (bonding step).

[0045] The main surface 101a of the metal plate 101 on the side of the second metal layer 110 contains a polycrystalline structure of at least one of copper and a copper alloy. Furthermore, the metal plate 101 has a texture on its main surface 101a in which the maximum value of the <111> axis accumulation exceeds 20 in pole analysis using X-ray diffraction.

[0046] As the metal plate 101, a metal plate may be used in which the arithmetic mean roughness Sa on the main surface 101a, measured in an environment of 20°C to 30°C, is 60 nm or less. The arithmetic mean roughness Sa on the main surface 101a of the metal plate 101 may be, for example, 50 nm or less, 40 nm or less, 30 nm or less, 20 nm or less, or 10 nm or less. Furthermore, by providing an anti-oxidation film or the like on the main surface 101a of the metal plate 101, the increase in surface roughness due to heat can be further suppressed by preventing direct contact with oxygen.

[0047] The second metal layer 110 includes at least one selected from the group consisting of gold, silver, gold alloys, and silver alloys. The first metal layer 111 includes at least one selected from the group consisting of gold, silver, gold alloys, and silver alloys. The second metal layer 110 and the first metal layer 111 may be composed of the same components or different components, but from the viewpoint of further improving the bonding between the second metal layer 110 and the first metal layer 111, it is preferable that they be composed of the same components.

[0048] The arithmetic mean roughness Sa (Sa2) of the main surface of the second metal layer 110 facing the first metal layer 111, and the arithmetic mean roughness Sa (Sa1) of the main surface of the first metal layer facing the second metal layer 110, may be adjusted according to the thickness of the second metal layer 110 and the first metal layer 111. The arithmetic mean roughness Sa of these main surfaces may all be, for example, less than 6 nm, 4 nm or less, 3 nm or less, or 2 nm or less. When atomic diffusion bonding is used to join the second metal layer 110 and the first metal layer 111, it is desirable that the surface of the joined member be smoother.

[0049] In this embodiment, the arithmetic mean roughness Sa is a parameter that extends Ra (arithmetic mean height of a line) to a surface, and represents the average of the absolute differences in height of each point relative to the average surface plane. The arithmetic mean roughness Sa is a value that is commonly used when evaluating surface roughness and is measured by a small surface roughness measuring instrument. For example, a white light interference microscope can be used as a small surface roughness measuring instrument.

[0050] The thickness of the second metal layer 110 and the thickness of the first metal layer 111 may be, for example, 5 nm to 1000 nm, 5 nm to 800 nm, 5 nm to 600 nm, 5 nm to 400 nm, or 5 nm to 200 nm, respectively. The second metal layer 110 may be an oxidation-preventive film on the metal plate 101.

[0051] The bonding of the second metal layer 110 and the first metal layer 111 may be carried out in an oxygen-containing atmosphere.

[0052] Furthermore, the bonding of the first metal layer 111 and the second metal layer 110 may be performed while pressure is applied in the lamination direction between the first metal layer 111 and the second metal layer 110. The pressure in this case may be, for example, 5 MPa to 100 MPa, 10 MPa to 80 MPa, or 20 MPa to 50 MPa.

[0053] Furthermore, as shown in Figure 8, the semiconductor chip 12 may further comprise a first underlayment 120, and the first metal layer 111 may be provided in close contact with the semiconductor chip 12 via the first underlayment 120. Also, as shown in Figure 8, the metal plate 101 may further comprise a second underlayment 1010, and the second metal layer 110 may be provided in close contact with the metal plate 101 via the second underlayment 1010. In Figure 8, the second underlayment 1010 is shown to cover the entire surface of the main surface 101a of the metal plate 101, but it may be formed in the same area as the second metal layer 110. The first underlayment and the second underlayment each contain at least one selected from the group consisting of Ti, V, Cr, Ni, Zr, Nb, Mo, Hf, Ta, W, and two or more alloys thereof.

[0054] <Modifications> Although several embodiments have been described above, this disclosure is not limited in any way to the embodiments described above. Furthermore, the descriptions of the embodiments described above can be applied to each other.

[0055] For example, the above embodiment described a case where the semiconductor module is a power semiconductor module, but this disclosure is not limited to such examples. It should be understood that the semiconductor module according to this disclosure includes various semiconductor devices such as light-emitting semiconductors and computing semiconductors. Furthermore, in the case of a semiconductor element that does not require electrical insulation, the semiconductor module in this disclosure may have another laminated structure with a metal plate 101 attached to the front side instead of an insulating substrate 10, or it may have only a metal plate 101.

[0056] The contents of this disclosure will be described in more detail below with reference to examples and comparative examples. However, this disclosure is not limited to the following examples.

[0057] <Preparation of Metal Plates> Three types of metal plates were prepared: a microcrystalline copper plate with a thickness of 0.3 mm (Manufacturing Example 1), a microcrystalline copper plate with a thickness of 0.9 mm (Manufacturing Example 2), and a microcrystalline copper plate with a thickness of 0.8 mm (Manufacturing Example 3).

[0058] <Analysis of Copper Plates> The crystal structure of each of the copper plates from manufacturing examples 1 to 3 was analyzed by pole analysis using X-ray diffraction.

[0059] First, the pole figures were measured at diffraction angles of 43.45°, 50.60°, and 74.40°, corresponding to the interplanar spacings of the fcc-{111}, {200}, and {220} planes of the copper that make up the copper plate. The measurement results are shown in Figure 9. ｓｉ and P ｈｉ These two angles are denoted. The x-y plane corresponds to the surface of the copper plate, and the angle from a specific direction x is P. ｈｉ Let P be the angle from the normal to the x-y plane. ｓｉ The measurement was performed at P ｈｉ The angle is calculated so that it is in the range of 0 to 360° at 3° intervals, and P ｓｉ The experiment was also conducted with the angles set to occur at 3° intervals within the range of 0 to 90°.

[0060] A pole figure was created by plotting the relationship between the measurement direction and the magnitude of the X-ray diffraction intensity at that time on a three-dimensional coordinate system as shown in Figure 10. By projecting the measurement direction onto the coordinate system, P ｓｉ and P ｈｉ The direction can be represented by the value of . After the measurement is complete, P can be used to determine the direction in which the diffraction peak occurs. ｈｉ A defocus curve was created using the background signal intensity at a position shifted by -3°, and a correction was made for the incident angle of the X-rays.

[0061] Furthermore, in order to quantitatively evaluate the texture of the copper plate, the Orientation Distribution Function (ODF) was analyzed based on the pole figures of the {111}, {200}, and {220} planes. For the analysis, MATLAB® (manufactured by MathWorks Inc.) was used as the programming language, and MTEX ​​5.8.1® (registered trademark) was used as the analysis software. ｓｉ A pole diagram was used in which the angle is in the range of 0° to 75°. The magnitude of the ODF of the {111} plane obtained by the analysis is shown in the pole diagram. Note that in the case of a random distribution in which the crystal orientations are equally dispersed in all directions, the ODF is 1 in all directions.

[0062] (Analysis results for copper plate of manufacturing example 1) The analysis results for the copper plate of manufacturing example 1 are shown in Figures 11 and 12. Figure 11(A) shows the pole figure on the {111} plane. The maximum count of diffraction intensity in this pole figure is 611, and in the same figure, contour lines with values ​​divided into nine parts are shown as curved surfaces (isolines). As shown in Figure 11(A), in the measurement results on the {111} plane, four poles with strong intensity are observed with good symmetry. The orientation of all these poles is P ｓｉ It is approximately 54.7°. Also, P at these poles ｈｉ These angles are 45°, 135°, 225°, and 315°, with each angle being 90° apart.

[0063] Figures 11(B) and 11(C) show pole figures for the {200} and {220} planes of the copper plate of Manufacturing Example 1, respectively. The maximum diffraction intensity counts in these pole figures are 262 and 100, respectively, and contour lines with values ​​obtained by dividing these into nine parts are shown as curved surfaces (isolines). In Figure 11, poles (positions with strong diffraction intensity) are observed at highly symmetrical positions in both pole figures. In the pole figure for the {200} plane shown in Figure 11(B), P corresponds to the surface normal of the copper plate. ｓｉ A strong pole is formed at a position where P is 0°, ｓｉ It can be confirmed that four poles are formed at positions where the angle is 90°. P at these four poles ｈｉ These are 0°, 90°, 180°, and 270°, with each interval being 90°.

[0064] From the above results, it was confirmed that the copper plate of Manufacturing Example 1 consists of a group of crystals in which the {200} plane is oriented parallel to the copper plate surface and the orientation of the <200> axis within the plane is aligned. Even if the crystals are different, if their orientations match, they will produce poles at the same position. Therefore, crystals with matching orientations will be collectively referred to as a group of crystals below.

[0065] Figure 12 is a pole diagram showing the magnitude of the ODF in the {111} plane. In Figure 12, contour lines with ODFs of 5, 10, 15, 20, 25, and 30 are shown as curved surfaces (isolines). The angles between each of the four poles R1, R2, R3, and R4 were all approximately 70.5° or 109.5° (complementary angle of 70.5° from 180°). The pole densities of the four poles were of similar magnitude, but the pole density of R1 was the largest at 31.48. Note that pole density is the ODF at the pole. Pole density is the relative volume fraction of the crystal group giving rise to that pole, expressed as a multiple of the ODF in a random distribution, and indicates the degree of accumulation of crystal orientations toward the orientation of that pole.

[0066] As described above, the copper plate of Manufacturing Example 1 has a texture in which the <111> axis of the crystal grains is tilted at approximately 54.7° from the normal direction of the copper plate, and it was confirmed that the maximum value of the polar density (accumulation) of the <111> axis is a large value of 31.48 in pole analysis using X-ray diffraction. In such a texture, as shown in Figure 4, multiple twin crystal grains are interconnected with the {111} plane as the twinning plane S, and the P of each twin crystal grain ｓｉ The angle also corresponds to a texture with a 54.7° angle. In other words, it is presumed that the boundaries appearing on the main surface of the copper plate are stable grain boundaries against temperature changes.

[0067] (Analysis results for copper plate of manufacturing example 2) Next, the analysis results for copper plate of manufacturing example 2 are shown in Figures 13, 14, and 15. Figure 9(A) shows the pole figure on the {111} plane. The maximum count of diffraction intensity in this pole figure is 1191, and in the same figure, contour lines with values ​​divided into 9 parts are shown as curved surfaces (isolines). Among the pole figures shown in Figure 13(A), the diffraction intensity at pole P enclosed by the dotted line is very strong, and the angle of this pole is P ｓｉ The angle is 22°, and P ｈｉ The angle was 126°. The orientation of the pole of the {111} plane corresponds to the orientation of the <111> axis of the crystal, and from Figure 13(A), it was confirmed that there are many crystal groups in which the <111> axis is oriented towards the pole P. However, it was also confirmed that there are multiple other poles, and that there are crystal groups in which the <111> axis is oriented towards specific directions other than pole P.

[0068] Figures 13(B) and 13(C) show the pole figures for the {200} and {220} planes of the copper plate of Manufacturing Example 2, respectively. The maximum diffraction intensity counts in these pole figures are 521 and 499, respectively, and contour lines with values ​​obtained by dividing these counts into nine parts are shown as curved surfaces (isolines). In Figure 13, it was confirmed that multiple poles exist on the {200} and {220} planes in both pole figures.

[0069] Figure 14 is a pole diagram showing the magnitude of the ODF in the {111} plane. In Figure 14, contour lines with ODFs of 5, 10, 15, 20, and 25 are shown as curved surfaces (isolines). In Figure 14, the pole density at P' is the largest, which corresponds to pole P in Figure 14(A). The pole density at P' in the {111} plane, that is, the concentration of the <111> axis oriented in the direction of P', showed a large value of 26.83.

[0070] Here, in Figure 14, the poles with high pole density are diffractions due to four crystal groups. When these crystal groups are denoted as A, B, C, and D, the pole diagram enclosed by dotted lines for crystal group A and crystal group B is shown in Figure 15(A), and the pole diagram enclosed by dotted lines for crystal group C and crystal group D is shown in Figure 15(B).

[0071] In Figure 15(A), the angles between crystal group A-1 and crystal groups A-2, A-3, or A-4 are all approximately 70.5°, confirming that the poles of crystal groups A-1 to A-4 are diffractions caused by four equivalent {111} planes originating from crystal group A. Similarly, in the pole diagram shown in Figure 15(A), it was confirmed that the poles of crystal groups B-1 to B-3 are diffractions caused by three equivalent {111} planes originating from crystal group B. Crystal group B has another pole caused by an equivalent {111} plane, but that is P ｓｉ Because it is located at 90°, it is not shown in Figure 15(A).

[0072] Here, the pole of crystal group A-1 and the pole of crystal group B-1 overlap, forming pole P' shown in Figure 15(A). Furthermore, the positions of the pole arising from crystal group A and the pole arising from crystal group B are symmetric with respect to the straight line Q, indicated by the dotted line in Figure 15(A). From these findings, it was confirmed that crystal group A and crystal group B have a texture that is in a twinning relationship with the <111> axis pointing towards pole P' as the twinning axis.

[0073] Furthermore, in Figure 15(B), the angles between crystal group C-1 and crystal groups C-2, C-3, or C-4 are all approximately 70.5°, confirming that the poles of crystal groups C-1 to C-4 are diffractions caused by four equivalent {111} planes arising from crystal group C. Similarly, in the pole diagram shown in Figure 15(B), it was confirmed that the poles of crystal groups D-1 to D-4 are diffractions caused by four equivalent {111} planes arising from crystal group D. Here, pole C-1 and pole D-1 form the same poles as poles A-2 and A-3 in Figure 15(A), respectively.

[0074] Furthermore, the pole positions of crystal group C and crystal group D are symmetric with respect to the same line Q shown in Figure 15(A) as the axis of symmetry. From these findings, it was confirmed that crystal group C and crystal group D have a texture that is in a twinning relationship with the <111> axis of crystal group A, which corresponds to poles A-2 and A-3, respectively, as the twinning axis.

[0075] From the above, it was confirmed that the copper plate of Manufacturing Example 2 has a texture where the entire surface of the copper plate is composed of crystal groups A to D that are twinned with each other. The copper plate of Manufacturing Example 2 is made of polycrystalline material having a texture with a {111} plane orientation, and it was confirmed that the maximum value of the <111> axis accumulation is a large 26.83 in pole analysis using X-ray diffraction. As shown in Figure 4, such a texture corresponds to a texture in which multiple twinned crystal grains are interconnected with the {111} plane as the twinning plane S. In other words, it is presumed that the boundaries appearing on the main surface of the copper plate are grain boundaries that are stable with respect to temperature changes.

[0076] (Analysis results for the copper plate of Manufacturing Example 3) Next, the analysis results for the copper plate of Manufacturing Example 3 are shown in Figures 16 and 17. Figures 16(A), 16(B), and 16(C) show the pole figures for the {111} plane, {200} plane, and {220} plane of the copper plate of Manufacturing Example 3, respectively. The maximum counts of diffraction intensity in these pole figures are 159, 64, and 35, respectively, and in the same figures, contour lines with values ​​divided into nine parts are shown as curved surfaces (isolines). In all of the pole figures in Figure 16, the diffraction intensity is very weak compared to the pole figures of the copper plates of Manufacturing Example 1 and Manufacturing Example 2, and a large number of poles are observed throughout the entire space. This is because the degree of accumulation of crystal orientations of copper crystal grains is low in the copper plate of Manufacturing Example 3.

[0077] Looking at the pole diagram in the {111} plane shown in Figure 16(A), the region S indicated by the dotted line is visible. １ and region S ２ Two groups of poles, each formed from multiple poles, are observed. These are typical textures produced by rolling, but the individual poles are separated, indicating a low degree of aggregation.

[0078] Figure 17 is a pole diagram showing the size of the ODF in the {111} plane. Due to the low pole density, in Figure 17, contour lines with ODF values ​​of 1, 2, 3, 4, 5, 6, and 7 are shown as curved surfaces (isolines). The pole S' enclosed by the dotted line has the highest pole density, which was 7.3. From this, it was confirmed that the copper plate of Manufacturing Example 3 had a maximum density of 7.3, and that it did not have the clear texture that the copper plates of Manufacturing Example 1 and Manufacturing Example 2 had, and that there were many grain boundaries with high grain boundary energy between the crystal grains on the surface of the copper plate.

[0079] <Evaluation of Thermal Stability of Copper Plates: Arithmetic Mean Roughness> The thermal stability of each copper plate prepared in Manufacturing Examples 1 to 3 was evaluated using the method described below. In the following explanation, the evaluations of the copper plates prepared in Manufacturing Examples 1 to 3 will be described as Examples 1-1, 1-2, and Comparative Example 1-1, respectively.

[0080] (Preparation of evaluation samples) A ​​2 nm thick underlayer made of tantalum (Ta) was applied to a portion of the main surface of the copper plates prepared in Manufacturing Examples 1 to 3 using a sputtering apparatus. A 50 nm thick metal layer made of gold (Au) was then applied on the underlayer using the same sputtering apparatus. In this way, evaluation samples were prepared.

[0081] (Thermal Stability Evaluation) The evaluation samples described above were placed on a hot plate with the side opposite to the side with the metal layer in contact with it, and were heat-treated at 150°C, 220°C, and 270°C for 10 minutes each. The arithmetic mean roughness at 25°C before heat treatment and after heat treatment were measured, and the changes were confirmed. The arithmetic mean roughness was measured using a white light interference microscope, and the same measurement was performed at six locations, with the arithmetic mean value taken as the arithmetic mean roughness of each sample. In addition, the arithmetic mean roughness was measured for both the area with the metal layer and the area without the metal layer on the surface with the metal layer. The results are shown in Table 1, Figure 18, and Figure 19.

[0082]

[0083] Figure 18 is a graph showing the relationship between the arithmetic mean roughness Sa and the heat treatment temperature in the area where the metal layer is provided, and Figure 19 is a graph showing the relationship between the arithmetic mean roughness Sa and the heat treatment temperature in the area where the metal layer is not provided. As shown in Table 1 and Figure 18, under the conditions of Comparative Example 1-1, where no clear texture is formed, the arithmetic mean roughness Sa increased sharply with increasing heat treatment temperature, and it was confirmed that even in the area where the metal layer is formed, it reached 60 nm after heat treatment at 270°C. On the other hand, under the conditions of Examples 1-1 and 1-2, where a texture with a high degree of integration of the <111> axis is formed, the increase in the arithmetic mean roughness Sa was suppressed even after heat treatment, and it was confirmed that it remained at a very low value of 5.5 nm and 2.4 nm, respectively, in the area where the metal layer is formed.

[0084] <Bonding layer thickness> Using a silicon wafer, the bonding strength with respect to the bonding layer thickness was evaluated using the method described later.

[0085] (Preparation of evaluation samples) A ​​5 nm thick underlayer made of tantalum (Ta) was applied to the surface of each of two silicon wafers using a sputtering apparatus. A metal layer made of gold (Au) was then applied to the underlayer using the same sputtering apparatus. The thickness of the gold layers on the two wafers was the same. The gold films on the two silicon wafers were joined together by atomic diffusion bonding in air. During bonding, the stacked wafers were heated at 100°C for 5 minutes while being pressurized at 20 MPa. In this way, evaluation samples with gold layer thicknesses of 2 nm, 20 nm, 50 nm, 100 nm, 300 nm, 500 nm, and 1000 nm were prepared. The thickness of the bonded layer in these evaluation samples was twice the thickness of the gold layer, at 4 nm, 40 nm, 100 nm, 200 nm, 600 nm, 1000 nm, and 2000 nm.

[0086] (Bonding Strength Evaluation) The bonding strength of the bonded wafers was evaluated using the blade method, which involves inserting a 100 μm thick blade into the bonding interface and measuring the delamination length. As a result, it was confirmed that in all samples, it was not possible to insert the blade into the bonding interface, and a bonding strength exceeding the fracture strength of silicon was achieved.

[0087] 1, 2... Power module 10, 20... Insulating substrate 100, 200... Ceramic plate 101, 102, 201, 202... Metal plate 101a... Main surface 1010... Second base layer 11... Bonding layer 110... Second metal layer 111... First metal layer 12, 21... Semiconductor chip 120... First base layer 22... Solder 3... Power module thermal resistance 30... Chip thermal resistance 31... Solder thermal resistance 32... Copper thermal resistance 33... Ceramic thermal resistance 34... Copper thermal resistance

Claims

1. A semiconductor module comprising, in this order, a semiconductor chip, a bonding layer, and a metal plate, wherein the bonding layer includes at least one selected from the group consisting of gold, silver, gold alloys, and silver alloys, the main surface of the metal plate on the bonding layer side includes a polycrystalline structure of at least one of copper and copper alloys, and the main surface of the metal plate has a texture in which the maximum value of the <111> axis integration exceeds 20 in pole analysis using X-ray diffraction.

2. The semiconductor module according to claim 1, wherein the thickness of the bonding layer is 2000 nm or less.

3. The semiconductor module according to claim 2, wherein the thickness of the bonding layer is 1000 nm or less.

4. The semiconductor module according to claim 3, wherein the thickness of the bonding layer is 500 nm or less.

5. The semiconductor module according to any one of claims 1 to 3, further comprising a base layer in at least a region of the metal plate on the bonding layer side facing the bonding layer, wherein the base layer comprises at least one selected from the group consisting of Ti, V, Cr, Ni, Zr, Nb, Mo, Hf, Ta, W and alloys of two or more elements therefrom.

6. The semiconductor module according to any one of claims 1 to 3, wherein the thickness of the metal plate is 0.1 mm or more and 1.0 mm or less.

7. The semiconductor module according to any one of claims 1 to 3, wherein the metal plate is a laminate of two or more metal sheets.

8. The semiconductor module according to any one of claims 1 to 3, further comprising a ceramic plate on the side of the metal plate opposite to the bonding layer side.

9. The semiconductor module according to any one of claims 1 to 3, wherein the semiconductor chip is a power semiconductor chip.

10. A method for manufacturing a semiconductor module, comprising the steps of: placing a semiconductor chip having a first metal layer on at least a portion of its surface and a metal plate having a second metal layer on at least a portion of its main surface such that the first metal layer and the second metal layer face each other; and joining the first metal layer and the second metal layer to form a bonding layer, wherein the first metal layer comprises at least one selected from the group consisting of gold, silver, gold alloys, and silver alloys; the second metal layer comprises at least one selected from the group consisting of gold, silver, gold alloys, and silver alloys; the main surface of the metal plate on the side with the second metal layer comprises a polycrystalline structure of at least one of copper and copper alloys; and the main surface of the metal plate has a texture on which the maximum value of the <111> axis integration exceeds 20 in pole analysis using X-ray diffraction.

11. The method for manufacturing a semiconductor module according to claim 10, wherein the arithmetic mean roughness Sa1 of the main surface of the first metal layer facing the second metal layer and the arithmetic mean roughness Sa2 of the main surface of the second metal layer facing the first metal layer are both less than 6 nm.

12. The method for manufacturing a semiconductor module according to claim 11, wherein the arithmetic mean roughness Sa1 of the main surface of the first metal layer facing the second metal layer and the arithmetic mean roughness Sa2 of the main surface of the second metal layer facing the first metal layer are both 2 nm or less.

13. The method for manufacturing a semiconductor module according to claim 10 or 11, wherein the thickness of the first metal layer and the thickness of the second metal layer are each 5 nm or more and 2000 nm or less.

14. The method for manufacturing a semiconductor module according to claim 13, wherein the thickness of the first metal layer and the thickness of the second metal layer are each 5 nm or more and 1000 nm or less.

15. A method for manufacturing a semiconductor module according to claim 11, wherein the semiconductor chip further comprises a first underlayer, the first metal layer is bonded to the semiconductor chip via the first underlayer, the metal plate further comprises a second underlayer, the second metal layer is bonded to the metal plate via the second underlayer, and the second underlayer and the first underlayer each contain at least one selected from the group consisting of Ti, V, Cr, Ni, Zr, Nb, Mo, Hf, Ta, W and alloys of two or more of these elements.

16. The method for manufacturing a semiconductor module according to any one of claims 10, 11, and 15, wherein the second metal layer is an oxidation-preventive film on the metal plate.

17. The method for manufacturing a semiconductor module according to any one of claims 10, 11, and 15, wherein the bonding of the first metal layer and the second metal layer is performed in an oxygen-containing atmosphere.

18. The method for manufacturing a semiconductor module according to any one of claims 10, 11, and 15, wherein the bonding of the first metal layer and the second metal layer is performed under conditions in which a pressure of 5 MPa to 100 MPa is applied in the stacking direction of the first metal layer and the second metal layer.

19. The method for manufacturing a semiconductor module according to claim 18, wherein the bonding of the first metal layer and the second metal layer is performed under conditions in which a pressure of 20 MPa or more and 50 MPa or less is applied in the stacking direction of the first metal layer and the second metal layer.

20. The method for manufacturing a semiconductor module according to any one of claims 10, 11, and 15, wherein the semiconductor chip is a power semiconductor chip.

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