Integrated battery and manufacturing method thereof

Abstract

According to exemplary embodiments, an integrated battery is provided. The integrated battery comprises: a substrate including multiple holes; multiple patterns which are in the multiple holes of the substrate and have a polarity opposite to that of the substrate; multiple energy source patterns configured to emit beta rays to the substrate and the multiple patterns; multiple first patterns surrounded by the multiple energy source patterns; and multiple second patterns surrounded by the multiple first patterns.

Description

Integrated battery and method of manufacturing the same

[0001] The present invention relates to an integrated battery and a method for manufacturing the same. The present application claims the benefit of Korean application No. 10-2024-0128699, filed on September 24, 2024, and Korean application No. 10-2025-0136613, filed on September 22, 2025, which are incorporated herein by reference in their entirety.

[0002] A beta battery (or beta radioactive battery) is a type of radioactive battery that produces electricity using the beta decay of radioactive isotopes. This battery generates power primarily by using semiconductor materials and radioactive isotopes that emit beta rays. Beta batteries operate by directly converting the energy released during the radioactive decay process into electrical energy.

[0003] Beta batteries have a very long lifespan because they can continuously produce energy over the half-life of a radioactive isotope. In addition, they can supply a constant power regardless of the environment, allowing for stable use even in extreme conditions.

[0004] The problem that the technical concept of the present invention aims to solve is to provide an integrated battery and a method for manufacturing the same.

[0005] According to exemplary embodiments of the present invention for solving the above-described problem, a direct cell is provided. The direct cell comprises: a substrate having a plurality of holes; a plurality of patterns having opposite polarity to the substrate and located within the plurality of holes of the substrate; a plurality of energy source patterns configured to irradiate beta rays onto the substrate and the plurality of patterns; a plurality of first patterns surrounded by the plurality of energy source patterns; and a plurality of second patterns surrounded by the plurality of first patterns.

[0006] Each of the above plurality of energy source patterns is interposed between a corresponding one of the plurality of first patterns and a corresponding one of the plurality of patterns.

[0007] The conductivity type of each of the plurality of first patterns is the same as the conductivity type of the above description, and the conductivity type of each of the plurality of second patterns is the same as the conductivity type of each of the plurality of patterns.

[0008] The conductivity type of each of the plurality of first patterns is the same as the conductivity type of each of the plurality of patterns, and the conductivity type of each of the plurality of second patterns is the same as the conductivity type of the description.

[0009] The lower surface of each of the plurality of patterns, the lower surface of each of the plurality of energy source patterns, the lower surface of each of the plurality of first patterns, and the lower surface of each of the plurality of second patterns form a co-plane with the lower surface of the above-described surface.

[0010] The lower surface of each of the plurality of patterns, the lower surface of each of the plurality of energy source patterns, and the lower surface of each of the plurality of first patterns form a co-plane with the lower surface of the substrate, and each of the plurality of first patterns has a cup shape.

[0011] The lower surface of each of the plurality of energy source patterns and the lower surface of each of the plurality of patterns form a co-plane with the lower surface of the substrate, and each of the plurality of energy source patterns has a cup shape.

[0012] The lower surface of each of the plurality of patterns forms a co-surface with the lower surface of the above-mentioned material, and each of the plurality of patterns has a cup shape.

[0013] According to exemplary embodiments, a direct cell is provided. The direct cell comprises: a substrate having a plurality of holes; a plurality of patterns having opposite polarity to the substrate, said substrate, said patterns; a plurality of energy source patterns said substrates; a plurality of first patterns said substrates spaced apart from the plurality of patterns; and a plurality of second patterns said substrates.

[0014] Each of the above plurality of energy source patterns is surrounded by a corresponding one among the above plurality of patterns.

[0015] Each of the above plurality of first patterns is surrounded by a corresponding one of the above plurality of energy source patterns.

[0016] Each of the above plurality of second patterns is surrounded by a corresponding one of the above plurality of first patterns.

[0017] According to exemplary embodiments, an integrated cell is provided. The integrated cell comprises a substrate having a plurality of recesses; a layer on the substrate; an energy source layer on the layer; a first layer on the energy source layer; and a second layer on the first layer.

[0018] The above layer has a conductivity type opposite to that of the above material, and the first layer has a conductivity type opposite to that of the second layer.

[0019] The conductivity type of the first layer is the same as the conductivity type of the above-described material, and the conductivity type of the second layer is the same as the conductivity type of the above layer.

[0020] The conductivity type of the first layer is the same as the conductivity type of the layer, and the conductivity type of the second layer is the same as the conductivity type of the description.

[0021] The above material includes an electric region having the plurality of recesses and a contact region spaced apart from the plurality of recesses, and the material, the layer, the energy source layer, the first layer and the second layer on the contact region form a stepped structure.

[0022] In the above contact area, the above material protrudes further horizontally based on the above layer.

[0023] In the above contact area, the layer protrudes further horizontally based on the first layer.

[0024] In the above contact area, the first layer protrudes further horizontally based on the second layer.

[0025] The first cell composed of the above-mentioned material and the above-mentioned layer is connected in series with the second cell composed of the above-mentioned first layer and the above-mentioned second layer.

[0026] The first cell composed of the above-mentioned material and the above-mentioned layer is connected in parallel with the second cell composed of the above-mentioned first layer and the above-mentioned second layer.

[0027] The integrated cell further comprises a first via landed on the substrate; a second via landed on the layer; a third via landed on the first layer; and a fourth via landed on the second layer.

[0028] Each of the first to fourth vias includes a passivation layer and a conductive layer surrounded by the passivation layer.

[0029] The first via penetrates the layer, the first layer, and the second layer.

[0030] The second via penetrates the first layer and the second layer.

[0031] The above third via penetrates the above second layer.

[0032] The above description includes an electrical region having the plurality of recesses, a first contact region and a second contact region spaced apart from the electrical region, the first via and the third via are on the first contact region, and the second via and the fourth via are on the second contact region.

[0033] The above integrated cell further includes a conductive line connected to each of the second via and the fourth via.

[0034] The above description includes an electrical region having the plurality of recesses, a first contact region and a second contact region spaced apart from the electrical region, the second via and the third via are on the first contact region, and the first via and the fourth via are on the second contact region.

[0035] The integrated cell further includes a first conductive line connected to each of the second via and the third via; and a second conductive line connected to each of the first via and the fourth via.

[0036] An integrated cell according to exemplary embodiments of the present invention includes an energy source having a uniform thickness and a conformal shape, so that the amount of energy source material used in manufacturing the integrated cell can be reduced and the manufacturing cost of the integrated cell can be reduced. Since a pn junction and a depletion region are formed on both sides centered on the energy source, the energy efficiency of the integrated cell can be improved.

[0037] The effects obtainable from the exemplary embodiments of the present invention are not limited to those mentioned above, and other unmentioned effects can be clearly derived and understood by those skilled in the art to which the exemplary embodiments of the present disclosure belong from the following description. That is, unintended effects resulting from the implementation of the exemplary embodiments of the present disclosure can also be derived by those skilled in the art from the exemplary embodiments of the present disclosure.

[0038] FIG. 1 is a flowchart for explaining a method for manufacturing an integrated cell according to exemplary embodiments.

[0039] FIG. 2 is a plan view illustrating a method for manufacturing an integrated cell according to exemplary embodiments.

[0040] Figure 3 is a cross-sectional view taken along the cutting line 2I-2I' of Figure 2.

[0041] FIG. 4 is a plan view illustrating a method for manufacturing an integrated cell according to exemplary embodiments.

[0042] Figure 5 is a cross-sectional view taken along the cutting line 4I-4I' of Figure 4.

[0043] FIG. 6 is a plan view illustrating a method for manufacturing an integrated cell according to exemplary embodiments.

[0044] Figure 7 is a cross-sectional view taken along the cutting line 6I-6I' of Figure 6.

[0045] FIG. 8 is a plan view illustrating a method for manufacturing an integrated cell according to exemplary embodiments.

[0046] FIG. 9 is a cross-sectional view taken along the cutting line 8I-8I' of FIG. 8.

[0047] FIG. 10 is a plan view illustrating a method for manufacturing an integrated cell according to exemplary embodiments.

[0048] FIG. 11 is a cross-sectional view taken along the cutting line 10I-10I' of FIG. 10.

[0049] FIG. 12 is a plan view illustrating a method for manufacturing an integrated cell according to exemplary embodiments.

[0050] FIG. 13 is a cross-sectional view taken along the cutting line 12I-12I' of FIG. 12.

[0051] FIG. 14 is a plan view illustrating a method for manufacturing an integrated cell according to exemplary embodiments.

[0052] FIG. 15 is a cross-sectional view taken along the cutting line 14I-14I' of FIG. 14.

[0053] FIG. 16 is a cross-sectional view illustrating a method for manufacturing an integrated cell according to exemplary embodiments. More specifically, FIG. 16 shows a portion corresponding to FIG. 15.

[0054] FIG. 17 is a drawing for illustrating an integrated cell according to other exemplary embodiments.

[0055] FIG. 18 is a drawing for illustrating an integrated cell according to other exemplary embodiments.

[0056] FIG. 19 is a drawing for illustrating an integrated cell according to other exemplary embodiments.

[0057] FIG. 20 is a drawing for illustrating an integrated cell according to other exemplary embodiments.

[0058] FIG. 21 is a plan view of an integrated cell according to exemplary embodiments.

[0059] FIG. 22 is a cross-sectional view taken along the cutting line 21I-21I' of FIG. 21.

[0060] FIG. 23 is a plan view of an integrated cell according to exemplary embodiments.

[0061] FIG. 24 is a cross-sectional view taken along the cutting line 23I-23I' of FIG. 23.

[0062] FIG. 25 is a plan view of an integrated cell according to exemplary embodiments.

[0063] FIG. 26 is a cross-sectional view taken along the cutting line 25I-25I' of FIG. 25.

[0064] FIG. 27 is a plan view of an integrated cell according to exemplary embodiments.

[0065] FIG. 28 is a cross-sectional view taken along the cutting line 27I-27I' of FIG. 27.

[0066] FIG. 29 is a flowchart illustrating a method for manufacturing an integrated cell according to exemplary embodiments.

[0067] FIG. 30 is a plan view illustrating a method for manufacturing an integrated cell according to exemplary embodiments.

[0068] FIG. 31 is a cross-sectional view taken along the cutting line 30I-30I' of FIG. 30.

[0069] FIG. 32 is a plan view illustrating a method for manufacturing an integrated cell according to exemplary embodiments.

[0070] FIG. 33 is a cross-sectional view taken along the cutting line 32I-32I' of FIG. 32.

[0071] FIG. 34 is a plan view illustrating a method for manufacturing an integrated cell according to exemplary embodiments.

[0072] FIG. 35 is a cross-sectional view taken along the cutting line 34I-34I' of FIG. 34.

[0073] FIG. 36 is a plan view illustrating a method for manufacturing an integrated cell according to exemplary embodiments.

[0074] FIG. 37 is a cross-sectional view taken along the cutting line 36I-36I' of FIG. 36.

[0075] FIG. 38 is a cross-sectional view of an integrated cell according to exemplary embodiments.

[0076] FIG. 39 is a cross-sectional view of an integrated cell according to exemplary embodiments.

[0077] FIG. 40 is a plan view of an integrated cell according to exemplary embodiments.

[0078] FIG. 41 is a cross-sectional view taken along the cutting line 41I-41I' of FIG. 40.

[0079] FIG. 42 is a cross-sectional view of an integrated cell according to exemplary embodiments.

[0080] FIG. 43 is a cross-sectional view of an integrated cell according to exemplary embodiments.

[0081] FIG. 44 is a cross-sectional view of an integrated cell according to exemplary embodiments.

[0082] FIG. 45 is a cross-sectional view of an integrated cell according to exemplary embodiments.

[0083] FIG. 46 is a flowchart illustrating a method for manufacturing different integrated cells in other exemplary embodiments.

[0084] FIGS. 47 to 53 are cross-sectional views illustrating a method for manufacturing other integrated cells in other exemplary embodiments.

[0085] Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the attached drawings. Prior to this, terms and words used in this specification and claims should not be interpreted as being limited to their ordinary or dictionary meanings. Instead, based on the principle that the inventor can appropriately define the concepts of terms to best describe his invention, they should be interpreted in a meaning and concept consistent with the technical spirit of the present invention.

[0086] Therefore, the embodiments described in this specification and the configurations illustrated in the drawings are merely the most preferred embodiments of the present invention and do not represent all of the technical ideas of the present invention; thus, it should be understood that various equivalents and modifications that can replace them may exist at the time of filing this application.

[0087] In addition, in describing the present invention, if it is determined that a detailed description of related known components or functions may obscure the essence of the invention, such detailed description is omitted.

[0088] Since embodiments of the present invention are provided to more fully explain the invention to those skilled in the art, the shapes and sizes of the components in the drawings may be exaggerated, omitted, or schematically depicted for clearer explanation. Accordingly, the size or proportion of each component does not entirely reflect the actual size or proportion.

[0089]

[0090] (1st and 2nd embodiments)

[0091] Figure 1 is a flowchart illustrating a method for manufacturing an integrated battery.

[0092] FIG. 2 is a plan view illustrating a method for manufacturing an integrated cell according to exemplary embodiments.

[0093] Figure 3 is a cross-sectional view taken along the cutting line 2I-2I' of Figure 2.

[0094] FIG. 4 is a plan view illustrating a method for manufacturing an integrated cell according to exemplary embodiments.

[0095] Figure 5 is a cross-sectional view taken along the cutting line 4I-4I' of Figure 4.

[0096] FIG. 6 is a plan view illustrating a method for manufacturing an integrated cell according to exemplary embodiments.

[0097] Figure 7 is a cross-sectional view taken along the cutting line 6I-6I' of Figure 6.

[0098] FIG. 8 is a plan view illustrating a method for manufacturing an integrated cell according to exemplary embodiments.

[0099] FIG. 9 is a cross-sectional view taken along the cutting line 8I-8I' of FIG. 8.

[0100] FIG. 10 is a plan view illustrating a method for manufacturing an integrated cell according to exemplary embodiments.

[0101] FIG. 11 is a cross-sectional view taken along the cutting line 10I-10I' of FIG. 10.

[0102] FIG. 12 is a plan view illustrating a method for manufacturing an integrated cell according to exemplary embodiments.

[0103] FIG. 13 is a cross-sectional view taken along the cutting line 12I-12I' of FIG. 12.

[0104] FIG. 14 is a plan view illustrating a method for manufacturing an integrated cell according to exemplary embodiments.

[0105] FIG. 15 is a cross-sectional view taken along the cutting line 14I-14I' of FIG. 14.

[0106] FIG. 16 is a cross-sectional view illustrating a method for manufacturing an integrated cell according to exemplary embodiments. More specifically, FIG. 16 shows a portion corresponding to FIG. 15.

[0107] Referring to FIGS. 1 to 3, a substrate (110) can be provided in P110. According to exemplary embodiments, the substrate (110) may include any one of a diamond substrate, a SiC substrate, a GaN substrate, a Bi2O3 / GeO2 substrate, a Sm2O3 / Bi2O3 / GeO2 substrate, a Sm2O3 / Bi2O3 / B2O3 substrate, a Sm2O3 / Bi2O3 / GeO2 / B2O3 substrate, and a sapphire substrate.

[0108] The substrate (110) can be processed by either ion implantation or diffusion. The substrate (110) can be doped with a dopant of a first conductivity type. The dopant of the first conductivity type may be a p-type dopant or an n-type dopant.

[0109] The p-type dopant may include one or more of boron (B), aluminum (Al), gallium (Ga), and indium (In). The n-type dopant may include one or more of nitrogen (N), phosphorus (P), arsenic (As), and antimony (Sb).

[0110] The substrate (110) may comprise a metal oxide having a bandgap energy of 2.7 eV or more. In some embodiments, the substrate (110) may comprise a material represented as AMO3 (wherein A is one or more selected from the group consisting of La, Ba, Sr, and K, and M is one or more selected from the group consisting of Al, In, Ga, Ti, Sn, Hf, Ta, and Zr).

[0111] For example, the substrate (110) is BaSnO3, BaHfO3, BaZrO3, BaHf 1-x Ti x O3(here 0 <x<1), Ba 1-x La x SnO3(here 0 <x<1), Bi4Ge3O 12 , Al2O3, Y2O3, La2O3, Ga2O3, Bi2O3, ZrO2, HfO2, Ta2O5, TiO2, LaInO3, LaGaO3, SrZrO3, SrHfO3, SrTaO7, LaIn 1-x Ga x O3(here 0 <x<1), LaGaO3, SrTiO3, KTaO3, HfSiO4, Ta3Ti2O x (Here 0 <x<1) 및 LaAlO3중 하나 이상을 포함할 수 있다.

[0112]

[0113] Next, referring to FIGS. 1, 4 and 5, a substrate (110) can be patterned in P120. The substrate (110) can be patterned by any one of reactive ion etching (RIE) including low-temperature etching and ion beam etching. The substrate (110) may also be patterned by a laser beam. The substrate (110) may also be patterned by anisotropic wet etching.

[0114] Before patterning the substrate (110), a mask pattern may be formed on the substrate (110). The mask pattern may be formed by photolithography. The mask pattern may expose the portion of the substrate (110) to be etched (i.e., the portion to be formed with a plurality of recesses (110R)) and cover the non-etched portion (i.e., the portion between the plurality of recesses (110R)). A hard mask may also be additionally provided between the mask pattern and the substrate (110).

[0115] A plurality of recesses (110R) may be formed by patterning the substrate (110). According to exemplary embodiments, the plurality of recesses (110R) may have a circular shape when viewed from above. When the plurality of recesses (110R) have a circular shape when viewed from above, it may be said that the plurality of recesses (110R) have a circular planar shape.

[0116] Two directions substantially parallel to the upper surface (110U) of the substrate (110) are defined as the X direction and the Y direction, and a direction substantially perpendicular to each of the X direction and the Y direction is defined as the Z direction. The X direction, the Y direction, and the Z direction may be substantially perpendicular to each other.

[0117] According to exemplary embodiments, a plurality of recesses (110R) may be arranged in a honeycomb structure. Arranging the plurality of recesses (110R) in a honeycomb structure means that the center (110RC) of each of the plurality of recesses (110R) is located at the vertices and centers of a plurality of regular hexagons of the same size that fill the plane.

[0118] Each of the plurality of recesses (110R) may have a variable width along the Z direction (e.g., a horizontal width such as the width in the X direction and / or the width in the Y direction). Each of the plurality of recesses (110R) may have a tapered shape in the Z direction. Each of the plurality of recesses (110R) may extend in the Z direction from the top surface (110U), and the width of each of the plurality of recesses (110R) may decrease as it moves away from the top surface (110U). The width of each of the plurality of recesses (110R) at a first depth from the top surface (110U) may be smaller than the width of each of the plurality of recesses (110R) at a second depth from the top surface (110U) which is smaller than the first depth.

[0119]

[0120] Next, referring to FIGS. 1, 6 and 7, a layer (120L) can be formed in P130. The layer (120L) may have a uniform thickness, and accordingly, the layer (120L) may have a conformal shape. That the layer (120L) has a conformal shape means that the shape of the structure prior to the formation of the layer (120L) (i.e., the substrate (110) and a plurality of recesses (110R)) is transferred to the shape of the layer (120L).

[0121] The layer (120L) may be formed by either Chemical Vapor Deposition (CVD) or Physical Vapor Deposition (PVD), but is not limited thereto. The layer (120L) may also be formed by an oxidation process of a metal layer formed by metal CVD.

[0122] The layer (120L) may comprise a metal oxide having a bandgap energy of 2.7 eV or more. In some embodiments, the layer (120L) may comprise a material represented as AMO3 (wherein A is one or more selected from the group consisting of La, Ba, Sr, and K, and M is one or more selected from the group consisting of Al, In, Ga, Ti, Sn, Hf, Ta, and Zr).

[0123] For example, layer (120L) is BaSnO3, BaHfO3, BaZrO3, BaHf 1-x Ti x O3(here 0 <x<1), Ba 1-x La x SnO3(here 0 <x<1), Bi4Ge3O 12 , Al2O3, Y2O3, La2O3, Ga2O3, Bi2O3, ZrO2, HfO2, Ta2O5, TiO2, LaInO3, LaGaO3, SrZrO3, SrHfO3, SrTaO7, LaIn 1-x Ga x O3(here 0 <x<1), LaGaO3, SrTiO3, KTaO3, HfSiO4, Ta3Ti2O x (Here 0 <x<1) 및 LaAlO3중 하나 이상을 포함할 수 있다.

[0124] The layer (120L) is stable even in high temperature and high humidity environments and has high carrier mobility. Carrier movement within the layer (120L) is free from inelastic collisions. Accordingly, an integrated cell manufactured based on the layer (120L) can have high energy efficiency and excellent heat dissipation characteristics.

[0125] According to exemplary embodiments, the mobility of the carrier of the layer (120L) is about 45 cm 2 / (Vs) may be greater than. According to exemplary embodiments, the mobility of the carrier in the layer (120L) is about 80 cm 2 / (Vs) may be greater than. According to exemplary embodiments, the mobility of the carrier in the layer (120L) is about 120 cm2 / (Vs) may be greater than. According to exemplary embodiments, the mobility of the carrier in the layer (120L) is about 300 cm 2 / (Vs) It can be more than

[0126] The layer (120L) may include one of a doped semiconductor material, a compound semiconductor, an oxide semiconductor, or a metal alloy. According to exemplary embodiments, the layer (120L) comprises silicon (Si) doped with boron (B), silicon (Si) doped with one of phosphorus (P) and arsenic (As), gallium arsenide (GaAs) doped with zinc (Zn), gallium arsenide (GaAs) doped with one of silicon (Si) and tellurium (Te), germanium (Ge) doped with boron (B), germanium (Ge) doped with one of phosphorus (P) and antimony (Sb), gallium nitride (GaN) doped with magnesium (Mg), gallium nitride (GaN) doped with silicon (Si), silicon carbide (SiC) doped with one of aluminum (Al) and boron (B), silicon carbide (SiC) doped with one of nitrogen (N) and phosphorus (P), indium phosphate (InP) doped with zinc (Zn), and indium doped with one of sulfur (S) and silicon (Si). It may also include one of phosphorus oxide (InP), cadmium telluride (CdTe), cadmium sulfide (CdS), tin oxide (SnO), and zinc oxide (ZnO).

[0127] The layer (120L) may be doped with a second conductivity type dopant opposite to the first conductivity type dopant. For example, if the first conductivity type dopant is a p-type dopant, the second conductivity type dopant may be an n-type dopant, and if the first conductivity type dopant is an n-type dopant, the second conductivity type dopant may be a p-type dopant. Accordingly, a pn junction and a depletion region therefrom may be formed between the substrate (110) and the layer (120L).

[0128]

[0129] Next, referring to FIGS. 1, 8 and 9, an energy source layer (130L) can be formed in P140. The energy source layer (130L) can be formed by any one of the methods of evaporation, sputtering, CVD, electroplating, and electroless plating. The energy source layer (130L) can have a uniform thickness, and accordingly, the energy source layer (130L) can have a conformal shape. When the energy source layer (130L) is formed by electroplating or electroless plating, a seed layer can be formed between the energy source layer (130L) and the layer (120L).

[0130] The energy source layer (130L) may contain a radioactive isotope. The energy source layer (130L) may be configured to emit radiation. The energy source layer (130L) may contain, for example, a radioactive isotope that emits beta rays. The energy source layer (130L) may contain, for example, tritium ( 3 H, tritium), calcium-45( 45 Ca), nickel-63 63 Ni), copper-67 67 Cu), strontium-90 ( 90 Sr), promethium-147( 147 Pm), osmium-194( 194 OS), Thulium-171( 171 Tm), tantalum-179( 179 Ta), cadmium-109( 109 Cd), germanium-68 68 Ge), cerium-159( 159 Ce) and tungsten-181( 181 It may include one or more of W). Radioactive isotopes may emit only beta rays, or they may also emit additional radiation other than beta rays, such as alpha rays or gamma rays.

[0131]

[0132] Next, referring to FIGS. 1, 10 and 11, a first layer (140L) can be formed in P150. The first layer (140L) can be formed by either CVD or epitaxial growth. The first layer (140L) can be doped with a first dopant. The first dopant may be introduced into the first layer (140L) during the growth of the first layer (140L), or the first layer (140L) may be doped by ion implantation and diffusion after the first layer (140L) is formed. The first layer (140L) may have a uniform thickness, and accordingly, the first layer (140L) may have a conformal shape.

[0133] According to exemplary embodiments, the first layer (140L) may be spaced apart from the layer (120L) with the energy source layer (130L) in between. The energy source layer (130L) may be interposed between the first layer (140L) and the layer (120L).

[0134]

[0135] Next, referring to FIGS. 1, 12 and 13, a second layer (150L) can be formed in P160. The second layer (150L) can be formed by either CVD or epitaxial growth. The second layer (150L) can be doped with a first dopant. The first dopant may be introduced into the second layer (150L) during the growth of the second layer (150L), or the second layer (150L) may be doped by ion implantation and diffusion after the second layer (150L) is formed. The second layer (150L) can be formed sufficiently to fill the recess (110R). Each of the first layer (140L) and the second layer (150L) may comprise one of a doped semiconductor material, a compound semiconductor, an oxide semiconductor, or a metal alloy.

[0136] The second layer (150L) can be doped with a second dopant having opposite polarity to the first dopant. Accordingly, the polarity of the second layer (150L) can be opposite to that of the first layer (140L), and a pn junction and a depletion region can be formed at the interface between the second layer (150L) and the first layer (140L).

[0137] According to exemplary embodiments, the first layer (140L) comprises silicon (Si) doped with boron (B) and the second layer (150L) may comprise silicon (Si) doped with either phosphorus (P) or arsenic (As).

[0138] According to exemplary embodiments, the first layer (140L) may comprise silicon (Si) doped with either phosphorus (P) or arsenic (As), and the second layer (150L) may comprise silicon (Si) doped with boron (B).

[0139] According to exemplary embodiments, the first layer (140L) may comprise gallium arsenide (GaAs) doped with zinc (Zn) and the second layer (150L) may comprise gallium arsenide (GaAs) doped with either silicon (Si) or tellurium (Te).

[0140] According to exemplary embodiments, the first layer (140L) may comprise gallium arsenide (GaAs) doped with either silicon (Si) or tellurium (Te), and the second layer (150L) may comprise gallium arsenide (GaAs) doped with zinc (Zn).

[0141] According to exemplary embodiments, the first layer (140L) may comprise germanium (Ge) doped with boron (B) and the second layer (150L) may comprise germanium (Ge) doped with either phosphorus (P) or antimony (Sb).

[0142] According to exemplary embodiments, the first layer (140L) may comprise germanium (Ge) doped with either phosphorus (P) or antimony (Sb), and the second layer (150L) may comprise germanium (Ge) doped with boron (B).

[0143] According to exemplary embodiments, the first layer (140L) may comprise gallium nitride (GaN) doped with magnesium (Mg) and the second layer (150L) may comprise gallium nitride (GaN) doped with silicon (Si).

[0144] According to exemplary embodiments, the first layer (140L) may comprise gallium nitride (GaN) doped with silicon (Si) and the second layer (150L) may comprise gallium nitride (GaN) doped with magnesium (Mg).

[0145] According to exemplary embodiments, the first layer (140L) may comprise silicon carbide (SiC) doped with either aluminum (Al) or boron (B), and the second layer (150L) may comprise silicon carbide (SiC) doped with either nitrogen (N) or phosphorus (P).

[0146] According to exemplary embodiments, the first layer (140L) may comprise silicon carbide (SiC) doped with either nitrogen (N) or phosphorus (P), and the second layer (150L) may comprise silicon carbide (SiC) doped with either aluminum (Al) or boron (B).

[0147] According to exemplary embodiments, the first layer (140L) may comprise indium phosphate (InP) doped with zinc (Zn) and the second layer (150L) may comprise indium phosphate (InP) doped with either sulfur (S) or silicon (Si).

[0148] According to exemplary embodiments, the first layer (140L) may comprise indium phosphate (InP) doped with either sulfur (S) or silicon (Si), and the second layer (150L) may comprise indium phosphate (InP) doped with zinc (Zn).

[0149] According to exemplary embodiments, the first layer (140L) may contain cadmium telluride (CdTe) and the second layer (150L) may contain cadmium sulfide (CdS).

[0150] According to exemplary embodiments, the first layer (140L) may contain cadmium sulfide (CdS) and the second layer (150L) may contain cadmium telluride (CdTe).

[0151] According to exemplary embodiments, the first layer (140L) may comprise tin oxide (SnO) and the second layer (150L) may comprise zinc oxide (ZnO).

[0152] According to exemplary embodiments, the first layer (140L) may comprise zinc oxide (ZnO) and the second layer (150L) may comprise tin oxide (SnO).

[0153] According to exemplary embodiments, the first layer (140L) may have the same conductivity type as the substrate (110), and the second layer (150L) may have the same conductivity type as the layer (120L). In one example, the first layer (140L) and the substrate (110) may be doped with an n-type dopant, and the second layer (150L) and the layer (120L) may be doped with a p-type dopant. In another example, the first layer (140L) and the substrate (110) may be doped with a p-type dopant, and the second layer (150L) and the layer (120L) may be doped with an n-type dopant.

[0154] According to other exemplary embodiments, the first layer (140L) may have the same conductivity type as layer (120L), and the second layer (150L) may have the same conductivity type as the substrate (110). In one example, the first layer (140L) and layer (120L) may be doped with an n-type dopant, and the second layer (150L) and the substrate (110) may be doped with a p-type dopant. In another example, the first layer (140L) and layer (120L) may be doped with a p-type dopant, and the second layer (150L) and the substrate (110) may be doped with an n-type dopant.

[0155]

[0156] Next, referring to FIGS. 1 and FIGS. 13 to 15, a first Chemical Mechanical Polishing (CMP) process can be performed at P170. The upper surface (110U) of the substrate (110) may be the endpoint of the first CMP process. The endpoint of the CMP process may be determined by a change in reflectance inside the CMP chamber or a change in the concentration of a specific chemical component.

[0157] By the first CMP process, the layer (120L) can be separated into a plurality of patterns (120). By the first CMP process, the energy source layer (130L) can be separated into a plurality of energy source patterns (130). By the first CMP process, the first layer (140L) can be separated into a plurality of first patterns (140). By the first CMP process, the second layer (150L) can be separated into a plurality of second patterns (150). The upper surface of each of the plurality of patterns (120), the upper surface of each of the plurality of energy source patterns (130), the upper surface of each of the plurality of first patterns (140), and the upper surface of each of the plurality of second patterns (150) can form a co-surface with the upper surface (110U) of the substrate (110).

[0158]

[0159] Next, referring to FIGS. 1, 15 and 16, a second CMP process can be performed at P180. A plurality of second patterns (150) may be the endpoints of the second CMP process. By the second CMP process, an integrated cell (100) comprising a substrate (110), a plurality of patterns (120), a plurality of energy source patterns (130), a plurality of first patterns (140) and a plurality of second patterns (150) may be provided.

[0160] By processing P180, multiple recesses (110R) can become multiple holes (110H) that extend to a new lower surface (110L') of the substrate (110). Each of the multiple holes (110H) can penetrate the substrate (110). The lower surface of each of the multiple patterns (120), the lower surface of each of the multiple energy source patterns (130), the lower surface of each of the multiple first patterns (140), and the lower surface of each of the multiple second patterns (150) can form a co-surface with the lower surface (110L') of the substrate (110).

[0161] According to exemplary embodiments, the substrate (110) may include a plurality of holes (110H) having a tapered shape. Each of the plurality of holes (110H) may extend in a Z direction perpendicular to the upper surface (110U) of the substrate (110). Each of the plurality of holes (110H) may penetrate the substrate (110).

[0162] Each of the plurality of patterns (120) may be in contact with the substrate (110). The plurality of patterns (120) may have opposite polarity to the substrate (110). Each of the plurality of patterns (120) may be located between the substrate (110) and a corresponding one of the plurality of energy source patterns (130). The thickness of each of the plurality of patterns (120) may be uniform.

[0163] Each of the plurality of energy source patterns (130) may be located within a corresponding of the plurality of holes (110H). Each of the plurality of energy source patterns (130) may be located between a corresponding of the plurality of patterns (120) and a corresponding of the plurality of first patterns (140). The thickness of each of the plurality of energy source patterns (130) may be uniform. Each of the plurality of energy source patterns (130) may be surrounded by a corresponding of the plurality of patterns (120).

[0164] Each of the plurality of first patterns (140) may be located within a corresponding of the plurality of holes (110H). Each of the plurality of first patterns (140) may be located between a corresponding of the plurality of energy source patterns (130) and a corresponding of the plurality of second patterns (150). The thickness of each of the plurality of first patterns (140) may be uniform. Each of the plurality of first patterns (140) may be surrounded by a corresponding of the plurality of energy source patterns (130). Each of the plurality of first patterns (140) may be spaced apart from a corresponding of the plurality of patterns (120) with a corresponding of the plurality of energy source patterns (130) in between.

[0165] Each of the plurality of second patterns (150) may be within a corresponding one of the plurality of holes (110H). Each of the plurality of second patterns (150) may have a tapered shape. Each of the plurality of second patterns (150) may be surrounded by a corresponding one of the plurality of first patterns (140).

[0166] Each of the plurality of energy source patterns (130) may be configured to emit beta rays. The depletion region between the substrate (110) and the plurality of patterns (120) irradiated by the beta rays may be configured to generate an electromotive force by electron-hole pair production. The depletion region between the plurality of first patterns (140) and the plurality of second patterns (150) irradiated by the beta rays may be configured to generate an electromotive force by electron-hole pair production.

[0167] According to exemplary embodiments, by providing a plurality of energy source patterns (130) that partially fill a plurality of holes (110H), the amount of material required to form the plurality of energy source patterns (130) can be reduced, and accordingly, the manufacturing cost of the integrated cell (100) can be reduced. In addition, since a pn junction and a depletion region are formed on the outer and inner sides of each of the plurality of energy source patterns (130), the utilization rate of beta particles emitted from the plurality of energy source patterns (130) can be increased, and accordingly, the energy efficiency of the integrated cell (100) can be improved.

[0168]

[0169] According to exemplary embodiments, each of the energy source patterns (130) may include a first surface and a second surface. The first surface may be opposite to the second surface. The first surface of each of the energy source patterns (130) may face the substrate (110). On the first surface of each of the energy source patterns (130), there may be any one of a doped diamond substrate, a doped SiC substrate, a doped GaN substrate, a doped Bi2O3 / GeO2 substrate, a doped Sm2O3 / Bi2O3 / GeO2 substrate, a doped Sm2O3 / Bi2O3 / B2O3 substrate, a doped Sm2O3 / Bi2O3 / GeO2 / B2O3 substrate, and a doped sapphire substrate.

[0170] On the first surface of each of the energy source patterns (130), there may be an element comprising a metal oxide having a bandgap energy of 2.7 eV or more. On the first surface of each of the energy source patterns (130), there may be a material represented as AMO3 (wherein A is one or more selected from the group consisting of La, Ba, Sr, and K, and M is one or more selected from the group consisting of Al, In, Ga, Ti, Sn, Hf, Ta, and Zr). On the first surface of each of the energy source patterns (130), there may be BaSnO3, BaHfO3, BaZrO3, BaHf1-x Ti x O3(here 0 <x<1), Ba 1-x La x SnO3(here 0 <x<1), Bi4Ge3O 12 , Al2O3, Y2O3, La2O3, Ga2O3, Bi2O3, ZrO2, HfO2, Ta2O5, TiO2, LaInO3, LaGaO3, SrZrO3, SrHfO3, SrTaO7, LaIn 1-x Ga x O3(here 0 <x<1), LaGaO3, SrTiO3, KTaO3, HfSiO4, Ta3Ti2O x (Here 0 <x<1) 및 LaAlO3중 하나 이상을 포함하는 요소가 있을 수 있다.

[0171] On the second surface of each of the energy source patterns (130), silicon (Si) doped with boron (B), silicon (Si) doped with one of phosphorus (P) and arsenic (As), gallium arsenide (GaAs) doped with zinc (Zn), gallium arsenide (GaAs) doped with one of silicon (Si) and tellurium (Te), germanium (Ge) doped with boron (B), germanium (Ge) doped with one of phosphorus (P) and antimony (Sb), gallium nitride (GaN) doped with magnesium (Mg), gallium nitride (GaN) doped with silicon (Si), silicon carbide (SiC) doped with one of aluminum (Al) and boron (B), silicon carbide (SiC) doped with one of nitrogen (N) and phosphorus (P), indium phosphate (InP) doped with zinc (Zn), and indium doped with one of sulfur (S) and silicon (Si). There may be elements containing one or more of phosphate (InP), cadmium telluride (CdTe), cadmium sulfide (CdS), tin oxide (SnO), and zinc oxide (ZnO).

[0172]

[0173] (3rd Example)

[0174] FIG. 17 is a drawing showing an integrated battery (101) according to other exemplary embodiments.

[0175] Referring to FIG. 17, the integrated cell (101) may include a substrate (110), a plurality of patterns (120), a plurality of energy source patterns (130), a plurality of first patterns (140) and a plurality of second patterns (150).

[0176] By setting the end point of the second CMP process of P180 (see FIG. 1) to the lower surface of each of the plurality of first patterns (140), the integrated cell (101) of FIG. 17 can be provided. The lower surface of each of the plurality of patterns (120), the lower surface of each of the plurality of energy source patterns (130), and the lower surface of each of the plurality of first patterns (140) can form a co-plane with the lower surface (110L') of the substrate (110). The lower surface of each of the plurality of second patterns (150) can be spaced apart from the lower surface (110L') of the substrate (110). Each of the plurality of first patterns (140) can have a cup shape.

[0177]

[0178] (Fourth Example)

[0179] FIG. 18 is a drawing showing an integrated battery (102) according to other exemplary embodiments.

[0180] Referring to FIG. 18, the integrated cell (102) may include a substrate (110), a plurality of patterns (120), a plurality of energy source patterns (130), a plurality of first patterns (140) and a plurality of second patterns (150).

[0181] By setting the end point of the second CMP process of P180 (see FIG. 1) to the lower surface of each of the plurality of energy source patterns (130), the integrated cell (102) of FIG. 18 can be provided. The lower surface of each of the plurality of patterns (120) and the lower surface of each of the plurality of energy source patterns (130) can be co-plane with the lower surface (110L') of the substrate (110). The lower surface of each of the plurality of second patterns (150) can be spaced apart from the lower surface (110L') of the substrate (110). The lower surface of each of the plurality of first patterns (140) can be spaced apart from the lower surface (110L') of the substrate (110).

[0182] Each of the plurality of energy source patterns (130) may have a cup shape. Each of the plurality of first patterns (140) may have a cup shape.

[0183]

[0184] (5th Example)

[0185] FIG. 19 is a drawing showing an integrated battery (103) according to other exemplary embodiments.

[0186] Referring to FIG. 19, the integrated cell (103) may include a substrate (110), a plurality of patterns (120), a plurality of energy source patterns (130), a plurality of first patterns (140) and a plurality of second patterns (150).

[0187] By setting the end point of the second CMP process of P180 (see FIG. 1) to the lower surface of a plurality of patterns (120), the integrated cell (103) of FIG. 19 can be provided. The lower surface of each of the plurality of patterns (120) can be co-plane with the lower surface (110L') of the substrate (110). The lower surface of each of the plurality of second patterns (150) can be spaced apart from the lower surface (110L') of the substrate (110). The lower surface of each of the plurality of first patterns (140) can be spaced apart from the lower surface (110L') of the substrate (110). The lower surface of each of the plurality of energy source patterns (130) can be spaced apart from the lower surface (110L') of the substrate (110).

[0188] Each of the plurality of patterns (120) may have a cup shape. Each of the plurality of energy source patterns (130) may have a cup shape. Each of the plurality of first patterns (140) may have a cup shape.

[0189]

[0190] (6th Example)

[0191] FIG. 20 is a drawing showing an integrated battery (104) according to other exemplary embodiments.

[0192] Referring to FIG. 20, the integrated cell (104) may include a substrate (110), a plurality of patterns (120), a plurality of energy source patterns (130), a plurality of first patterns (140) and a plurality of second patterns (150).

[0193] By setting the end point of the second CMP process of P180 (see FIG. 1) to a position spaced apart from the lower surface of the plurality of patterns (120), the integrated cell (104) of FIG. 20 can be provided. For example, the end point of the second CMP process may include the removal of a target thickness of the substrate (110). The lower surface of each of the plurality of second patterns (150) may be spaced apart from the lower surface (110L') of the substrate (110). The lower surface of each of the plurality of first patterns (140) may be spaced apart from the lower surface (110L') of the substrate (110). The lower surface of each of the plurality of energy source patterns (130) may be spaced apart from the lower surface (110L') of the substrate (110). The lower surface of the plurality of patterns (120) may be spaced apart from the lower surface (110L') of the substrate (110).

[0194] Each of the plurality of patterns (120) may have a cup shape. Each of the plurality of energy source patterns (130) may have a cup shape. Each of the plurality of first patterns (140) may have a cup shape.

[0195]

[0196] (9th Example)

[0197] FIG. 21 is a plan view of an integrated cell (100a) according to exemplary embodiments.

[0198] FIG. 22 is a cross-sectional view taken along the cutting line 21I-21I' of FIG. 21.

[0199] Referring to FIGS. 21 and 22, the integrated cell (100a) may include a substrate (110), a plurality of patterns (120), a plurality of energy source patterns (130), a plurality of first patterns (140) and a plurality of second patterns (150).

[0200] The material (110), the plurality of patterns (120), the plurality of energy source patterns (130), the plurality of first patterns (140), and the plurality of second patterns (150) are substantially the same as those described with reference to FIGS. 1 to 16, except for the arrangement of the plurality of holes (110H), so a redundant description thereof is omitted.

[0201] Unlike in FIG. 16, where multiple holes (110H) are arranged in a honeycomb structure, in this example, multiple holes (110H) may be arranged in a non-honeycomb structure. At least some of the centers of the multiple holes (110H) may be offset from the positions for forming the honeycomb structure. When each of the multiple holes (110H) aligned along the Y direction is defined as a hole array (HAR), adjacent hole arrays (HAR) may be staggered. The multiple holes (110H) may be arranged in a zigzag pattern along the X direction.

[0202] A plurality of patterns (120), a plurality of energy source patterns (130), a plurality of first patterns (140), and a plurality of second patterns (150) together fill a plurality of holes (110H), and the description of the arrangement of the plurality of holes (110H) may also apply to the plurality of patterns (120), a plurality of energy source patterns (130), a plurality of first patterns (140), and a plurality of second patterns (150).

[0203]

[0204] (10th Example)

[0205] FIG. 23 is a plan view of an integrated cell (100b) according to exemplary embodiments.

[0206] FIG. 24 is a cross-sectional view taken along the cutting line 23I-23I' of FIG. 23.

[0207] Referring to FIGS. 23 and 24, the integrated cell (100b) may include a substrate (110), a plurality of patterns (120), a plurality of energy source patterns (130), a plurality of first patterns (140), and a plurality of second patterns (150). Since the substrate (110), the plurality of patterns (120), the plurality of energy source patterns (130), the plurality of first patterns (140), and the plurality of second patterns (150) are substantially the same as those described with reference to FIGS. 1 through 16, except for the arrangement of a plurality of holes (110H), a redundant description thereof is omitted.

[0208] Unlike in FIG. 16, where multiple holes (110H) are arranged in a honeycomb structure, in this example, multiple holes (110H) can be arranged in a matrix. Multiple holes (110H) can be aligned in the X direction. Multiple holes (110H) can be aligned in the Y direction.

[0209] A plurality of patterns (120), a plurality of energy source patterns (130), a plurality of first patterns (140), and a plurality of second patterns (150) together fill a plurality of holes (110H), and the description of the arrangement of the plurality of holes (110H) may also apply to the plurality of patterns (120), a plurality of energy source patterns (130), a plurality of first patterns (140), and a plurality of second patterns (150).

[0210]

[0211] (11th Example)

[0212] FIG. 25 is a plan view of an integrated cell (100c) according to exemplary embodiments.

[0213] FIG. 26 is a cross-sectional view taken along the cutting line 25I-25I' of FIG. 25.

[0214] Referring to FIGS. 25 and 26, the integrated cell (100c) may include a substrate (110), a plurality of patterns (120'), a plurality of energy source patterns (130'), a plurality of first patterns (140'), and a plurality of second patterns (150'). Since the substrate (110), the plurality of patterns (120'), the plurality of energy source patterns (130'), the plurality of first patterns (140'), and the plurality of second patterns (150') are substantially the same as those described with reference to FIGS. 1 through 16, except for changes in the shape of the plurality of holes (110H'), a redundant description thereof is omitted.

[0215] Unlike the plurality of holes (110H) in FIG. 16 having a circular shape, in this example, the plurality of holes (110H') may have a line shape. The plurality of holes (110H') may form a line and space structure. Each of the plurality of holes (110H') may extend in the X direction. The plurality of holes (110H') may be spaced apart from each other in the Y direction.

[0216] Each of the plurality of patterns (120') may be on the side wall of the corresponding of the plurality of holes (110H'). Each of the plurality of patterns (120') may extend in the X direction. Each of the plurality of patterns (120') may have a uniform thickness.

[0217] Multiple energy source patterns (130') may be on multiple patterns (120'). Each of the multiple energy source patterns (130') may extend in the X direction. Each of the multiple energy source patterns (130') may have a uniform thickness.

[0218] A plurality of first patterns (140') may be on a plurality of energy source patterns (130'). Each of the plurality of first patterns (140') may extend in the X direction. Each of the plurality of first patterns (140') may have a uniform thickness.

[0219] A plurality of second patterns (150') may be on a plurality of first patterns (140'). Each of the plurality of second patterns (150') may be extended in the X direction. Each of the plurality of second patterns (150') may have a line shape. Each of the plurality of second patterns (150') may have a tapered shape in the Z direction.

[0220]

[0221] (12th Example)

[0222] FIG. 27 is a plan view of an integrated cell (100d) according to exemplary embodiments.

[0223] FIG. 28 is a cross-sectional view taken along the cutting line 27I-27I' of FIG. 27.

[0224] Referring to FIGS. 27 and 28, the integrated cell (100d) may include a substrate (110), a plurality of patterns (120"), a plurality of energy source patterns (130"), a plurality of first patterns (140"), and a plurality of second patterns (150"). Since the substrate (110), the plurality of patterns (120"), the plurality of energy source patterns (130"), the plurality of first patterns (140"), and the plurality of second patterns (150") are substantially the same as those described with reference to FIGS. 1 through 16, except for changes in the shape of the plurality of holes (110H"), a redundant description thereof is omitted.

[0225] According to exemplary embodiments, an additional etching process may be formed to roughen a plurality of holes (110H) before a material layer is formed to form a plurality of patterns (120") such as a layer (120L, see FIG. 7). The additional etching process may be, for example, a wet etching process.

[0226] According to exemplary embodiments, each of the plurality of holes (110H") may have a roughened circular shape when viewed from above. According to exemplary embodiments, each of the plurality of holes (110H") may have a star shape when viewed from above.

[0227] According to exemplary embodiments, each of the patterns (120) may have a roughened ring shape when viewed from above. Each of the patterns (120) may have a hollow star shape when viewed from above.

[0228] According to exemplary embodiments, each of the plurality of energy source patterns (130) may have a roughened ring shape when viewed from above. According to exemplary embodiments, each of the plurality of energy source patterns (130) may have a hollow star shape when viewed from above.

[0229] According to exemplary embodiments, each of the plurality of first patterns (140) may have a roughened ring shape when viewed from above. According to exemplary embodiments, each of the plurality of first patterns (140) may have a hollow star shape when viewed from above.

[0230] According to exemplary embodiments, each of the plurality of second patterns (150") may have a roughened circle when viewed from above. According to exemplary embodiments, each of the plurality of second patterns (150") may have a star shape when viewed from above.

[0231] According to exemplary embodiments, the interface between the substrate (110) and the plurality of patterns (120) can be roughened. According to exemplary embodiments, the interface between the plurality of patterns (120) and the plurality of energy source patterns (130) can be roughened. According to exemplary embodiments, the interface between the plurality of energy source patterns (130) and the plurality of first patterns (140) can be roughened. According to exemplary embodiments, the interface between the plurality of first patterns (140) and the plurality of second patterns (150) can be roughened.

[0232]

[0233] (Examples 13 and 14)

[0234] FIG. 29 is a flowchart illustrating a method for manufacturing an integrated cell according to other exemplary embodiments.

[0235] FIG. 30 is a plan view illustrating a method for manufacturing an integrated cell according to exemplary embodiments.

[0236] FIG. 31 is a cross-sectional view taken along the cutting line 30I-30I' of FIG. 30.

[0237] FIG. 32 is a plan view illustrating a method for manufacturing an integrated cell according to exemplary embodiments.

[0238] FIG. 33 is a cross-sectional view taken along the cutting line 32I-32I' of FIG. 32.

[0239] FIG. 34 is a plan view illustrating a method for manufacturing an integrated cell according to exemplary embodiments.

[0240] FIG. 35 is a cross-sectional view taken along the cutting line 34I-34I' of FIG. 34.

[0241] For the convenience of explanation, parts that overlap with those explained with reference to Figures 1 to 16 will be omitted, and the differences will be explained mainly.

[0242] Referring to FIGS. 29 and FIGS. 31, the processing of P110 to P160 is substantially the same as described with reference to FIGS. 1 to 16, but the substrate (110) may include an electrical region (VR) and a contact region (CR). The substrate (110) of the electrical region (VR) may be patterned as in FIG. 3 and may include a plurality of recesses (110R). The substrate (110) of the contact region (CR) may not be patterned, and the substrate (110) of the contact region (CR) may not include a plurality of recesses (110R). The substrate (110) of the contact region (CR) may be spaced apart from the plurality of recesses (110R).

[0243] Next, a CMP process can be performed at P171. By the CMP process of P171, the upper portion of the second layer (150L) may be partially removed and the upper surface of the second layer (150L) may be flattened. In the CMP process of P171, the layer (120L), the energy source layer (130L), the first layer (140L), and the second layer (150L) may not be separated. P171 may be omitted.

[0244]

[0245] Next, referring to FIGS. 29, 32 and 33, a step structure (SS) can be formed in P191. The step structure (SS) can be formed through a repetitive photolithography and etching process. The step structure (SS) may include a first layer (140L) protruding in a horizontal direction (e.g., Y direction) with respect to a second layer (150L), a layer (120L) protruding in a horizontal direction (e.g., Y direction) with respect to the first layer (140L), and a substrate (110) protruding in a horizontal direction (e.g., Y direction) with respect to the layer (120L). Accordingly, in the contact area (CR), the upper surface of the first layer (140L), the upper surface of the layer (120L), and the upper surface (110U) of the substrate (110) may be exposed.

[0246]

[0247] Next, referring to FIGS. 29, 34 and 35, vias (V11, V12, V13, V14) can be formed in P193. Forming the vias (V11, V12, V13, V14) may include depositing an insulating material to form an insulating material layer, etching the insulating material layer to form an insulating layer (IL1) comprising via holes exposing the upper surface of the substrate (110), via holes exposing the upper surface of the layer (120L), via holes exposing the upper surface of the first layer (140L), and via holes exposing the upper surface of the second layer (150L), providing a conductive material layer to fill the via holes, and separating the conductive material layer into vias (V11, V12, V13, V14) through a planarization process.

[0248] Each via (V11) can be landed on the substrate (110). Each via (V11) can be in contact with the substrate (110). Each via (V11) can be extended in the Z direction. Each via (V11) can penetrate the insulating layer (IL1). The vias (V11) can be arranged in the X direction. As the vias (V11) are arranged in the X direction, a voltage drop in the X direction of the substrate (110) can be prevented.

[0249] Each via (V12) can be landed on the layer (120L). Each via (V12) can be in contact with the layer (120L). Each via (V12) can be extended in the Z direction. Each via (V12) can penetrate the insulating layer (IL1). The vias (V12) can be arranged in the X direction. As the vias (V12) are arranged in the X direction, a voltage drop in the X direction of the layer (120L) can be prevented.

[0250] Each of the vias (V13) can be landed on the first layer (140L). Each of the vias (V13) can be in contact with the first layer (140L). Each of the vias (V13) can extend in the Z direction. Each of the vias (V13) can penetrate the insulating layer (IL1). The vias (V13) can be arranged in the X direction. As the vias (V13) are arranged in the X direction, a voltage drop in the X direction of the first layer (140L) can be prevented.

[0251] Each via (V14) can be landed on the second layer (150L). Each via (V14) can be in contact with the second layer (150L). Each via (V14) can be extended in the Z direction. Each via (V14) can penetrate the insulating layer (IL1). The vias (V14) can be arranged in the X direction. As the vias (V14) are arranged in the X direction, a voltage drop in the X direction of the second layer (150L) can be prevented.

[0252]

[0253] Next, referring to FIGS. 29, 36 and 37, conductive lines (M11, M12, M13, M14) can be formed in P200. By forming the conductive lines (M11, M12, M13, M14), an integrated cell (105a) comprising a substrate (110), a layer (120L), an energy source layer (130L), a first layer (140L), a second layer (150L), insulating layers (IL1, IL2), vias (V11, V12, V13, V14) and conductive lines (M11, M12, M13, M14) can be provided.

[0254] The formation of conductive lines (M11, M12, M13, M14) may include forming an insulating layer (IL2) on an insulating layer (IL1), patterning the insulating layer (IL2) so that vias (V11, V12, V13, V14) are exposed, depositing a conductive material in contact with the vias (V11, V12, V13, V14), and performing CMP. Unlike in FIGS. 34 to 37, the vias (V11, V12, V13, V14) and conductive lines (M11, M12, M13, M14) may be formed by a dual damascene process.

[0255] A conductive line (M11) can be extended in the X direction. The conductive line (M11) can be in contact with each of the vias (V11). A conductive line (M12) can be extended in the X direction. The conductive line (M12) can be in contact with each of the vias (V12). A conductive line (M13) can be extended in the X direction. The conductive line (M13) can be in contact with each of the vias (V13). A conductive line (M14) can be extended in the X direction. The conductive line (M14) can be in contact with each of the vias (V14).

[0256] Each of the insulating layers (IL1, IL2) may comprise one or more of silicate (e.g., TEOS), silicon nitride (SiN, silicon nitride), hafnium oxide, hafnium silicon oxide, hafnium aluminum oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, and aluminum oxide.

[0257] Each of the vias (V11, V12, V13, V14) and the conductive lines (M11, M12, M13, M14) may contain one or more of aluminum (Al), copper (Cu), tungsten (W), and titanium (Ti).

[0258] According to exemplary embodiments, vias (V11) and conductive lines (M11) can form a first output terminal of a cell composed of a substrate (110) and a layer (120L).

[0259] According to exemplary embodiments, vias (V12) and conductive lines (M12) can form a second output terminal of a cell composed of a substrate (110) and a layer (120L).

[0260] According to exemplary embodiments, vias (V13) and conductive lines (M13) can form a first output terminal of a cell composed of a first layer (140L) and a second layer (150L).

[0261] According to exemplary embodiments, vias (V14) and conductive lines (M14) can form a second output terminal of a cell composed of a first layer (140L) and a second layer (150L).

[0262] According to exemplary embodiments, by forming a contact area (CR) horizontally separated from an electrical area (VR), a wiring structure connected to a first layer (140L) and a second layer (150L) formed with a relatively narrow pitch can be easily formed.

[0263]

[0264] (15th Example)

[0265] FIG. 38 is a cross-sectional view of an integrated cell (105b) according to exemplary embodiments.

[0266] Referring to FIG. 38, the integrated cell (105b) may include a substrate (110), a layer (120L), an energy source layer (130L), a first layer (140L), a second layer (150L), insulating layers (IL1, IL2, IL3, IL4), vias (V11, V12, V13, V14), conductive lines (M11, M123, M14), vias (V2) and a conductive line (M2).

[0267] The substrate (110), layer (120L), energy source layer (130L), first layer (140L), second layer (150L), insulating layers (IL1, IL2), vias (V11, V12, V13, V14) and conductive lines (M11, M14) are substantially the same as those described with reference to FIGS. 29 to 37, so a redundant description thereof is omitted.

[0268] The insulating layer (IL3) may be on the insulating layer (IL2). The insulating layer (IL4) may be on the insulating layer (IL3). The insulating layers (IL3, IL4) may include the materials exemplified in relation to the insulating layers (IL1, IL2).

[0269] The conductive line (M123) can be extended in the X direction. The conductive line (M123) can be in contact with each of the vias (V12). The conductive line (M123) can be in contact with each of the vias (V13). Accordingly, the layer (120L) can be connected to the first layer (140L) through the vias (V12), the conductive line (M123), and the vias (V13).

[0270] vias (V2) can penetrate the insulating layer (IL3). Some vias (V2) can land on a conductive line (M11). Some vias (V2) can be in contact with the conductive line (M11). Some vias (V2) can land on a conductive line (M14). Some vias (V2) can be in contact with the conductive line (M14). The conductive line (M2) can be in contact with each of the vias (V2). Each of the conductive line (M2) and the vias (V2) may contain one or more of aluminum (Al), copper (Cu), tungsten (W), and titanium (Ti).

[0271] According to exemplary embodiments, the substrate (110) can be connected to a second layer (150L) through vias (V11), a conductive line (M11), vias (V2), a conductive line (M2), vias (V2), a conductive line (M14), and vias (V14).

[0272] Accordingly, when the second layer (150L) and the substrate (110) have the same conductivity type and the first layer (140L) and the layer (120L) have the same conductivity type, the cell composed of the substrate (110) and the layer (120L) can be connected in parallel with the cell composed of the first layer (140L) and the second layer (150L).

[0273]

[0274] (16th Example)

[0275] FIG. 39 is a cross-sectional view of an integrated cell (105c) according to exemplary embodiments.

[0276] Referring to FIG. 39, the integrated cell (105c) may include a substrate (110), a layer (120L), an energy source layer (130L), a first layer (140L), a second layer (150L), insulating layers (IL1, IL2, IL3, IL4), vias (V11, V12, V13, V14), conductive lines (M11, M12, M13, M14), vias (V2), and conductive lines (M2).

[0277] The substrate (110), layer (120L), energy source layer (130L), first layer (140L), second layer (150L), insulating layers (IL1, IL2, IL3, IL4), vias (V11, V12, V13, V14), conductive lines (M11, M12, M13, M14), vias (V2) and conductive lines (M2) are substantially the same as those described with reference to FIGS. 29 to 38, except for the connection aspect, so a redundant description of these is omitted.

[0278] Some vias (V2) may land on a conductive line (M11). Some vias (V2) may be in contact with the conductive line (M11). Some vias (V2) may land on a conductive line (M12). Some vias (V2) may be in contact with the conductive line (M12). Some vias (V2) may land on a conductive line (M14). Some vias (V2) may be in contact with the conductive line (M14).

[0279] One of the conductive lines (M2) can be in contact with each of the vias (V2) on the conductive line (M11). Another of the conductive lines (M2) can be in contact with each of the vias (V2) on the conductive line (M12) and each of the vias (V2) on the conductive line (M14).

[0280] According to exemplary embodiments, the layer (120L) can be connected to the second layer (150L) through vias (V12), a conductive line (M12), vias (V2), conductive lines (M2), vias (V2), a conductive line (M14), and vias (V14).

[0281] According to exemplary embodiments, vias (V11), a conductive line (M11), vias (V2), and a conductive line (M2) connected to the substrate (110) may be the first output terminals of the integrated cell (105c). According to exemplary embodiments, vias (V13) and a conductive line (M13) connected to the first layer (140L) may be the second output terminals of the integrated cell (105c).

[0282] According to exemplary embodiments, when the second layer (150L) and the substrate (110) are of type p and the first layer (140L) and the layer (120L) are of type n, the cell composed of the substrate (110) and the layer (120L) can be connected in series with the cell composed of the first layer (140L) and the second layer (150L).

[0283]

[0284] (17th Example)

[0285] FIG. 40 is a plan view of an integrated cell according to exemplary embodiments.

[0286] FIG. 41 is a cross-sectional view taken along the cutting line 40I-40I' of FIG. 40.

[0287] Referring to FIGS. 40 and 41, the integrated cell (106) may include a substrate (110), a layer (120L), an energy source layer (130L), a first layer (140L), a second layer (150L), insulating layers (IL1, IL2), vias (V11, V12, V13, V14) and conductive lines (M11, M12, M13, M14).

[0288] The substrate (110) may include an electrical region (VR) and contact regions (CR1, CR2). The substrate (110) of the electrical region (VR) may be patterned as in FIG. 3 and may include a plurality of recesses (110R).

[0289] The substrate (110) of the contact regions (CR1, CR2) may not be patterned, and the substrate (110) of the contact regions (CR1, CR2) may not include a plurality of recesses (110R). The substrate (110) of the contact regions (CR1, CR2) may be spaced apart from the plurality of recesses (110R). An electrical region (VR) may be located between the contact regions (CR1, CR2). The contact regions (CR1, CR2) may be spaced apart from each other in the Y direction.

[0290] A step structure (SS1) may be present on the contact area (CR1). The step structure (SS1) may include a layer (120L) protruding in a horizontal direction (e.g., Y direction) based on the first layer (140L) and the second layer (150L), and a substrate (110) protruding in a horizontal direction (e.g., Y direction) based on the layer (120L).

[0291] A step structure (SS2) may be present on the contact area (CR2). The step structure (SS2) may include a first layer (140L) protruding in a horizontal direction (e.g., Y direction) relative to the second layer (150L).

[0292] According to exemplary embodiments, vias (V11, V12) and conductive lines (M11, M12) may be in a contact area (CR1), and vias (V13, V14) and conductive lines (M11, M12) may be in a contact area (CR2). Accordingly, interference between wirings can be prevented, and the degree of freedom in wiring design can be enhanced.

[0293]

[0294] (18th Example)

[0295] FIG. 42 is a cross-sectional view of an integrated cell (107a) according to exemplary embodiments.

[0296] Referring to FIG. 42, the integrated cell (107a) may include a substrate (110), a layer (120L), an energy source layer (130L), a first layer (140L), a second layer (150L), insulating layers (IL1, IL2), vias (V11', V12', V13', V14') and conductive lines (M11, M12, M13, M14).

[0297] The integrated cell (107a) is generally similar to the direct cell (106) of FIG. 41, except that it includes vias (V11', V12', V13', V14') instead of vias (V11, V12, V13, V14).

[0298] Each of the vias (V11', V12', V13', V14') may include a passivation layer (VI) and a conductive layer (VC). The passivation layer (VI) may include an insulating material. The conductive layer (VC) may include a conductive material. The conductive layer (VC) may be surrounded by the passivation layer (VI).

[0299] A passivation layer (VI) may be on the inner wall of the via hole. The passivation layer (VI) can prevent an unwanted short circuit in the conductive layer (VC) of each of the vias (V11', V12', V13', V14'). The passivation layer (VI) of each of the vias (V11') can prevent a short circuit between the conductive layer (VC) and the layer (120L), the energy source layer (130L), the first layer (140L), and the second layer (150L).

[0300] Each conductive layer (VC) of the vias (V11') may be spaced apart from the layer (120L), energy source layer (130L), first layer (140L), and second layer (150L) with a passivation layer (VI) in between. Each conductive layer (VC) of the vias (V11') may be in contact with the substrate (110). Each of the vias (V11') may be configured to be electrically connected to the substrate (110), which is the landed layer.

[0301] Each passivation layer (VI) of the vias (V12') can prevent a short circuit between the conductive layer (VC) and the energy source layer (130L), the first layer (140L) and the second layer (150L).

[0302] Each conductive layer (VC) of the vias (V12') may be spaced apart from the energy source layer (130L), the first layer (140L), and the second layer (150L) with a passivation layer (VI) in between. Each conductive layer (VC) of the vias (V12') may be in contact with layer (120L). Each via (V12') may be configured to be electrically connected to layer (120L), which is the landed layer.

[0303] Each passivation layer (VI) of the vias (V13') can prevent a short circuit between the conductive layer (VC) and the second layer (150L). Each conductive layer (VC) of the vias (V13') can be spaced apart from the second layer (150L) with the passivation layer (VI) in between. Each conductive layer (VC) of the vias (V12') can be in contact with the first layer (140L). Each of the vias (V12') can be configured to be electrically connected to the first layer (140L), which is the landed layer.

[0304] The conductive line (M11) can be in contact with the conductive layer (VC) of each via (V11'). The conductive line (M12) can be in contact with the conductive layer (VC) of each via (V12'). The conductive line (M13) can be in contact with the conductive layer (VC) of each via (V13'). The conductive line (M14) can be in contact with the conductive layer (VC) of each via (V14').

[0305] According to exemplary embodiments, each of the vias (V11', V12', V13', V14') includes a passivation layer (VI), so that processes for forming a stepped structure can be omitted, thereby increasing the throughput of manufacturing the integrated cell (107a) and reducing manufacturing costs.

[0306]

[0307] (19th Example)

[0308] FIG. 43 is a cross-sectional view of an integrated cell (107b) according to exemplary embodiments.

[0309] Referring to FIG. 43, the integrated cell (107b) may include a substrate (110), a layer (120L), an energy source layer (130L), a first layer (140L), a second layer (150L), insulating layers (IL1, IL2), vias (V11', V12', V13', V14') and conductive lines (M11, M124, M13).

[0310] The integrated cell (107b) is largely similar to the direct cell (107a) of FIG. 42, except for the connection and arrangement of vias (V11', V12', V13', V14') and conductive lines (M11, M124, M13).

[0311] In this example, vias (V11', V13') may be on a contact area (CR1), and vias (V12', V14') may be on a contact area (CR2). There may be an electrical area (VR) between vias (V11', V13') and vias (V12', V14').

[0312] The conductive line (M11) may be the first output terminal of the integrated cell (107b). The conductive line (M13) may be the second output terminal of the integrated cell (107b).

[0313] The conductive line (M124) can be extended in the X direction. The conductive line (M124) can be in contact with the conductive layer (VC) of each via (V12'). The conductive line (M124) can be in contact with the conductive layer (VC) of each via (V14'). The layer (120L) can be connected to the second layer (150L) through the vias (V12'), the conductive line (M124), and the vias (V14').

[0314] According to exemplary embodiments, when the second layer (150L) and the substrate (110) are of type p and the first layer (140L) and the layer (120L) are of type n, the cell composed of the substrate (110) and the layer (120L) can be connected in series with the cell composed of the first layer (140L) and the second layer (150L).

[0315] According to exemplary embodiments, the integrated cell (107b) can achieve serial connection through a single via layer and a single wiring layer by separating the contact region (CR1) and the contact region (CR2), thereby increasing the integration density of the integrated cell (107b). Additionally, by providing vias (V11', V12', V13', V14') including a passivation layer (CI), the throughput of manufacturing the integrated cell (107b) can be increased and manufacturing costs can be reduced.

[0316]

[0317] (20th Example)

[0318] FIG. 44 is a cross-sectional view of an integrated cell (107c) according to exemplary embodiments.

[0319] Referring to FIG. 44, the integrated cell (107c) may include a substrate (110), a layer (120L), an energy source layer (130L), a first layer (140L), a second layer (150L), insulating layers (IL1, IL2), vias (V11', V12', V13', V14') and conductive lines (M114, M123).

[0320] The integrated cell (107c) is generally similar to the direct cell (107a) of FIG. 43, except for the connection and arrangement of vias (V11', V12', V13', V14') and conductive lines (M114, M123).

[0321] In this example, vias (V12', V13') may be on a contact area (CR1), and vias (V11', V14') may be on a contact area (CR2). There may be an electrical area (VR) between vias (V12', V13') and vias (V11', V14').

[0322] The conductive line (M114) can be extended in the X direction. The conductive line (M114) can be in contact with the conductive layer (VC) of each via (V11'). The conductive line (M114) can be in contact with the conductive layer (VC) of each via (V14'). The substrate (110) can be connected to the second layer (150L) through the vias (V11'), the conductive line (M114), and the vias (V14').

[0323] The conductive line (M123) can be extended in the X direction. The conductive line (M123) can be in contact with the conductive layer (VC) of each via (V12'). The conductive line (M123) can be in contact with the conductive layer (VC) of each via (V13'). The layer (120L) can be connected to the first layer (140L) through the vias (V12'), the conductive line (M123), and the vias (V13').

[0324] According to exemplary embodiments, when the second layer (150L) and the substrate (110) are of type p and the first layer (140L) and the layer (120L) are of type n, the cell composed of the substrate (110) and the layer (120L) can be connected in parallel with the cell composed of the first layer (140L) and the second layer (150L).

[0325] According to exemplary embodiments, the integrated cell (107c) can achieve parallel connection through a single via layer and a single wiring layer by separating the contact region (CR1) and the contact region (CR2), thereby increasing the integration density of the integrated cell (107c). Additionally, by providing vias (V11', V12', V13', V14') including a passivation layer (CI), the throughput of manufacturing the integrated cell (107c) can be increased and manufacturing costs can be reduced.

[0326]

[0327] (21st Example)

[0328] FIG. 45 is a cross-sectional view of an integrated cell (107d) according to exemplary embodiments.

[0329] Referring to FIG. 45, the integrated cell (107d) may include a substrate (110), a layer (120L), an energy source layer (130L), a first layer (140L), a second layer (150L), insulating layers (IL1, IL2), vias (V11', V12', V13', V14'), conductive lines (M11, M124, M13), an intermediate insulating layer (ILI), intermediate vias (VIL), a third layer (210L), a fourth layer (220L), an energy source layer (230L), a fifth layer (240L), a sixth layer (250L), insulating layers (IL5, IL6), vias (V31', V32', V33', V34') and conductive lines (M31, M324, M33).

[0330] The substrate (110), layer (120L), energy source layer (130L), first layer (140L), second layer (150L), insulating layers (IL1, IL2), vias (V11', V12', V13', V14'), and conductive lines (M11, M124, M13) are generally similar to those described in relation to the integrated cell (107b) of FIG. 43.

[0331] The structure and shape of the third layer (210L) are generally similar to the structure and shape of the substrate (110). The third layer (210L) may include one or more of the materials exemplified in relation to the second layer (150L).

[0332] The structure and shape of the fourth layer (220L) are generally similar to the structure and shape of the layer (120L). The fourth layer (220L) may include one or more of the materials exemplified in relation to the first layer (140L).

[0333] The structure, shape, and composition of the energy source layer (230L) are generally similar to the structure, shape, and composition of the energy source layer (130L). The structure, shape, and composition of the fifth layer (240L) are generally similar to the structure, shape, and composition of the first layer (140L). The structure, shape, and composition of the sixth layer (250L) are generally similar to the structure, shape, and composition of the second layer (150L).

[0334] An intermediate insulating layer (ILI) may be located between the third layer (210L) and the insulating layer (IL2). The intermediate insulating layer (ILI) may include the materials exemplified in relation to the insulating layers (IL1, IL2).

[0335] Intermediate vias (VIL) can penetrate the intermediate insulating layer (ILI). Each intermediate via (VIL) can land on a conductive line (M13). Each intermediate via (VIL) can be in contact with the conductive line (M13). Each intermediate via (VIL) can be in contact with the third layer (210L). A cell composed of the third layer (210L) and the fourth layer (220L) can be connected in series with a cell composed of the first layer (140L) and the second layer (150L) by the intermediate vias (VIL).

[0336] The structure, shape, and composition of the insulating layers (IL5, IL6) are generally similar to the structure, shape, and composition of the insulating layers (IL1, IL2).

[0337] Each of the vias (V31', V32', V33', V34') may include a passivation layer (VI) and a conductive layer (VC). The vias (V31', V33') may be on a contact region (CR1), and the vias (V32', V34') may be on a contact region (CR2). There may be an electrical region (VR) between the vias (V31', V33') and the vias (V32', V34').

[0338] Each of the vias (V31') can penetrate the intermediate insulating layer (ILI), the third layer (210L), the fourth layer (220L), the energy source layer (230L), the fifth layer (240L), the sixth layer (250L), and the insulating layer (IL5). Each of the conductive layers (VC) of the vias (V31') can be spaced apart from the third layer (210L), the fourth layer (220L), the energy source layer (230L), the fifth layer (240L), and the sixth layer (250L) with a passivation layer (VI) in between.

[0339] Each of the vias (V31') can be landed on a conductive line (M11). The conductive layer (VC) of each via (V31') can be in contact with the conductive line (M11). Each of the vias (V12') can be configured to be electrically connected to the conductive line (M11), which is the landed layer.

[0340] The conductive line (M31) may be extended in the X direction. The conductive line (M31) may be in contact with the conductive layer (VC) of each via (V31'). The conductive line (M31) may be the first output terminal of the integrated cell (107d).

[0341] Each of the vias (V32') can penetrate the energy source layer (230L), the fifth layer (240L), the sixth layer (250L), and the insulating layer (IL5). Each of the conductive layers (VC) of the vias (V32') can be spaced apart from the energy source layer (230L), the fifth layer (240L), and the sixth layer (250L) with a passivation layer (VI) in between.

[0342] Each of the vias (V32') can be landed on the fourth layer (220L). The conductive layer (VC) of each via (V32') can be in contact with the fourth layer (220L). The conductive layer (VC) of each via (V32') can be configured to be electrically connected to the fourth layer (220L).

[0343] Each of the vias (V33') can penetrate the sixth layer (250L) and the insulating layer (IL5). Each of the conductive layers (VC) of the vias (V32') can be spaced apart from the sixth layer (250L) with a passivation layer (VI) in between.

[0344] Each of the vias (V33') can be landed on the fifth layer (240L). The conductive layer (VC) of each via (V33') can be in contact with the fifth layer (240L). The conductive layer (VC) of each via (V33') can be configured to be electrically connected to the fifth layer (240L).

[0345] The conductive line (M33) may be extended in the X direction. The conductive line (M33) may be in contact with the conductive layer (VC) of each via (V33'). The conductive line (M33) may be a second output terminal of the integrated cell (107d).

[0346] Each of the vias (V34') can penetrate the insulating layer (IL5). Each of the vias (V34') can be landed on the sixth layer (250L). The conductive layer (VC) of each of the vias (V34') can be in contact with the sixth layer (250L). The conductive layer (VC) of each of the vias (V34') can be configured to be electrically connected to the sixth layer (250L).

[0347] The conductive line (M324) can be extended in the X direction. The conductive line (M324) can be in contact with the conductive layer (VC) of each via (V32'). The conductive line (M324) can be in contact with the conductive layer (VC) of each via (V34'). The fourth layer (220L) can be connected to the sixth layer (250L) through the vias (V12'), the conductive line (M124), and the vias (V14').

[0348] According to exemplary embodiments, when the third layer (210L) and the sixth layer (250L) are of the p type and the fourth layer (220L) and the fifth layer (240L) are of the n type, the cell composed of the third layer (210L) and the fourth layer (220L) can be connected in series with the cell composed of the fifth layer (240L) and the sixth layer (250L). The integrated cell (107d) according to exemplary embodiments includes a structure in which four layers of pn junctions are connected in series, and thus can have high integration density and output.

[0349] (Examples 22 and 23)

[0350] FIG. 46 is a flowchart illustrating a method for manufacturing different integrated cells in other exemplary embodiments.

[0351] FIGS. 47 to 53 are cross-sectional views illustrating a method for manufacturing other integrated cells in other exemplary embodiments.

[0352] Referring to FIGS. 46 and 47, providing a substrate (110) at P110, patterning the substrate (110) at P120, and forming a layer (120L) at P130 are generally similar to those described with reference to FIGS. 1 to 7.

[0353] Next, in P141, a first scintillation layer (160L) can be formed. The first scintillation layer (160L) can be formed by a deposition process such as CVD. The first scintillation layer (160L) can have a uniform thickness. The first scintillation layer (160L) can have a conformal shape. The first scintillation layer (160L) can be configured to emit photons in response to high-energy radiation such as alpha rays. The first scintillation layer (160L) may include, but is not limited to, one or more of Ba2Ca(BO3)2, BaHfO3, BaI2:Ce, BeO, BaF2, BaMgF4, Cs2LiLuCi6:Ce, K2YF5, KCaF3, and YI3:Ce. Various examples of the first scintillator layer (160L) are disclosed at https: / scintillator.lbl.gov / inorganic-scintillator-library / .

[0354]

[0355] Next, referring to FIGS. 46 and FIGS. 48, an energy source layer (170L) can be formed at P143. The energy source layer (170L) may have a uniform thickness. The energy source layer (170L) may have a conformal shape. The energy source layer (170L) may be formed by any one of the methods of evaporation, sputtering, CVD, electroplating, and electroless plating. If the energy source layer (170L) is formed by electroplating or electroless plating, a seed layer may be formed between the energy source layer (170L) and the first scintillation layer (160L).

[0356] The energy source layer (170L) may contain a radioisotope that emits only alpha rays, or emits additional radiation other than alpha rays, such as beta rays or gamma rays. The energy source layer (170L) is neodymium-144 ( 144 Nd), Samarium-147 ( 147 Sm), terbium-158( 158 Tb), Tellurium-104( 104 Te), Bismuth-212( 212 Bi), astatin-210( 210 At), astatin-211( 211 At), Radon-222( 222 Rn), Francium-223( 223 Fr), Radium-224 ( 224 Ra), Radium-226 ( 226 Ra), Actinium-225( 225 Ac), Actinium-227 ( 227 Ac), Thorium-228( 228 Th), Thorium-230( 230 Th), Thorium-232( 232 Th), Protactinium-231( 231 Pa), Uranium-234( 234 U), Uranium-235( 235 U), Uranium-238( 238 U), Neptunium-237( 237 Np), Plutonium-238( 238 Pu), Plutonium-239( 239 Pu), Plutonium-240( 240 Pu), Plutonium-241( 241 Pu), Americium-241( 241 Am), Americium-243( 243 Am), Curium-242( 242 Cm), Curium-243( 243 Cm), Curium-244( 244 Cm), Curium-245( 245 Cm), Berkelium-247( 247 Bk), Berkelium-249( 249 Bk), Californium-249( 249Cf), Californium-250( 250 Cf), Californium-251( 251 Cf), Californium-252( 252 Cf), Einsteinium-252( 252 Es), Einsteinium-253( 253 Es), Fermium-257( 257 Fm), Mendelevium-258( 258 Md), Nobelium-255( 255 No), Lawrencium-260( 260 Lr), polonium-208( 208 Po), Polonium-210( 210 Po) and polonium-212 ( 212 It may include one or more of Po).

[0357]

[0358] Next, referring to FIGS. 46 and 49, a second scintillation layer (180L) can be formed at P145. The second scintillation layer (180L) can be formed by a deposition process such as CVD. The second scintillation layer (180L) can have a uniform thickness. The second scintillation layer (180L) can have a conformal shape. The second scintillation layer (180L) can be configured to emit photons in response to high-energy radiation. The second scintillation layer (180L) may include the materials exemplified in relation to the first scintillation layer (160L).

[0359]

[0360] Next, referring to FIGS. 46 and FIGS. 50, a first layer (140L) can be formed in P150. The formation of the first layer (140L) is as described with reference to FIGS. 1, FIGS. 10 and FIGS. 11.

[0361]

[0362] Next, referring to FIGS. 46 and FIGS. 51, a second layer (150L) can be formed in P160. The formation of the second layer (150L) is as described with reference to FIGS. 1, FIGS. 12 and FIGS. 13.

[0363]

[0364] Next, referring to FIGS. 46, 51, and 52, a first CMP process can be performed at P170. By the first CMP process, a layer (120L) can be separated into a plurality of patterns (120). By the first CMP process, a first scintillation layer (160L) can be separated into a plurality of first scintillation patterns (160). By the first CMP process, an energy source layer (170L) can be separated into a plurality of energy source patterns (170). By the first CMP process, a second scintillation layer (180L) can be separated into a plurality of second scintillation patterns (180). By the first CMP process, a first layer (140L) can be separated into a plurality of first patterns (140). By the first CMP process, a second layer (150L) can be separated into a plurality of second patterns (150).

[0365] Each upper surface of a plurality of patterns (120), each upper surface of a plurality of first flash patterns (160), each upper surface of a plurality of energy source patterns (170), each upper surface of a plurality of second flash patterns (180), each upper surface of a plurality of first patterns (140) and each upper surface of a plurality of second patterns (150) can form a co-surface with the upper surface (110U) of the substrate (110).

[0366]

[0367] Next, referring to FIGS. 46, 52 and 53, a second CMP process can be performed at P180. A plurality of second patterns (150) may be the endpoints of the second CMP process. By the second CMP process, an integrated cell (108) comprising a substrate (110), a plurality of patterns (120), a plurality of first scintillation patterns (160), a plurality of energy source patterns (170), a plurality of second scintillation patterns (180), a plurality of first patterns (140) and a plurality of second patterns (150) may be provided.

[0368] By processing P180, multiple recesses (110R) can become multiple holes (110H) that extend to a new lower surface (110L') of the substrate (110). Each of the multiple holes (110H) can penetrate the substrate (110). The lower surface of each of the multiple patterns (120), the lower surface of each of the multiple first flash patterns (160), the lower surface of each of the multiple energy source patterns (170), the lower surface of each of the multiple second flash patterns (180), the lower surface of each of the multiple first patterns (140), and the lower surface of each of the multiple second patterns (150) can form a co-plane with the lower surface (110L') of the substrate (110).

[0369] Each of the plurality of first flash patterns (160) may be within a corresponding of the plurality of holes (110H). Each of the plurality of first flash patterns (160) may be between a corresponding of the plurality of patterns (120) and a corresponding of the plurality of energy source patterns (170). The thickness of each of the plurality of first flash patterns (160) may be uniform. Each of the plurality of first flash patterns (160) may be surrounded by a corresponding of the plurality of patterns (120).

[0370] Each of the plurality of energy source patterns (170) may be located within a corresponding of the plurality of holes (110H). Each of the plurality of energy source patterns (170) may be located between a corresponding of the plurality of first flash patterns (160) and a corresponding of the plurality of second flash patterns (180). The thickness of each of the plurality of energy source patterns (170) may be uniform. Each of the plurality of energy source patterns (170) may be surrounded by a corresponding of the plurality of first flash patterns (160).

[0371] Each of the plurality of second flash patterns (180) may be within a corresponding of the plurality of holes (110H). Each of the plurality of second flash patterns (180) may be between a corresponding of the plurality of energy source patterns (170) and a corresponding of the plurality of first patterns (140). The thickness of each of the plurality of second flash patterns (180) may be uniform. Each of the plurality of second flash patterns (180) may be surrounded by a corresponding of the plurality of energy source patterns (170).

[0372] Each of the plurality of first patterns (140) may be between a corresponding of the plurality of second flash patterns (180) and a corresponding of the plurality of second patterns (150). Each of the plurality of first patterns (140) may be surrounded by a corresponding of the plurality of second flash patterns (180).

[0373] Each of the plurality of energy source patterns (170) may be configured to emit alpha rays. The plurality of first scintillation patterns (160) and the plurality of second scintillation patterns (180) irradiated by alpha rays may be configured to emit photons.

[0374] The depletion region between the substrate (110) and the plurality of patterns (120), irradiated by photons emitted from the plurality of first scintillation patterns (160), may be configured to generate an electromotive force by electron-hole pair production. The depletion region between the plurality of first patterns (140) and the plurality of second patterns (150), irradiated by photons emitted from the plurality of second scintillation patterns (180), may be configured to generate an electromotive force by electron-hole pair production.

[0375]

[0376] The present invention has been described in more detail above through drawings and embodiments. However, the configurations described in the drawings or embodiments described in this specification are merely one embodiment of the present invention and do not represent all technical concepts of the present invention; therefore, it should be understood that various equivalents and modifications that can replace them may exist at the time of filing this application.

Claims

1. A material including multiple holes; A plurality of patterns located within the plurality of holes of the above description and having a polarity opposite to that of the above description; A plurality of energy source patterns configured to irradiate beta rays onto the above-mentioned description and a plurality of the above-mentioned patterns; A plurality of first patterns surrounded by the plurality of energy source patterns; and An integrated battery comprising a plurality of second patterns surrounded by the plurality of first patterns.

2. In Paragraph 1, An integrated cell characterized in that each of the plurality of energy source patterns is interposed between a corresponding one of the plurality of first patterns and a corresponding one of the plurality of patterns.

3. In Paragraph 1, The conductivity type of each of the plurality of first patterns above is the same as the conductivity type described above, and An integrated battery characterized in that the conductivity type of each of the plurality of second patterns is the same as the conductivity type of each of the plurality of patterns.

4. In Paragraph 1, The conductivity type of each of the plurality of first patterns is the same as the conductivity type of each of the plurality of patterns, and An integrated battery characterized in that the conductivity type of each of the plurality of second patterns is the same as the conductivity type of the above-described above.

5. In Paragraph 1, An integrated battery characterized in that the lower surface of each of the plurality of patterns, the lower surface of each of the plurality of energy source patterns, the lower surface of each of the plurality of first patterns, and the lower surface of each of the plurality of second patterns form a co-plane with the lower surface of the substrate.

6. In Paragraph 1, The lower surface of each of the plurality of patterns, the lower surface of each of the plurality of energy source patterns, and the lower surface of each of the plurality of first patterns form a co-plane with the lower surface of the above-described material, and An integrated battery characterized in that each of the above plurality of first patterns has a cup shape.

7. In Paragraph 1, The lower surface of each of the plurality of energy source patterns and the lower surface of each of the plurality of patterns form a co-plane with the lower surface of the above-described material, and An integrated cell characterized in that each of the above plurality of energy source patterns has a cup shape.

8. In Paragraph 1, The lower surface of each of the above plurality of patterns forms a co-surface with the lower surface of the above description, and An integrated battery characterized in that each of the above plurality of patterns has a cup shape.

9. A material including multiple holes; A plurality of patterns located within the plurality of holes of the above description and having a polarity opposite to that of the above description; Multiple energy source patterns within the aforementioned plurality of holes; A plurality of first patterns within the plurality of holes and spaced apart from the plurality of patterns; and An integrated cell comprising a plurality of second patterns within the plurality of holes.

10. In Paragraph 9, An integrated cell characterized in that each of the plurality of energy source patterns is surrounded by a corresponding one of the plurality of patterns.

11. In Paragraph 9, An integrated cell characterized in that each of the plurality of first patterns is surrounded by a corresponding one of the plurality of energy source patterns.

12. In Paragraph 9, An integrated battery characterized in that each of the plurality of second patterns is surrounded by a corresponding one of the plurality of first patterns.

13. A record including multiple recesses; Layer on the above description; Energy source layer on the above layer; A first layer on the energy source layer above; and An integrated battery comprising a second layer on the first layer.

14. In Paragraph 13, The above layer has a conductivity type opposite to that of the above material, and An integrated battery characterized in that the first layer has a conductivity type opposite to that of the second layer.

15. In Paragraph 13, The conductivity type of the first layer above is the same as the conductivity type of the above description, and An integrated battery characterized in that the conductivity type of the second layer is the same as the conductivity type of the layer.

16. In Paragraph 13, The conductivity type of the first layer above is the same as the conductivity type of the layer above, and An integrated battery characterized in that the conductivity type of the second layer above is the same as the conductivity type of the above-described material.

17. In Paragraph 13, The above description includes an electrical region having the plurality of recesses and a contact region spaced apart from the plurality of recesses, and An integrated battery characterized in that the substrate, the layer, the energy source layer, the first layer, and the second layer on the contact region constitute a stepped structure.

18. In Paragraph 17, An integrated battery characterized in that the substrate in the above contact area protrudes further horizontally relative to the above layer.

19. In Paragraph 17, An integrated battery characterized in that the layer protrudes further horizontally with respect to the first layer in the contact area.

20. In Paragraph 17, An integrated battery characterized in that the first layer protrudes further horizontally with respect to the second layer in the contact area.

21. In Paragraph 13, An integrated battery characterized in that a first cell composed of the above-described material and the above-described layer is connected in series with a second cell composed of the above-described first layer and the above-described second layer.

22. In Paragraph 13, An integrated cell characterized in that a first cell composed of the above-described material and the above-described layer is connected in parallel with a second cell composed of the above-described first layer and the above-described second layer.

23. In Paragraph 13, A first via landed on the above description; A second via landed on the above layer; A third via landed on the first layer above; and An integrated cell further comprising a fourth via landed on the second layer.

24. In Paragraph 23, An integrated cell characterized in that each of the first to fourth vias comprises a passivation layer and a conductive layer surrounded by said passivation layer.

25. In Paragraph 24, An integrated cell characterized in that the first via penetrates the layer, the first layer, and the second layer.

26. In Paragraph 24, An integrated cell characterized in that the second via penetrates the first layer and the second layer.

27. In Paragraph 24, An integrated cell characterized in that the third via penetrates the second layer.

28. In Paragraph 23, The above description includes an electric region having the plurality of recesses, a first contact region and a second contact region spaced apart from the electric region, and The first via and the third via are on the first contact region, and An integrated cell characterized in that the second via and the fourth via are located on the second contact region.

29. In Paragraph 28, An integrated cell further comprising a conductive line connected to each of the second via and the fourth via.

30. In Paragraph 23, The above description includes an electric region having the plurality of recesses, a first contact region and a second contact region spaced apart from the electric region, and The second via and the third via are on the first contact region, and An integrated cell characterized in that the first via and the fourth via are located on the second contact region.

31. In Paragraph 23, A first conductive line connected to each of the second via and the third via; and An integrated cell further comprising a second conductive line connected to each of the first via and the fourth via.

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