Integrated cell and manufacturing method therefor

Abstract

According to exemplary embodiments, an integrated cell is provided. The integrated cell includes a beta-ray source layer, and a first radiovoltaic structure and a second radiovoltaic structure on the beta-ray source layer, wherein the first radiovoltaic structure and the second radiovoltaic structure respectively include a first semiconductor layer on the beta-ray source layer and a second semiconductor layer on the first semiconductor layer.

Description

Integrated battery and method of manufacturing the same

[0001] The present invention relates to an integrated battery and a method for manufacturing the same. The present application claims the benefit of Korean application No. 10-2024-0128728, filed on September 24, 2024, which is incorporated herein by reference in its entirety.

[0002] A beta battery (or beta radioactive battery) is a type of radioactive battery that produces electricity using the beta decay of radioactive isotopes. This battery generates power primarily by using semiconductor materials and radioactive isotopes that emit beta rays. Beta batteries operate by directly converting the energy released during the radioactive decay process into electrical energy.

[0003] Beta batteries have a very long lifespan because they can continuously produce energy over the half-life of a radioactive isotope. In addition, they can supply a constant power regardless of the environment, allowing for stable use even in extreme conditions.

[0004] The problem that the technical concept of the present invention aims to solve is to provide an integrated battery and a method for manufacturing the same.

[0005] According to exemplary embodiments of the present invention for solving the above-described problem, a direct cell is provided. The integrated cell comprises a beta ray source layer; and a first radiovoltaic structure and a second radiovoltaic structure on the beta ray source layer, wherein each of the first radiovoltaic structure and the second radiovoltaic structure comprises a first semiconductor layer on the beta ray source layer and a second semiconductor layer on the first semiconductor layer.

[0006] The above beta ray source layer has a flat shape.

[0007] The first radiation structure and the second radiation structure are connected in parallel with each other.

[0008] The integrated cell further includes a first conductive pattern that overlaps with the second semiconductor layer of each of the first radiation field structure and the second radiation field structure.

[0009] The integrated cell further includes a second conductive pattern that overlaps with the first semiconductor layer of each of the first radiation structure and the second radiation structure.

[0010] The above first and second radiation structures are connected in series with each other.

[0011] The integrated cell further includes a third conductive pattern that overlaps the first semiconductor layer of the first radiation structure and the second semiconductor layer of the second radiation structure.

[0012] According to exemplary embodiments, an integrated cell is provided. The integrated cell comprises a planar beta-ray source layer; and a first radiative structure, a second radiative structure, a third radiative structure, and a fourth radiative structure on a first surface of the beta-ray source layer, wherein the first radiative structure, the second radiative structure, the third radiative structure, and the fourth radiative structure are arranged in a matrix, and each of the first radiative structure, the second radiative structure, the third radiative structure, and the fourth radiative structure comprises a first semiconductor layer and a second semiconductor layer on the first semiconductor layer.

[0013] The first radiation structure is superimposed with the second radiation structure in a first direction parallel to the first surface, the third radiation structure is superimposed with the fourth radiation structure in the first direction, the first radiation structure is superimposed with the third radiation structure in a second direction parallel to the first surface of the beta ray source layer and perpendicular to the first direction, and the second radiation structure is superimposed with the fourth radiation structure in the second direction.

[0014] The above-mentioned first radiation structure is connected in series with the above-mentioned second radiation structure.

[0015] The above third radiation structure is connected in series with the above fourth radiation structure.

[0016] The above-mentioned first radiation structure is connected in parallel with the above-mentioned third radiation structure.

[0017] The above second radiation structure is connected in parallel with the above fourth radiation structure.

[0018] The integrated cell further includes a first conductive pattern that overlaps each of the second semiconductor layer of the first radiation structure and the second semiconductor layer of the third radiation structure in a third direction perpendicular to the first surface.

[0019] The integrated cell further includes a second conductive pattern that overlaps in the third direction with each of the first semiconductor layer of the second radiation structure and the first semiconductor layer of the fourth radiation structure.

[0020] The integrated cell further includes a third conductive pattern that overlaps in the third direction with each of the first semiconductor layer of the first radiation structure, the first semiconductor layer of the third radiation structure, the second semiconductor layer of the second radiation structure, and the second semiconductor layer of the fourth radiation structure.

[0021] The above third challenge pattern is between the above first challenge pattern and the above second challenge pattern.

[0022] According to exemplary embodiments, an integrated cell is provided. The integrated cell comprises: a beta ray source layer configured to emit beta rays; a first cell layer on a first surface of the beta ray source layer; and a second cell layer on a second surface of the beta ray source layer, wherein the first cell layer comprises a first radiation preform and a second radiation preform, the second cell layer comprises a third radiation preform and a fourth radiation preform, and the beta ray source layer has a planar shape.

[0023] Each of the above first radiation preform, the above second radiation preform, the above third radiation preform, and the above fourth radiation preform includes a first semiconductor layer and a second semiconductor layer on the first semiconductor layer.

[0024] The first radiation structure is connected in series with the second radiation structure, and the third radiation structure is connected in series with the fourth radiation structure.

[0025] The first radiation structure is connected in parallel with the second radiation structure, and the third radiation structure is connected in parallel with the fourth radiation structure.

[0026] According to exemplary embodiments of the present invention, a plurality of radiation structures formed within the first and second cell layers can be connected in series and in parallel, thereby providing an integrated cell having desired electrical performance (i.e., voltage and current performance) with a relatively simple manufacturing process.

[0027] According to exemplary embodiments, by forming a flat beta-ray source layer, the amount of beta-ray source material wasted in manufacturing processes such as planarization can be reduced or minimized, thereby reducing the manufacturing cost of the integrated cell.

[0028] In addition, by forming first and second cell layers on both sides based on a single beta ray source layer, the utilization rate of beta rays emitted from the beta ray source layer can be improved.

[0029] The effects obtainable from the exemplary embodiments of the present invention are not limited to those mentioned above, and other unmentioned effects can be clearly derived and understood by those skilled in the art to which the exemplary embodiments of the present disclosure belong from the following description. That is, unintended effects resulting from the implementation of the exemplary embodiments of the present disclosure can also be derived by those skilled in the art from the exemplary embodiments of the present disclosure.

[0030] Figure 1 is a flowchart illustrating a method for manufacturing an integrated battery.

[0031] FIG. 2 is a plan view illustrating a method for manufacturing an integrated cell according to exemplary embodiments.

[0032] Figure 3 is a cross-sectional view taken along the cutting line 2A-2A' of Figure 2.

[0033] FIG. 4 is a plan view illustrating a method for manufacturing an integrated cell according to exemplary embodiments.

[0034] Figure 5 is a cross-sectional view taken along the cutting line 4A-4A' of Figure 4.

[0035] Figure 6 is a cross-sectional view taken along the cutting line 4B-4B' of Figure 4.

[0036] Figure 7 is a cross-sectional view taken along the cutting line 4C-4C' of Figure 4.

[0037] FIG. 8 is a plan view illustrating a method for manufacturing an integrated cell according to exemplary embodiments.

[0038] FIG. 9 is a cross-sectional view taken along the cutting line 8A-8A' of FIG. 8.

[0039] FIG. 10 is a cross-sectional view taken along the cutting line 8B-8B' of FIG. 8.

[0040] FIG. 11 is a cross-sectional view taken along the cutting line 8C-8C' of FIG. 8.

[0041] FIG. 12 is a plan view illustrating a method for manufacturing an integrated cell according to exemplary embodiments.

[0042] FIG. 13 is a cross-sectional view taken along the cutting line 12A-12A' of FIG. 12.

[0043] FIG. 14 is a cross-sectional view taken along the cutting line 12B-12B' of FIG. 12.

[0044] FIG. 15 is a cross-sectional view taken along the cutting line 12C-12C' of FIG. 12.

[0045] FIG. 16 is a plan view illustrating a method for manufacturing an integrated cell according to exemplary embodiments.

[0046] FIG. 17 is a cross-sectional view taken along the cutting line 16A-16A' of FIG. 16.

[0047] FIG. 18 is a cross-sectional view taken along the cutting line 16B-16B' of FIG. 16.

[0048] FIG. 19 is a cross-sectional view taken along the cutting line 16C-16C' of FIG. 16.

[0049] FIG. 20 is a plan view illustrating a method for manufacturing an integrated cell according to exemplary embodiments.

[0050] FIG. 21 is a cross-sectional view taken along the cutting line 20A-20A' of FIG. 20.

[0051] FIG. 22 is a cross-sectional view taken along the cutting line 20B-20B' of FIG. 20.

[0052] FIG. 23 is a cross-sectional view taken along the cutting line 20C-20C' of FIG. 20.

[0053] FIGS. 24 to 29 are cross-sectional views illustrating a method for manufacturing a secondary battery according to exemplary embodiments.

[0054] FIG. 30 is a circuit diagram showing an integrated cell according to exemplary embodiments.

[0055] FIGS. 31 to 33 are cross-sectional views showing integrated cells according to other exemplary embodiments.

[0056] Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the attached drawings. Prior to this, terms and words used in this specification and claims should not be interpreted as being limited to their ordinary or dictionary meanings. Instead, based on the principle that the inventor can appropriately define the concepts of terms to best describe his invention, they should be interpreted in a meaning and concept consistent with the technical spirit of the present invention.

[0057] Therefore, the embodiments described in this specification and the configurations illustrated in the drawings are merely the most preferred embodiments of the present invention and do not represent all of the technical ideas of the present invention; thus, it should be understood that various equivalents and modifications that can replace them may exist at the time of filing this application.

[0058] In addition, in describing the present invention, if it is determined that a detailed description of related known components or functions may obscure the essence of the invention, such detailed description is omitted.

[0059] Since embodiments of the present invention are provided to more fully explain the invention to those skilled in the art, the shapes and sizes of the components in the drawings may be exaggerated, omitted, or schematically depicted for clearer explanation. Accordingly, the size or proportion of each component does not entirely reflect the actual size or proportion.

[0060]

[0061] (1st and 2nd embodiments)

[0062] Figure 1 is a flowchart illustrating a method for manufacturing an integrated battery.

[0063] FIG. 2 is a plan view illustrating a method for manufacturing an integrated cell according to exemplary embodiments.

[0064] Figure 3 is a cross-sectional view taken along the cutting line 2A-2A' of Figure 2.

[0065] FIG. 4 is a plan view illustrating a method for manufacturing an integrated cell according to exemplary embodiments.

[0066] Figure 5 is a cross-sectional view taken along the cutting line 4A-4A' of Figure 4.

[0067] Figure 6 is a cross-sectional view taken along the cutting line 4B-4B' of Figure 4.

[0068] Figure 7 is a cross-sectional view taken along the cutting line 4C-4C' of Figure 4.

[0069] FIG. 8 is a plan view illustrating a method for manufacturing an integrated cell according to exemplary embodiments.

[0070] FIG. 9 is a cross-sectional view taken along the cutting line 8A-8A' of FIG. 8.

[0071] FIG. 10 is a cross-sectional view taken along the cutting line 8B-8B' of FIG. 8.

[0072] FIG. 11 is a cross-sectional view taken along the cutting line 8C-8C' of FIG. 8.

[0073] FIG. 12 is a plan view illustrating a method for manufacturing an integrated cell according to exemplary embodiments.

[0074] FIG. 13 is a cross-sectional view taken along the cutting line 12A-12A' of FIG. 12.

[0075] FIG. 14 is a cross-sectional view taken along the cutting line 12B-12B' of FIG. 12.

[0076] FIG. 15 is a cross-sectional view taken along the cutting line 12C-12C' of FIG. 12.

[0077] FIG. 16 is a plan view illustrating a method for manufacturing an integrated cell according to exemplary embodiments.

[0078] FIG. 17 is a cross-sectional view taken along the cutting line 16A-16A' of FIG. 16.

[0079] FIG. 18 is a cross-sectional view taken along the cutting line 16B-16B' of FIG. 16.

[0080] FIG. 19 is a cross-sectional view taken along the cutting line 16C-16C' of FIG. 16.

[0081] FIG. 20 is a plan view illustrating a method for manufacturing an integrated cell according to exemplary embodiments.

[0082] FIG. 21 is a cross-sectional view taken along the cutting line 20A-20A' of FIG. 20.

[0083] FIG. 22 is a cross-sectional view taken along the cutting line 20B-20B' of FIG. 20.

[0084] FIG. 23 is a cross-sectional view taken along the cutting line 20C-20C' of FIG. 20.

[0085] FIGS. 24 to 29 are cross-sectional views illustrating a method for manufacturing a secondary battery according to exemplary embodiments.

[0086] FIG. 30 is a circuit diagram showing an integrated cell according to exemplary embodiments.

[0087]

[0088] Referring to FIGS. 1 to 3, in P110, a first semiconductor layer (120L), an active layer (130L), and a second semiconductor layer (140L) can be formed on a substrate (110).

[0089] The substrate (110) may be a growth substrate for the first semiconductor layer (120L), the active layer (130L), and the second semiconductor layer (140L). The substrate (110) may be one of a sapphire substrate, a Si substrate, a SiC substrate, an MgAl2O4 substrate, an MgO substrate, a LiAlO2 substrate, a LiGaO2 substrate, a GaN substrate, a Sm2O3 / Bi2O3 / GeO2 substrate, a Sm2O3 / Bi2O3 / B2O3 substrate, and a Sm2O3 / Bi2O3 / GeO2 / B2O3 substrate.

[0090] Two directions that are parallel to and intersect each other on the upper surface of the substrate (110) are defined as the X direction and the Y direction, respectively, and a direction substantially perpendicular to the upper surface of the substrate (110) is defined as the Z direction. The X direction, the Y direction, and the Z direction may be substantially perpendicular to each other. The definitions of the directions described above are the same in all subsequent drawings.

[0091] The first semiconductor layer (120L), the active layer (130L), and the second semiconductor layer (140L) may be formed by any one of Metal Organic Chemical Vapor Deposition (MOCVD), Hydrode Vapor Phase Epitaxy (HVPE), and Molecular Beam Epitaxy (MBE). The first semiconductor layer (120L) may be on a substrate (110). The second semiconductor layer (140) may be on the first semiconductor layer (120L). The active layer (130L) may be between the first semiconductor layer (120L) and the second semiconductor layer (140L).

[0092] The first semiconductor layer (120L) and the second semiconductor layer (140L) may have opposite conductivity types. For example, if the first semiconductor layer (120L) is doped with a p-type dopant, the second semiconductor layer (140L) may be doped with an n-type dopant. For example, if the first semiconductor layer (120L) is doped with an n-type dopant, the second semiconductor layer (140L) may be doped with a p-type dopant.

[0093] For example, the first semiconductor layer (120L) and the active layer (130L) may be intrinsic semiconductor layers. The active layer (130L) may be omitted. If the active layer (130L) is omitted, the first semiconductor layer (120L) and the second semiconductor layer (140L) may come into contact with each other.

[0094] According to exemplary embodiments, the first semiconductor layer (120L) comprises silicon (Si) doped with boron (B) and the second semiconductor layer (140L) may comprise silicon (Si) doped with either phosphorus (P) or arsenic (As).

[0095] According to exemplary embodiments, the first semiconductor layer (120L) may comprise silicon (Si) doped with either phosphorus (P) or arsenic (As), and the second semiconductor layer (140L) may comprise silicon (Si) doped with boron (B).

[0096] According to exemplary embodiments, the first semiconductor layer (120L) may comprise gallium arsenide (GaAs) doped with zinc (Zn) and the second semiconductor layer (140L) may comprise gallium arsenide (GaAs) doped with either silicon (Si) or tellurium (Te).

[0097] According to exemplary embodiments, the first semiconductor layer (120L) may comprise gallium arsenide (GaAs) doped with either silicon (Si) or tellurium (Te), and the second semiconductor layer (140L) may comprise gallium arsenide (GaAs) doped with zinc (Zn).

[0098] According to exemplary embodiments, the first semiconductor layer (120L) may comprise germanium (Ge) doped with boron (B) and the second semiconductor layer (140L) may comprise germanium (Ge) doped with either phosphorus (P) or antimony (Sb).

[0099] According to exemplary embodiments, the first semiconductor layer (120L) may comprise germanium (Ge) doped with either phosphorus (P) or antimony (Sb), and the second semiconductor layer (140L) may comprise germanium (Ge) doped with boron (B).

[0100] According to exemplary embodiments, the first semiconductor layer (120L) may comprise gallium nitride (GaN) doped with magnesium (Mg) and the second semiconductor layer (140L) may comprise gallium nitride (GaN) doped with silicon (Si).

[0101] According to exemplary embodiments, the first semiconductor layer (120L) may comprise gallium nitride (GaN) doped with silicon (Si) and the second semiconductor layer (140L) may comprise gallium nitride (GaN) doped with magnesium (Mg).

[0102] According to exemplary embodiments, the first semiconductor layer (120L) may comprise silicon carbide (SiC) doped with either aluminum (Al) or boron (B), and the second semiconductor layer (140L) may comprise silicon carbide (SiC) doped with either nitrogen (N) or phosphorus (P).

[0103] According to exemplary embodiments, the first semiconductor layer (120L) may comprise silicon carbide (SiC) doped with either nitrogen (N) or phosphorus (P), and the second semiconductor layer (140L) may comprise silicon carbide (SiC) doped with either aluminum (Al) or boron (B).

[0104] According to exemplary embodiments, the first semiconductor layer (120L) may comprise indium phosphate (InP) doped with zinc (Zn) and the second semiconductor layer (140L) may comprise indium phosphate (InP) doped with either sulfur (S) or silicon (Si).

[0105] According to exemplary embodiments, the first semiconductor layer (120L) may comprise indium phosphate (InP) doped with either sulfur (S) or silicon (Si), and the second semiconductor layer (140L) may comprise indium phosphate (InP) doped with zinc (Zn).

[0106] According to exemplary embodiments, the first semiconductor layer (120L) may comprise cadmium telluride (CdTe) and the second semiconductor layer (140L) may comprise cadmium sulfide (CdS).

[0107] According to exemplary embodiments, the first semiconductor layer (120L) may comprise cadmium sulfide (CdS) and the second semiconductor layer (140L) may comprise cadmium telluride (CdTe).

[0108] According to exemplary embodiments, the first semiconductor layer (120L) may comprise tin oxide (SnO) and the second semiconductor layer (140L) may comprise zinc oxide (ZnO).

[0109] According to exemplary embodiments, the first semiconductor layer (120L) may comprise zinc oxide (ZnO) and the second semiconductor layer (140L) may comprise tin oxide (SnO).

[0110]

[0111] Next, referring to FIGS. 1 through 7, the active layer (130L) and the second semiconductor layer (140L) can be etched in P120. The first semiconductor layer (120L) may be partially exposed by the etching of P120. For the etching of the active layer (130L) and the second semiconductor layer (140L), a mask pattern may be formed on the second semiconductor layer (140). The mask pattern may include an opening that exposes the portion of the active layer (130L) and the second semiconductor layer (140L) to be etched. The mask pattern may be a hard mask, but is not limited thereto. The active layer (130L) and the second semiconductor layer (140L) may be processed by either dry etching or wet etching.

[0112] The active layer (130L) can be separated into active layers (130) by etching P120. The second semiconductor layer (140L) can be separated into second semiconductor layers (140) by etching P120. The stacked structure of the separated active layers (130) and second semiconductor layers (140) can be referred to as a mesa, and the etching process of P120 can be referred to as a mesa etch.

[0113] In the etching of P120, the first semiconductor layer (120L) may be etched to a predetermined depth by over-etching, but is not limited thereto. In the etching of P120, the first semiconductor layer (120L) may not be etched, and only the upper surface of the first semiconductor layer (120L) may be partially exposed.

[0114]

[0115] Next, referring to FIGS. 1 and FIGS. 4 through 11, at P130, insulating material can be deposited and the insulating material and the first semiconductor layer (120L) can be etched so that a portion of the substrate (110) is exposed. The insulating material can be conformally deposited on the first semiconductor layer (120L), the active layers (130), and the second semiconductor layers (140).

[0116] By etching P130, the first semiconductor layer (120L) can be separated into the first semiconductor layers (120). By etching P130, insulating layers (151) can be formed. As the first semiconductor layer (120L) is separated into the first semiconductor layers (120), first to fourth radiovoltaic structures (RV1, RV2, RV3, RV4) can be formed. The portion of the upper surface of the substrate (110) exposed by the etching of the first semiconductor layer (120L) may be referred to as an isolation region. The isolation region may horizontally surround each of the first to fourth radiovoltaic structures (RV1, RV2, RV3, RV4).

[0117] Each of the first to fourth radiation preforms (RV1, RV2, RV3, RV4) may include a first semiconductor layer (120), an active layer (130), a second semiconductor layer (140), and an insulating layer (151). Here, the term "radiation preform" means that a depletion region included in a radiation preform, such as the active layer (130), generates an electromotive force through electron-hole pair production in response to radiation (e.g., beta rays).

[0118] The insulating layer (151) may cover a portion of the second semiconductor layer (140) and the first semiconductor layer (120). The insulating layer (151) may include a portion on the second semiconductor layer (140) and a portion on the first semiconductor layer (120). The insulating layer (151) may be on a portion of the first semiconductor layer (120) exposed by mesa etching.

[0119] Each of the insulating layers (151) may contain an insulating material. Each of the insulating layers (151) may be SiO2, SiN, SiO x N y It may include one or more of TiO2, Si3N4, Al2O3, TiN, AlN, ZrO2, TiAlN, and TiSiN.

[0120]

[0121] Next, referring to FIGS. 1 and FIGS. 12 through 15, a contact electrode (160) can be formed on the second semiconductor layer (140) of each of the first to fourth radiation structures (RV1, RV2, RV3, RV4) in P140. The formation of the contact electrode (160) may include forming a mask pattern that at least partially exposes the second semiconductor layer (140) of each of the first to fourth radiation structures (RV1, RV2, RV3, RV4), etching a portion of the insulating layers (151) that overlap with the second semiconductor layers (140), depositing an electrode material, and removing the mask pattern through an ashing or lift-off process.

[0122] The contact electrode (160) may include at least one metal selected from the group consisting of copper (Cu), aluminum (Al), nickel (Ni), silver (Ag), gold (Au), platinum (Pt), tin (Sn), lead (Pb), titanium (Ti), chromium (Cr), palladium (Pd), indium (In) and zinc (Zn), metal alloy, and carbon (C).

[0123]

[0124] Next, referring to FIGS. 1 and FIGS. 16 to 19, an insulating layer (153) can be formed in P150. By covering the previous workpiece and forming an insulating material having a uniform thickness, and then partially etching the insulating material, an insulating layer (153) comprising first and second contact holes (153H1, 153H2) can be provided.

[0125] Each of the first contact holes (153H1) can expose a contact electrode (150) of a corresponding one of the first to fourth radiation pre-structures (RV1, RV2, RV3, RV4). Each of the first contact holes (153H1) can further expose a second semiconductor layer (140) of a corresponding one of the first to fourth radiation pre-structures (RV1, RV2, RV3, RV4). Each of the second contact holes (153H2) can expose a first semiconductor layer (120) of a corresponding one of the first to fourth radiation pre-structures (RV1, RV2, RV3, RV4).

[0126]

[0127] Next, referring to FIGS. 1 and FIGS. 20 through 23, first to third conductive patterns (171, 173, 175) may be formed in P160. The formation of the first to third conductive patterns (171, 173, 175) may include forming a mask including an opening that exposes a location to which the first to third conductive patterns (171, 173, 175) are to be formed, depositing a conductive material, and removing the mask through an ashing or lift-off process.

[0128] The first conductive pattern (171) may overlap with each of the first and third radiative structures (RV1, RV3) in the Z direction. The first conductive pattern (171) may overlap with the second semiconductor layer (140) of each of the first and third radiative structures (RV1, RV3) in the Z direction. The first conductive pattern (171) may come into contact with the contact electrode (150) of each of the first and third radiative structures (RV1, RV3). The second semiconductor layer (140) of the first radiative structure (RV1) and the second semiconductor layer (140) of the third radiative structure (RV3) may be short-circuited by the first conductive pattern (171).

[0129] According to other exemplary embodiments, the contact electrode (160) of each of the first to fourth radiation pre-structures (RV1, RV2, RV3, RV4) may be omitted, in which case the first conductive pattern (171) may be in direct contact with the second semiconductor layer (140) of each of the first and third radiation pre-structures (RV1, RV3).

[0130] The second conductive pattern (173) may overlap with each of the second and fourth radiative structures (RV2, RV4) in the Z direction. The second conductive pattern (173) may come into contact with the first semiconductor layer (120) of each of the second and fourth radiative structures (RV2, RV4). The first semiconductor layer (120) of the second radiative structures (RV2) and the first semiconductor layer (120) of the fourth radiative structure (RV4) may be short-circuited by the first conductive pattern (171).

[0131] The third conductive pattern (175) may be located between the first conductive pattern (171) and the second conductive pattern (173). The third conductive pattern (175) may overlap with each of the first to fourth radiative structures (RV1, RV2, RV3, RV4) in the Z direction. The third conductive pattern (175) may be in contact with the first semiconductor layer (120) of each of the first and third radiative structures (RV1, RV3) and the contact electrode (150) of each of the second and fourth radiative structures (RV2, RV4). The third conductive pattern (175) may overlap with the first semiconductor layer (120) of each of the first and third radiative structures (RV1, RV3) and the second semiconductor layer (140) of each of the second and fourth radiative structures (RV2, RV4) in the Z direction. The first semiconductor layer (120) of each of the first and third radiation structures (RV1, RV3) can be short-circuited with the second semiconductor layer (140) of each of the second and fourth radiation structures (RV2, RV4) by the third challenge pattern (175).

[0132] According to other exemplary embodiments, the contact electrode (160) of each of the first to fourth radiation structures (RV1, RV2, RV3, RV4) may be omitted, in which case the third conductive pattern (175) may be in direct contact with the first semiconductor layer (120) of each of the first and third radiation structures (RV1, RV3) and the second semiconductor layer (140) of each of the second and fourth radiation structures (RV2, RV4).

[0133] A first external connection terminal for outputting the resulting voltage of the first to fourth radiation structures (RV1, RV2, RV3, RV4) may be further formed on the first conduction pattern (171), and a second external connection terminal for outputting the resulting voltage of the first to fourth radiation structures (RV1, RV2, RV3, RV4) may be further formed on the second conduction pattern (173). As a result of the processes P110 to P160, a first electric layer (VL1) comprising the first to fourth radiation structures (RV1, RV2, RV3, RV4) which are electrically connected to each other may be formed on the substrate (110).

[0134]

[0135] Next, referring to FIGS. 1 and FIGS. 24 to 26, a beta-ray source layer (200) can be formed in P170. The beta-ray source layer (200) can be formed on the lower surface of the substrate (110). Accordingly, the beta-ray source layer (200) can be spaced apart from the first to fourth radiation pre-structures (RV1, RV2, RV3, RV4) with the substrate (110) in between.

[0136] The beta ray source layer (200) can be formed by any one of the methods of evaporation, sputtering, CVD, electroplating, and electroless plating. The beta ray source layer (200) can have a uniform thickness, and accordingly, the beta ray source layer (200) can have a conformal shape.

[0137] The beta-ray source layer (200) may contain a radioactive isotope. The beta-ray source layer (200) may contain tritium ( 3 H, tritium), calcium-45( 45 Ca), nickel-63 63 Ni), copper-67 67 Cu), strontium-90 ( 90 Sr), promethium-147( 147Pm), osmium-194( 194 OS), Thulium-171( 171 Tm), tantalum-179( 179 Ta), cadmium-109( 109 Cd), germanium-68 68 Ge), cerium-159( 159 Ce) and tungsten-181( 181 It may include one or more of W). Radioactive isotopes may emit only beta rays, or they may also emit additional radiation other than beta rays, such as alpha rays or gamma rays.

[0138]

[0139] Next, referring to FIGS. 27 to 30, a second cell layer (VL2) comprising a substrate (110) and fifth to eighth radiation pre-structures (RV5, RV6, RV7, RV8) on the substrate (110) may be formed.

[0140] The second battery layer (VL2) can be formed by performing manufacturing processes P110 to P160 on the substrate (110). The second battery layer (VL2) may then be attached to a beta-ray source layer (200). Accordingly, an integrated battery (10) comprising a first battery layer (VL1), a second battery layer (VL2), and a beta-ray source layer (200) between them may be provided.

[0141] The beta ray source layer (200) may have a flat shape. The beta ray source layer (200) may include a first surface facing the first battery layer (VL1). The first battery layer (VL1) may be on the first surface. The beta ray source layer (200) may include a second surface facing the second battery layer (VL2). The second surface may be opposite to the first surface. The second battery layer (VL2) may be on the second surface.

[0142] The first battery layer (VL1) may include a substrate (110), first to fourth radiation structures (RV1, RV2, RV3, RV4), an insulating layer (153), and first to third conductive patterns (171, 173, 175). The second battery layer (VL2) may include a substrate (110), fifth to eighth radiation structures (RV5, RV6, RV7, RV8), an insulating layer (153), and first to third conductive patterns (171, 173, 175).

[0143] The beta ray source layer (200) can be configured to irradiate beta rays (βR) onto the first battery layer (VL1). The first battery layer (VL1) can be configured to generate an electromotive force in response to the beta rays (βR).

[0144] At this time, the beta ray source layer (200) can be formed on the lower surface of the substrate (110) and, since it has a uniform thickness, the directions with respect to the upper surface of the substrate (110) can be redefined with respect to the first surface of the beta ray source layer (200). That is, the X direction and the Y direction can each be substantially parallel to the first surface of the beta ray source layer (200), and the Z direction can be substantially perpendicular to the first surface of the beta ray source layer (200).

[0145] Each of the first to fourth radiation pre-structures (RV1, RV2, RV3, RV4) may be on the substrate (110). Each of the first to fourth radiation pre-structures (RV1, RV2, RV3, RV4) may be on the beta-ray source layer (200). Each of the first to fourth radiation pre-structures (RV1, RV2, RV3, RV4) may be on the first surface of the beta-ray source layer (200). The first to fourth radiation pre-structures (RV1, RV2, RV3, RV4) may be arranged in a matrix.

[0146] The first and second radiation structures (RV1, RV2) may be spaced apart in the X direction. The first and second radiation structures (RV1, RV2) may overlap in the X direction. The third and fourth radiation structures (RV3, RV4) may be spaced apart in the X direction. The third and fourth radiation structures (RV3, RV4) may overlap in the X direction.

[0147] The first and third radiation structures (RV1, RV3) may be spaced apart in the Y direction. The first and third radiation structures (RV1, RV3) may overlap in the Y direction. The second and fourth radiation structures (RV2, RV4) may be spaced apart in the Y direction. The second and fourth radiation structures (RV2, RV4) may overlap in the Y direction.

[0148] The first and fourth radiation structures (RV1, RV4) may be spaced apart in the X and Y directions. The second and third radiation structures (RV2, RV3) may be spaced apart in the X and Y directions.

[0149] Each of the first to fourth radiation pre-structures (RV1, RV2, RV3, RV4) may include a first semiconductor layer (120), a second semiconductor layer (140) on the first semiconductor layer (120), an active layer (130) between the first semiconductor layer (120) and the second semiconductor layer (140), an insulating layer (151) on the first and second semiconductor layers (120, 140), and a contact electrode (160) on the second semiconductor layer (140).

[0150] Each of the first to fourth radiation pre-structures (RV1, RV2, RV3, RV4) of the first cell layer (VL1) irradiated by beta rays (βR) can be configured to generate an electromotive force through electron-hole pair production.

[0151] By means of the first to third conduction patterns (171, 173, 175), the first and third radiation structures (RV1, RV3) can be connected in parallel with each other, and the second and fourth radiation structures (RV2, RV4) can be connected in parallel with each other. The first and third radiation structures (RV1, RV3) can be connected in series with the second and fourth radiation structures (RV2, RV4).

[0152] Each of the 5th to 8th radiation prestructures (RV5, RV6, RV7, RV8) may be on the substrate (110). Each of the 5th to 8th radiation prestructures (RV5, RV6, RV7, RV8) may be on the beta-ray source layer (200). Each of the 1st to 4th radiation prestructures (RV1, RV2, RV3, RV4) may be on the second surface of the beta-ray source layer (200). The 5th to 8th radiation prestructures (RV5, RV6, RV7, RV8) may be arranged in a matrix.

[0153] The fifth and sixth radiation structures (RV5, RV6) may be spaced apart in the X direction. The fifth and sixth radiation structures (RV5, RV6) may overlap in the X direction. The seventh and eighth radiation structures (RV7, RV8) may be spaced apart in the X direction. The seventh and eighth radiation structures (RV7, RV8) may overlap in the X direction.

[0154] The fifth and seventh radiation structures (RV5, RV7) may be spaced apart in the Y direction. The fifth and seventh radiation structures (RV5, RV7) may overlap in the Y direction. The sixth and eighth radiation structures (RV6, RV8) may be spaced apart in the Y direction. The sixth and eighth radiation structures (RV6, RV8) may overlap in the Y direction.

[0155] The 5th and 8th radiation structures (RV5, RV8) may be spaced apart in the X and Y directions. The 6th and 7th radiation structures (RV6, RV7) may be spaced apart in the X and Y directions.

[0156] Each of the 5th to 8th radiation pre-structures (RV5, RV6, RV7, RV8) may include a first semiconductor layer (120), a second semiconductor layer (140) on the first semiconductor layer (120), an active layer (130) between the first semiconductor layer (120) and the second semiconductor layer (140), an insulating layer (151) on the first and second semiconductor layers (120, 140), and a contact electrode (160) on the second semiconductor layer (140).

[0157] Each of the 5th to 8th radiation prestructures (RV5, RV6, RV7, RV8) of the second cell layer (VL2) irradiated by beta rays (βR) can be configured to generate an electromotive force by electron-hole pair production.

[0158] By means of the first to third conduction patterns (171, 173, 175), the fifth and seventh radiation structures (RV5, RV7) can be connected in parallel with each other, and the sixth and eighth radiation structures (RV6, RV8) can be connected in parallel with each other. The fifth and seventh radiation structures (RV5, RV7) can be connected in series with the sixth and eighth radiation structures (RV6, RV8).

[0159] According to exemplary embodiments, the first cell layer (VL1) may be configured to output a resulting voltage according to the series and parallel connection of the first to fourth radiation structures (RV1, RV2, RV3, RV4), and the second cell layer (VL2) may be configured to output a resulting voltage according to the series and parallel connection of the fifth to eighth radiation structures (RV5, RV6, RV7, RV8).

[0160] According to exemplary embodiments, a plurality of radiation structures formed within the first and second cell layers (VL1, VL2) can be connected in series and in parallel, so that an integrated cell (10) having desired electrical performance (i.e., voltage and current performance) can be provided with a relatively simple manufacturing process.

[0161] According to exemplary embodiments, by forming a flat beta-ray source layer (200), the amount of beta-ray source material wasted in manufacturing processes such as flattening can be reduced or minimized, thereby reducing the manufacturing cost of the integrated cell.

[0162] In addition, by forming first and second cell layers (VL1, VL2) on both sides based on one layer of beta ray source layer (200), the utilization rate of beta rays (βR) emitted from the beta ray source layer (200) can be improved.

[0163]

[0164] (3rd Example)

[0165] FIGS. 31 to 33 are cross-sectional views showing an integrated cell (10') according to other exemplary embodiments.

[0166] Referring to FIGS. 31 to 33, the integrated cell (10') may include a first cell layer (VL1'), a second cell layer (VL2'), and a beta ray source layer (200) between them.

[0167] Each of the first and second cell layers (VL1', VL2') may not include a substrate (110, see FIG. 27). The substrate (110, see FIG. 27) of each of the first and second cell layers (VL1', VL2') may be separated after the formation of the first to fourth pre-radiation structures (RV1, RV2, RV3, RV4) and the fifth to eighth pre-radiation structures (RV5, RV6, RV7, RV8). The substrate (110, see FIG. 27) may be separated from the first to fourth pre-radiation structures (RV1, RV2, RV3, RV4) and the fifth to eighth pre-radiation structures (RV5, RV6, RV7, RV8) by methods such as laser lift-off or chemical lift-off.

[0168] Accordingly, the beta ray source layer (200) can be in contact with the first semiconductor layer (120) of each of the first to eighth radiation pre-structures (RV1, RV2, RV3, RV4, RV5, RV6, RV7, RV8). The first surface of the beta ray source layer (200) can be in contact with the first semiconductor layer (120) of the first to fourth radiation pre-structures (RV1, RV2, RV3, RV4). The second surface of the beta ray source layer (200) can be in contact with the first semiconductor layer (120) of each of the fifth to eighth radiation pre-structures (RV5, RV6, RV7, RV8). Furthermore, since each of the first and second battery layers (VL1', VL2') does not include a substrate (110, see FIG. 27), absorption of beta particles by the substrate (110, see FIG. 27) can be prevented, and the energy efficiency of the integrated battery (10') can be improved.

[0169]

[0170] The present invention has been described in more detail above through drawings and embodiments. However, the configurations described in the drawings or embodiments described in this specification are merely one embodiment of the present invention and do not represent all technical concepts of the present invention; therefore, it should be understood that various equivalents and modifications that can replace them may exist at the time of filing this application.

Claims

1. Beta ray source layer; and It includes a first radiovoltaic structure and a second radiovoltaic structure on the above-mentioned beta ray source layer, An integrated battery characterized in that each of the first radiation preform and the second radiation preform comprises a first semiconductor layer on the beta ray source layer and a second semiconductor layer on the first semiconductor layer.

2. In Paragraph 1, An integrated cell characterized in that the above beta ray source layer has a planar shape.

3. In Paragraph 1, An integrated battery characterized in that the first radiation field structure and the second radiation field structure are connected in parallel with each other.

4. In Paragraph 1, An integrated cell further comprising a first conductive pattern that overlaps with the second semiconductor layer of each of the first radiation field structure and the second radiation field structure.

5. In Paragraph 1, An integrated cell further comprising a second conductive pattern that overlaps with the first semiconductor layer of each of the first radiation field structure and the second radiation field structure.

6. In Paragraph 1, An integrated battery characterized in that the first and second radiation structures are connected in series.

7. In Paragraph 1, An integrated cell further comprising a third conductive pattern that overlaps with the first semiconductor layer of the first radiation structure and the second semiconductor layer of the second radiation structure.

8. A flat beta ray source layer; and The above-mentioned beta ray source layer includes a first radiation prestructure, a second radiation prestructure, a third radiation prestructure, and a fourth radiation prestructure on a first surface, wherein The first radiation structure, the second radiation structure, the third radiation structure, and the fourth radiation structure are arranged in a matrix, and An integrated battery characterized in that each of the above-mentioned first radiation preform, the above-mentioned second radiation preform, the above-mentioned third radiation preform, and the above-mentioned fourth radiation preform comprises a first semiconductor layer and a second semiconductor layer on the first semiconductor layer.

9. In Paragraph 8, The first radiation structure is superimposed with the second radiation structure in a first direction parallel to the first surface, and The above third radiation structure overlaps with the fourth radiation structure in the above first direction, and The first radiation preform structure is superimposed with the third radiation preform structure and the second direction parallel to the first surface of the beta ray source layer and perpendicular to the first direction, and An integrated battery characterized in that the above-mentioned second radiation field structure overlaps with the above-mentioned fourth radiation field structure in the above-mentioned second direction.

10. In Paragraph 8, An integrated battery characterized in that the first radiation structure is connected in series with the second radiation structure.

11. In Paragraph 8, An integrated battery characterized in that the above-mentioned third radiation structure is connected in series with the above-mentioned fourth radiation structure.

12. In Paragraph 8, An integrated battery characterized in that the first radiation field structure is connected in parallel with the third radiation field structure.

13. In Paragraph 8, An integrated battery characterized in that the above-mentioned second radiation structure is connected in parallel with the above-mentioned fourth radiation structure.

14. In Paragraph 8, An integrated cell further comprising a first conductive pattern that overlaps each of the second semiconductor layer of the first radiation structure and the second semiconductor layer of the third radiation structure in a third direction perpendicular to the first surface.

15. In Paragraph 14, An integrated cell further comprising a second conductive pattern that overlaps in the third direction with each of the first semiconductor layer of the second radiation structure and the first semiconductor layer of the fourth radiation structure.

16. In Paragraph 15, An integrated cell further comprising a third conductive pattern overlapping in the third direction with each of the first semiconductor layer of the first radiation structure, the first semiconductor layer of the third radiation structure, the second semiconductor layer of the second radiation structure, and the second semiconductor layer of the fourth radiation structure.

17. In Paragraph 16, An integrated battery characterized in that the third conductivity pattern is located between the first conductivity pattern and the second conductivity pattern.

18. A beta ray source layer configured to emit beta rays; A first cell layer on the first surface of the above beta ray source layer; and It includes a second cell layer on a second surface opposite to the first surface of the beta ray source layer, and The first battery layer includes a first radiation field structure and a second radiation field structure, and The second battery layer includes a third radiation field structure and a fourth radiation field structure, and An integrated cell characterized in that the above beta ray source layer has a planar shape.

19. In Paragraph 18, An integrated battery characterized in that each of the above-mentioned first radiation preform, the above-mentioned second radiation preform, the above-mentioned third radiation preform, and the above-mentioned fourth radiation preform comprises a first semiconductor layer and a second semiconductor layer on the first semiconductor layer.

20. In Paragraph 18, The first radiation structure is connected in series with the second radiation structure, and An integrated battery characterized in that the above-mentioned third radiation structure is connected in series with the above-mentioned fourth radiation structure.

21. In Paragraph 18, The first radiation structure is connected in parallel with the second radiation structure, and An integrated battery characterized in that the above-mentioned third radiation field structure is connected in parallel with the above-mentioned fourth radiation field structure.

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