Digital audio signal switcher and network-based public address receiver including same

Abstract

Disclosed is a digital audio signal switcher comprising: an input multiplexer for receiving a first digital audio signal and a second digital audio signal; an output multiplexer for outputting an output digital audio signal; and a finite state machine (FSM)-based fade circuit unit, for, in response to an audio selection signal indicating switching between the first digital audio signal and the second digital audio signal, generating a faded-out digital audio signal and causing the output multiplexer to output the faded-out digital audio signal as the output digital audio signal, and subsequently, after clock switching, generating a faded-in digital audio signal and causing the output multiplexer to output the faded-in digital audio signal as the output digital audio signal.

Description

Digital audio signal switching device and network-based public address receiver including the same

[0001] The present disclosure relates to a digital audio signal switcher and a network-based public address (PA) receiver including the same.

[0002] A Public Address (PA) system is installed in environments such as buildings or complexes—e.g., apartment complexes, schools, government offices, large buildings, airports, shopping malls, etc.—and is configured to broadcast sounds, such as announcements or background music, over a wide area. A PA system may also be equipped with the function of performing emergency broadcasts to notify of emergency situations (e.g., fire, explosion, flooding, power outage, earthquake, etc.) occurring within or near the environment in which it is installed.

[0003] Recently, many examples of PA systems are being implemented on a large scale, such as by connecting multiple regional facilities to a network. In this regard, examples of audio data being transmitted over a network include: (i) a general-latency audio receiver (which may also be referred to as a general-purpose audio player) that receives and plays audio data (e.g., an audio file) with some general possible delay over an IP network, such as a Transmission Control Protocol (TCP) / Internet Protocol (IP) network; and (ii) a low-latency audio receiver that receives and processes audio data (e.g., an uncompressed audio stream) over an IP network with low latency, according to a Layer 3-based audio data transmission solution (e.g., Layer 3 networking such as DANTE, Ravenna, Q-LAN, etc.), and possibly also according to Layer 2 networking (e.g., Audio Video Bridging (AVB) networking or other types of Audio over Ethernet (AoE) networking).A general-purpose audio playback device may include a general-purpose central processing unit (CPU), memory, a networking device (e.g., a network interface card (NIC)), and an audio device (e.g., an audio codec chip with a digital-to-analog converter (DAC) function) coupled via a bus (e.g., including a 32-bit bus), wherein audio data received via the networking device is sufficiently buffered in memory via the bus for playback, shared with the general-purpose CPU via the bus (e.g., for subsequent processing), and inter-IC sound (I. 2 S) It can be provided to an audio device via a bus in a format compatible with an audio interface, such as an interface. A low-latency audio receiving device can output the received audio data for playback via a specific audio interface (e.g., a Time-Division Multiplexing (TDM) audio interface that allows audio data of two or more channels to be transmitted through a single data line) according to a synchronized clock or a variable clock.

[0004] In this regard, Korean Registered Patent No. 10-2611887 discloses a network-based PA receiver that integrates a configuration for general delay reception of audio data and a configuration for low delay reception for a network-based PA. As can be seen therein, an audio selector may be used to perform switching between outputting audio data formatted according to various audio interface formats. However, if the clock is not properly synchronized when performing such switching, a glitch may occur, and consequently, the level of the data signal may surge, causing noise such as a bomb sound (which could potentially tear the speaker's horn) to be generated momentarily from the speaker. An Asynchronous Sample Rate Converter (ASRC) can be utilized to match the clocks between the two signals, but this is a somewhat expensive solution, and there remains a possibility that a bomb sound may still occur when the difference in the levels of these signals is large.

[0005] A digital audio signal switching device and a network-based public address receiver including the same are disclosed in this document.

[0006] In the example, the digital audio signal switching unit comprises an input multiplexer that receives a first digital audio signal and a second digital audio signal, an output multiplexer that outputs an output digital audio signal, and, in response to an audio select signal indicating switching between the first digital audio signal and the second digital audio signal, generates a fade-out digital audio signal by performing a fade-out process on the current digital audio signal output by the output multiplexer among the first digital audio signal and the second digital audio signal as the current output digital audio signal, and causes the output multiplexer to output the fade-out digital audio signal as the output digital audio signal, and subsequently, for the next digital audio signal which is different among the first digital audio signal and the second digital audio signal, generates a fade-in digital audio signal by performing a fade-in process after clock switching from the current clock signal for the transmission of the current digital audio signal to the next clock signal for the transmission of the next digital audio signal, and causes the output multiplexer to output the fade-in digital audio signal as the output digital audio signal, a finite state machine. Machine: Includes a fade circuit based on FSM.

[0007] The foregoing overview is provided to introduce, in a simplified form, some aspects that will be further described later in the detailed description. This overview is not intended to identify important or essential features of the claimed subject matter, nor is it intended to be used to define the scope of the claimed subject matter. Furthermore, the claimed subject matter is not limited to any or all advantageous implementations discussed herein.

[0008] According to the present disclosure, in switching between digital audio signals, the clock is switched at an appropriate timing through fade processing of these signals, thereby preventing the occurrence of noise such as panning sound in a cost-effective manner.

[0009] Figure 1 shows an exemplary network-based PA system in which audio data for a PA is transmitted in a networked environment.

[0010] Figure 2 is a block diagram showing an example of a digital audio signal switching device of Figure 1.

[0011] FIG. 3 is a block diagram showing an exemplary detailed configuration of the digital audio signal switching device exemplified in FIG. 2.

[0012] Figure 4 is a state diagram for explaining the operation of the Finite State Machine (FSM) of Figure 3.

[0013] The various terms used in this disclosure are selected from the conventions of common terminology in consideration of their function within this document, as they may be perceived differently depending on the intent, practices, or emergence of new technology of those skilled in the art. In specific instances, some terms may be given meanings as set forth in the detailed description. Accordingly, terms used in this document should be defined consistently with their meaning in the context of this disclosure, rather than merely by their names.

[0014] In this document, terms such as "include," "have," etc., are used to specify the presence of the elements listed below, e.g., certain features, numbers, steps, actions, components, information, or combinations thereof. Unless otherwise indicated, these terms and variations thereof are not intended to exclude the presence or addition of other elements.

[0015] As used in this document, terms “first,” “second,” etc. are intended to identify several similar elements. Unless otherwise stated, such terms are not intended to impose limitations, such as a specific order of use of these elements or their elements, but are used merely to refer to several elements separately. For example, while an element may be referred to as the term “first” in one example, the same element may be referred to by a different ordinal number, such as “second” or “third,” in another example. In such examples, these terms do not limit the scope of this disclosure. Furthermore, the use of the term “and / or” in a list of elements includes any one or more of the listed items, as well as all possible combinations of these items. Moreover, expressions in the singular form include the meaning of the plural form unless explicitly stated otherwise.

[0016] Certain examples of the present disclosure will now be described in detail with reference to the attached drawings. However, the present disclosure may be embodied in many different forms and should not be construed as being limited to the examples set forth in this document. Rather, these examples are provided to provide a better understanding of the scope of the present disclosure.

[0017] FIG. 1 shows an exemplary network-based PA system (100) in which audio data for PA is transmitted in a networked environment. The exemplary network-based PA system (100) can provide PA throughout a target environment (e.g., a complex including multiple buildings, a collection of local offices distributed across multiple remote areas, at least part of a building, a building structure, or an indoor and / or outdoor environment of similar things). For example, the target environment may be divided into multiple zones, and performing PA through the PA system (100) may include broadcasting the same or different notifications (e.g., voice alarms) across some of the zones.

[0018] In the example of FIG. 1, the network-based PA system (100) includes a network-based PA transmitter (105), a network-based PA receiver (110), and a network (108).

[0019] A network-based PA transmitter (105) can transmit audio data of any format (which is based on sound source data derived from, for example, a CD player (Compact Disc Player: CDP), a Text-To-Speech (TTS) synthesizer, a Remote Microphone (RM) or similar) to a network-based PA receiver (110) via a network (108).

[0020] The network (108) may include wired and / or wireless networks, for example, a Local Area Network (LAN), a Metropolitan Area Network (MAN), a Wide Area Network (WAN), the Internet, a Virtual Private Network (VPN), or a combination thereof, and may be an Internet Protocol (IP) based network in particular.

[0021] A network-based PA receiver (110) may be placed in any type of device that receives PA audio data from a network-based PA transmitter (105) via a network (108) at the receiving side of a network-based PA system (100) (which may have any suitable type of additional function, such as generating and outputting an amplified audio signal from the received PA audio data, routing one or more audio signals generated from the received PA audio data to one or more audio output channels and assigning each audio output channel to an audio processing device such as an audio amplifier, speaker, audio mixer and / or audio matrix, or distributing to a specific area of ​​the target environment of the network-based PA system (100), such as enabling or disabling relaying to at least one speaker installed in the area, and / or driving a speaker transducer while acting as a Power over Ethernet (PoE) switch). The network-based PA receiver (110) may be implemented to include a digital audio signal switcher (112), which will be described in more detail below.

[0022] FIG. 2 is a block diagram showing an example of a digital audio signal switch (112). As shown in FIG. 2, the digital audio signal switch (112) includes an input multiplexer (210), an output multiplexer (220), and a finite state machine (FSM) based fade circuit (250).

[0023] In the illustrated example, the input multiplexer (210) receives a first digital audio signal and a second digital audio signal, and the output multiplexer (220) outputs an output digital audio signal. This output digital audio signal may be the first digital audio signal or the second digital audio signal. Furthermore, as discussed in detail below, the output multiplexer (220) may output a fade-processed digital audio signal provided by the FSM-based fade circuit (250) as the output digital audio signal. The fade-processed digital audio signal may be generated by the FSM-based fade circuit (250) when an audio select signal indicating switching between the first digital audio signal and the second digital audio signal is received by the FSM-based fade circuit (250).

[0024] For example, for the sake of discussion, let us assume that the output multiplexer (220) is currently outputting one of the first digital audio signal and the second digital audio signal (which may be referred to as the "current digital audio signal" for convenience below) as an output digital audio signal. Then, the FSM-based fade circuit (250) generates a faded digital audio signal in response to the aforementioned audio selection signal as follows, and causes this signal to be output as output digital audio data.

[0025] - First, the FSM-based fade circuit (250) performs fade-out processing on the current digital audio signal to generate a faded-out digital audio signal as a faded digital audio signal, and causes the output multiplexer (220) to output this signal as an output digital audio signal.

[0026] - Subsequently, the FSM-based fade circuit (250) generates a faded-in digital audio signal as a faded digital audio signal by performing a fade-in process on the first digital audio signal and the second digital audio signal that is not the current digital audio signal (which may be referred to as the "next digital audio signal" for convenience below) after clock switching from the clock signal for transmitting the current digital audio signal (which may be referred to as the "current clock signal" for convenience below) to the clock signal for transmitting the next digital audio signal (which may be referred to as the "next clock signal" for convenience below), and causes the output multiplexer (220) to output this signal as an output digital audio signal.

[0027] In this example, the FSM-based fade circuit (250) can also cause the output multiplexer (220) to output the next digital audio signal as an output digital audio signal following the faded-in digital audio signal.

[0028] In this example, the input multiplexer (210) may also receive a current clock signal and a next clock signal, and the aforementioned clock switching may include the input multiplexer (210) switching from outputting the current clock signal to outputting the next clock signal. Additionally, in this example, the output multiplexer (220) may receive a first digital audio signal through a first signal line, a second digital audio signal through a second signal line, and a faded digital audio signal (which is one of the faded-out digital audio signal and the faded-in digital audio signal as described above) through a third signal line.

[0029] In relation to the example described above, we examine an exemplary operation in which the FSM-based fade circuit (250) performs fade processing. First, the FSM-based fade circuit (250) can generate a faded digital audio signal by performing a stepwise fade-out of a set number of fade-out steps Nfo, and can cause the output multiplexer (220) to output this generated signal as an output digital audio signal. Subsequently, when the number of times the stepwise fade-out is performed reaches Nfo, the FSM-based fade circuit (250) can cause the output multiplexer (220) to maintain the output digital audio signal at the final level of the faded digital audio signal (e.g., a mute level such as a zero level) (e.g., continuously outputting the faded digital audio signal that has reached such a level as an output digital audio signal) and cause the input multiplexer (210) to perform clock switching. Since the clock is switched while these levels are maintained, it may be useful for preventing the occurrence of a blast sound even if a glitch occurs. Furthermore, the FSM-based fade circuit (250) can generate a faded digital audio signal by performing a stepwise fade-in Nfi, a set number of fade-ins equal to or different from Nfo, and cause the output multiplexer (220) to output this generated signal as an output digital audio signal. Subsequently, when the number of stepwise fade-ins reached Nfi, the FSM-based fade circuit (250) can cause the output multiplexer (220) to output the next digital audio signal as an output digital audio signal.

[0030] Now, with reference to FIG. 3, an exemplary detailed configuration of a digital audio signal switching device (112) is discussed. In particular, in FIG. 3, the FSM-based fade circuit section (250) is illustrated as including an FSM (310), a counter (320), and a stepwise fade circuit (330).

[0031] In the example of FIG. 3, the input multiplexer (210) can receive a data signal (a_audio_pdata) as a first digital audio signal, and can receive a master clock signal (a_audio_mclk), a left / right channel selection clock signal (a_audio_lrclk), and a bit clock signal (a_audio_bclk) as clock signals for the signal (a_audio_pdata). Additionally, the input multiplexer (210) can receive a data signal (b_audio_pdata) as a second digital audio signal, and can receive a master clock signal (b_audio_mclk), a left / right channel selection clock signal (b_audio_lrclk), and a bit clock signal (b_audio_bclk) as clock signals for the signal (b_audio_pdata).

[0032] In the example of FIG. 3, the output multiplexer (220) can receive a data signal (a_audio_pdata) (i.e., a first digital audio signal), a data signal (b_audio_pdata) (i.e., a second digital audio signal), and a faded digital audio signal output from the step-by-step fade circuit (330) of the FSM-based fade circuit (250), and can output one of these signals as an output digital audio signal (o_audio_pdata).

[0033] In the example of FIG. 3, the counter (320) is configured to count the number of fade steps Nf when triggered. In this example, the number of fade-out steps Nfo and the number of fade-in steps Nfi are both set to be equal to the number of fade steps Nf (i.e., Nfo = Nfi = Nf). Additionally, the step-by-step fade circuit (330) is configured to generate a faded digital audio signal by performing a step-by-step fade-out of the set number of fade steps Nf, and to generate a faded digital audio signal by performing a step-by-step fade-in of the set number of fade steps Nf. For example, Nf can be set to 256, 128, 64, or 32. The larger the value of Nf, the longer the execution time of the fade process will be. For example, the time required for the fade process for the data signal (a_audio_pdata) can be calculated by multiplying Nf by the reciprocal of the frequency of the left / right channel selection clock signal (a_audio_lrclk). The same applies to the data signal (b_audio_pdata). For example, if Nf is 256, and the frequency of the left / right channel selection clock signal (a_audio_lrclk) is 48kHz, and the frequency of the left / right channel selection clock signal (b_audio_lrclk) is 44.1kHz, then the time taken for the step-by-step fade-out of Nf is 20.83us * 256 = 5.332ms, and the time taken for the step-by-step fade-in of Nf is 22.67us * 256 = 5.803ms.

[0034] In the example of FIG. 3, the FSM (310) is configured to control the overall operation of the FSM-based fade circuit (250). As depicted in FIG. 3, the FSM (310) may receive an audio select signal (audio_select) indicating switching between a first digital audio signal and a second digital audio signal, and may receive a system clock signal (sys_clk) and a system reset signal (sys_rstn). The audio select signal (audio_select) may be a signal (e.g., a binary signal) indicating which of the first digital audio signal and the second digital audio signal is selected to be output (i.e., the next digital audio signal).

[0035] Additionally, in the example of FIG. 3, the FSM (310) may cause the input multiplexer (210) to switch between outputting a first digital audio signal to the step-by-step fade circuit (330) and outputting a second digital audio signal to the step-by-step fade circuit (330) in response to the audio select signal (audio_select). These output signals are denoted as data signals to be faded (Audio L data, Audio R data) or simply data signals (Audio L data, Audio R data), where Audio L data and Audio R data represent its two channels. For example, the FSM (310) may signal the input multiplexer (210) to switch the data signals to be faded (Audio L data, Audio R data) from the current digital audio signal to the next digital audio signal (e.g., by changing the value of a variable representing the level of a binary pulse as described below).

[0036] Furthermore, in the example of FIG. 3, the FSM (310) can switch between the input multiplexer (210) outputting the master clock signal (a_audio_mclk), the left / right channel selection clock signal (a_audio_lrclk), and the bit clock signal (a_audio_bclk) as the selected master clock signal (Selected mclk), the selected left / right channel selection clock signal (Selected lrclk), and the selected bit clock signal (Selected bclk), respectively, and outputting the master clock signal (b_audio_mclk), the left / right channel selection clock signal (b_audio_lrclk), and the bit clock signal (b_audio_bclk) as the selected master clock signal (Selected mclk), the selected left / right channel selection clock signal (Selected lrclk), and the selected bit clock signal (Selected bclk), respectively. These output signals may be provided as the output master clock signal (o_audio_mclk), output left / right channel selection clock signal (o_audio_lrclk), and output bit clock signal (o_audio_bclk) of the clock processing device (112). For example, the FSM (310) may signal the input multiplexer (210) to switch the selected master clock signal (Selected mclk), the selected left / right channel selection clock signal (Selected lrclk), and the selected bit clock signal (Selected bclk) from the current digital audio signal to the next digital audio signal (e.g., by changing other variable values ​​representing the level of the binary pulse as described below).

[0037] To this end, we will look at how the FSM (310) can operate with reference to FIG. 4.

[0038] As illustrated in FIG. 4, the FSM (310) can be characterized by a standby state, a fade-out state, a zero state, and a fade-in state, which are denoted as READY, FADEOUT, ZERO, and FADEIN, respectively.

[0039] In the READY state, the FSM (310) resets the variables (fade_out_start), (fade_en), (audio_zero_en), and (fade_in_start) (which may each represent the level of a binary pulse) to their initial values ​​of 0, and resets the flags (change_flag), (fade_out_done), (audio_change_done), and (fade_in_done) to their initial values ​​of 0. When an audio select signal (audio_select) is received in the READY state, the value of the flag (change_flag) is changed to 1, and in response, the FSM (310) transitions to the FADEOUT state.

[0040] In the fade-out state, the FSM (310) assigns 1 to the variable (fade_out_start), which triggers the start of the fade-out process and counting by the counter (320). Additionally, in the fade-out state, the FSM (310) assigns 1 to the variable (fade_en), which triggers the output of the faded digital audio signal (here, the faded digital audio signal) from the output multiplexer (220) (specifically, in response to a binary pulse having a level corresponding to this value, the output multiplexer (220) outputs the faded digital audio signal). When the counting of the counter (320), triggered by the current assigned value 1 of the variable (fade_out_start), reaches the number of fade steps Nf, the value of the flag (fade_out_done) is changed to 1, and in response, the FSM (310) transitions to the zero state (ZERO).

[0041] In the zero state (ZERO), the FSM (310) resets the variable (fade_out_start) to its initial value and assigns 1 to the variable (audio_zero_en), which triggers clock switching by the input multiplexer (210) (i.e., switching of the selected master clock signal (Selected mclk), the selected left and right channel selection clock signal (Selected lrclk), and the selected bit clock signal (Selected bclk) (specifically, in response to a binary pulse having a level corresponding to this value, the input multiplexer (210) switches the clock). It is noted that during the zero state (ZERO), the value of the variable (fade_en) is maintained, and thus the output multiplexer (220) continues to output the faded digital audio signal (e.g., having already reached a final level such as a mute level through fade-out). When an event indicating the completion of clock switching occurs (e.g., the expiration of a timer started at such trigger or signaling from the input multiplexer (210)), the value of the flag (audio_change_done) is changed to 1, and in response, the FSM (310) transitions to a fade-in state (FADEIN).

[0042] In the fade-in state, the FSM (310) resets the variable (audio_zero_en) to its initial value and assigns 1 to the variable (fade_in_start), which triggers the start of the fade-in process and counting by the counter (320). Additionally, the value 1 of the variable (fade_in_start) triggers the input multiplexer (210) to switch the data signals (Audio L data, Audio R data) to be faded (specifically, in response to a binary pulse having a level corresponding to this value, the input multiplexer (210) switches the data signals (Audio L data, Audio R data). When the counting of the counter (320), triggered by the current assigned value 1 of the variable (fade_in_start), reaches the number of fade steps Nf, the value of the flag (fade_in_done) is changed to 1, and in response, the FSM (310) transitions to a standby state (READY). During the fade-in state (FADEIN), the value of the variable (fade_en) is maintained, and the output multiplexer (220) outputs a faded digital audio signal (here, a fade-in digital audio signal) (specifically, in response to a binary pulse having a level corresponding to this value, the output multiplexer (220) outputs a faded digital audio signal). Subsequently, in the standby state (READY), the FSM (310) resets at least the variable (fade_en) and the variable (fade_in_start) to their initial values.If the value of the variable (fade_en) is the initial value 0, the output multiplexer (220) can output the first digital audio signal or the second digital audio signal as the output digital audio signal (o_audio_pdata) instead of the faded digital audio signal. For example, in response to a binary pulse having a level corresponding to this value, the output multiplexer (220) switches the output digital audio signal (o_audio_pdata) from the current digital audio signal to the next digital audio signal.

[0043] Referring again to FIG. 3, for example, the step-by-step fade circuit (330) may include a multiplier that multiplies a predetermined step-by-step factor to the data signal (Audio L data, Audio R data) to be faded at each of the Nf steps of the fade processing. Additionally, for example, the step-by-step fade circuit (330) may determine the level difference by calculating the difference between the respective levels of the first digital audio signal and the second digital audio signal received by the input multiplexer (210) at each of the Nf steps of the fade-out processing, and adjust the number of steps in the fade-in processing based on such level difference.

[0044] The following are various examples of digital audio signal switching devices.

[0045] In Example 1, the digital audio signal switching unit comprises an input multiplexer that receives a first digital audio signal and a second digital audio signal, an output multiplexer that outputs an output digital audio signal, and, in response to an audio select signal indicating switching between the first digital audio signal and the second digital audio signal, generates a fade-out digital audio signal by performing a fade-out process on the current digital audio signal output by the output multiplexer among the first digital audio signal and the second digital audio signal, and causes the output multiplexer to output the fade-out digital audio signal as the output digital audio signal, and subsequently, for the next digital audio signal which is different among the first digital audio signal and the second digital audio signal, generates a fade-in digital audio signal by performing a fade-in process after clock switching from the current clock signal for transmitting the current digital audio signal to the next clock signal for transmitting the next digital audio signal, and causes the output multiplexer to output the output digital audio signal as the output digital audio signal It includes a Finite State Machine (FSM)-based fade circuit that outputs a faded-in digital audio signal.

[0046] Example 2 includes the subject of Example 1, wherein the above FSM-based fade circuit also generates the above fade-in digital audio signal and causes the above output multiplexer to output the above fade-in digital audio signal as the above output digital audio signal, and subsequently causes the above output multiplexer to output the above next digital audio signal as the above output digital audio signal.

[0047] Example 3 includes the subject of Example 1 or Example 2, and the above clock switching includes the above input multiplexer switching from outputting the above current clock signal to outputting the above next clock signal.

[0048] Example 4 includes the subject of any of Examples 1 to 3, wherein the input multiplexer also receives the current clock signal and the next clock signal, and the FSM-based fade circuit generates the faded digital audio signal by performing a step-by-step fade-out for a set number of fade-out steps, and when the number of times the step-by-step fade-out is performed reaches the set number of fade-out steps, the output multiplexer causes the output digital audio signal to be maintained at the final level of the faded digital audio signal, and the input multiplexer causes the clock switching to be performed, and generates the faded digital audio signal by performing a step-by-step fade-in for a set number of fade-in steps equal to or different from the set number of fade-out steps.

[0049] Example 5 includes the topic of Example 4, and the final level above is the mute level.

[0050] Example 6 includes the subject of Example 4 or Example 5, and when the number of times the above step-by-step fade-in is performed reaches the above set number of fade-in steps, the above output multiplexer outputs the above next digital audio signal as the above output digital audio signal by the above FSM-based fade circuit.

[0051] Example 7 includes the subject of any of Examples 4 to 6, and the above FSM-based fade circuit also calculates the difference between the respective levels of the above first digital audio signal and the above second digital audio signal at each step of the above-set fade-out step count to determine the level difference, and adjusts the above-set fade-in step count based on the above level difference.

[0052] Example 8 includes the subject of any of Examples 1 through 7, wherein the output multiplexer receives the first digital audio signal through the first signal line, the second digital audio signal through the second signal line, and one of the faded-out digital audio signal and the faded-in digital audio signal through the third signal line.

[0053] In Example 9, the network-based public address (PA) receiver includes a digital audio signal switching device of any of Examples 1 through 8.

[0054] The foregoing description is provided to illustrate and describe several examples in detail. Those skilled in the art will understand that many modifications and variations are possible in light of the foregoing teachings without departing from the scope of this disclosure. In various examples, suitable results may be achieved even if the foregoing techniques are performed in a different order and / or some of the components of the foregoing systems, architectures, devices, circuits and similars are combined or assembled in a different way, or replaced or substituted by other components or equivalents thereof.

[0055] Therefore, the scope of the present disclosure should not be limited to the disclosed forms, but should be determined by the claims and equivalents set forth below.

Claims

1. An input multiplexer that receives a first digital audio signal and a second digital audio signal, and An output multiplexer that outputs an output digital audio signal, and A finite state machine (FSM)-based fade circuit comprising, in response to an audio select signal indicating switching between the first digital audio signal and the second digital audio signal, generating a fade-out digital audio signal by performing a fade-out process on the current digital audio signal currently output as the output digital audio signal by the output multiplexer among the first digital audio signal and the second digital audio signal, and causing the output multiplexer to output the fade-out digital audio signal as the output digital audio signal, and subsequently, for the next digital audio signal which is different among the first digital audio signal and the second digital audio signal, generating a fade-in digital audio signal by performing a fade-in process after clock switching from the current clock signal for the transmission of the current digital audio signal to the next clock signal for the transmission of the next digital audio signal, and causing the output multiplexer to output the fade-in digital audio signal as the output digital audio signal. Digital audio signal switching device.

2. In Paragraph 1, The above FSM-based fade circuit also generates the fade-in digital audio signal and causes the output multiplexer to output the fade-in digital audio signal as the output digital audio signal, and subsequently causes the output multiplexer to output the next digital audio signal as the output digital audio signal. Digital audio signal switching device.

3. In Paragraph 1, The above clock switching includes the input multiplexer switching from outputting the current clock signal to outputting the next clock signal. Digital audio signal switching device.

4. In Paragraph 1, The above input multiplexer also receives the current clock signal and the next clock signal, and The above FSM-based fade circuit generates a faded digital audio signal by performing a step-by-step fade-out for a set number of fade-out steps, and when the number of times the step-by-step fade-out is performed reaches the set number of fade-out steps, the output multiplexer causes the output digital audio signal to be maintained at the final level of the faded digital audio signal, while the input multiplexer causes the clock switching to be performed, and generates a faded digital audio signal by performing a step-by-step fade-in for a set number of fade-in steps that is the same as or different from the set number of fade-out steps. Digital audio signal switching device.

5. In Paragraph 4, When the number of times the above step-by-step fade-in is performed reaches the set number of fade-in steps, the output multiplexer outputs the next digital audio signal as the output digital audio signal by the FSM-based fade circuit. Digital audio signal switching device.

6. In Paragraph 4, The above FSM-based fade circuit also calculates the difference between the respective levels of the first digital audio signal and the second digital audio signal at each step of the set number of fade-out steps to determine the level difference, and adjusts the set number of fade-in steps based on the level difference. Digital audio signal switching device.

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