System and method for power estimation

Abstract

A system and method for power estimation for an electronic circuit design is disclosed. The method comprises receiving a request for performing power estimation for a first electronic circuit design of a first electronic device, wherein the request is indicative of one or more first nets in the first electronic circuit design. Further, one or more first attributes associated with at least one of the first nets in the first electronic circuit design are determined from the request based on the one or more first attributes of the first net, a capacitance model corresponding to the first net is identified, from a plurality of capacitance models stored in a database. The capacitance model of the first net is further used to perform the power estimation for the first electronic circuit design, and a power report file is generated based on the power estimation on an output device.

Description

SYSTEM AND METHOD FOR POWER ESTIMATIONTECHNICAL FIELD

[0001] This application is related to electronic design automation and, more specifically, to a computing system and method for power estimation.BACKGROUND

[0002] Current methodologies for capacitance estimation in early stages of System-on- Chip (SOC) development are based on wire load models embedded in technology libraries. These models, while facilitating initial interconnect delay calculations, are inherently approximations and their accuracy diminishes, particularly in lower technology nodes where WLMs might be absent. Additionally, the placement and routing approach, though precise, is time-intensive and impractical for merely acquiring quick power estimates. Furthermore, the utilization of capacitance constraints in Synopsis Design Constraints files introduces assumptions, thereby compromising accuracy. This inadequacy in early-stage power estimation methods poses significant challenges for accurate power computation, affecting design efficiency and optimization.

[0003] The pressing issue is the lack of a methodology that can deliver precise power estimations at the RTL stage without embarking on the exhaustive Place and Route process. Existing techniques such as wire load models fall short in accuracy, and placement and routing are impractical for quick estimations. This is because wire load models require specific technology node sizes, and wire load models are unavailable for say 3 nm technology nodes thereby making wire load models inaccurate for lower technology nodes.SUMMARY

[0004] This application discloses a computing system and method for power estimation associated with electronic circuit designs is disclosed.

[0005] According to a first aspect, a method for power estimation is disclosed. The method includes receiving a request for performing power estimation for a first electronic circuit design of a first electronic device, wherein the request is indicative of one or more first nets in the first electronic circuit design. The method further includes determining one or more first attributes associated with at least one of the first nets in the first electronic circuit design from the request. In an embodiment, the one or more first attributes of the first net comprise at least a sink type, a source type, and a fanout count associated with the first net.

[0006] The method further includes identifying a capacitance model corresponding to the first net, from a plurality of capacitance models stored in a database, based on the one or more first attributes of the first net. In an embodiment, the plurality of capacitance models stored in the database, is generated by receiving one or more parasitic files descriptive of one or more second electronic circuit designs. Further, a plurality of second attributes associated with one or more second nets in each of the second electronic circuit designs is extracted, from the respective parasitic files, wherein each of the second nets in the second electronic circuit design is associated with a capacitance value. In an embodiment, the one or more second attributes associated with the second net comprise at least a driving port type, a sink port type, a fanout count and the capacitance value associated with the second net. Further, the second nets in the second electronic circuit designs are grouped, into a plurality of capacitance classes based on commonalities between the corresponding second attributes. Further, a representative capacitance corresponding to each of the capacitance classes is computed based on the capacitance values of the second nets in the capacitance class. Furthermore, the plurality of capacitance models is generated based on the second attributes of the nets in each of the capacitance classes and the corresponding representative capacitance. In an embodiment, identifying the capacitance model corresponding to the first net based on the one or more first attributes, includes identifying a capacitance class from the plurality of capacitance classes by comparing at least one of the first attributes to the corresponding second attribute associated with each of the capacitance classes, and obtaining the capacitance model associated with the capacitance class identified from the database.

[0007] The method further includes using the capacitance model of the first net to perform the power estimation for the first electronic circuit design. In an implementation, using the capacitance model of the first net to perform the power estimation for the first electronic circuit design, includes performing state dependent path dependent power analysis based on the capacitance value. Further, a power report file is generated based on the power estimation on an output device.

[0008] According to a second aspect, a system may be arranged and configured to execute the steps of the computer-implemented method according to the first aspect.

[0009] According to a third aspect, a computer program product may comprise computer program code which, when executed by the system according to the second aspect, causes the system to carry out the method according to the first aspect.

[0010] According to a fourth aspect, a computer-readable medium may comprise the computer program product according to the third aspect. By way of example, the described computer-readable medium may be non-transitory and may further be a software component on a storage device.

[0011] These and other aspects are apparent from the embodiment s) described below.BRIEF DESCRIPTION OF FIGURES

[0012] FIG. 1 shows an illustrative example of a computing device, in accordance with an embodiment.

[0013] FIG. 2 illustrates an example of a multi-core processor unit that may be employed with various embodiments.

[0014] FIG. 3 A illustrates an example system including a design verification system and a system that may be implemented according to various embodiments.

[0015] FIG. 3B shows the power estimation system, in accordance with an embodiment.

[0016] FIG. 3C shows a capacitance model generation system, in accordance with an embodiment.

[0017] FIG. 4A shows a flowchart of a method for performing power estimation, in accordance with an embodiment.

[0018] FIG. 4B shows a flowchart of a method for computing the power estimate using path dependent and state dependent power analysis, in accordance with an embodiment.

[0019] FIG. 5 illustrates an example power estimation look-up table utilized to implement state dependent and path dependent power estimation according to various embodiments.

[0020] FIG. 6 shows a method of creating a database of capacitance models, in accordance with an embodiment.DETAILED DESCRIPTIONIllustrative Operating Environment

[0021] Various examples may be implemented through the execution of software instructions by a computing device 101, such as a programmable computer. Accordingly, FIG. 1 shows an illustrative example of a computing device 101. As seen in this figure, the computing device 101 includes a computing unit 103 with a processing unit 105 and a system memory 107. The processing unit 105 may be any type of programmable electronic device for executing software instructions but is conventionally a microprocessor. The system memory 107 may include both a read-only memory (ROM) 109 and a random-access memory (RAM) 111. As will be appreciated by those of ordinary skill in the art, both theread-only memory (ROM) 109 and the random-access memory (RAM) 111 may store software instructions for execution by the processing unit 105.

[0022] The processing unit 105 and the system memory 107 are connected, either directly or indirectly, through a bus 113 or alternate communication structure, to one or more peripheral devices 115-123. For example, the processing unit 105 or the system memory 107 may be directly or indirectly connected to one or more additional memory storage devices, such as a hard disk drive 117, which can be magnetic and / or removable, a removable optical disk drive 119, and / or a flash memory card. The processing unit 105 and the system memory 107 also may be directly or indirectly connected to one or more input devices 121 and one or more output devices 123. The input devices 121 may include, for example, a keyboard, a pointing device (such as a mouse, touchpad, stylus, trackball, or joystick), a scanner, a camera, and a microphone. The output devices 123 may include, for example, a monitor display, a printer, and speakers. With various examples of the computing device 101, one or more of the peripheral devices 115-123 may be internally housed with the computing unit 103. Alternately, one or more of the peripheral devices 115-123 may be external to the housing for the computing unit 103 and connected to the bus 113 through, for example, a Universal Serial Bus (USB) connection.

[0023] With some implementations, the computing unit 103 may be directly or indirectly connected to a network interface 115 for communicating with other devices making up a network. The network interface 115 can translate data and control signals from the computing unit 103 into network messages according to one or more communication protocols, such as the transmission control protocol (TCP) and the Internet protocol (IP). Also, the network interface 115 may employ any suitable connection agent (or combination of agents) for connecting to a network, including, for example, a wireless transceiver, a modem, or an Ethernet connection. Such network interfaces and protocols are well known in the art, and thus is not discussed here in more detail.

[0024] The computing device 101 is illustrated as an example only, and it not intended to be limiting. Various embodiments may be implemented using one or more computing devices that include the components of the computing device 101 illustrated in FIG. 1, which include only a subset of the components illustrated in FIG. 1, or which include an alternate combination of components, including components that are not shown in FIG. 1. For example, various embodiments may be implemented using a multi-processor computer, aplurality of single and / or multiprocessor computers arranged into a network, or some combination of both.

[0025] With some implementations, the processor unit 105 can have more than one processor core. Accordingly, FIG. 2 illustrates an example of a multi-core processor unit 105 that may be employed with various embodiments. As seen in this figure, the processor unit 105 includes a plurality of processor cores 201A and 201B. Each processor core 201A and 20 IB includes a computing engine 203 A and 203B, respectively, and a memory cache 205 A and 205B, respectively. As known to those of ordinary skill in the art, a computing engine 203 A and 203B can include logic devices for performing various computing functions, such as fetching software instructions and then performing the actions specified in the fetched instructions. These actions may include, for example, adding, subtracting, multiplying, and comparing numbers, performing logical operations such as AND, OR, NOR and XOR, and retrieving data. Each computing engine 203 A and 203B may then use its corresponding memory cache 205A and 205B, respectively, to quickly store and retrieve data and / or instructions for execution.

[0026] Each processor core 201 A and 20 IB is connected to an interconnect 207. The particular construction of the interconnect 207 may vary depending upon the architecture of the processor unit 105. With some processor cores 201 A and 201B, such as the Cell microprocessor created by Sony Corporation, Toshiba Corporation and IBM Corporation, the interconnect 207 may be implemented as an interconnect bus. With other processor units 201A and 201B, however, such as the Opteron™ and Athlon™ dual-core processors available from Advanced Micro Devices of Sunnyvale, California, the interconnect 207 may be implemented as a system request interface device. In any case, the processor cores 201 A and 20 IB communicate through the interconnect 207 with an input / output interface 209 and a memory controller 210. The input / output interface 209 provides a communication interface to the bus 113. Similarly, the memory controller 210 controls the exchange of information to the system memory 107. With some implementations, the processor unit 105 may include additional components, such as a high-level cache memory accessible shared by the processor cores 201 A and 201B. The description of the computer network illustrated in FIG. 1 and FIG. 2 is provided as an example only and is not intended to suggest any limitation as to the scope of use or functionality of alternate embodiments.

[0027] FIG. 3 A illustrates an example system including a design verification system 310 and a system 320 that may be implemented according to various embodiments. FIG. 4Aillustrates a flowchart showing an example implementation of power estimation for an electronic circuit design 301, according to various embodiments. Referring to FIG. 3A, the design verification system 310, for example, implemented with a computer network 101 described above with reference to FIG. 1, can receive the circuit design 301 describing an electronic device as input. In some embodiments, the circuit design 301 can describe the electronic device both in terms of an exchange of data signals between components in the electronic device, such as hardware registers, flip-flops, combinational logic, or the like, and in terms of logical operations that can be performed on the data signals in the electronic device. The circuit design 301 can model the electronic device at a register transfer level (RTL), for example, with code in a hardware description language (HDL), such as System Verilog, Very high speed integrated circuit Hardware Design Language (VHDL), System C, or the like.

[0028] The design verification system 310 can perform functional verification of the circuit design 301 describing the electronic device. The design verification system 310 can utilize a test bench 302 to generate test stimulus during functional verification operations, such as clock signals, activation signals, power signals, control signals, data signals, or the like. The test stimulus, when grouped, may form test bench transactions capable of prompting operation of the circuit design 301 being functionally verified by the design verification system 310. In some embodiments, the test bench 302 can be written in an object-oriented programming language, for example, System Verilog or the like, which, when executed during elaboration, can dynamically generate test bench components for verification of the circuit design 301. A methodology library, for example, a Universal Verification Methodology (UVM) library, an Open Verification Methodology (OVM) library, an Advanced Verification Methodology (AVM) library, a Verification Methodology Manual (VMM) library, or the like, can be utilized as a base for creating the test bench 302. The design verification system 310 can record output created during functional verification of the circuit design 301 with stimulus from the test bench 302, called waveform data 305.

[0029] The design verification system 310, for example, implemented with a computer network 101 described above with reference to FIG. 1, can receive the circuit design 301 describing the electronic device, a parasitic file 303, a technology library 304, and the waveform data 305 generated during functional verification of the circuit design 301 by the design verification system 310. In some embodiments, the circuit design 301 can be specified as a gate-level netlist, which can be a synthesized version of the circuit design 301 specifiedin the register transfer level (RTL) format. The gate-level netlist can describe logic gates and their interconnections or nets in the electronic device. In other embodiments, the design verification system 310 can include a synthesis engine, which can synthesize the RTL version of the circuit design 301 into the gate-level netlist.

[0030] The system 320, for example, implemented with a computer network 101 described above with reference to FIG. 1, can receive the circuit design 301 describing the electronic device, a technology library 304, and the waveform data 305 generated during functional verification of logic gates in the circuit design 301 by the design verification system 310. In some embodiments, the circuit design 301 can be specified as a gate-level netlist, which can be a synthesized version of the circuit design 301 specified in the register transfer level (RTL) format. The gate-level netlist can describe logic gates and their interconnections or nets in the electronic device. In other embodiments, the design verification system 310 can include a synthesis engine, which can synthesize the RTL version of the circuit design 301 into the gate-level netlist.

[0031] The system 320 further obtains one or more capacitance models stored in a database 332, based on one or more attributes corresponding to nets present in the gate-level netlist. This enables defining of the electronic device described in the first electronic circuit design 301 as a group of electrically independent capacitance models. The technology library 304, for example, specified in a Liberty format, can describe standard cells in terms of timing information, internal energy, leakage power, pin capacitances, area, functionality, operating conditions, or the like.

[0032] FIG. 4A shows a flowchart of a method 400 for performing power estimation, in accordance with an embodiment. In an embodiment, the system includes an input processing system 322, that, in a block 402 of FIG. 4A, receives a request for performing power estimation for the first electronic circuit design (circuit design 301) describing the first electronic device. The request is indicative of one or more first nets in the first electronic circuit design. In an embodiment, the request includes the first electronic circuit design, a technology library 304, and the waveform data 305 generated during the functional verification of at least one connected component in the first electronic circuit design. In some embodiments, the first electronic circuit design can be specified as a gate-level netlist, which can be a synthesized version of the first electronic circuit design specified in the register transfer level (RTL) format. The gate-level netlist can describe logic gates and their interconnections or nets in the electronic device. The term ‘net’ as used herein refers to anelectrical connection between different components or points in an integrated circuit (IC) layout. In other embodiments, the design verification system 310 can include a synthesis engine, which can synthesize the RTL version of the first electronic circuit design into the gate-level netlist. The technology library 304, for example, specified in a Liberty format, can describe standard cells in terms of timing formation, power estimation, area, functionality, operating conditions, or the like.

[0033] The system 320 includes a data extraction system 324 that, in a block 404 of FIG. 4A, determines one or more first attributes associated with at least one of the first nets in the first electronic circuit design from the request. In the present embodiment, the one or more first attributes of the first net comprise at least a sink type, a source type and a fanout count, which can be extracted from the technology library 304.

[0034] The system 320 further includes a capacitance modelling system 326 that, in a block 406 of FIG. 4 A, identifies a capacitance model corresponding to the first net, from a plurality of capacitance models stored in the database 332, based on the one or more first attributes of the first net. The capacitance model corresponding to the first net is identified by identifying a capacitance class from a plurality of capacitance classes by comparing at least one of the first attributes to a corresponding second attribute associated with each of the capacitance classes. For example, each of the capacitance classes may be associated with a fanout count, say class 1 corresponds to fanout count of 1, class 2 corresponds to fanout count of 2 and so on. Similarly, a capacitance class may be associated with a plurality of second attributes, such as fanout count, sink port type and source port type too. The capacitance class having a set of second attributes matching the first attributes of the first net are identified. If the first attributes of the first net match the second attributes of a capacitance class, the capacitance class is identified. Further, the capacitance model associated with the capacitance class is obtained from the database 332. The system 320 further includes a capacitance model generation system 328, that generates capacitance models based on one or more parasitic files associated with one or more second electronic circuit designs. FIG. 3C shows a capacitance model generation system 328, in accordance with an embodiment, as described later. A method of forming the capacitance classes from a plurality of second electronic circuit designs, is also explained later, with reference to FIG. 6 and FIG. 3C.

[0035] The system 320 further includes a power estimation system 334, that, in a block 408 of FIG. 4 A, uses the capacitance model of the first net to perform the power estimation for the first electronic circuit design. In a preferred embodiment, the power estimation isperformed using event-by-event state dependent path dependent (SDPD) power computation technique.

[0036] FIG. 4B shows a method 410 of computing the power estimate, by the power estimation system 334, using path dependent and state dependent power analysis, in accordance with an embodiment. FIG. 3B shows the power estimation system 334 in accordance with an embodiment. Referring to FIGS. 3B and 4B, the power estimation system can include a mapping system 336 that, in a block 412 of FIG. 4B can map signals in the waveform data 305 to associated edges of logic gates in the first electronic circuit design. The edges of the logic gates can correspond to the inputs and / or the outputs of the logic gates associated with the arcs utilized for path dependent and state dependent dynamic power estimate.

[0037] The power estimation system 334 can include a waveform analysis system 338 to read the waveform data 305. In some embodiments, the waveform analysis system 338, in a block 414 of FIG. 4B, can implement a time-based iterator to read the waveform data 305 for signals corresponding to all logic gates. The time-based iterator can read the waveform data 305 according to the temporal performance of the functional verification as opposed to on a signal-by-signal basis, which allows the waveform analysis system 324 to read the waveform data 305 once for all signals, instead of once for each signal in the waveform data 305.

[0038] The waveform analysis system 338 can review the signals read from the waveform data 305 and, in a decision block 416 can detect when at least one of the signals in the waveform data 305 toggles or changes value. When, in the decision block 416, the waveform analysis system 338 detects a toggle of at least one of the signals read from the waveform data, execution can proceed to a block 418 of FIG. 4B, where a toggle density system 340 of the system 320 can correlate the detected signal toggle to one of multiple arcs of the logic gates based, at least in part, on the mapping. The mapping of the signals to the edges can indicate to the toggle density system 340 when value changes in the signals correspond to activations of arcs associated with the logic gates. In some embodiments, the mapping can identify when a signal corresponds to an edge of a logic gate associated with an arc for the logic gate and the toggle density system 340 can determine which arc of the logic gate was activated based on the toggle of the signal. Once the detected signal toggle has been correlated to the arc, an internal power estimation table look-up for the arc using a capacitance and slew value of the logical gate is performed within the technology library 304, for specific WHEN conditions.

[0039] When, in the decision block 416, the waveform analysis system 338 does not detect a toggle of at least one of the signals read from the waveform data 305 or after the toggle density system 340 correlates the detected signal toggle to one of multiple arcs of the logic gates, execution can proceed to the block 420, where the waveform analysis system 338 can determine whether additional waveform data 305 remains to be read. When, in the decision block 420, the waveform analysis system 338 determines additional waveform data 305 remains to be read, execution can return to the block 414, where the waveform analysis system 338 can continue to read the waveform data 305 with the time-based iterator. When, in the decision block 420, the waveform analysis system 338 determines no additional waveform data remains to be read, execution can proceed to the block 422, where a power consumption system 342 in the system 320 can compute a power estimate for each arc.

[0040] The power consumption system 342, in a block 424, can generate an estimate of power consumption for the first electronic circuit design based on an accumulation of the power estimates for the signals. In an embodiment, the technology library 304 can specify the internal power details for logic gates, for example, power estimates for different arcs associated with the logic gates. For example, the technology library 304 can include a power estimate table for each arc, which can be indexable by a combination of an input capacitance and a slew associated with the arcs of the logic gates. Each logic gate can have one or more different types of arcs, such an input-output (VO) arc or a self-arc. The VO arc can correspond to a path between an input of the logic gate and an output of the logic gate, for example, activated when a change occurs on the output of the logic gate. The self-arc also can correspond to a path between an input of the logic gate and an output of the logic gate, for example, activated when a change occurs on the input of the logic gate, while the output remains the same. Embodiments of the power estimation look-up table are described below in greater detail with reference to FIG. 5. FIG. 5 illustrates an example power estimation lookup table 500 utilized to implement state dependent and path dependent power estimation according to various embodiments. Referring to FIG. 5, the power estimation look-up table 500 can correspond to an arc of a logic gate described in a technology library, for example, specified in a Liberty format. The power estimation look-up table 500 can correspond to a two-dimensional array of energy utilization values 503 associated with dynamic power consumption for the arc of the logic gate under differing conditions. The columns of the power estimation look-up table 500 can correspond to different input capacitance value 501 loading the input of the logic gate associated with the arc. The rows of the power estimationlook-up table 500 can correspond to different slew values 502 for the input of the logic gate associated with the arc. The combination of an input capacitance value 501 and a slew value 502 can identify one of the energy utilization values 503 in the power estimation look-up table 500. In some embodiments, the power consumption system 342 can add the power estimates for each of the arcs, which can correspond to a total dynamic energy estimate for the first electronic circuit design. The power consumption system 342 also can determine a total power estimate for the first electronic circuit design by dividing the total dynamic energy estimate by the duration of the functional verification of the first electronic circuit design.

[0041] The power consumption system 342, in block 426, can generate a power report file 335 based on the power estimation on an output device. In an embodiment, the power report file 335 provides a static power and a dynamic power associated with the first electronic circuit design.

[0042] FIG. 6 shows a method 600 of creating a database of capacitance models, in accordance with an embodiment. Referring to FIGS. 3C and 6, the capacitance model generation system 328 includes an extraction system 344 that, at step 602 of FIG. 6 receives one or more parasitic files descriptive of one or more second electronic circuit designs. The parasitic files are, for example, in Standard Parasitic Exchange Format. SPEF is an IEEE standard file format that represents the parasitic resistance and capacitance of wires. The extraction system 344, at step 604 of FIG. 6, extracts a plurality of second attributes associated with one or more second nets in each of the second electronic circuit designs, from the respective parasitic files. Each of the second nets in the second electronic circuit design is associated with a capacitance value. The capacitance model generation system 328 further includes a bucketing system 346 that, at step 606 of FIG. 6, groups the second nets in the second electronic circuit design, into a plurality of capacitance classes based on commonalities between the corresponding second attributes. For example, all second nets with the same sink type, source type and fanout count are grouped into a single capacitance class. The capacitance model generation system 328 further includes a capacitance configuring system 348 that, at step 608 of FIG. 6, can compute a representative capacitance corresponding to each of the capacitance classes based on capacitance values of the second nets in the capacitance class. In an embodiment, the capacitance configuring system 348 further generates the plurality of capacitance models based on the second attributes of the nets in each of the capacitance classes and the corresponding representative capacitance.

[0043] Embodiments of the power estimation described above can leverage parasitic files such as Switching Parasitic Extraction Files (SPEFs) from previous electronic circuit designs to create capacitance models, facilitating accurate power estimation at the RTL stage without the need for exhaustive Place and Route (PnR) processes. This approach significantly improves estimation accuracy, reduces design time, and enhances efficiency, particularly compared to traditional wire load models and placement-routing methods. This also simplifies data management through bucketing based on shared net characteristics and calculating representative capacitance values, ensuring efficient handling of large and complex designs.

[0044] The system and apparatus described above may use dedicated processor systems, micro controllers, programmable logic devices, microprocessors, or any combination thereof, to perform some or all of the operations described herein. Some of the operations described above may be implemented in software and other operations may be implemented in hardware. Any of the operations, processes, and / or methods described herein may be performed by an apparatus, a device, and / or a system substantially similar to those as described herein and with reference to the illustrated figures.

[0045] The processing device may execute instructions or "code" stored in memory. The memory may store data as well. The processing device may include, but may not be limited to, an analog processor, a digital processor, a microprocessor, a multi-core processor, a processor array, a network processor, or the like. The processing device may be part of an integrated control system or system manager or may be provided as a portable electronic device configured to interface with a networked system either locally or remotely via wireless transmission.

[0046] The processor memory may be integrated together with the processing device, for example RAM or FLASH memory disposed within an integrated circuit microprocessor or the like. In other examples, the memory may comprise an independent device, such as an external disk drive, a storage array, a portable FLASH key fob, or the like. The memory and processing device may be operatively coupled together, or in communication with each other, for example by an I / O port, a network connection, or the like, and the processing device may read a file stored on the memory. Associated memory may be "read only" by design (ROM) by virtue of permission settings, or not. Other examples of memory may include, but may not be limited to, WORM, EPROM, EEPROM, FLASH, or the like, which may be implemented in solid state semiconductor devices. Other memories may comprise moving parts, such as aknown rotating disk drive. All such memories may be "machine-readable" and may be readable by a processing device. It must be understood that the memory type directly affects power estimation, and distinguishing between volatile and non-volatile types is essential for accurate analysis. For example, volatile memory like DRAM consumes more power due to continuous refreshing, whereas non-volatile memory like Flash retains data with minimal power consumption.

[0047] Operating instructions or commands may be implemented or embodied in tangible forms of stored computer software (also known as "computer program" or "code"). Programs, or code, may be stored in a digital memory and may be read by the processing device. “Computer-readable storage medium" (or alternatively, "machine-readable storage medium") may include all of the foregoing types of memory, as well as new technologies of the future, as long as the memory may be capable of storing digital information in the nature of a computer program or other data, at least temporarily, and as long at the stored information may be "read" by an appropriate processing device. The term "computer-readable" may not be limited to the historical usage of "computer" to imply a complete mainframe, minicomputer, desktop or even laptop computer. Rather, "computer-readable" may comprise storage medium that may be readable by a processor, a processing device, or any computing system. Such media may be any available media that may be locally and / or remotely accessible by a computer or a processor, and may include volatile and non-volatile media, and removable and non-removable media, or any combination thereof.

[0048] A program stored in a computer-readable storage medium may comprise a computer program product. For example, a storage medium may be used as a convenient means to store or transport a computer program. For the sake of convenience, the operations may be described as various interconnected or coupled functional blocks or diagrams. However, there may be cases where these functional blocks or diagrams may be equivalently aggregated into a single logic device, program, or operation with unclear boundaries. Conclusion

[0049] While the application describes specific examples of carrying out embodiments of the disclosure, those skilled in the art will appreciate that there are numerous variations and permutations of the above-described systems and techniques that fall within the spirit and scope of the disclosure as set forth in the appended claims. For example, while specific terminology has been employed above to refer to electronic design automation processes, itshould be appreciated that various examples of the disclosure may be implemented using any desired combination of electronic design automation processes.

[0050] One of skill in the art will also recognize that the concepts taught herein can be tailored to a particular application in many other ways. In particular, those skilled in the art will recognize that the illustrated examples are but one of many alternative implementations that are apparent upon reading this disclosure.

[0051] Although the specification may refer to “an,” “one,” “another,” or “some” example(s) in several locations, this does not necessarily mean that each such reference is to the same example(s), or that the feature only applies to a single example.List of References101 computing device103 computing unit105 processing unit107 system memory109 read-only memory (ROM)111 random-access memory (RAM)113 bus115-123 peripheral devices115 network interface117 hard disk drive119 optical disk drive121 input devices123 output devices201A and 201B processor cores203 A and 203B computing engine205A and 205B memory cache207 interconnect209 input / output interface210 memory controller310 design verification system301 first electronic circuit design302 test benchtechnology library waveform data system input processing system data extraction system capacitance modeling system capacitance model generation system database power estimation system power report file mapping system waveform analysis system toggle density system power consumption system extraction system bucketing system capacitance configuring system

Claims

CLAIMS1. A computer-implemented method for power estimation in an electronic circuit design including at least one logic gate, the method comprising:• receiving a request for performing a power estimation for a first electronic circuit design of a first electronic device, wherein the request is indicative of one or more first nets in the first electronic circuit design;• determining one or more first attributes associated with at least one first net of the one or more first nets in the first electronic circuit design from the request;• identifying a capacitance model corresponding to the at least one first net, from a plurality of capacitance models stored in a database, based on the one or more first attributes of the at least one first net;• using the capacitance model of the at least one first net to perform the power estimation for the first electronic circuit design; and• generating a power report file based on the power estimation on an output device.

2. The computer-implemented method of claim 1, wherein the one or more first attributes of the at least one first net comprise at least a sink type, a source type, and a fanout count associated with the at least one first net.

3. The computer-implemented method of claim 1, wherein the plurality of capacitance models stored in the database is generated by:• receiving one or more parasitic files descriptive of one or more second electronic circuit designs;• extracting a plurality of second attributes associated with one or more second nets in each second electronic circuit design of the one or more second electronic circuit designs, from the respective parasitic files, wherein each second net of the one or more second nets in the respective second electronic circuit design is associated with a capacitance value;• grouping the one or more second nets in the second electronic circuit designs into a plurality of capacitance classes based on commonalities between the corresponding second attributes;• computing a representative capacitance corresponding to each capacitance class of the capacitance classes based on the capacitance values of the one or more second nets in the capacitance class; and• generating the plurality of capacitance models based on the second attributes of the one or more second nets in each capacitance class of the capacitance classes and the corresponding representative capacitance.

4. The computer-implemented method of claim 3, wherein the one or more second attributes associated with each second net comprise at least a driving port type, a sink port type, a fanout count, and the capacitance value associated with the respective second net.

5. The computer-implemented method of claim 3, wherein the representative capacitance of the capacitance class is an average of the capacitance values of the one or more second nets in the capacitance class.

6. The computer-implemented method of claim 3, wherein the identifying of the capacitance model comprises:• identifying a capacitance class from the plurality of capacitance classes by comparing at least one first attribute of the first attributes to the corresponding second attribute associated with each capacitance class of the capacitance classes; and• obtaining the capacitance model associated with the capacitance class identified from the database.

7. The computer-implemented method of claim 1, wherein the using of the capacitance model comprises:• performing state dependent path dependent power analysis based on the capacitance value.

8. The computer-implemented method of claim 7, wherein the request further comprises waveform data generated during a functional verification of the first electronic circuitdesign, and wherein the waveform data enables state dependent path dependent power analysis.

9. A system for power estimation in an electronic circuit design including at least one logic gate, the system comprising: a memory system configured to store computer-executable instructions; and a computing system, which, in response to execution of the computer-executable instructions, is configured to:• receive a request for performing a power estimation for a first electronic circuit design of a first electronic device, wherein the request is indicative of one or more first nets in the first electronic circuit design;• determine one or more first attributes associated with at least one first net of the one or more first nets in the first electronic circuit design from the request;• identify a capacitance model corresponding to the at least one first net, from a plurality of capacitance models stored in a database, based on the one or more first attributes of the at least one first net;• use the capacitance model of the at least one first net to perform the power estimation for the first electronic circuit design; and• generate a power report file based on the power estimation on an output device.

10. The system of claim 9, wherein the computing system, in response to execution of the computer-executable instructions, is further configured to: generate the plurality of capacitance models stored in the database by:• receiving one or more parasitic files descriptive of one or more second electronic circuit designs;• extracting a plurality of second attributes associated with one or more second nets in each second electronic circuit design of the one or more second electronic circuit designs, from the respective parasitic files, wherein each second net of the one or more second nets in the respective second electronic circuit design is associated with a capacitance value;• grouping the one or more second nets in the respective second electronic circuit design, into a plurality of capacitance classes based on commonalities between the corresponding second attributes;• computing a representative capacitance corresponding to each capacitance class of the capacitance classes based on capacitance values of the one or more second nets in the capacitance class; and• generating the plurality of capacitance models based on the second attributes of the one or more second nets in each capacitance class of the capacitance classes and the corresponding representative capacitance.

11. The system of claim 10, wherein the computing system, in response to execution of the computer-executable instructions, is further configured to: identify the capacitance model corresponding to the first net based on the one or more first attributes by:• identifying a capacitance class from the plurality of capacitance classes by comparing at least one first attribute of the first attributes to the corresponding second attribute associated with each capacitance class of the capacitance classes; and• obtaining the capacitance model associated with the respective capacitance class identified from the database.

12. The system of claim 9, wherein the computing system, in response to execution of the computer-executable instructions, is further configured to: use the capacitance model of the at least one first net to perform the power estimation for the first electronic circuit design by performing state dependent path dependent power analysis based on the capacitance value.

13. The system of claim 12, wherein the request further comprises waveform data generated during a functional verification of the first electronic circuit design, and wherein the waveform data enables state dependent path dependent power analysis.

14. An apparatus comprising at least one computer-readable memory device storing instructions configured to cause one or more processing devices to perform operations comprising:• receiving a request for performing power estimation for a first electronic circuit design of a first electronic device, wherein the request is indicative of one or more first nets in the first electronic circuit design;• determining one or more first attributes associated with at least one first net of the one or more first nets in the first electronic circuit design from the request;• identifying a capacitance model corresponding to the at least one first net, from a plurality of capacitance models stored in a database, based on the one or more first attributes of the at least one first net;• using the capacitance model of the at least one first net to perform the power estimation for the first electronic circuit design; and• generating a power report file based on the power estimation on an output device.

15. The apparatus of claim 14, wherein the plurality of capacitance models stored in the database is generated by:• receiving one or more parasitic files descriptive of one or more second electronic circuit designs;• extracting a plurality of second attributes associated with one or more second nets in each second electronic circuit design of the one or more second electronic circuit designs, from the respective parasitic files, wherein each second net of the one or more second nets in the respective second electronic circuit design is associated with a capacitance value;• grouping the one or more second nets in the respective second electronic circuit design into a plurality of capacitance classes based on commonalities between the corresponding second attributes;• computing a representative capacitance corresponding to each capacitance class of the capacitance classes based on capacitance values of the one or more second nets in the capacitance class; and• generating the plurality of capacitance models based on the second attributes of the one or more second nets in each capacitance class of the capacitance classes and the corresponding representative capacitance.

16. The apparatus of claim 15, wherein the representative capacitance of a capacitance class is an average of the capacitance values of the one or more second nets in the capacitance class.

17. The apparatus of claim 15, wherein the identifying of the capacitance model comprises:• identifying a capacitance class from the plurality of capacitance classes by comparing at least one first attribute of the one or more first attributes to the corresponding second attribute associated with each capacitance class of the capacitance classes; and• obtaining the capacitance model associated with the capacitance class identified from the database.

18. The apparatus of claim 14, wherein the using of the capacitance model comprises:• performing state dependent path dependent power analysis based on the capacitance value.

19. The apparatus of claim 18, wherein the request further comprises waveform data generated during a functional verification of the first electronic circuit design, and wherein the waveform data enables state dependent path dependent power analysis.

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