Approximation of least reliable bits for soft decoding of error correction codes

Abstract

An Error Correction Code (ECC) decoder (32) includes a Least Reliable Bit (LRB) approximator (36) and decoding circuitry (40, 44). The LRB approximator is configured to receive a set of soft metrics corresponding to respective bits of an input codeword of the ECC, and to approximate, from among the bits of the input codeword, one or more LRBs that are least reliable in the input codeword according to the soft metrics. The decoding circuitry is configured to decode the input codeword based on the soft metrics and the approximated LRBs.

Description

[0001] PCT / US25 3i28S85TAugust 2025 (25.08.2025)

[0002] APPROXIMATION OF LEAST RELIABLE BITS FOR SOFT DECODING OF ERROR CORRECTION CODES

[0003] CROSS-REFERENCE TO RELATED APPLICATIONS

[0004] This application claims the benefit of U.S. Provisional Patent Application 63 / 700,694,

[0005] 5 filed September 29, 2024, whose disclosure is incorporated herein by reference.

[0006] FIELD OF THE INVENTION

[0007] The present invention relates generally to Error Correction Coding (ECC), and particularly to methods and systems for approximation of Least Reliable Bits (LRB).

[0008] BACKGROUND OF THE INVENTION

[0009] 10 Error correction codes (ECCs) are widely used in digital communication systems and data storage devices to detect and correct errors that may occur during data transmission or storage. An ECC adds redundancy to the original data, allowing the receiver or reader to identify and correct errors. Soft decoding techniques, which utilize reliability information associated with each received bit, have become increasingly popular due to their superior error-correcting performance compared to hard decision decoding.

[0010] In soft decoding, soft metrics such as Log-Likelihood Ratios (LLRs), are commonly used to represent the reliability of each received bit. The LLR values are typically extracted from demodulated symbols and provide a measure of the probability that a particular bit is a 'O' or a T'. The magnitude of an LLR indicates the reliability of the corresponding bit, with larger

[0011] 20 magnitudes suggesting higher reliability.

[0012] Various schemes have been developed for soft decoding of ECCs. Many of these schemes are iterative. In a typical iteration of a soft decoder, the decoder calculates a syndrome and a set of Least Reliable Bits (LRBs). The LRBs, also known as Least Reliable Positions (LRPs), comprise the indices of the bits in the codeword that correspond to the smallest- magnitude LLRs. The decoder generates test patterns by flipping bit values of selected LRBs and attempting to decode the resulting codewords. One common example of such a scheme is the well-known Chase algorithm.

[0013] SUMMARY OF THE INVENTION

[0014] An embodiment of the present invention that is described herein provides an Error

[0015] 30 Correction Code (ECC) decoder including a Least Reliable Bit (LRB) approximator and decoding circuitry. The LRB approximator is configured to receive a set of soft metrics corresponding to respective bits of an input codeword of the ECC, and to approximate, from PCT / US25 3i28S85TAugust 2025 (25.08.2025) among the bits of the input codeword, one or more LRBs that are least reliable in the input codeword according to the soft metrics. The decoding circuitry is configured to decode the input codeword based on the soft metrics and the approximated LRBs.

[0016] In some embodiments, the soft metrics are Log Likelihood Ratios (LLRs).

[0017] 5 In an example embodiment, the soft metrics are represented using n-bit values, and the LRB approximator is configured to approximate the LRBs by processing k-bit approximations of the soft metrics, k<n. In another embodiment, the LRB approximator is configured to approximate the LRBs by excluding the soft metrics that are larger than a defined threshold value.

[0018] 10 In yet another embodiment, the bits of the input codeword are classified into at least first and second types, and the LRB approximator is configured to approximate the LRBs by allowing no more that a first number of LRBs among the bits of the first type, and no more than a second number of LRBs among the bits of the second type, the first number being different from the second number.

[0019] In a disclosed embodiment, the LRB approximator is configured to approximate the LRBs by allocating respective maximal quotas for the LRBs in respective incremental batches of the soft metrics. In an embodiment, the LRB approximator is configured to output at least some of the LRBs incrementally, to match a progress of the decoding circuitry. In another embodiment, the decoding circuitry is configured to calculate a syndrome of the input codeword,

[0020] 20 and the LRB approximator is configured to approximate the LRBs by excluding one or more combinations of the LRBs based on the syndrome.

[0021] There is additionally provided, in accordance with an embodiment of the present invention, an error correction coding method including receiving a set of soft metrics corresponding to respective bits of an input codeword of an Error Correction Code (ECC), and approximating, from among the bits of the input codeword, one or more LRBs that are least reliable in the input codeword according to the soft metrics. The input codeword is decoded based on the soft metrics and the approximated LRBs.

[0022] The present invention will be more fully understood from the following detailed description of the embodiments thereof, taken together with the drawings in which:

[0023] 30 BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Fig. l is a block diagram that schematically illustrates a receiver comprising a soft ECC decoder that uses LRB approximation, in accordance with an embodiment of the present invention; and PCT / US25 3i28S85TAugust 2025 (25.08.2025)

[0025] Figs. 2-4 are flow charts that schematically illustrate example methods for LRB approximation, in accordance with embodiments of the present invention.

[0026] DETAILED DESCRIPTION OF EMBODIMENTS

[0027] OVERVIEW

[0028] 5 Embodiments that are described herein address a critical challenge in Error Correction Code (ECC) decoding: the efficient identification of Least Reliable Bits (LRBs). In soft decoders, for example decoders employing the Chase decoding algorithm, the process of finding LRBs is one of the dominant factors that determine chip area and power consumption. As data transmission rates and storage densities increase, there is a pressing need for more efficient LRB

[0029] 10 selection methods that can maintain decoding performance while reducing hardware complexity and energy usage.

[0030] To address this challenge, in some embodiments the soft decoder approximates the LRBs rather than attempts to unconditionally find the exact LRBs. In the present context, the phrase "approximating LRBs", in various grammatical forms, means identifying the LRBs from a given set of soft metrics (e.g., LLRs) while allowing some small deviations from the exact set of LRBs. Deviations in this context may include identifying an LRB that is not genuinely an LRB, or missing a genuine LRB. Such deviations, if rare or small, are tolerable in most practical cases. In return, schemes that approximate the LRBs require far less resources (e.g., computation time, chip area, power consumption) relative to schemes that aim to find the exact LRBs

[0031] 20 unconditionally.

[0032] Various example schemes for approximating LRBs are described herein. The disclosed techniques are applicable to a wide variety of ECC types and soft decoder architectures.

[0033] SYSTEM DESCRIPTION

[0034] Fig. l is a block diagram that schematically illustrates a receiver comprising a soft ECC decoder that uses LRB approximation, in accordance with an embodiment of the present invention. The figure shows a receiver 20 that processes input samples of a received signal through multiple stages, so as to extract and decode bits. The received signal is encoded with an ECC.

[0035] Receiver 20 comprises a demodulator 24, which receives the input samples and converts

[0036] 30 them into symbols. Each symbol conveys one or more bits. The symbols are then passed to a Log Likelihood Ratio (LLR) extractor 28, which calculates a respective LLR value for each bit. PCT / US25 3i28S85TAugust 2025 (25.08.2025)

[0037] The LLR values (also referred to as "LLRs" for brevity) are input to an iterative ECC decoder 32, which decodes the ECC and outputs decoded bits.

[0038] An inset at the bottom of the figure shows the internal structure of ECC decoder 32, in accordance with an example embodiment. In this example, decoder 32 comprises a Least

[0039] 5 Reliable Bits (LRB) approximator 36, which implements one or more of the approximate LRB selection techniques described herein. LRB approximator 36 efficiently identifies a specified number of LRBs from among the input LLR values, using methods that reduce computational complexity and hardware requirements.

[0040] Iterative ECC decoder 32 also comprises a syndrome calculator 40 and a Chase decoder

[0041] 10 44. Syndrome calculator 40 processes the input LLRs to calculate syndromes. Chase decoder 44 uses the approximated LRBs and syndrome information to perform iterative decoding operations on the received LLRs, so as to decode the ECC.

[0042] In an example embodiment, the ECC is a Bose-Chaudhuri-Hocquenghem (BCH) code, with each codeword comprising N bits. Alternatively, however, any other suitable ECC can be used. The number of LRBs that LRB approximator selects per codeword may be, for example, 4 LRBs, 6 LRBs, 8 LRBs, or any other suitable number.

[0043] The configuration of receiver 20 shown in Fig. 1, and the configurations of its components such as ECC decoder 32, are example configurations that are chosen purely for the sake of conceptual clarity. Any other suitable configurations can be used in alternative

[0044] 20 embodiments. For example, partitioning of ECC decoder 32 into elements, and the task partitioning ("division of labor") among the various elements, may differ from the example of Fig. 1. In the present context, syndrome calculator 40 and Chase decoder 44 are referred to jointly as "decoding circuitry". More generally, ECC decoder 32 may comprise, in addition to LRB selector 36, decoding circuitry having any other suitable configuration or functionality. For example, other types of decoders that use LRBs, not necessarily using the Chase algorithm, may be used. As yet another example, the disclosed techniques are not limited to use with LLRs, and may be used with any other suitable type of soft metrics.

[0045] In various embodiments, receiver 20 shown in Fig. 1, and its components such as ECC decoder 32, may be implemented using suitable software, using suitable hardware such as one

[0046] 30 or more Application-Specific Integrated Circuits (ASICs) or Field-Programmable Gate Arrays (FPGAs), or using a combination of hardware and software elements.

[0047] In some embodiments, certain functions of ECC decoder 32, e.g., the functions of LRB selector 36, may be implemented using one more general-purpose processors, which are programmed in software to carry out the techniques described herein. The software may be PCT / US25 3i28S85TAugust 2025 (25.08.2025) downloaded to the processors in electronic form, over a network, for example, or it may, alternatively or additionally, be provided and / or stored on non-transitory tangible media, such as magnetic, optical, or electronic memory.

[0048] Fig. 2 is a flow chart that schematically illustrates an example method for LRB

[0049] 5 approximation, in accordance with an embodiment of the present invention. The method begins at an input stage 50, in which LRB approximator 36 receives LLR values of bits of an input codeword.

[0050] The process then branches into two operations, which may be executed in parallel: a syndrome calculation stage 54, in which syndrome calculator 40 calculates a syndrome from the

[0051] 10 input codeword, and an LRB approximation stage 58, in which LRB approximator 36 approximates LRBs using one or more of the techniques described herein. The results from both parallel stages feed into a decoding stage 62, in which chase decoder 44 attempts to find a candidate codeword by iterating over the approximated LRBs.

[0052] Following the decoding attempt, the method proceeds to an iteration checking stage 66, in which iterative ECC decoder 32 checks whether the maximal number of iterations specified for the decoding process has been reached. If iterative ECC decoder 32 determines that the maximum iterations have not been reached yet (NO branch), the method loops back to perform the next decoding iteration.

[0053] If iterative ECC decoder 32 determines that the maximal number of iterations has been

[0054] 20 reached (YES branch), the method proceeds to a solution checking stage 70. In this stage, iterative ECC decoder 32 checks whether a valid solution has been found, i.e., whether the current candidate codeword is a valid codeword of the ECC. If so (YES branch), the method proceeds to a success termination stage 74, in which iterative ECC decoder 32 outputs the decoded codeword. If not (NO branch), the method moves to a failure termination stage 78, where iterative ECC decoder 32 indicates a decoding failure.

[0055] The method flow of Fig. 2 is an example flow that is chosen purely for the sake of conceptual clarity. In alternative embodiments, any other suitable flow can be used. For example, in some embodiments, if a valid codeword is found before the maximal number of iterations is performed, the iterative decoder may output the codeword once found. As another

[0056] 30 example, in some embodiments the iterative decoder may use a termination condition that terminates the iterative decoding process before executing the maximal number of iterations. PCT / US25 3i28S85TAugust 2025 (25.08.2025)

[0057] EXAMPLE LRB APPROXIMATION SCHEMES

[0058] 1: Reducing the number of LLR bits in comparison operations

[0059] In some embodiments, LRB approximator 36 approximates the LRBs by reducing the number of bits used in comparing LLRs to one another. In these embodiments, LLR extractor

[0060] 5 28 represents the LLRs using n-bit values. Instead of comparing the full n-bit LLR values, LLR approximator 36 identifies the LRBs using k-bit approximations of the LLRs where k is less than n. This reduction in bit precision allows for more efficient comparison operations, as it reduces the size and power consumption of the comparison logic required to identify the LRBs.

[0061] In various embodiments, LRB approximator 36 may use any suitable technique for deriving k-bit approximations from the n-bit LLRs. In one example, approximator 36 uses the k Least-Significant Bits (LSBs) of the LLRs and saturate the higher-order bits, under the assumption that larger values will not qualify as LRBs anyhow. As another example, approximator 36 may round or truncate the n-bit LLRs to produce respective k-bit approximations.

[0062] 15 In an example embodiment, the original LLRs are represented using eight bits (n=8), and LRB approximator 36 identifies the LRBs by comparing 6-bit approximations (k=6) of the LLRs. Alternatively, any other suitable n and k values can be used.

[0063] Typically, although the LRBs are identified using k-bit approximations, subsequent processing (e.g., in Chase decoder 44) is performed using the complete n-bit LLRs.

[0064] 20 2: Skipping comparison of large LLRs

[0065] In some embodiments, LRB approximator 36 approximates the LRBs by excluding LLRs that are larger than a defined threshold value. In these embodiments, LRB approximator 36 applies a predefined threshold to filter out LLR values that exceed a certain reliability level, since larger magnitude LLRs correspond to more reliable bits that are unlikely to be selected as LRBs.

[0066] This threshold-based filtering allows LRB approximator 36 to reduce the computational burden by eliminating highly reliable bits from consideration at an early stage. Instead of processing all received LLR values, the approximator focuses its comparison operations only on the subset of LLR values that fall below the defined threshold.

[0067] 30 In various embodiments, LRB approximator 36 may use any suitable technique for setting the threshold value. In one example, the threshold may be predetermined based on system requirements or channel characteristics. As another example, the threshold may be dynamically adjusted based on real-time decoding performance metrics or changing channel conditions. PCT / US25 3i28S85TAugust 2025 (25.08.2025)

[0068] In an example embodiment, LRB approximator 36 may apply a threshold corresponding to a reliability level that eliminates the top 50% of most reliable bits, allowing the remaining LLR values to be processed for LRB selection. Alternatively, any other suitable threshold level can be used.

[0069] 5 If the resulting number of LRB candidates (after filtering using the threshold) is smaller than the specified number of LRBs, LRB approximator 36 may use the smaller number, or it may add additional candidates arbitrarily to reach the specified number.

[0070] 3: Differential LRB allocation by bit type

[0071] In some practical scenario, the bits of the input codeword can be classified in advance

[0072] 10 into several (e.g., two) types, such that one type is more likely to contain LRBs than another.

[0073] Consider, for example, a scenario in which the bits originate from different types of modulation symbols, and their LLRs therefore have different reliability distributions. Examples of such cases can be found, for example, in an article by Pyndiah, entitled "Near-Optimum Decoding of Product Codes: Block Turbo Codes," IEEE Transactions on Communications, vol. 46, no. 8, August 1998, pages 1003-1010. A demonstrative example is four-symbol Pulse- Amplitude Modulation (PAM4) in which there are four possible modulation symbols ("-3", "- 1", "1" and "3"). A PAM4 symbol is typically represented by two bits, one encoding the sign of the symbol ("+" or "-") and the other encoding the symbol magnitude (" 1" or "3"). The bits encoding the signs of the PAM4 symbols are more reliable than the bits encoding the symbol

[0074] 20 magnitudes, and therefore less likely to contain LRBs.

[0075] As another example, in some iterative decoding schemes, the LLRs at the input to a soft- decoder may differ in the number of previous iterations they have gone through. Consider an iterative decoder that performs multiple iterations, each invoking a soft-decoder. The input to the soft-decoder may comprise multiple types of LLRs: for some of the bits, the input LLRs have been processed in a certain number of previous iterations, whereas for other bits the LLRs have been processed in a different number of previous iterations. The number of previous iterations affects the reliability distribution of the bits — more previous iterations generally imply higher reliability — and therefore the likelihood of a bit to be LRB differs between those LLR types.

[0076] 30 An example decoding scheme of this sort is an Open Forward Error Correction (OFEC) decoder. OFEC codes are described, for example, in an Optical Internetworking Forum (OIF) specification entitled "OIF Implementation Agreement for 800ZR Coherent Interfaces," OIF- 800ZR-01.0, October 8, 2024. In a typical OFEC decoder, each soft-decoder operates on a block PCT / US25 3i28S85TAugust 2025 (25.08.2025) divided into two types of bits, often called "front" and "back" bits. In that setting, the front bits have been decoded in a certain number (denoted S) of previous iterations, while the back bits were decoded in S+l prior iterations. Therefore, in this example the back bits are typically more reliable than front bits, and therefore back-bit LLRs are less likely to be LRBs than front-bit

[0077] 5 LLRs.

[0078] In some embodiments, LRB approximator 36 takes advantage of this a-priori information, and allocates different numbers of LRBs to the different types of bits. For example, when the bits of the input codeword are classified into a first type and a second type, LRB approximator 36 allows no more than a first number of LRBs (denoted Nl) among the bits of

[0079] 10 the first type, and no more than a second number of LRBs (denoted N2) among the bits of the second type, where the first number is different from the second number.

[0080] Note that N1+N2 may be larger than the total number of LRBs (denoted N) specified for the entire codeword. ForN=6, for example, LRB approximator 36 may allocateNl=3 andN2=5. Alternatively, any other suitable allocation scheme can be used. After finding the Nl least reliable bits among the bits of the first type, and finding the N2 least reliable bits among the bits of the second type, LRB approximator 36 finds the N least reliable bits among the Nl bits and the N2 bits.

[0081] Fig. 3 is a flow chart that schematically illustrates an example method for LRB approximation, in accordance with an embodiment of the present invention. The method begins

[0082] 20 at a bit classification stage 80, in which LRB approximator 36 classifies the bits of the input codeword into first and second types based on their characteristics, error probabilities, or positions within the codeword. The process then proceeds to an LRB allocation stage 84, in which LRB approximator 36 allocates a first number Nl of LRBs to bits of the first type and a second number N2 of LRBs to bits of the second type, in which Nl is different from N2.

[0083] Following the allocation, the method branches into two operations, which may be executed in parallel or sequentially. In an Nl identification stage 88, LRB approximator 36 identifies the Nl least reliable bits among the bits of the first type. In an N2 identification stage 92, LRB approximator 36 identifies the N2 least reliable bits among the bits of the second type.

[0084] The results from the two LRB identification stages feed into an LRB merging stage 96,

[0085] 30 in which LRB approximator 36 selects the final N LRBs from among the combined set of Nl and N2 candidate LRBs identified in the previous stages. PCT / US25 3i28S85TAugust 2025 (25.08.2025)

[0086] 4: Incremental LRB allocation by batch processing

[0087] In some scenarios, e.g., in receivers that operate in a pipelined manner, the LLRs of the input codewords become available to ECC decoder 32 in incremental batches over time, not all at once. In some embodiments, LRB approximator 36 performs the LRB approximation process

[0088] 5 incrementally, as well, to match the availability schedule of the LLRs.

[0089] In some embodiments, LRB approximator 36 allocates a maximal quota for the number of LRBs that can be selected in each respective incremental batch of LLRs. For example, consider a receiver that calculates a total of 256 LLRs for an input codeword, in eight successive batches of thirty-two LLRs. LRB approximator 36 may allocate a maximum of four LRBs per

[0090] 10 batch. Alternatively, any other suitable batch size and quota allocation can be used. The total number of LRBs for the entire codeword is typically less than the number of LRBs per batch times the number of batches.

[0091] The incremental approach enables the LRB approximator to process each batch of LLRs as it becomes available, and also reduces the overall number of comparisons. Approximator 36 gradually accumulates the required total number of LRBs from the per-batch results.

[0092] Fig. 4 is a flow chart that schematically illustrates an example method for LRB approximation, in accordance with an embodiment of the present invention. The flow chart illustrates a single iteration of the above-described batch processing scheme.

[0093] The method begins at an LLR-batch input stage 100, in which LRB approximator 36

[0094] 20 receives a batch of N1 input LLR values. The process then proceeds to an LLR retaining stage 104, in which LRB approximator 36 retains only the N2 LLR values with the lowest reliabilities from the current batch, in which N2 is less than N1 and represents the quota allocation for the current batch.

[0095] The method continues to an LLR merging stage 108, in which LRB approximator 36 compares the N2 LLR values from the current batch with N3 intermediate LLR values retained from previous iteration, and selects the N3 LLR values with the lowest reliabilities from this combined set. N3 is typically equal to the total number of LRBs specified for the codeword.

[0096] The process of Fig. 4 is typically repeated until all LLR batches have been processed. At the end of the process, the N3 intermediate LLRs correspond to the final set of LRBs.

[0097] 30 5: Incremental LRB output matching decoder flow

[0098] In some embodiments, LRB approximator 36 outputs at least some of the LRBs incrementally, to match the progress of the subsequent decoding circuitry that uses the LRBs. In example embodiments, LRB approximator 36 optimizes its output rate and format to align PCT / US25 3i28S85TAugust 2025 (25.08.2025) with the input requirements of chase decoder 44, rather than computing and outputting all LRBs simultaneously.

[0099] This flow-matched output allows LRB approximator 36 to extend the computation time for individual LRBs, and deliver LRBs when chase decoder 44 requires them for processing.

[0100] 5 Approximator 36 typically provides the LRBs in a sequence that enables chase decoder 44 to start processing test patterns as soon as the first LRBs become available.

[0101] In various embodiments, LRB approximator 36 may use any suitable technique for matching the output flow to the decoder requirements. In one example, the approximator may output LRBs in the order that chase decoder 44 will process them for test pattern generation. As another example, the output timing may be synchronized with the decoder's enumeration sequence to minimize idle time in the decoding pipeline.

[0102] In an example embodiment, chase decoder 44 may enumerate test patterns sequentially, allowing LRB approximator 36 to provide the first 2-3 LRBs immediately while continuing to compute additional LRBs in parallel with the ongoing decoding operations. Alternatively, any

[0103] 15 other suitable incremental output scheme can be used.

[0104] This approach allows LRB approximator 36 to reduce hardware resource requirements by relaxing latency constraints on the selection logic, while enabling pipelined operation that improves overall decoding throughput and reduces processing delays.

[0105] 6: Syndrome-based LRB filtering

[0106] 20 In some embodiments, LRB approximator 36 excludes one or more combinations of the LRBs based on syndrome information calculated by syndrome calculator 40. In these embodiments, LRB approximator 36 defers the LRB calculation until after syndrome calculator 40 computes the syndrome, or until after chase decoder 44 performs hard decoding of the base test pattern with no bits flipped.

[0107] This syndrome-based filtering allows LRB approximator 36, for example, to exclude certain higher-order test patterns that are deemed irrelevant based on the syndrome characteristics. If syndrome calculator 40 determines that the syndrome of the base test pattern is zero or corresponds to a small number of errors, LRB approximator 36 may exclude some LRB combinations that would generate unnecessary higher-order test patterns.

[0108] 30 In an example embodiment, LRB approximator 36 may use the input syndrome to decide that some LRB patterns do not need to be evaluated. For example, given a certain input syndrome, LRB approximator 36 may find that a specific LRB pattern will result in an illegal codeword, or result in the same codeword as another pattern. The LRB approximator can use PCT / US25^i^8^TAugust 2025 (25.08.2025) this information to skip certain bits or patterns. For example, for a set of four LRBs, if LRB approximator 36 concludes that all patterns that flip LRB #3 are skipped, this LRB can be excluded from the calculation altogether.

[0109] The LRB approximation schemes described above are example schemes that are chosen 5 purely by way of example. In alternative embodiments, any other suitable LRB approximation technique can be used.

[0110] It will thus be appreciated that the embodiments described above are cited by way of example, and that the present invention is not limited to what has been particularly shown and described hereinabove. Rather, the scope of the present invention includes both combinations 10 and sub-combinations of the various features described hereinabove, as well as variations and modifications thereof which would occur to persons skilled in the art upon reading the foregoing description and which are not disclosed in the prior art. Documents incorporated by reference in the present patent application are to be considered an integral part of the application except that to the extent any terms are defined in these incorporated documents in a manner that 15 conflicts with the definitions made explicitly or implicitly in the present specification, only the definitions in the present specification should be considered.

Claims

PCT / US25143285 5 August 2025 (25.08.2025)CLAIMS1. An Error Correction Code (ECC) decoder, comprising: a Least Reliable Bit (LRB) approximator, configured to: receive a set of soft metrics corresponding to respective bits of an input codeword5 of the ECC; and approximate, from among the bits of the input codeword, one or more LRBs that are least reliable in the input codeword according to the soft metrics; and decoding circuitry, configured to decode the input codeword based on the soft metrics and the approximated LRBs.

2. The ECC decoder according to claim 1, wherein the soft metrics comprise Log Likelihood Ratios (LLRs).

3. The ECC decoder according to claim 1 or 2, wherein the soft metrics are represented using n-bit values, and wherein the LRB approximator is configured to approximate the LRBs by processing k-bit approximations of the soft metrics, k<n.15 4. The ECC decoder according to claim 1 or 2, wherein the LRB approximator is configured to approximate the LRBs by excluding the soft metrics that are larger than a defined threshold value.

5. The ECC decoder according to claim 1 or 2, wherein the bits of the input codeword are classified into at least first and second types, and wherein the LRB approximator is configured20 to approximate the LRBs by allowing no more that a first number of LRBs among the bits of the first type, and no more than a second number of LRBs among the bits of the second type, the first number being different from the second number.

6. The ECC decoder according to claim 1 or 2, wherein the LRB approximator is configured to approximate the LRBs by allocating respective maximal quotas for the LRBs in respective incremental batches of the soft metrics.

7. The ECC decoder according to claim 1 or 2, wherein the LRB approximator is configured to output at least some of the LRBs incrementally, to match a progress of the decoding circuitry.

8. The ECC decoder according to claim 1 or 2, wherein:30 the decoding circuitry is configured to calculate a syndrome of the input codeword; andPCT / US25 3i28S85TAugust 2025 (25.08.2025) the LRB approximator is configured to approximate the LRBs by excluding one or more combinations of the LRBs based on the syndrome.

9. An error correction coding method, comprising: receiving a set of soft metrics corresponding to respective bits of an input codeword of5 an Error Correction Code (ECC); approximating, from among the bits of the input codeword, one or more LRBs that are least reliable in the input codeword according to the soft metrics; and decoding the input codeword based on the soft metrics and the approximated LRBs.

10. The method according to claim 9, wherein the soft metrics comprise Log Likelihood Ratios (LLRs).

11. The method according to claim 9 or 10, wherein the soft metrics are represented using n-bit values, and wherein approximating the LRBs comprises processing k-bit approximations of the soft metrics, k<n.

12. The method according to claim 9 or 10, wherein approximating the LRBs comprises15 excluding the soft metrics that are larger than a defined threshold value.

13. The method according to claim 9 or 10, wherein the bits of the input codeword are classified into at least first and second types, and wherein approximating the LRBs comprises allowing no more that a first number of LRBs among the bits of the first type, and no more than a second number of LRBs among the bits of the second type, the first number being different20 from the second number.

14. The method according to claim 9 or 10, wherein approximating the LRBs comprises allocating respective maximal quotas for the LRBs in respective incremental batches of the soft metrics.

15. The method according to claim 9 or 10, wherein approximating the LRBs comprises outputting at least some of the LRBs incrementally, to match a progress of decoding of the input codeword.

16. The method according to claim 9 or 10, wherein: decoding the input codeword comprises calculating a syndrome of the input codeword; and30 approximating the LRBs comprises excluding one or more combinations of the LRBs based on the syndrome.

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