Semiconductor device and power conversion device

Abstract

According to the present invention, an energizing control unit (20) includes a switching element (SW) that is connected in series with a pulse current generation unit (10) and a DUT (30), and a pulse current is provided to the DUT (30) in an on period of the switching element (SW). A voltage holding unit (36) clamps a voltage between main electrodes of a semiconductor element (1). A control unit (40) performs on / off control of the semiconductor element (1) and the switching element (SW). The control unit (40) adjusts a time difference between the timing of turning on the semiconductor element (1) and the timing of turning on the switching element (SW), and measures an electrical characteristic of the semiconductor element (1) on the basis of the current flowing in the DUT (30) and the voltage between a first main electrode and a second main electrode.

Description

Semiconductor Device and Power Conversion Device

[0001] The present disclosure relates to a semiconductor device and a power conversion device that measure the electrical characteristics of a device under test.

[0002] In order to create a device model of a power semiconductor device (hereinafter also simply referred to as a "semiconductor device") used in computer simulations such as SPICE (Simulation Program with Integrated Circuit Emphasis), it is necessary to accurately measure the electrical characteristics (static characteristics and dynamic characteristics) of the semiconductor device. Conventionally, the electrical characteristics of semiconductor devices have been measured by a curve tracer or a double pulse test.

[0003] In recent years, wide-gap semiconductor devices, which are advancing in industrial applications, need to reproduce the transient electrical characteristics of semiconductor devices because they switch at high speed under high voltage and high current conditions. As a method for measuring the electrical characteristics of wide-bandgap semiconductor devices, for example, Japanese Patent Application Laid-Open No. 2022-141621 (Patent Document 1) discloses a method for suppressing the influence of circuit parasitic impedance by measuring the static characteristics and dynamic characteristics of a device under test (DUT: Device Under Test) in one system.

[0004] In addition, International Publication No. 2019 / 146460 (Patent Document 2) discloses a measurement method for measuring the drain current and drain-source voltage of a first transistor serving as a DUT using a voltage source and a current source connected in series to the first transistor and a rectifying element connected in parallel in the reverse direction to an inductive load serving as the current source. In this measurement method, during the excitation period in which an excitation current flows through the inductive load, the excitation current is shunted to a path that does not pass through the first transistor. According to this, it is possible to suppress the temperature change due to self-heating of the first transistor during the excitation period of the inductive load.

[0005] Japanese Patent Application Laid-Open No. 2022-141621 International Publication No. 2019 / 146460

[0006] In addition to the temperature changes due to self-heating mentioned above, one of the transient characteristic variations of wide-bandgap semiconductors is threshold voltage hysteresis in SiC (silicon carbide) elements. Specifically, this is a phenomenon in which the on-resistance of a SiC element changes because the threshold voltage of the SiC element changes transiently depending on the state of the applied gate voltage. To evaluate this phenomenon, it is necessary to independently control the state of the applied gate voltage to the SiC element and the state of current flowing through the SiC element. The method described in Patent Document 2 can suppress the self-heating of the SiC element that becomes a DUT, but it cannot independently control the state of the applied gate voltage to the SiC element and the state of current flowing through the SiC element.

[0007] This disclosure was made to solve the above-mentioned problems, and its purpose is to provide a semiconductor device and a power converter that can independently control the state of the gate voltage applied to a semiconductor element that is a device under test and the state of the current flowing through the semiconductor element.

[0008] A semiconductor device according to this disclosure is a semiconductor device for measuring the electrical characteristics of a device under test (DUT). The DUT includes a semiconductor element having a first main electrode, a second main electrode, and a control electrode. The semiconductor element is turned on or off in response to a control voltage applied to the control electrode. The semiconductor device comprises a pulse current generation unit, an energization control unit, a voltage holding unit, a control unit, and a drive circuit. The pulse current generation unit is electrically connected in series with the DUT and generates a pulse current. The energization control unit includes a first switch element electrically connected in series with the pulse current generation unit and the DUT. The energization control unit supplies a pulse current to the DUT during the ON period of the first switch element. The voltage holding unit clamps the voltage between the first main electrode and the second main electrode of the semiconductor element. The control unit generates a first control signal for controlling the ON / OFF of the semiconductor element and a second control signal for controlling the ON / OFF of the first switch element. The drive circuit applies a first control voltage to the control electrode to turn on the semiconductor element, or a second control voltage to turn off the semiconductor element, according to a first control signal. The control unit adjusts the time difference between the timing of turning on the semiconductor element and the timing of turning on the first switch element, and measures the electrical characteristics of the semiconductor element based on the current flowing through the DUT and the voltage between the first main electrode and the second main electrode.

[0009] According to this disclosure, the state of gate voltage applied to the semiconductor element under test and the state of current flowing through the semiconductor element can be controlled independently. This makes it possible to evaluate the threshold voltage hysteresis in the SiC element.

[0010] This is a circuit diagram of a semiconductor device according to Embodiment 1. This is a timing chart showing an example of the operation of the semiconductor device. This is a diagram for explaining the significance of delay time. This is a diagram showing an example of the measurement results of the Ids-Vds characteristics of a semiconductor element by a semiconductor device. This is a circuit diagram of a semiconductor device according to Embodiment 3. This is a timing chart showing a first example of the operation of the semiconductor device according to Embodiment 3. This is a timing chart showing a second example of the operation of the semiconductor device according to Embodiment 3. This is a circuit diagram of a semiconductor device according to Embodiment 4. This is a timing chart showing an example of the operation of the semiconductor device according to Embodiment 4. This is a circuit diagram of a semiconductor device according to Embodiment 5. This is a circuit diagram of a gate driver. This is a timing chart showing an example of the operation of the semiconductor device according to Embodiment 5. This is a block diagram showing the configuration of a power conversion system to which a power conversion device according to Embodiment 6 is applied.

[0011] Embodiments of the present disclosure will be described below. Unless otherwise specified, the same or corresponding parts in the following drawings will be denoted by the same reference numerals, and their descriptions will not be repeated.

[0012] Embodiment 1. <Example of Semiconductor Device Configuration> Figure 1 is a circuit diagram of a semiconductor device according to Embodiment 1. The semiconductor device 100 according to Embodiment 1 is a device for measuring the electrical characteristics of a device under test (hereinafter referred to as "DUT") 30.

[0013] DUT30 includes a power semiconductor element 1 (hereinafter also simply referred to as "semiconductor element 1"). In Figure 1, an N-channel MOSFET (Metal Oxide Semiconductor Field Effect Transistor) is used as the semiconductor element 1, but any voltage-driven semiconductor element such as an IGBT (Insulated Gate Bipolar Transistor) can be used.

[0014] The semiconductor device 1 has a gate (G) which is a control electrode, a drain (D) which is a first main electrode (high voltage side), and a source (S) which is a second main electrode (low voltage side). In the semiconductor device 1, the conduction state (on state) and non-conduction state (off state) between the first main electrode (D) and the second main electrode (S) are switched according to the control voltage applied to the control electrode (G). MOSFETs include Si (silicon) MOSFETs, SiC (silicon carbide) MOSFETs, or GaN (gallium nitride) MOSFETs, etc.

[0015] The current Ids (hereinafter also referred to as "drain current Ids") flowing from the drain to the source of semiconductor element 1 changes depending on the gate-source voltage VgDUT (hereinafter also simply referred to as "gate voltage VgDUT"), which is the gate voltage relative to the source.

[0016] DUT30 has a diode connected in antiparallel between the drain and source of the semiconductor element 1. The diode is provided to allow a freewheeling current to flow when the semiconductor element 1 is turned off. If the semiconductor element 1 is a MOSFET, the freewheeling diode may be a parasitic diode (body diode). If the semiconductor element 1 is an IGBT that does not have a built-in diode, the freewheeling diode is a diode connected in antiparallel to the IGBT.

[0017] The semiconductor device 100 is used to measure the electrical characteristics (static and dynamic characteristics) of the semiconductor element 1 that constitutes the DUT 30. In Figure 1, the semiconductor device 100 measures the Ids-Vds characteristic, which shows the relationship between the drain current Ids and the drain-source voltage Vds of the MOSFET semiconductor element 1, and the Isd-Vsd characteristic, which shows the relationship between the forward current Isd flowing through the diode of the semiconductor element 1 and the source-drain voltage Vsd.

[0018] As shown in Figure 1, the semiconductor device 100 includes a pulse current generation unit 10, a current control unit 20, gate drivers 22 and 32, a voltage holding unit 36, a voltage sensor 34, a current sensor 42, and a control unit 40.

[0019] The pulse current generation unit 10 is electrically connected in series with the DUT 30 and is configured to generate a pulse current that flows through the DUT 30. Specifically, the pulse current generation unit 10 includes a voltage source 11, a current source 12, and a rectifier element 14. The voltage source 11 and the current source 12 are electrically connected in series with the DUT 30.

[0020] The voltage source 11 is a component for setting the voltage VDUT (corresponding to the drain-source voltage Vds of the semiconductor element 1) applied to the DUT 30. The voltage source 11 is, for example, a capacitor, with its positive terminal connected to the first terminal of the current source 12 and its negative terminal connected to the source of the semiconductor element 1. The voltage source 11 may also be a rechargeable battery such as a lithium-ion battery.

[0021] The current source 12 is a component for setting the current value of the pulse current flowing through the DUT 30 (corresponding to the drain current Ids of the semiconductor element 1). The second terminal of the current source 12 is connected to the first terminal of the power supply control unit 20. The second terminal of the power supply control unit 20 is connected to the first main electrode (D) of the semiconductor element 1.

[0022] The current source 12 is composed of a plurality (for example, two) of reactors L1 and L2 (inductive loads) and a switch 18. The reactors L1 and L2 have different inductance values. The switch 18 is controlled by the control unit 40 and connects either reactor L1 or L2 between the first terminal and the second terminal of the current source 12. That is, the current source 12 is configured to be able to change the inductance value of the inductive load. The current source 12 may include three or more reactors.

[0023] Although not shown in the diagram, the current source 12 may include a reactor, a magnetic material to be inserted into the reactor, an insertion mechanism for inserting the magnetic material into the reactor, and a switch 18. In this case, the switch 18 is controlled by the control unit 40 and drives the insertion mechanism to switch whether or not the magnetic material is inserted into the reactor. By switching whether or not the magnetic material is inserted into the reactor, the inductance value of the reactor changes. That is, the current source 12 is configured to be able to change the inductance value of the inductive load.

[0024] The rectifier element 14 is connected in antiparallel to the current source 12. The rectifier element 14 is provided to allow a freewheeling current to flow when the semiconductor element 1 is off. In Figure 1, the rectifier element 14 is composed of a parasitic diode (body diode) of an N-channel MOSFET. The N-channel MOSFET is fixed in the off state by applying a negative voltage between the gate and source. With this configuration, during the off period of the semiconductor element 1, the current flowing to the inductive load (reactor L1 or L2) via the rectifier element 14 can be regenerated. Therefore, it is possible to prevent excessive surge voltage from being applied to the semiconductor element 1.

[0025] In addition to the parasitic diode of the MOSFET, the rectifier element 14 can be a SiC-based shot barrier diode or a Si-based PiN diode, etc.

[0026] The power supply control unit 20 is a component for switching the supply and interruption of pulse current from the pulse current generation unit 10 to the DUT 30. The power supply control unit 20 includes a switch element SW. The switch element SW is connected between the first terminal and the second terminal of the power supply control unit 20. That is, the switch element SW is electrically connected in series with the pulse current generation unit 10 and the semiconductor element 1. As a result, a closed circuit is formed in the semiconductor device 100 by the pulse current generation unit 10 (voltage source 11 and current source 12), the switch element SW, and the semiconductor element 1. The switch element SW corresponds to one embodiment of the "first switch element".

[0027] The switch element SW is a semiconductor element, for example, an N-channel MOSFET. The switch element SW switches between a conductive state (on state) and a non-conductive state (off state) between the drain and source according to the gate-source voltage VgSW (hereinafter also simply referred to as "gate voltage VgSW"), which is the voltage of the gate relative to the source. In Figure 1, an N-channel MOSFET is used as the switch element SW, but any voltage-driven semiconductor element such as an IGBT can be used.

[0028] When the switch element SW is turned on during the ON period of the semiconductor element 1, a pulse current is supplied from the pulse current generation unit 10 to the DUT 30, and a drain current Ids begins to flow through the semiconductor element 1. When the switch element SW is turned off in this state, the supply of pulse current from the pulse current generation unit 10 to the DUT 30 is interrupted, and the drain current Ids decreases to 0. In other words, the state of current flowing through the semiconductor element 1 is switched by turning the switch element SW on and off.

[0029] Furthermore, it is preferable that the switching element SW is an element that can switch faster than the semiconductor element 1 so as not to restrict the transient response of the semiconductor element 1. Therefore, for example, if the semiconductor element 1 is a SiC-based semiconductor element, it is preferable that the switching element SW is a SiC-based or GaN-based semiconductor element.

[0030] Furthermore, it is preferable that the switch element SW is a semiconductor element with a higher rated current than the semiconductor element 1. This is because if the rated current of the switch element SW is lower than the rated current of the semiconductor element 1, the voltage may not be properly distributed to the semiconductor element 1 due to current saturation of the switch element SW.

[0031] The voltage holding section 36 is a part for clamping the terminal voltage of the DUT 30 (corresponding to the drain-source voltage Vds of the semiconductor element 1). The voltage holding section 36 is composed of, for example, a resistive element connected between the drain and source of the semiconductor element 1. The resistance value of the resistive element is set to be smaller than the off-resistance of the switch element SW and sufficiently larger than the on-resistance of the semiconductor element 1. In this way, when both the semiconductor element 1 and the switch element SW are in the off state, no voltage is applied between the drain and source of the semiconductor element 1.

[0032] The control unit 40 generates a control signal to control the on / off state of the semiconductor element 1 and outputs the generated control signal to the gate driver 32. The gate driver 32 is provided in conjunction with the semiconductor element 1 and drives the semiconductor element 1 according to the control signal provided by the control unit 40. Specifically, in response to an H (logic high) level control signal (first control signal), the gate driver 32 applies a gate voltage VgDUT (first control voltage) to the gate of the semiconductor element 1 to turn on the semiconductor element 1. In addition, in response to an L (logic low) level control signal (second control signal), the gate driver 32 applies a gate voltage VgDUT (second control voltage) to the gate of the semiconductor element 1 to turn off the semiconductor element 1.

[0033] The gate driver 32 is configured to variably control the gate voltage VgDUT for turning on the semiconductor element 1. Specifically, the gate driver 32 can set the gate voltage VgDUT for turning on the semiconductor element 1 to multiple voltage levels (see Figure 2).

[0034] The control unit 40 further generates a control signal to control the on / off state of the switch element SW, and outputs the generated control signal to the gate driver 22. The gate driver 22 is provided in correspondence with the switch element SW and drives the switch element SW according to the control signal provided by the control unit 40. Specifically, in response to an H-level control signal, the gate driver 22 applies a gate voltage VgSW to the gate of the switch element SW to turn the switch element SW on. Also, in response to an L-level control signal, the gate driver 22 applies a gate voltage VgSW to the gate of the switch element SW to turn the switch element SW off.

[0035] In Embodiment 1, the control unit 40 is configured to independently control the on / off state of the semiconductor element 1 and the on / off state of the switch element SW. Therefore, the control unit 40 can create a time difference between the timing of turning on the semiconductor element 1 and the timing of turning on the switch element SW. Furthermore, the control unit 40 can variably adjust this time difference.

[0036] In one scenario, the control unit 40 can turn on the semiconductor element 1 by applying a gate voltage VgDUT from the gate driver 32 to the gate of the semiconductor element 1, and then turn on the switch element SW by applying a gate voltage VgSW from the gate driver 22 to the gate of the switch element SW. In this case, after the semiconductor element 1 is turned on by receiving the gate voltage VgDUT, a drain current Ids will begin to flow at the timing when the switch element SW is turned on.

[0037] Thus, the control unit 40 is configured to independently control the state in which the gate voltage VgDUT is applied to the semiconductor element 1 and the state in which the current flows through the semiconductor element 1. With this configuration, it is possible to use the semiconductor device 100 to evaluate, for example, the threshold voltage fluctuation due to gate bias stress in a SiC-MOSFET. The method for evaluating the threshold voltage fluctuation of a SiC-MOSFET using the semiconductor device 100 will be explained in detail later.

[0038] The current sensor 42 detects the current flowing through the DUT 30 (corresponding to the drain current Ids of the semiconductor element 1) and provides a signal indicating the detected value to the control unit 40. The voltage sensor 34 detects the terminal voltage VDUT of the DUT 30 (corresponding to the drain-source voltage Vds of the semiconductor element 1) and provides a signal indicating the detected value to the control unit 40. Based on the output signals of the current sensor 42 and the voltage sensor 34, the control unit 40 measures the electrical characteristics of the semiconductor element 1. For example, the control unit 40 measures the Ids-Vds characteristics of the semiconductor element 1.

[0039] The control unit 40 may be composed of a digital electronic circuit that performs calculations using an FPGA (Field Programmable Gate Array) or the like via an A / D converter, or it may be composed of an analog electronic circuit such as a comparator, operational amplifier, and differential amplifier circuit. Alternatively, it may be composed of both a digital electronic circuit and an analog electronic circuit.

[0040] <Operation of Semiconductor Device> Next, the operation of the semiconductor device 100 according to Embodiment 1 will be described.

[0041] Figure 2 is a timing chart showing an operation example of the semiconductor device 100. In Figure 2, waveforms of the gate voltage VgSW of the switch element SW, the gate voltage VgDUT of the semiconductor element 1, the drain current Ids of the semiconductor element 1, and the terminal voltage VDUT of the DUT 30 (the drain-source voltage Vds of the semiconductor element 1) are shown.

[0042] As shown in Figure 2, at time t0, the control unit 40 generates a control signal of L level and outputs it to the gate driver 32. In response to the control signal of L level, the gate driver 32 applies a gate voltage VgDUT for turning off the semiconductor element 1 to the gate of the semiconductor element 1. This gate voltage VgDUT is GND or a negative voltage.

[0043] Also, the control unit 40 generates a control signal of L level and outputs it to the gate driver 22. In response to the control signal of L level, the gate driver 22 applies a gate voltage VgSW for turning off the switch element SW to the gate of the switch element SW. [[ID=I0]]

[0044] Therefore, at time t0, both the semiconductor element 1 and the switch element SW are in the off state. The drain current Ids of the semiconductor element 1 is 0. Also, due to the voltage holding unit 36 described above, the terminal voltage VDUT of the DUT 30 (the drain-source voltage Vds of the semiconductor element 1) is a value close to 0.

[0045] At time t1, the control unit 40 generates a control signal of H level and outputs it to the gate driver 32. In response to the control signal of H level, the gate driver 32 applies a gate voltage VgDUT for turning on the semiconductor element 1 to the gate of the semiconductor element 1. This gate voltage VgDUT is a positive voltage higher than the threshold voltage of the semiconductor element 1. In response to this gate voltage VgDUT, the semiconductor element 1 is turned on. However, since the switch element SW is in the off state, no current flows through the semiconductor element 1, and the drain current Ids remains 0.

[0046] At time t2 after time t1, the control unit 40 generates a control signal of the H level and outputs it to the gate driver 22. In response to the control signal of the H level, the gate driver 22 applies a gate voltage VgSW for turning on the switching element SW to the gate of the switching element SW. Upon receiving this gate voltage VgSW, the switching element SW is turned on.

[0047] When the switching element SW is turned on, a pulse current is supplied from the pulse current generation unit 10 to the DUT 30. As a result, at time t2, a drain current Ids starts to flow through the semiconductor element 1. Simultaneously with the drain current Ids, the terminal voltage VDUT (drain-source voltage Vds) of the DUT 30 also starts to increase.

[0048] At time t3, the control unit 40 generates a control signal of the L level and outputs it to the gate driver 22. In response to the control signal of the L level, the gate driver 22 applies a gate voltage VgSW for turning off the switching element SW to the gate of the switching element SW. Upon receiving this gate voltage VgSW, the switching element SW is turned off.

[0049] When the switching element SW is turned off, the supply of the pulse current from the pulse current generation unit 10 to the DUT 30 is interrupted. As a result, at time t3, the drain current Ids of the semiconductor element 1 decreases to 0. The terminal voltage VDUT (drain-source voltage Vds) of the DUT 30 also decreases to a value close to 0.

[0050] Subsequently, at time t4, the control unit 40 generates a control signal of the L level and outputs it to the gate driver 32. In response to the control signal of the L level, the gate driver 32 applies a gate voltage VgDUT for turning off the semiconductor element 1 to the gate of the semiconductor element 1. Upon receiving this gate voltage VgDUT, the semiconductor element 1 is turned off.

[0051] In the example shown in Figure 2, the control unit 40 applies a gate voltage VgDUT to the gate of the semiconductor element 1 at time t1 to turn on the semiconductor element 1, and then at time t2, applies a gate voltage VgSW to the gate of the switch element SW to turn on the switch element SW. In other words, the control unit 40 delays the timing of turning on the switch element SW by a time difference tdelay (hereinafter also referred to as "delay time tdelay") relative to the timing of turning on the semiconductor element 1.

[0052] This delay time tdelay corresponds to the period during which the gate voltage VgDUT is applied to the semiconductor device 1, but the drain current Ids does not flow. By providing such a delay time tdelay, it becomes possible to evaluate the fluctuation of the threshold voltage due to gate bias stress in the SiC-MOSFET.

[0053] In detail, semiconductor devices using wide-bandgap semiconductors such as SiC generally have less stable gate oxide film quality compared to Si semiconductor devices. Therefore, in SiC-MOSFETs, it is known that the threshold voltage fluctuates as time elapses after the gate voltage is applied, due to carriers being trapped in defects in the gate oxide film. This fluctuation in threshold voltage can lead to malfunctions of the SiC-MOSFET and increased switching losses.

[0054] The degree of threshold voltage fluctuation depends on the duration for which the gate voltage of the SiC-MOSFET is applied. Therefore, the Ids-Vds characteristics of the SiC-MOSFET vary depending on the length of time the gate voltage is applied to the SiC-MOSFET before current is supplied to it.

[0055] In the example shown in Figure 2, the delay time tdelay corresponds to the time during which the gate voltage VgDUT is applied to the semiconductor element 1 before the current is supplied to the semiconductor element 1. When the semiconductor element 1 is a SiC-MOSFET, the Ids-Vds characteristics of the semiconductor element 1 vary depending on the length of the delay time tdelay.

[0056] Figure 3 is a diagram illustrating the significance of the delay time tdelay. Figure 3(A) is a timing chart showing the operation of the semiconductor device 100. Figure 3(B) is a comparative example of Embodiment 1, and is a timing chart showing the operation of a semiconductor device without the current control unit 20 (switching element SW) and the voltage holding unit 36. In both Figure 3(A) and Figure 3(B), the semiconductor element 1 is a SiC-MOSFET.

[0057] Figure 3(A) shows the waveforms of the gate voltage VgSW of the switch element SW, the gate voltage VgDUT of the semiconductor element 1, the drain current Ids of the semiconductor element 1, the terminal voltage VDUT of DUT30 (drain-source voltage Vds of the semiconductor element 1), and the threshold voltage VthDUT of the semiconductor element 1. The waveforms of VgSW, VgDUT, Ids, and VDUT shown in Figure 3 are substantially the same as the waveforms of VgSW, VgDUT, Ids, and VDUT shown in Figure 2.

[0058] As shown in Figure 3(A), at time t1, the gate voltage VgDUT is applied to turn on the semiconductor element 1, causing the threshold voltage VthDUT of the semiconductor element 1 to start rising. At time t2, when the gate voltage VgSW is applied to the switch element SW, current begins to flow through the semiconductor element 1. The value of the threshold voltage VthDUT (marked with an "x" in the figure) at time t2 depends on the magnitude of the gate voltage VgDUT that was applied immediately before time t2, and the duration for which the gate voltage VgDUT was applied.

[0059] Figure 3(B), a comparative example, shows the waveforms of the gate voltage VgDUT of semiconductor element 1, the drain current Ids of semiconductor element 1, the terminal voltage VDUT of DUT 30 (drain-source voltage Vds of semiconductor element 1), and the threshold voltage VthDUT of semiconductor element 1.

[0060] In the comparative example, since there is no current control unit 20 (switching element SW), current starts flowing through the semiconductor element 1 at the same time as the application of the gate voltage VgDUT to the semiconductor element 1 begins at time t1. Therefore, only the turn-on characteristics of the semiconductor element 1 corresponding to the threshold voltage VthDUT before fluctuation (marked with an "x" in the figure) can be measured.

[0061] In contrast, in Embodiment 1, by providing a current control unit 20 (switching element SW), it is possible to adjust the time difference (delay time tdelay) between the timing of applying the gate voltage VgDUT to the semiconductor element 1 and the timing of when current begins to flow through the semiconductor element 1. This makes it possible to measure the turn-on characteristics of the semiconductor element 1 at any transient threshold voltage VthDUT.

[0062] (Evaluation of threshold voltage fluctuation due to gate bias stress) An overview of the method for evaluating the threshold voltage fluctuation due to gate bias stress of a SiC-MOSFET using a semiconductor device 100 according to Embodiment 1 will be described.

[0063] In the semiconductor device 100, the control unit 40 is configured to variably adjust the time difference (delay time tdelay) between the timing of turning on the semiconductor element 1 and the timing of turning on the switch element SW. Therefore, by setting the gate voltage VgDUT for turning on the semiconductor element 1 as a fixed value, the Ids-Vds characteristics of the semiconductor element 1 can be measured for multiple delay time tdelay patterns. From the acquired measurement results, the dependence of the Ids-Vds characteristics of the semiconductor element 1 on the gate voltage application time can be evaluated.

[0064] Furthermore, in the semiconductor device 100, the gate driver 32 is configured to variably control the gate voltage VgDUT for turning on the semiconductor element 1. Therefore, by setting the delay time Tdelay to a fixed value, the Ids-Vds characteristics of the semiconductor element 1 can be measured at multiple voltage levels of gate voltage VgDUT. From the acquired measurement results, the gate voltage dependence of the turn-on characteristics of the semiconductor element 1 can be evaluated.

[0065] Figure 4 shows an example of the measurement results of the Ids-Vds characteristics of the semiconductor device 1 using the semiconductor device 100. The semiconductor device 1 is a SiC-MOSFET.

[0066] In Figure 4, the gate voltage VgDUT for turning on semiconductor element 1 is set to two voltage levels, VgDUT1 and VgDUT2. The voltage value of VgDUT1 is greater than the voltage value of VgDUT2 (VgDUT1 > VgDUT2). The delay time tdelay is set to two patterns, tdelay1 and tdelay2. The length of tdelay1 is shorter than the length of tdelay2 (tdelay1 < tdelay2).

[0067] Figure 4 shows four curves C1 to C4 representing the Ids-Vds characteristics of semiconductor device 1. Curve C1 is the Ids-Vds characteristic when the gate voltage VgDUT1 and delay time tdelay1. Curve C2 is the Ids-Vds characteristic when the gate voltage VgDUT1 and delay time tdelay2. Curve C3 is the Ids-Vds characteristic when the gate voltage VgDUT2 and delay time tdelay1. Curve C4 is the Ids-Vds characteristic when the gate voltage VgDUT2 and delay time tdelay2.

[0068] Since curves C1 and C2 have the same gate voltage VgDUT value, comparing the two allows us to evaluate the effect of the delay time tdelay on the threshold voltage Vth of the semiconductor element 1. For example, as shown in Figure 4, by fitting each of curves C1 and C2 to the characteristic approximation formula of the MOSFET, the threshold voltage Vth for each Ids-Vds characteristic can be derived.

[0069] The characteristic approximation formula for the MOSFET corresponding to the linear region of the Ids-Vds characteristic shown in curve C1 is given, for example, by equation (1).

[0070]

[0071] The characteristic approximation formula for the MOSFET corresponding to the linear region of the Ids-Vds characteristic shown by curve C2 is given, for example, by equation (2).

[0072]

[0073] Ids_lin is the drain current Ids in the linear region, Vds is the drain-source voltage, Vgs is the gate-source voltage, and Vth is the threshold voltage. W is the gate width, L is the gate length, Cox is the gate capacitance per unit area, and μn is the carrier mobility.

[0074] In equations (1) and (2) above, by setting the threshold voltage Vth as a function of the delay time tdelay, Vth(tdelay), it is possible to derive a value of the threshold voltage Vth that depends on the delay time tdelay. This makes it possible to evaluate the amount of variation in the threshold voltage Vth that depends on the delay time tdelay.

[0075] Furthermore, in Figure 4, since curves C1 and C3 have the same delay time tdelay, comparing the two allows for a quantitative evaluation of the effect of the magnitude of the gate voltage VgDUT on the threshold voltage Vth of the semiconductor element 1.

[0076] As described above, according to the semiconductor device 100 of Embodiment 1, by adjusting the time difference between the timing of turning on the semiconductor element 1 and the timing of turning on the switch element SW, it is possible to independently control the state in which the gate voltage VgDUT is applied to the semiconductor element 1 and the state in which the current flows through the semiconductor element 1. Therefore, as shown in Figure 4, it is possible to evaluate the fluctuation of the threshold voltage due to gate bias stress in a SiC-MOSFET using the semiconductor device 100.

[0077] Embodiment 2. Embodiment 2 will explain the significance of the pulse current generation unit 10.

[0078] As shown in Figure 1, the pulse current generation unit 10 includes a voltage source 11, a current source 12, and a rectifier element 14. The current source 12 is composed of a plurality of reactors L1 and L2 (inductive loads) and a switch 18. The reactors L1 and L2 have different inductance values. The switch 18 is controlled by the control unit 40 and connects either reactor L1 or L2 between the first and second terminals of the current source 12. In other words, the current source 12 is configured to be able to change the inductance value of the inductive loads.

[0079] By changing the inductance value of the inductive load in the current source 12, the rate of change of the pulse current supplied to the DUT 30 changes. Therefore, in the timing chart shown in Figure 2, the rate of increase of the drain current Ids changes after the timing (time t2) when the switch element SW is turned on.

[0080] In the semiconductor device 100 according to Embodiment 1, the Ids-Vds characteristics of the semiconductor element 1 can be measured at multiple current rise rates by switching the inductance value of the inductive load of the current source 12. This makes it possible to eliminate the influence of element characteristics that fluctuate according to the current rise rate.

[0081] Specifically, the drain current Ids of semiconductor element 1 is composed of the channel current Ichannel and the displacement current Icharge. The displacement current Icharge is the current that flows due to the change in the drain-source voltage Vds, dVds / dt, that occurs when the Ids-Vds characteristic of the MOSFET enters the saturation region from the linear region during measurement.

[0082] The voltage change dVds / dt of the drain-source voltage Vds changes according to the rate of increase of the drain current Ids. Therefore, by measuring the Ids-Vds characteristics of the semiconductor element 1 at multiple rate of increase of current, the Ids-Vds characteristics of the semiconductor element 1 can be measured at multiple voltage changes dVds / dt. Then, based on the difference between the multiple measured Ids-Vds characteristics, the displacement current Icharge can be removed from the drain current Ids, and the channel current Ichannel can be derived.

[0083] Embodiment 3. <Example of Semiconductor Device Configuration> Figure 5 is a circuit diagram of a semiconductor device according to Embodiment 3. The semiconductor device 100 according to Embodiment 3 differs from the semiconductor device 100 shown in Figure 1 in that the semiconductor element 1 in the DUT 30 is connected in the reverse direction. Specifically, the source of the semiconductor element 1 is connected to the source of the switch element SW that constitutes the current control unit 20, and the drain of the semiconductor element 1 is connected to GND. Therefore, a forward voltage is applied to the diode connected in antiparallel between the drain and source of the semiconductor element 1.

[0084] <Semiconductor Device Operation> According to the semiconductor device 100 according to Embodiment 3, the forward characteristics of the diode included in the DUT 30 can be measured. Figure 6 is a timing chart showing a first example of operation of the semiconductor device 100 according to Embodiment 3. Figure 6 shows the waveforms of the gate voltage VgSW of the switch element SW, the gate voltage VgDUT of the semiconductor element 1, the current Isd flowing from the source to the drain of the semiconductor element 1, and the terminal voltage VDUT of the DUT 30 (source-drain voltage Vsd of the semiconductor element 1).

[0085] As shown in Figure 6, at time t0, the control unit 40 outputs an L-level control signal to each of the gate drivers 32 and 22. In response to the L-level control signal, the gate driver 32 applies a gate voltage VgDUT to the gate of the semiconductor element 1 to turn off the semiconductor element 1. In response to the L-level control signal, the gate driver 22 applies a gate voltage VgSW to the gate of the switch element SW to turn off the switch element SW. At time t0, both the semiconductor element 1 and the switch element SW are in the off state, so the current Isd is 0. The terminal voltage VDUT of DUT 30 (source-drain voltage Vsd of the semiconductor element 1) is close to 0.

[0086] At time t1, the control unit 40 generates an H-level control signal and outputs it to the gate driver 32. In response to the H-level control signal, the gate driver 32 applies a gate voltage VgDUT to the gate of the semiconductor element 1 to turn it on. Upon receiving the gate voltage VgDUT, the semiconductor element 1 is turned on. However, since the switch element SW is in the off state, no current flows through the semiconductor element 1, and the current Isd remains 0.

[0087] At time t2, the control unit 40 outputs an H-level control signal to the gate driver 22. In response to the H-level control signal, the gate driver 22 applies a gate voltage VgSW to the gate of the switch element SW to turn it on. Upon receiving this gate voltage VgSW, the switch element SW is turned on.

[0088] When the switch element SW is turned on, a pulse current is supplied from the pulse current generation unit 10 to the DUT 30. As a result, at time t2, a current Isd begins to flow through the semiconductor element 1. This current Isd includes the current flowing in the reverse direction from the source to the drain of the MOSFET and the current flowing through the diode. Simultaneously with the current Isd, the terminal voltage VDUT (source-drain voltage Vsd) of the DUT 30 also begins to increase.

[0089] At time t3, the control unit 40 generates an L-level control signal and outputs it to the gate driver 22. In response to the L-level control signal, the gate driver 22 applies a gate voltage VgSW to the gate of the switch element SW to turn it off. Upon receiving this gate voltage VgSW, the switch element SW is turned off.

[0090] When the switch element SW is turned off, the supply of pulse current from the pulse current generation unit 10 to the DUT 30 is interrupted. As a result, at time t3, the current Isd decreases to 0. The terminal voltage VDUT (source-drain voltage Vsd) of the DUT 30 also decreases to a value close to 0.

[0091] Next, at time t4, the control unit 40 outputs an H-level control signal to the gate driver 22. In response to the H-level control signal, the gate driver 22 applies a gate voltage VgSW to the gate of the switch element SW to turn on the switch element SW. Upon receiving this gate voltage VgSW, the switch element SW is turned on.

[0092] When the switch element SW is turned on, a pulse current is supplied from the pulse current generation unit 10 to the DUT 30. As a result, at time t4, current Isd begins to flow again through the semiconductor element 1. Simultaneously with the current Isd, the terminal voltage VDUT (source-drain voltage Vsd) of the DUT 30 also begins to increase.

[0093] At time t5, the control unit 40 generates an L-level control signal and outputs it to the gate driver 32. In response to the L-level control signal, the gate driver 32 applies a gate voltage VgDUT to the gate of the semiconductor element 1 to turn it off. Upon receiving this gate voltage VgDUT, the semiconductor element 1 is turned off. However, a forward current flows through the diode of the semiconductor element 1.

[0094] At time t6, the control unit 40 generates a high-level control signal and outputs it to the gate driver 32. In response to the high-level control signal, the gate driver 32 applies a gate voltage VgDUT to the gate of the semiconductor element 1 to turn it on. Upon receiving the gate voltage VgDUT, the semiconductor element 1 is turned on. Therefore, the current Isd includes the current flowing in the reverse direction from the source to the drain of the MOSFET and the current flowing through the diode.

[0095] At time t7, the control unit 40 generates an L-level control signal and outputs it to the gate driver 22. In response to the L-level control signal, the gate driver 22 applies a gate voltage VgSW to the gate of the switch element SW to turn it off. Upon receiving this gate voltage VgSW, the switch element SW is turned off.

[0096] When the switch element SW is turned off, the supply of pulse current from the pulse current generation unit 10 to the DUT 30 is interrupted. As a result, at time t7, the current Isd decreases to 0. The terminal voltage VDUT (source-drain voltage Vsd) of the DUT 30 also decreases to a value close to 0.

[0097] In Embodiment 3, two pulsed gate voltages VgSW are sequentially applied to the switch element SW of the current control unit 20. During the period when the switch element SW is turned on by receiving the first pulsed gate voltage VgSW (the period from time t2 to t3), the electrical characteristics (Isd-Vsd characteristics) of the semiconductor element 1 when it is conducting in reverse can be measured.

[0098] Furthermore, during the period when the switching element SW is turned on in response to the gate voltage VgSW of the second pulse (the period from time t4 to t7), the semiconductor element 1 can be turned off and turned on, thereby allowing measurement of the turn-off of the semiconductor element 1 and the transient characteristics of the diode during the turn-off phase.

[0099] Figure 7 is a timing chart showing a second operation example of the semiconductor device 100 according to Embodiment 3. The second operation example differs from the first operation example shown in Figure 6 in that the semiconductor device 1 is in the OFF state during the period (time t2 to t3) when the switching element SW is turned ON in response to the gate voltage VgSW of the first pulse. Therefore, in the second operation example, the electrical characteristics of the diode can be measured during the period t2 to t3.

[0100] In the second example of operation, at time t8, prior to time t4 when the switch element SW is turned on, the control unit 40 generates an H-level control signal and outputs it to the gate driver 32. In response to the H-level control signal, the gate driver 32 applies a gate voltage VgDUT to the gate of the semiconductor element 1 to turn it on. Upon receiving the gate voltage VgDUT, the semiconductor element 1 is turned on.

[0101] In the second example of operation, by turning off and on the semiconductor element 1 during the period when the switching element SW is turned on in response to the gate voltage VgSW of the second pulse (the period from time t4 to t7), the transient characteristics of the diode during the turn-off of the semiconductor element 1 can be measured.

[0102] However, as explained in Embodiment 1, the threshold voltage of the semiconductor element 1 fluctuates depending on the time difference (delay time tdelay) between the timing of turning on the semiconductor element 1 and the timing of turning on the switch element SW. Therefore, the transient characteristics of the diode may differ between the first and second operating examples. Taking advantage of this, Embodiment 3 makes it possible to evaluate how the transient characteristics of the diode change under the influence of fluctuations in the threshold voltage of the semiconductor element 1 by making the length of the delay time tdelay variable.

[0103] Embodiment 4. <Example of Semiconductor Device Configuration> Figure 8 is a circuit diagram of a semiconductor device according to Embodiment 4. The semiconductor device 100 according to Embodiment 4 differs from the semiconductor device 100 shown in Figure 1 in that the current control unit 26 includes a switch element SW2 and is equipped with a gate driver 24.

[0104] As shown in Figure 8, the switch element SW2 is electrically connected in series with the pulse current generation unit 10. The switch element SW2 is further electrically connected to the series circuit of the switch element SW and DUT 30. The switch element SW2 corresponds to one embodiment of the "second switch element".

[0105] The switch element SW2 is the same semiconductor element as the switch element SW, and is composed of, for example, an N-channel MOSFET. The switch element SW2 switches between a conductive state (on state) and a non-conductive state (off state) between its drain and source according to the gate voltage VgSW2. In Figure 8, an N-channel MOSFET is used as the switch element SW2, but any voltage-driven semiconductor element such as an IGBT can be used.

[0106] The control unit 40 generates a control signal to control the on / off state of the switch element SW2 and outputs the generated control signal to the gate driver 24. The gate driver 24 is provided in correspondence with the switch element SW2 and drives the switch element SW2 according to the control signal provided by the control unit 40. Specifically, in response to an H-level control signal, the gate driver 24 applies a gate voltage VgSW2 to the gate of the switch element SW2 to turn the switch element SW2 on. Also, in response to an L-level control signal, the gate driver 24 applies a gate voltage VgSW2 to the gate of the switch element SW2 to turn the switch element SW2 off.

[0107] In Embodiment 4, the control unit 40 is configured to independently control the on / off state of semiconductor element 1, the on / off state of switch element SW, and the on / off state of switch element SW2. When switch element SW2 is turned on, a current Ids2 (hereinafter also referred to as "drain current Ids2") flows from the drain to the source of switch element SW2.

[0108] <Semiconductor Device Operation> Figure 9 is a timing chart showing an example of operation of the semiconductor device 100 according to Embodiment 4. Figure 9 shows the waveforms of the gate voltage VgSW of the switch element SW, the gate voltage VgSW2 of the switch element SW2, the gate voltage VgDUT of the semiconductor element 1, the drain current Ids of the semiconductor element 1, the drain current Ids2 of the switch element SW2, and the terminal voltage VDUT of DUT30 (drain-source voltage Vds of the semiconductor element 1).

[0109] As shown in Figure 9, at time t0, the control unit 40 generates an L-level control signal and outputs it to the gate driver 32. In response to the L-level control signal, the gate driver 32 applies a gate voltage VgDUT to the gate of the semiconductor element 1 to turn off the semiconductor element 1.

[0110] Furthermore, the control unit 40 generates an L-level control signal and outputs it to the gate drivers 22 and 24. In response to the L-level control signal, the gate driver 22 applies a gate voltage VgSW to the gate of the switch element SW to turn it off. In response to the L-level control signal, the gate driver 24 applies a gate signal VgSW2 to the gate of the switch element SW2 to turn it off.

[0111] Therefore, at time t0, both semiconductor element 1 and switching elements SW and SW2 are in the off state. The drain current Ids of semiconductor element 1 and the drain current Ids2 of switching element SW2 are 0. Also, the terminal voltage VDUT of DUT30 (drain-source voltage Vds of semiconductor element 1) is close to 0.

[0112] At time t1, the control unit 40 generates an H-level control signal and outputs it to the gate driver 24. In response to the H-level control signal, the gate driver 24 applies a gate voltage VgSW2 to the gate of the switch element SW2 to turn it on. Upon receiving this gate voltage VgSW2, the switch element SW2 is turned on.

[0113] When the switch element SW2 is turned on, a pulse current is supplied to the switch element SW2 from the pulse current generation unit 10. As a result, at time t1, a drain current Ids2 begins to flow through the switch element SW2.

[0114] At time t2, the control unit 40 generates an L-level control signal and outputs it to the gate driver 24. In response to the L-level control signal, the gate driver 24 applies a gate voltage VgSW2 to the gate of the switch element SW2 to turn it off. Upon receiving this gate voltage VgSW2, the switch element SW2 is turned off.

[0115] When the switch element SW2 is turned off, the supply of pulse current from the pulse current generation unit 10 to the switch element SW2 is interrupted. As a result, at time t2, the drain current Ids2 of the switch element SW2 decreases to 0.

[0116] Next, at time t3, the control unit 40 generates an H-level control signal and outputs it to the gate driver 32. In response to the H-level control signal, the gate driver 32 applies a gate voltage VgDUT to the gate of the semiconductor element 1 to turn it on. Upon receiving this gate voltage VgDUT, the semiconductor element 1 is turned on.

[0117] At time t4, the control unit 40 generates an H-level control signal and outputs it to the gate driver 22. In response to the H-level control signal, the gate driver 22 applies a gate voltage VgSW to the gate of the switch element SW to turn it on. Upon receiving this gate voltage VgSW, the switch element SW is turned on.

[0118] When the switch element SW is turned on, a pulse current is supplied from the pulse current generation unit 10 to the DUT 30. As a result, a drain current Ids begins to flow through the semiconductor element 1, and at the same time, the terminal voltage VDUT (drain-source voltage Vds) of the DUT 30 also begins to increase.

[0119] At time t5, the control unit 40 generates an L-level control signal and outputs it to the gate driver 22. In response to the L-level control signal, the gate driver 22 applies a gate voltage VgSW to the gate of the switch element SW to turn it off. Upon receiving this gate voltage VgSW, the switch element SW is turned off.

[0120] When the switch element SW is turned off, the supply of pulse current from the pulse current generation unit 10 to the DUT 30 is interrupted. As a result, at time t5, the drain current Ids of the semiconductor element 1 decreases to 0. The terminal voltage VDUT (drain-source voltage Vds) of the DUT 30 also decreases to a value close to 0.

[0121] At time t5, the control unit 40 further generates an L-level control signal and outputs it to the gate driver 32. In response to the L-level control signal, the gate driver 32 applies a gate voltage VgDUT to the gate of the semiconductor element 1 to turn it off. Upon receiving this gate voltage VgDUT, the semiconductor element 1 is turned off.

[0122] In this embodiment 5, prior to turning on the switch element SW and the semiconductor element 1, the switch element SW2 is turned on for a certain period of time (the period from time t2 to t3). During this period, the pulse current flowing from the pulse current generation unit 10 to the switch element SW2 rises from zero. Then, after turning off the switch element SW2, when the switch element SW is turned on, the pulse current that rose during the previous period flows through the semiconductor element 1.

[0123] In the pulse current generation unit 10, when the switch element SW2 is turned on at time t1, an excitation current begins to flow to the reactor of the current source 12. Since this excitation current is supplied to the switch element SW2, no excitation current flows to the semiconductor element 1. Therefore, it is possible to suppress the self-heating of the semiconductor element 1 caused by the flow of excitation current to the semiconductor element 1. As a result, fluctuations in the electrical characteristics of the semiconductor element 1 due to temperature changes caused by self-heating are suppressed, making it possible to improve the measurement accuracy of the electrical characteristics of the semiconductor element 1.

[0124] Embodiment 5. Figure 10 is a circuit diagram of a semiconductor device according to Embodiment 5. The semiconductor device according to Embodiment 5 differs from the semiconductor device shown in Figure 8 in that it includes a gate driver 32A instead of the gate driver 32.

[0125] The gate driver 32A is configured to output a gate voltage VgDUT having at least three voltage levels by switching between them. Figure 11 is a circuit diagram of the gate driver 32A. As shown in Figure 11, the gate driver 32A is configured to include a drive signal generation unit 320 and a drive circuit 322.

[0126] The drive signal generation unit 320 generates a gate voltage VgDUT to be applied to the gate of the semiconductor element 1 by operating the drive circuit 322 according to a control signal provided by the control unit 40.

[0127] The drive circuit 322 includes four transistors Q1 to Q4. Transistors Q1 and Q2 are connected in series between the positive power supply node (VL+) and the negative power supply node (VL-). Each of transistors Q1 and Q2 is composed of, for example, a CMOS (Complementary Metal Oxide Semiconductor) inverter. The connection nodes of transistors Q1 and Q2 are connected to the gate of semiconductor element 1.

[0128] Transistors Q3 and Q4 are connected in series between the positive power node (VH+) and the negative power node (VH-). Each of transistors Q3 and Q4 is, for example, composed of a MOSFET. The connection nodes of transistors Q3 and Q4 are connected to the gates of semiconductor element 1. The source of semiconductor element 1 is connected to the ground node (GND).

[0129] The drive circuit 322 is controlled by the drive signal generation unit 320 and can switch the voltage level of the gate voltage VgDUT applied to the gate of the semiconductor element 1 at high speed (for example, about 1 μs) between VH+, VH-, VL+, and VL-. The four voltage levels have the relationship VH+ > VL+ > 0 and VH- < VL- < 0. VH+ and VH- correspond to the stress voltage on the semiconductor element 1. VL+ and VL- correspond to the drive voltage for turning the semiconductor element 1 on and off. Note that VL- is a voltage level below the threshold voltage of the semiconductor element 1. VH- = VL- may also be the case.

[0130] In Embodiment 5, by switching the gate voltage VgDUT of the semiconductor element 1 between multiple voltage levels, the dependence of the switching characteristics of the semiconductor element 1 on transient threshold voltage fluctuations can be evaluated.

[0131] Figure 12 is a timing chart showing an example of operation of a semiconductor device 100 according to Embodiment 5. Figure 12 shows the waveforms of the gate voltage VgSW of the switch element SW, the gate voltage VgSW2 of the switch element SW2, the gate voltage VgDUT of the semiconductor element 1, the drain current Ids of the semiconductor element 1, the drain current Ids2 of the switch element SW2, and the terminal voltage VDUT of DUT30 (drain-source voltage Vds of the semiconductor element 1).

[0132] As shown in Figure 12, at time t0, the control unit 40 controls the gate driver 32A to apply a gate voltage VgDUT of voltage level (VH-) to the gate of the semiconductor element 1.

[0133] Furthermore, the control unit 40 generates an L-level control signal and outputs it to the gate drivers 22 and 24. In response to the L-level control signal, the gate driver 22 applies a gate voltage VgSW to the gate of the switch element SW to turn it off. In response to the L-level control signal, the gate driver 24 applies a gate signal VgSW2 to the gate of the switch element SW2 to turn it off.

[0134] Therefore, at time t0, both semiconductor element 1 and switch elements SW and SW2 are in the off state. The drain current Ids of semiconductor element 1 and the drain current Ids2 of switch element SW2 are 0.

[0135] In Embodiment 5, in order to measure the switching characteristics of the semiconductor element 1, the terminal voltage VDUT of DUT 30 (drain-source voltage Vds of the semiconductor element 1) is applied to a voltage corresponding to the terminal voltage of the voltage source 11.

[0136] At time t1, the control unit 40 controls the gate driver 32A to apply a gate voltage VgDUT of voltage level (VH+) to the gate of the semiconductor element 1. As a result, a stress voltage is applied to the gate of the semiconductor element 1.

[0137] Next, at time t2, the control unit 40 generates an H-level control signal and outputs it to the gate driver 24. In response to the H-level control signal, the gate driver 24 applies a gate voltage VgSW2 to the gate of the switch element SW2 to turn it on. Upon receiving this gate voltage VgSW2, the switch element SW2 is turned on.

[0138] When the switch element SW2 is turned on, a pulse current is supplied to the switch element SW2 from the pulse current generation unit 10. As a result, at time t2, a drain current Ids2 begins to flow through the switch element SW2. Meanwhile, a stress voltage continues to be applied to the gate of the semiconductor element 1.

[0139] At time t3, the control unit 40 generates an L-level control signal and outputs it to the gate driver 24. In response to the L-level control signal, the gate driver 24 applies a gate voltage VgSW2 to the gate of the switch element SW2 to turn it off. Upon receiving this gate voltage VgSW2, the switch element SW2 is turned off.

[0140] When the switch element SW2 is turned off, the supply of pulse current from the pulse current generation unit 10 to the switch element SW2 is interrupted. As a result, at time t3, the drain current Ids2 of the switch element SW2 decreases to 0.

[0141] At time t4, the control unit 40 controls the gate driver 32A to apply a gate voltage VgDUT of voltage level (VL+) to the gate of the semiconductor element 1. This stops the application of stress voltage to the gate of the semiconductor element 1, and a drive voltage is applied to the gate of the semiconductor element 1.

[0142] At time t5, the control unit 40 generates an H-level control signal and outputs it to the gate driver 22. In response to the H-level control signal, the gate driver 22 applies a gate voltage VgSW to the gate of the switch element SW to turn it on. Upon receiving this gate voltage VgSW, the switch element SW is turned on.

[0143] At this time, the control unit 40 controls the gate driver 32A to apply a gate voltage VgDUT of voltage level (VH-) to the gate of the semiconductor element 1 in order to temporarily turn off the semiconductor element 1. As a result, no current flows through the semiconductor element 1 even when the switch element SW is turned on.

[0144] At time t6, the control unit 40 controls the gate driver 32A to apply a gate voltage VgDUT of voltage level (VL2+) to the gate of the semiconductor element 1. VL2+ is a voltage higher than the threshold voltage of the semiconductor element 1 and lower than VH+. When the semiconductor element 1 is turned by receiving the gate voltage VgDUT of VL2+, a drain current Ids begins to flow through the semiconductor element 1. The terminal voltage VDUT (drain-source voltage Vds) of DUT 30 drops to 0.

[0145] At time t7, the control unit 40 controls the gate driver 32A to apply a gate voltage VgDUT of voltage level (VL-) to the gate of the semiconductor element 1. Upon receiving this gate voltage VgDUT, the semiconductor element 1 is turned off. As the semiconductor element 1 is turned off, the drain current Ids of the semiconductor element 1 decreases to 0, while the terminal voltage VDUT of DUT 30 increases.

[0146] Furthermore, at time t8, the control unit 40 generates an L-level control signal and outputs it to the gate driver 22. In response to the L-level control signal, the gate driver 22 applies a gate voltage VgSW to the gate of the switch element SW to turn it off. Upon receiving this gate voltage VgSW, the switch element SW is turned off.

[0147] In this embodiment 5, a stress voltage can be applied to the gate of the semiconductor element 1 during the period when an excitation current is flowing through the switch element SW2. By measuring the drain current Ids of the semiconductor element 1 during the period from time t6 to t7 after the stress voltage is applied, the dependence of the switching characteristics of the semiconductor element 1 on the fluctuation of the threshold voltage Vth can be evaluated.

[0148] Furthermore, the gate driver 32A shown in Embodiment 5 can also be applied to the gate driver 32 shown in Embodiment 1. As described above, the gate driver 32A is configured to switch and output gate voltages VgDUT having at least three voltage levels. Therefore, by applying the gate driver 32A to Embodiment 1, the Ids-Vds characteristics of the semiconductor element 1 can be measured at gate voltages VgDUT of multiple voltage levels, including stress voltage. From the obtained measurement results, the gate voltage dependence of the turn-on characteristics of the semiconductor element 1 can be evaluated.

[0149] Furthermore, in the example of operation shown in Figure 12, a pattern was described in which the gate voltage VgDUT is changed in two stages, VL+ and VH-, during the period from time t4 when the application of stress voltage to the gate of semiconductor element 1 is stopped to time t6 when the drive voltage is applied to the gate of semiconductor element 1. However, the pattern of the gate voltage VgDUT during this period is not limited to this.

[0150] For example, if VL+ is lower than the threshold voltage of semiconductor element 1, then the following four patterns may be applied. The first pattern is to maintain the gate voltage VgDUT at VL+ during the period from time t4 to t6. The second pattern is to set the gate voltage VgDUT to VL+ during the period from time t4 to t5, and to set the gate voltage VgDUT to VL- during the period from time t5 to t6. The third pattern is to maintain the gate voltage VgDUT at VL- during the period from time t4 to t6. The fourth pattern is to maintain the gate voltage VgDUT at VH- during the period from time t4 to t6.

[0151] Embodiment 6. Embodiment 6 applies the semiconductor device according to Embodiments 1 to 5 to a power converter. The following describes the case in which the present disclosure is applied to a three-phase inverter.

[0152] Figure 13 is a block diagram showing the configuration of a power conversion system to which a power conversion device according to Embodiment 6 is applied.

[0153] As shown in Figure 13, the power conversion system comprises a power supply 1000, a power conversion device 2000, and a load 3000. The power supply 1000 is a DC power supply and supplies DC power to the power conversion device 2000. The power supply 1000 can be made up of various materials, for example, a DC grid, a solar cell, or a storage battery. Alternatively, the power supply 1000 may be made up of a rectifier circuit or AC / DC converter connected to an AC grid. Furthermore, the power supply 1000 may be made up of a DC / DC converter that converts the DC power supplied from the DC grid into power usable by the load 3000.

[0154] The power converter 2000 is a three-phase inverter connected between the power supply 1000 and the load 3000, and converts the DC power supplied from the power supply 1000 into three-phase AC power and supplies it to the load 3000. As shown in Figure 13, the power converter 2000 has a main conversion circuit 2010 that converts DC power to AC power, and a control circuit 2030 that outputs control signals to the main conversion circuit 2010 for controlling the main conversion circuit 2010.

[0155] Load 3000 is a three-phase motor driven by AC power supplied from power converter 2000, and is used, for example, as a motor for hybrid vehicles, electric vehicles, railway vehicles, elevators, or air conditioners.

[0156] The details of the power converter 2000 are described below. The main conversion circuit 2010 is equipped with switching elements (not shown), and by switching the switching elements, it converts the DC power supplied from the power supply 1000 into AC power and supplies it to the load 3000. There are various specific circuit configurations for the main conversion circuit 2010, but the main conversion circuit 2010 according to this embodiment is a two-level three-phase full-bridge circuit and can be composed of six switching elements and six freewheeling diodes antiparallel to each switching element. The main conversion circuit 2010 includes a semiconductor device 2020 having each switching element and a drive circuit to drive each switching element. Each switching element and each drive circuit provided in the semiconductor device 2020 are the semiconductor elements 1 and gate drivers 32 of the semiconductor device according to the above-described embodiments 1 to 5. The six switching elements are connected in series in pairs to form upper and lower arms, and each upper and lower arm constitutes each phase (U phase, V phase, W phase) of the full-bridge circuit. Then, the output terminals of each upper and lower arm, i.e., the three output terminals of the main conversion circuit 2010, are connected to the load 3000.

[0157] The control circuit 2030 controls the switching elements of the main converter circuit 2010 so that the desired power is supplied to the load 3000. Specifically, it calculates the time (on time) that each switching element of the main converter circuit 2010 should be in the ON state based on the power to be supplied to the load 3000. For example, the main converter circuit 2010 can be controlled by PWM control, which modulates the on time of the switching elements according to the voltage to be output. The control circuit then outputs a control command (control signal) to the drive circuit of the main converter circuit 2010 so that an ON signal is output to the switching elements that should be in the ON state at each point in time, and an OFF signal is output to the switching elements that should be in the OFF state. The drive circuit outputs an ON signal or an OFF signal as a drive signal to the gate electrode of each switching element according to this control signal.

[0158] In the power conversion device according to Embodiment 6, since the semiconductor device 2020 constituting the main conversion circuit 2010 is a semiconductor device according to Embodiments 1 to 5, the electrical characteristics of the semiconductor device can be measured by independently controlling the state of the gate voltage applied to the semiconductor device and the state of the current flowing through the semiconductor device, similar to Embodiments 1 to 5.

[0159] Embodiment 6 describes an example of applying the present disclosure to a two-level three-phase inverter, but the present disclosure is not limited to this and can be applied to various power conversion devices. In Embodiment 6, a two-level power conversion device was used, but a three-level or multi-level power conversion device may also be used, and the present disclosure may be applied to a single-phase inverter when supplying power to a single-phase load. Furthermore, when supplying power to a DC load, the present disclosure can also be applied to a DC / DC converter or an AC / DC converter.

[0160] Furthermore, regarding the embodiments described above, it was intended from the outset that the configurations described in the embodiments could be appropriately combined, including combinations not mentioned in the specification, to the extent that no inconvenience or inconsistency arises.

[0161] The embodiments disclosed herein should be considered in all respects to be illustrative and not restrictive. The scope of this disclosure is indicated by the claims and not by the foregoing description, and all modifications within the meaning and scope of the claims are intended to be included.

[0162] 1 Power semiconductor element, 10 Pulse current generation unit, 11 Voltage source, 12 Current source, 14 Rectifier element, 18 Switch, 20, 26 Power supply control unit, 22, 24, 32, 32A Gate driver, 30 DUT, 34 Voltage sensor, 36 Voltage holding unit, 40 Control unit, 42 Current sensor, 100 Semiconductor device, 320 Drive signal generation unit, 322 Drive circuit, 1000 Power supply, 2000 Power converter, 2010 Main converter circuit, 2020 Semiconductor device, 2030 Control circuit, 3000 Load, L1, L2 Reactor, SW, SW2 Switch element.

Claims

1. A semiconductor device for measuring the electrical characteristics of a device under test (DUT), wherein the DUT includes a semiconductor element having a first main electrode, a second main electrode, and a control electrode, the semiconductor element being turned on or off in accordance with a control voltage applied to the control electrode, and comprising: a pulse current generation unit electrically connected in series with the DUT and generating a pulse current; a first switch element electrically connected in series with the pulse current generation unit and the DUT, and an energization control unit that supplies the pulse current to the DUT during the on period of the first switch element; a voltage holding unit that clamps the voltage between the first main electrode and the second main electrode of the semiconductor element; a control unit that generates a first control signal for controlling the on / off state of the semiconductor element and a second control signal for controlling the on / off state of the first switch element; and a drive circuit that applies a first control voltage for turning on the semiconductor element or a second control voltage for turning off the semiconductor element to the control electrode in accordance with the first control signal. A semiconductor device comprising a control unit that adjusts the time difference between the timing for turning on the semiconductor element and the timing for turning on the first switch element, and measures the electrical characteristics of the semiconductor element based on the current flowing through the DUT and the voltage between the first main electrode and the second main electrode.

2. The semiconductor device according to claim 1, wherein the drive circuit controls the first control voltage in a variable manner.

3. The semiconductor device according to claim 1, wherein the drive circuit is configured to switch between applying at least three control voltages, including the first control voltage and the second control voltage, to the control electrode of the semiconductor element.

4. The semiconductor device according to claim 1, wherein the control unit adjusts the time difference between the timing for turning on the semiconductor element and the timing for turning on the first switch element, such that the first switch element is turned on when a set time has elapsed since the semiconductor element was turned on.

5. The semiconductor device according to claim 1, wherein the pulse current generation unit includes a voltage source and a current source electrically connected in series with the DUT, and a rectifier element connected in antiparallel to the current source, the current source includes an inductive load, and the rate of increase of the current flowing through the DUT is changed by changing the inductance value of the inductive load.

6. The semiconductor device according to claim 1, wherein the DUT further includes a diode connected in antiparallel to the semiconductor element, and the DUT is electrically connected in series with the pulse current generation unit and the energization control unit to apply a forward voltage to the diode.

7. The current control unit further includes a second switch element that is electrically connected in series with the pulse current generation unit and electrically connected in parallel with the series circuit of the first switch element and the DUT, wherein the control unit turns on the second switch element when the first switch element and the semiconductor element are in the off state, turns off the second switch element and then turns on the semiconductor element, and turns on the first switch element when a set time has elapsed since the semiconductor element was turned on, the semiconductor device according to claim 1.

8. The current supply control unit further includes a second switch element that is electrically connected in series with the pulse current generation unit and electrically connected in parallel with the series circuit of the first switch element and the DUT; the drive circuit is configured to switch between and apply at least three control voltages, including the first control voltage and the second control voltage, to the control electrode of the semiconductor element; the control unit turns on the second switch element when the first switch element and the semiconductor element are in the off state; the drive circuit temporarily applies a third control voltage greater than the first control voltage to the control electrode of the semiconductor element during the on period of the second switch element; the control unit turns off the second switch element, then turns on the first switch element and the semiconductor element, and measures the electrical characteristics of the semiconductor element based on the current flowing through the DUT and the voltage between the first main electrode and the second main electrode, as described in claim 1.

9. The semiconductor device according to claim 1, wherein the first switching element can switch at a higher speed than the semiconductor element and has a higher rated current than the semiconductor element.

10. The semiconductor device according to claim 1, wherein the voltage holding portion includes a resistive element between the first main electrode and the second main electrode of the semiconductor element, and the resistance value of the resistive element is set to be smaller than the off-resistance of the first switching element and larger than the on-resistance of the semiconductor element.

11. A power conversion device having the semiconductor device described in any one of claims 1 to 10, comprising a main conversion circuit that converts and outputs input power, and a control circuit that outputs a control signal to the main conversion circuit for controlling the main conversion circuit.

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