Image sensor

Abstract

The present invention improves image quality in an image sensor in which high-sensitivity sub-pixels and low-sensitivity sub-pixels are disposed.　The image sensor comprises a pixel array unit and a column processing unit. Disposed in the pixel array unit of the image sensor are a plurality of pixels, each including a high-sensitivity sub-pixel that has a sensitivity higher than a prescribed value and a low-sensitivity sub-pixel that has a sensitivity lower than a prescribed value. At least two low-sensitivity sub-pixels are disposed adjacently. The column processing unit performs AD conversion of the respective pixel signals of the low-sensitivity sub-pixels and the high-sensitivity sub-pixels.

Description

Image sensor

[0001] This technology relates to an image sensor. Specifically, it relates to an image sensor capable of expanding the dynamic range.

[0002] Conventionally, in image sensors and the like, in order to achieve a wider dynamic range than normal, an image synthesis technology called HDR (High Dynamic Range) synthesis has been used. For example, an image sensor has been proposed in which a pair of photodiodes (in other words, sub-pixels) with different sensitivities are provided for each pixel, and the pixel signals of each of the sub-pixels are HDR synthesized (see, for example, Patent Document 1). In this image sensor, each of the sub-pixels is arranged such that the four sides of the low-sensitivity sub-pixel are surrounded by the high-sensitivity sub-pixels.

[0003] Japanese Patent Application Laid-Open No. 2017-163010

[0004] In the above-mentioned conventional technology, the dynamic range is expanded by HDR synthesizing the pixel signals of a pair of sub-pixels with different sensitivities. However, in the above-mentioned image sensor, there is a problem that color mixing and blooming occur between the high-sensitivity sub-pixel and the low-sensitivity sub-pixel, resulting in a deterioration of the image quality.

[0005] This technology was created in view of such a situation, and aims to improve the image quality in an image sensor in which high-sensitivity sub-pixels and low-sensitivity sub-pixels are arranged.

[0006] This technology was made to solve the above-mentioned problems. Its first aspect is an image sensor comprising a pixel array portion in which a plurality of pixels each including a high-sensitivity sub-pixel having a sensitivity higher than a predetermined value and a low-sensitivity sub-pixel having a sensitivity lower than the above-mentioned predetermined value are arranged, and at least two of the above-mentioned low-sensitivity sub-pixels are arranged adjacent to each other, and a column processing portion that AD-converts the pixel signals of each of the above-mentioned low-sensitivity sub-pixels and the above-mentioned high-sensitivity sub-pixels. This brings about the effect of improving the image quality.

[0007] Furthermore, in this first aspect, the high-sensitivity subpixel and the low-sensitivity subpixel may be separated by a first RDTI (Rear Deep Trench Isolation), and two adjacent low-sensitivity subpixels may be separated by a second RDTI. This results in the suppression of color mixing and blooming.

[0008] Furthermore, in this first aspect, the depth of the first RDTI may differ from the depth of the second RDTI. This results in the effect of suppressing color mixing and blooming.

[0009] Furthermore, in this first aspect, the embedding material for the first RDTI may be different from the embedding material for the second RDTI. This results in the effect of suppressing color mixing and blooming.

[0010] Furthermore, in this first aspect, the high-sensitivity subpixel and the low-sensitivity subpixel may be separated by a first FFTI (Front Full Trench Isolation), and two adjacent low-sensitivity subpixels may be separated by a second FFTI. This has the effect of suppressing color mixing and blooming.

[0011] Furthermore, in this first aspect, the width of the first FFTI may differ from the width of the second FFTI. This has the effect of suppressing color mixing and blooming.

[0012] Furthermore, in this first aspect, the embedding material for the first FFTI may be different from the embedding material for the second FFTI. This results in the effect of suppressing color mixing and blooming.

[0013] Furthermore, in this first aspect, when viewed from the optical axis direction, each of the multiple pixels and the low-sensitivity sub-pixels may be rectangular, and when viewed from the optical axis direction, the high-sensitivity sub-pixel may have a shape in which a part of the rectangle is cut out. This results in the photodiodes of the pixels having symmetrical structures such as circles or squares, which facilitates the potential design and optical design of each pixel.

[0014] Furthermore, in this first aspect, when viewed from the optical axis direction, each of the multiple pixels may be a polygon with more than four sides, the high-sensitivity sub-pixel may be a shape with a part of a square cut out when viewed from the optical axis direction, and the low-sensitivity sub-pixel may be a rhombus when viewed from the optical axis direction. This results in the suppression of the microloading effect.

[0015] Furthermore, in this first aspect, each of the multiple pixels, when viewed from the optical axis direction, is a polygon with more than four sides, and each of the high-sensitivity subpixels and low-sensitivity subpixels, when viewed from the optical axis direction, may be rectangular. This has the effect of facilitating the potential design and optical design of the low-sensitivity subpixels and high-sensitivity subpixels.

[0016] Furthermore, in this first aspect, each of the multiple pixels, when viewed from the optical axis direction, is rectangular, the high-sensitivity sub-pixel, when viewed from the optical axis direction, is shaped like a rectangle with a part cut out, and the low-sensitivity sub-pixel, when viewed from the optical axis direction, may be a right triangle. This has the effect of making it easier to separate the pixels.

[0017] Furthermore, in this first aspect, each of the plurality of pixels includes a color filter, and the color filter may be arranged in a Bayer array. This results in the application of general coding.

[0018] Furthermore, in this first aspect, each of the plurality of pixels includes a color filter, and the color filters may be arranged in a quad Bayer array. This results in the effect of suppressing color mixing or facilitating FD addition.

[0019] Furthermore, in this first aspect, the system further comprises a first on-chip lens arranged in the low-sensitivity sub-pixel and a plurality of second on-chip lenses arranged in the high-sensitivity sub-pixel, wherein the area of ​​each of the plurality of second on-chip lenses may be the same as that of the first on-chip lens. This has the effect of making the on-chip lenses lower in height.

[0020] Furthermore, in this first aspect, the device further comprises a first on-chip lens positioned across two or more low-sensitivity sub-pixels and a second on-chip lens positioned across two or more high-sensitivity sub-pixels, wherein the area of ​​the second on-chip lens may be larger than that of the first on-chip lens. This reduces process variations and enables Phase Detection Autofocus (PDAF).

[0021] Furthermore, in this first aspect, the high-sensitivity sub-pixel may include a first photodiode and a transfer transistor that transfers charge from the first photodiode to a first floating diffusion layer, while the low-sensitivity sub-pixel may include a second photodiode, a second floating diffusion layer that holds the charge generated by the second photodiode, a capacitive element inserted between the connection node of the second photodiode and the second floating diffusion layer and the power supply voltage, and a floating capacitance gate transistor that opens and closes a path between the connection node of the capacitive element and the second floating diffusion layer and a predetermined node in the high-sensitivity sub-pixel. This results in the generation of a pixel signal.

[0022] Furthermore, in this first aspect, the high-sensitivity sub-pixel further comprises an amplifying transistor that outputs a voltage corresponding to the voltage of the first floating diffusion layer, and a selection transistor that outputs a pixel signal of the output voltage to a vertical signal line according to a selection signal, wherein the floating capacitance gate transistors of two adjacent low-sensitivity sub-pixels share a gate, and the selection transistors of two adjacent high-sensitivity sub-pixels share a gate. This results in a reduction in the number of horizontal signal lines to be wired.

[0023] Furthermore, in this first aspect, at least two of the plurality of pixels may share the first floating diffusion layer. This has the effect of allowing the size of the transistor to be increased.

[0024] This is a block diagram showing an example configuration of an image sensor in the first embodiment of this technology. This is an example of a plan view of the pixel array in the first embodiment of this technology. This is an example of a plan view of the pixel array in a comparative example. This is a plan view showing an example of an on-chip lens arrangement in the first embodiment of this technology. This is an example of a cross-sectional view of a pixel in the first embodiment of this technology. This is a circuit diagram showing an example of a pixel configuration in the first embodiment of this technology. This is a diagram showing an example of a transistor layout in the first embodiment of this technology. This is a diagram showing an example of an RDTI formation method in the first embodiment of this technology. This is an example of a plan view of the pixel array in the second embodiment of this technology. This is an example of a plan view of the pixel array in the first modified example of the second embodiment of this technology. This is an example of a plan view of the pixel array in the second modified example of the second embodiment of this technology. This is an example of a plan view of the pixel array in the third embodiment of this technology. This is an example of a plan view of the pixel array in a modified example of the third embodiment of this technology. This is an example of a cross-sectional view of a pixel in the fourth embodiment of this technology. This is an example of a plan view of the pixel array in the fifth embodiment of this technology. This is an example of a plan view of the pixel array in a modified example of the fifth embodiment of this technology. This is a plan view showing an example of an on-chip lens arrangement in the sixth embodiment of this technology. This is a circuit diagram showing an example of a pixel configuration in the seventh embodiment of this technology. This is a diagram for explaining the gate sharing structure in the seventh embodiment of this technology. This is a diagram showing an example of a transistor layout in the seventh embodiment of this technology. This is an example of a plan view of the pixel array section in the eighth embodiment of this technology. This is a circuit diagram showing an example of a pixel configuration in the eighth embodiment of this technology. This is a diagram for explaining the configuration of the imaging device. This is a block diagram showing an example of a schematic configuration of a vehicle control system. This is an explanatory diagram showing an example of the installation positions of the external information detection unit and the imaging unit.

[0025] The following describes the embodiments for implementing this technology (hereinafter referred to as embodiments). The description will be in the following order: 1. First embodiment (an example in which multiple low-sensitivity subpixels are arranged adjacently) 2. Second embodiment (an example in which multiple rhombus-shaped low-sensitivity subpixels are arranged adjacently) 3. Third embodiment (an example in which multiple right-angled triangular low-sensitivity subpixels are arranged adjacently) 4. Fourth embodiment (an example in which multiple low-sensitivity subpixels are arranged adjacently and separated by FDTI) 5. Fifth embodiment (an example in which multiple low-sensitivity subpixels are arranged adjacently and the color filters are arranged in a quad-Bayer array) 6. Sixth embodiment (an example in which multiple low-sensitivity subpixels are arranged adjacently and the on-chip lens has a large aperture) 7. Seventh embodiment (an example in which multiple low-sensitivity subpixels are arranged adjacently and multiple transistors share a gate) 8. Eighth embodiment (an example in which multiple low-sensitivity subpixels are arranged adjacently and multiple pixels share a floating diffusion layer) 9. Examples of imaging device usage: 10. Examples of applications to moving objects

[0026] <1. First Embodiment> [Example of Image Sensor Configuration] Figure 1 is a block diagram showing an example of the configuration of an image sensor 100 in the first embodiment of this technology. This image sensor 100 includes a vertical drive unit 110, a system control unit 120, a pixel array unit 200, a column processing unit 130, a horizontal drive unit 140, a signal processing unit 150, and a data storage unit 160.

[0027] Multiple pixels, such as pixels 211, are arranged in a two-dimensional grid in the pixel array section 200. Hereinafter, a set of pixels arranged horizontally will be referred to as a "row," and a set of pixels arranged vertically will be referred to as a "column."

[0028] The vertical drive unit 110 selects and drives rows sequentially, outputting analog signals as pixel signals. This vertical drive unit 110 is composed of a shift register, an address decoder, and the like.

[0029] The system control unit 120 controls the operating timing of the vertical drive unit 110, the column processing unit 130, and the horizontal drive unit 140 in synchronization with the vertical synchronization signal VSYNC.

[0030] The column processing unit 130 performs analog-to-digital (AD) conversion and cord-related double sampling (CDS) processing on the pixel signals from each column. The column processing unit 130 outputs the processed digital signals to the signal processing unit 150 according to the control of the horizontal drive unit 140. An analog-to-digital converter (ADC) is also provided for each column in the column processing unit 130.

[0031] The horizontal drive unit 140 controls the column processing unit 130 to sequentially output the pixel signals for each column. This horizontal drive unit 140 is composed of a shift register, an address decoder, and the like.

[0032] The signal processing unit 150 performs various signal processing, such as HDR synthesis, on the digital signals from the column processing unit 130. The signal processing unit 150 outputs image data, which is an arrangement of the processed digital signals, as a frame to the outside. In addition, the signal processing unit 150 temporarily stores the necessary data in the data storage unit 160 during processing.

[0033] Furthermore, at least a portion of the processing performed by the signal processing unit 150 can be carried out externally from the image sensor 100, for example, by a DSP (Digital Signal Processing) circuit.

[0034] [Example of Pixel Array Configuration] Figure 2 is an example of a plan view of the pixel array section 200 in the first embodiment of this technology. The pixel array section 200 has multiple pixels arranged, for example, pixels 211, 212, 213, and 214. Pixels 211 to 214 are arranged in a 2x2 grid. In the figure, the areas enclosed by dotted lines indicate the respective ranges of pixels 211 to 214.

[0035] Pixels 211 and 214 are G (Green) pixels that receive green light through a color filter, and pixel 212 is a B (Blue) pixel that receives blue light through a color filter. Pixel 213 is an R (Red) pixel that receives red light through a color filter. Each of these pixels includes a high-sensitivity subpixel and a low-sensitivity subpixel. A high-sensitivity subpixel is a subpixel whose sensitivity is higher than a predetermined value, and a low-sensitivity subpixel is a subpixel whose sensitivity is lower than that predetermined value.

[0036] Pixel 211 includes a high-sensitivity sub-pixel 220 and a low-sensitivity sub-pixel 230, and pixel 212 includes a high-sensitivity sub-pixel 240 and a low-sensitivity sub-pixel 250. Pixel 213 includes a high-sensitivity sub-pixel 260 and a low-sensitivity sub-pixel 250, and pixel 214 includes a high-sensitivity sub-pixel 280 and a low-sensitivity sub-pixel 290.

[0037] Furthermore, the color filters of each pixel are arranged, for example, using a Bayer array. This allows for the application of general Bayer coding. In the figure, "R," "Gr," "Gb," and "B" attached to each pixel indicate the color transmitted by the color filter of that pixel. Focusing on the minimum repeating range of four pixels arranged in a 2x2 grid (e.g., pixels 211 to 214), the Gr and Gb pixels are arranged diagonally with respect to the row (or column) direction. With the top of the paper as the north side, the R pixels are placed to the east of the Gr pixels, and the B pixels are placed to the west of the Gb pixels.

[0038] Furthermore, when viewed from the optical axis direction, the shape of each pixel and low-sensitivity subpixel is rectangular (or square, for example). High-sensitivity subpixels have a larger area than low-sensitivity subpixels, and their shape is a rectangle with the portion corresponding to the low-sensitivity subpixel cut out.

[0039] Furthermore, in the pixel array section 200, subpixels are arranged such that at least two low-sensitivity subpixels are adjacent to each other. Here, "adjacent" means that the edges of the two pixels are touching, or that the vertices of the two pixels are touching. The figure shows an example where the edges are touching.

[0040] For example, within pixel 211, the low-sensitivity sub-pixel 230 is arranged at the southeast corner, and within pixel 212, the low-sensitivity sub-pixel 250 is arranged at the northeast corner. Within pixel 213, the low-sensitivity sub-pixel 270 is arranged at the southwest corner, and within pixel 214, the low-sensitivity sub-pixel 290 is arranged at the northwest corner. With this arrangement, four low-sensitivity sub-pixels are adjacent to each other at the center of the minimum repetition region and are arranged in a 2-row × 2-column pattern.

[0041] Then, the subsequent column processing unit 130 converts the pixel signals of the high-sensitivity sub-pixels and the low-sensitivity sub-pixels into digital signals. The signal processing unit 150 HDR-combines those digital signals to generate a combined image.

[0042] Generally, since the high-sensitivity sub-pixels have a larger light reception amount than the low-sensitivity sub-pixels, light may leak from the high-sensitivity sub-pixels to the low-sensitivity sub-pixels and cause color mixing. Also, when the illuminance is extremely high, the charge overflowing from the high-sensitivity sub-pixels may leak into the low-sensitivity sub-pixels, resulting in blooming. Thus, when sub-pixels with different sensitivities are adjacent, color mixing and blooming are likely to occur in the low-sensitivity sub-pixels. On the other hand, color mixing and blooming are less likely to occur between sub-pixels with the same sensitivity.

[0043] Here, assume, as in Patent Document 1, a configuration in which the periphery of the low-sensitivity sub-pixels is arranged to be surrounded by high-sensitivity sub-pixels as a comparative example.

[0044] FIG. 3 is an example of a plan view of the pixel array unit 200 in the comparative example. In this comparative example, a low-sensitivity sub-pixel of the same color is arranged northwest of the high-sensitivity sub-pixel. For example, the low-sensitivity sub-pixel 230 is arranged northwest of the high-sensitivity sub-pixel 220, and the low-sensitivity sub-pixel 250 is arranged northwest of the high-sensitivity sub-pixel 240. The low-sensitivity sub-pixel 270 is arranged northwest of the high-sensitivity sub-pixel 260, and the low-sensitivity sub-pixel 290 is arranged northwest of the high-sensitivity sub-pixel 280. In this arrangement, the low-sensitivity sub-pixels are surrounded on all four sides by four high-sensitivity sub-pixels. For example, the low-sensitivity sub-pixel 290 is surrounded by the high-sensitivity sub-pixels 220, 240, 260, and 280. Then, when light or charge leaks from those four high-sensitivity sub-pixels into the low-sensitivity sub-pixel 290, color mixing and blooming occur. The arrows in the figure indicate the directions in which light and charge leak.

[0045] In contrast, in the array illustrated in FIG. 2, four low-sensitivity sub-pixels are arranged adjacent to each other at the center of the minimum repeating region. In this array, only a part of the four sides of the low-sensitivity sub-pixel is adjacent to the high-sensitivity sub-pixel, and the rest is adjacent to the low-sensitivity sub-pixel. For example, two sides of the low-sensitivity sub-pixel 230 are adjacent to the high-sensitivity sub-pixel 220, and the remaining two sides are adjacent to the low-sensitivity sub-pixels 250 and 270. Therefore, compared with a comparative example in which light or charge leaks into the surrounding four high-sensitivity sub-pixels, the leaking light and charge can be reduced, and color mixing can suppress blooming. As a result, the noise of the low-sensitivity sub-pixel is reduced, and the SNR (Signal-Noise Ratio) is improved. Since the pixel signal of the low-sensitivity sub-pixel is used in a high-brightness subject area (such as sky) in the composite image, for example, the roughness in that area is reduced, and the image quality is improved.

[0046] FIG. 4 is a plan view showing an example of the arrangement of on-chip lenses in the first embodiment of the present technology. Three on-chip lenses 311 are arranged for each of the high-sensitivity sub-pixels (such as 220). One on-chip lens 312 is arranged for each of the low-sensitivity sub-pixels (such as 230). The areas of these on-chip lenses 311 and 312 are, for example, the same.

[0047] In the figure, the optical axis is defined as the Z-axis, and the axis at an angle of 45 degrees with respect to the row direction (or column direction) is defined as the X-axis. The axis perpendicular to the X-axis and the Z-axis is defined as the Y-axis.

[0048] The on-chip lenses 311 and 312 are examples of the first on-chip lens and the second on-chip lens described in the claims.

[0049] FIG. 5 is an example of a cross-sectional view of the pixels 212 and 213 in the first embodiment of the present technology. This figure shows a cross-sectional view of the pixel array unit 200 cut along the line segment A - A' along the X-axis in FIG. 4 and viewed from the Y-axis direction.

[0050] As illustrated in Figure 5, a photodiode 241 is formed in the high-sensitivity sub-pixel 240. A photodiode 251 is formed in the low-sensitivity sub-pixel 250. With the light-receiving side facing upwards, a color filter 321 is formed above these photodiodes, and on-chip lenses 311 and 312 are positioned above the color filter 321. The cross-sectional views of the high-sensitivity sub-pixel 260 and the low-sensitivity sub-pixel 270 are similar.

[0051] Furthermore, adjacent high-sensitivity sub-pixels 240 and low-sensitivity sub-pixels 250 are separated by an RDTI 331 formed between them. Adjacent low-sensitivity sub-pixels 250 and 270 are separated by an RDTI 332 formed between them.

[0052] Let Z1 be the Z-coordinate of the upper surface of the silicon substrate on which the photodiode is formed, and Z4 be the Z-coordinate of the lower surface. RDDI 331 is formed to a depth that extends from Z1 to Z3, which is between Z1 and Z4, without penetrating the silicon substrate. RDDI 332 is formed to a depth that extends from Z1 to Z2, which is between Z1 and Z3. That is, the depth of RDTI 331 is smaller than that of RDTI 332. Furthermore, it is preferable that the width of RDTI 331 is wider than that of RDTI 332. This maximizes the volume of the photodiode for the low-sensitivity sub-pixel.

[0053] Furthermore, as the embedding material for RDTI331 and 332, for example, silicon dioxide (SiO₂), which has a lower refractive index than silicon, can be used. ２ ) and tungsten (W), which has a high light absorption rate, are used.

[0054] Furthermore, the embedding materials for RDTI 331 and 332 may be different. In this case, for example, RDTI 331 may be embedded with a metal such as tungsten (W), and RDTI 332 may be embedded with an insulating film such as silicon dioxide (SiO2).

[0055] Note that RDTI 331 and 332 are examples of the first and second RDTI described in the claims.

[0056] As illustrated in Figures 4 and 5, by aligning the sizes of the on-chip lenses 311 and 312, the on-chip lenses can be made lower in height during the manufacturing process, bringing their vertices closer to the photodiode. This reduces color mixing when light is incident at an oblique angle. Furthermore, by varying the sizes of the obliquely aligned on-chip lenses 311 and 312, the sensitivity ratio of the sub-pixels can also be changed.

[0057] Furthermore, by grouping multiple low-sensitivity subpixels together, the separation structure can be changed between subpixels with different sensitivities and between subpixels with the same sensitivity, as illustrated in Figure 5. Specifically, the RDTI 331 between subpixels with different sensitivities can be made deeper than the RDTI 332, and the width of the RDTI 331 can be increased. This allows for the preferential suppression of blooming and color mixing between pixels with different sensitivities. In addition, generally, the larger the surface area of ​​the boundary between the pixel separation structure (RDTI, etc.) and the silicon, the more likely dark current is to occur, but this can also be optimized.

[0058] [Example of Pixel Configuration] Figure 6 is a circuit diagram showing an example configuration of pixels 211 and 212 in the first embodiment of this technology. Pixel 211 comprises a photodiode 221, a transfer transistor 222, a reset transistor 223, an FDG transistor 224, a floating diffusion layer 225, an amplification transistor 226, and a selection transistor 227. These elements are arranged within a high-sensitivity sub-pixel 220. Furthermore, pixel 211 comprises a photodiode 231, a capacitive element 232, a floating diffusion layer 233, and an FCG transistor 234. These elements are arranged within a low-sensitivity sub-pixel 230.

[0059] Furthermore, for each transistor within the pixel 211, such as the transfer transistor 222, nMOS (n-channel metal oxide semiconductor) transistors are used.

[0060] In the high-sensitivity sub-pixel 220, the photodiode 221 generates electric charge by photoelectric conversion. The photodiode 221 is an example of the first photodiode described in the claims.

[0061] The transfer transistor 222 transfers charge from the photodiode 221 to the floating diffusion layer 225 according to the transfer signal TGL1 from the vertical drive unit 110.

[0062] The reset transistor 223 initializes the floating diffusion layers 225 and 233 according to the reset signal RST1 from the vertical drive unit 110.

[0063] The FDG transistor 224 controls the conversion gain when converting charge to voltage according to the control signal FDG1 from the vertical drive unit 110. The reset transistor 223 and the FDG transistor 224 are connected in series between the power supply voltage VDD and the floating diffusion layer 225.

[0064] The floating diffusion layer 225 accumulates electric charge and generates a voltage corresponding to the amount of charge.

[0065] The amplifying transistor 226 constitutes a source follower circuit and outputs a voltage from the source corresponding to the voltage of the floating diffusion layer 225. The floating diffusion layer 225 is an example of the first floating diffusion layer described in the claims.

[0066] The selection transistor 227 outputs an analog signal of the voltage output by the amplification transistor 226 as a pixel signal to the column processing unit 130, according to the selection signal SEL1 from the vertical drive unit 110. This pixel signal is output via the vertical signal line 209.

[0067] In the low-sensitivity sub-pixel 230, the photodiode 231 generates an electric charge by photoelectric conversion. The photodiode 231 is an example of the second photodiode described in the claims.

[0068] The floating diffusion layer 233 is connected to the cathode of the photodiode 231. The floating diffusion layer 233 also accumulates charge from the photodiode 231 and generates a voltage corresponding to the amount of charge. Note that the floating diffusion layer 233 is an example of the second floating diffusion layer described in the claims.

[0069] The capacitive element 232 is inserted between the connection node of the photodiode 231 and the floating diffusion layer 233 and the power supply voltage MIM-VDD. For example, an MIM (Metal-Insulator-Metal) capacitance is used as this capacitive element 232.

[0070] The FCG transistor 234 opens and closes the path between the connection node of the capacitive element 232 and the floating diffusion layer 233 and the connection node of the reset transistor 223 and the FDG transistor 224, according to the control signal FCG1 from the vertical drive unit 110. The FCG transistor 234 is an example of a floating capacitance gate transistor as described in the claims.

[0071] Pixel 212 comprises a photodiode 241, a transfer transistor 242, a reset transistor 243, an FDG transistor 244, a floating diffusion layer 245, an amplification transistor 246, and a selection transistor 247. These elements are arranged within a high-sensitivity sub-pixel 240. Furthermore, pixel 212 comprises a photodiode 251, a capacitive element 252, a floating diffusion layer 253, and an FCG transistor 254. These elements are arranged within a low-sensitivity sub-pixel 250.

[0072] The circuit configuration of pixel 212 is the same as that of pixel 211. The vertical drive unit 110 supplies the control signal FCG2, reset signal RST2, control signal FDG2, transfer signal TGL2, and selection signal SEL2 to the pixel 212.

[0073] Figure 7 shows an example of the transistor layout in the first embodiment of this technology. Focusing on the high-sensitivity sub-pixel 220 and the low-sensitivity sub-pixel 230, the high-sensitivity sub-pixel 220 contains a transfer transistor 222, a reset transistor 223, an FDG transistor 224, an amplification transistor 226, and a selection transistor 227. The low-sensitivity sub-pixel 230 contains an FCG transistor 234. The layout of the other sub-pixels is similar.

[0074] Figure 8 shows an example of a method for forming RDTI 331 and 332 in the first embodiment of this technology.

[0075] As illustrated in figure a, an RDT (Rear Deep Trench) mask 400 is formed on the semiconductor substrate on which the photodiodes 221 and 231 are formed. This RDT mask 400 masks areas other than those where the RDT is formed.

[0076] Then, as illustrated in figure b, RDTI 331 and 332 are formed by dry etching using the RDT mask 400.

[0077] Thus, according to the first embodiment of this technology, in a pixel array 200 in which a plurality of pixels are arranged, each containing high-sensitivity subpixels and low-sensitivity subpixels, at least two low-sensitivity subpixels are arranged adjacent to each other. This makes it possible to suppress color mixing and blooming and improve image quality.

[0078] <2. Second Embodiment> In the first embodiment described above, square low-sensitivity subpixels were arranged, but the image sensor is not limited to this arrangement. The image sensor 100 in this second embodiment differs from the first embodiment in that the low-sensitivity subpixels are rotated to form a rhombus.

[0079] Figure 9 is an example of a plan view of the pixel array in a second embodiment of this technology. In this second embodiment, the shape of the low-sensitivity sub-pixel 230, as viewed from the Z-axis direction, is a rhombus (in other words, a rectangle) obtained by rotating a square 45 degrees with respect to the row direction (or column direction). The shape of the high-sensitivity sub-pixel 220 is a shape in which a part of a square (in other words, a rectangle) is cut out. The shape of the pixel 211, which includes these sub-pixels, is a polygon with more than four sides. The same applies to pixels other than pixel 211.

[0080] As illustrated in Figure 2, in the first embodiment in which the low-sensitivity subpixel is square, there are a maximum of four edges that converge at the vertices of the boundary between the high-sensitivity subpixel and the low-sensitivity subpixel.

[0081] In contrast, as illustrated in Figure 9, when the low-sensitivity subpixel is rhombus-shaped, a maximum of three edges are needed to merge at the vertices at the boundary between the high-sensitivity and low-sensitivity subpixels. Therefore, when the RDTI between pixels is deepened by dry etching, the microloading effect caused by the difference in pattern density can be suppressed compared to the first embodiment. This makes it possible to reduce the difference in depth and width of the RDTI between the edges and their merging points (in other words, the vertices).

[0082] Thus, according to the second embodiment of this technology, since the low-sensitivity sub-pixels are rhombic in shape, the microloading effect can be suppressed.

[0083] [First Modification] In the second embodiment described above, the low-sensitivity sub-pixel 230 was rhombus-shaped, but the high-sensitivity sub-pixel 220 can also be rotated to form a rhombus shape. The image sensor 100 in this first modification of the second embodiment differs from the second embodiment in that, in addition to the low-sensitivity sub-pixel 230, the high-sensitivity sub-pixel 220 is also rhombus-shaped.

[0084] Figure 10 is an example of a plan view of the pixel array 200 in a first modification of the second embodiment of this technology. In this first modification of the second embodiment, the shape of both the low-sensitivity sub-pixel 230 and the high-sensitivity sub-pixel 220, as viewed from the Z-axis direction, is a rhombus obtained by rotating a square 45 degrees with respect to the row direction (or column direction). The shape of the pixel 211, which includes these sub-pixels, is a polygon with more than four sides. The same applies to pixels other than pixel 211.

[0085] In the second embodiment illustrated in Figure 9, the high-sensitivity sub-pixel 220 was not rectangular. However, in the first modified example of the second embodiment illustrated in Figure 10, the high-sensitivity sub-pixel 220 is rectangular (rhombic), which simplifies optical design and potential design compared to Figure 9.

[0086] Furthermore, in Figure 10, when the image sensor 100 samples low-sensitivity subpixels and reads out the pixel data, and arranges them for display on the display, they can be arranged at equal intervals in both the horizontal and vertical directions. This improves image quality.

[0087] Thus, according to the first modification of the second embodiment of this technology, since the high-sensitivity sub-pixels 220 are also rectangular (rhombic) in addition to the low-sensitivity sub-pixels 230, optical design and potential design become easier. Furthermore, when arranging the pixel data of the sampled low-sensitivity sub-pixels for display on a display, they can be arranged at equal intervals in both the horizontal and vertical directions.

[0088] [Second Modification] In the first modification of the second embodiment described above, both the high-sensitivity sub-pixel 220 and the low-sensitivity sub-pixel 230 were rhombus-shaped, but they can also be rotated to form squares. The image sensor 100 in this second modification of the second embodiment differs from the first modification of the second embodiment in that both the high-sensitivity sub-pixel 220 and the low-sensitivity sub-pixel 230 are square.

[0089] Figure 11 is an example of a plan view of the pixel array 200 in a second modification of the second embodiment of this technology. In this second modification of the second embodiment, the entire array exemplified in Figure 10 is rotated by 45 degrees with respect to the row direction (or column direction), making both the high-sensitivity sub-pixels 220 and the low-sensitivity sub-pixels 230 square (rectangle). This makes it possible to form RDTI along the crystal orientation of silicon.

[0090] Thus, according to the second modification of the second embodiment of this technology, since both the high-sensitivity sub-pixel 220 and the low-sensitivity sub-pixel 230 are square, RDTI can be formed along the crystal orientation of silicon.

[0091] <3. Third Embodiment> In the first embodiment described above, the low-sensitivity subpixels were rectangular. However, with this shape, there are two sides between the high-sensitivity subpixels and the low-sensitivity subpixels, and it is necessary to form RDTIs on each of those sides to separate them. The image sensor 100 in this third embodiment differs from the first embodiment in that the low-sensitivity subpixels are right triangles, thereby facilitating separation between pixels.

[0092] Figure 12 is an example of a plan view of the pixel array section 200 in a third embodiment of the present technology. In this third embodiment, the shape of the low-sensitivity subpixels is a right triangle when viewed from the Z-axis direction, and the shape of the pixels is rectangular. The shape of the high-sensitivity subpixels is a rectangle with the portion of the low-sensitivity subpixels cut out.

[0093] Furthermore, subpixels are arranged such that the vertices of two or more low-sensitivity subpixels touch (in other words, are adjacent). For example, in a right-angled triangle low-sensitivity subpixel, both acute angles are 45 degrees, and the two sides other than the hypotenuse are half the length of the pixel's sides. Also, in pixel 211, low-sensitivity subpixel 230 is positioned to the northwest, and in pixel 212, low-sensitivity subpixel 250 is positioned to the southeast. In pixel 213, low-sensitivity subpixel 270 is positioned to the southeast, and in pixel 214, low-sensitivity subpixel 290 is positioned to the northwest. In this case, for example, the vertex of low-sensitivity subpixel 250 and the vertex of low-sensitivity subpixel 290 touch.

[0094] As illustrated in the figure, by making the low-sensitivity subpixel a right triangle, the side between the high-sensitivity subpixel and the low-sensitivity subpixel becomes one side. Therefore, when separating the low-sensitivity subpixel, it is only necessary to form an RDTI diagonally, making separation between pixels easier.

[0095] Thus, according to the third embodiment of this technology, since the low-sensitivity sub-pixels are shaped like right triangles, separation between pixels becomes easier.

[0096] [Modification] In the third embodiment described above, subpixels were arranged so that the vertices of two or more low-sensitivity subpixels were touching, but they can also be arranged so that the edges of those low-sensitivity subpixels are touching. The image sensor 100 in this modification of the third embodiment differs from the third embodiment in that the edges of two or more low-sensitivity subpixels are touching.

[0097] Figure 13 is an example of a plan view of the pixel array section 200 in a modified example of the third embodiment of the present technology. In the modified example of the third embodiment, subpixels are arranged so that the sides of two or more low-sensitivity subpixels are in contact with each other. For example, in a right-angled triangular low-sensitivity subpixel, one of the two acute angles is greater than 45 degrees, and the longer of the two sides other than the hypotenuse is longer than half the length of the pixel's side. In this case, for example, the side of low-sensitivity subpixel 250 and the side of low-sensitivity subpixel 290 are in contact.

[0098] As illustrated in the figure, in a configuration where two or more low-sensitivity subpixels are arranged so that their edges touch, the area of ​​the low-sensitivity subpixel can be changed by adjusting the acute angle of the low-sensitivity subpixel. Therefore, the sensitivity ratio of high-sensitivity and low-sensitivity subpixels can be easily changed by adjusting the acute angle.

[0099] Thus, according to this modification of the third embodiment of the present technology, since the sides of two or more right-angled triangles of low-sensitivity subpixels are arranged to be touching, the sensitivity ratio of high-sensitivity subpixels and low-sensitivity subpixels can be easily changed by adjusting the acute angles.

[0100] <4. Fourth Embodiment> In the first embodiment described above, pixels were separated by RDTI, but the configuration is not limited to this. The image sensor 100 in this fourth embodiment differs from the first embodiment in that pixels are separated by FFTI.

[0101] Figure 14 is an example of a cross-sectional view of pixels 212 and 213 in a fourth embodiment of this technology. In this fourth embodiment, an FFTI 341 penetrating the silicon substrate is formed between a high-sensitivity sub-pixel 240 and a low-sensitivity sub-pixel 250. An FFTI 342 penetrating the silicon substrate is also formed between the low-sensitivity sub-pixels 250 and 270. By forming FFTIs deeper than RDTIs, color mixing and blooming can be reduced compared to the case where RDTIs are formed.

[0102] Furthermore, it is preferable that the width of FFTI341 is wider than that of FFTI342.

[0103] Furthermore, the embedding materials for FFTI 341 and 342 may be different. In this case, for example, FFTI 341 may be embedded with a metal such as tungsten (W), and FFTI 342 may be embedded with an insulating film such as silicon dioxide (SiO2).

[0104] FFTI 341 and 342 are examples of the first and second FFTI described in the claims.

[0105] Furthermore, the second and third embodiments, as well as their variations, can be applied to the fourth embodiment.

[0106] Thus, according to the fourth embodiment of this technology, since FFTI is formed and separated between pixels, color mixing and blooming can be reduced compared to the case where RDTI is formed.

[0107] <5. Fifth Embodiment> In the first embodiment described above, the color filters of each pixel were arranged in a Bayer array, but the arrangement method is not limited to a Bayer array. The image sensor 100 in this fifth embodiment differs from the first embodiment in that the color filters are arranged in a quad Bayer array.

[0108] Figure 15 is an example of a plan view of the pixel array section 200 in the fifth embodiment of this technology. In this fifth embodiment, the color filters of each pixel are arranged in a quad-Bayer array. In a quad-Bayer array, four pixels of the same color are arranged adjacent to each other in a 2x2 grid. Furthermore, when four pixels of the same color are added together, the arrangement of the added pixels becomes a Bayer array.

[0109] By using a quad Bayer array, each of the four adjacent low-sensitivity subpixels becomes the same color, further suppressing color mixing. For example, if pixels 211 to 214 are the same color, all four low-sensitivity subpixels clustered in the center of them will also become the same color.

[0110] Furthermore, the second, third, and fourth embodiments, as well as their variations, can be applied to the fifth embodiment.

[0111] Thus, according to the fifth embodiment of this technology, since the color filters are arranged in a quad Bayer array, color mixing can be further suppressed.

[0112] [Modified Version] In the fifth embodiment described above, the color filters were arranged in a quad Bayer array, and low-sensitivity sub-pixels were concentrated in the center of four pixels of the same color. However, it is preferable to facilitate the sharing of transistors and floating diffusion layers. The image sensor 100 in this modified version of the fifth embodiment differs from the fifth embodiment in that the low-sensitivity sub-pixels are arranged to avoid the center of four pixels of the same color.

[0113] Figure 16 is an example of a plan view of the pixel array section 200 in a modified example of the fifth embodiment of the present technology. In this modified example of the fifth embodiment, the filters for each pixel are arranged in a quad Bayer array, similar to the fifth embodiment.

[0114] However, focusing on four pixels of the same color, the low-sensitivity sub-pixels are positioned to avoid the center of those pixels. For example, in pixels 211 to 214 of the same color, the low-sensitivity sub-pixel 230 is positioned in the northwest of pixel 211, and the low-sensitivity sub-pixel 250 is positioned in the southwest of pixel 212. The low-sensitivity sub-pixel 270 is positioned in the northeast of pixel 213, and the low-sensitivity sub-pixel 290 is positioned in the southeast of pixel 214.

[0115] By placing low-sensitivity sub-pixels away from the center of four pixels of the same color, a floating diffusion layer (not shown) or transistors can be placed near the center of those pixels and shared by the four pixels. This makes FD addition of four pixels of the same color easier.

[0116] Furthermore, the second, third, and fourth embodiments, as well as their respective variations, can be applied to the modifications of the fifth embodiment.

[0117] Thus, according to the modified fifth embodiment of this technology, in the quad Bayer array, low-sensitivity subpixels are arranged while avoiding the center of four pixels of the same color, making FD addition of those pixels easier.

[0118] <6. Sixth Embodiment> In the first embodiment described above, one on-chip lens was placed in the low-sensitivity sub-pixel and three on-chip lenses were placed in the high-sensitivity sub-pixel. However, the aperture of these on-chip lenses can be increased. The image sensor 100 in this sixth embodiment differs from the first embodiment in that the on-chip lenses have a larger aperture.

[0119] Figure 17 is a plan view showing an example of the arrangement of on-chip lenses 311 and 312 in the sixth embodiment of this technology. In the sixth embodiment, the on-chip lens 312 has a larger aperture than in the first embodiment and is arranged across the low-sensitivity sub-pixels 230, 250, 270 and 290. The on-chip lens 311 also has a larger aperture than in the first embodiment and is arranged across four high-sensitivity sub-pixels of the same color, including the high-sensitivity sub-pixel 280. Furthermore, the area of ​​the on-chip lens 311 is larger than the area of ​​the on-chip lens 312.

[0120] As illustrated in the figure, increasing the diameter of the on-chip lenses 311 and 312 reduces process variations.

[0121] Furthermore, by arranging the on-chip lens 311 across four high-sensitivity sub-pixels of the same color, the signal processing unit 150 can perform PDAF using the pixel signals of these high-sensitivity sub-pixels. In this case, the vertical drive unit 110 drives two of the four high-sensitivity sub-pixels that share the on-chip lens 311, and then drives the remaining two pixels. The signal processing unit 150 detects the difference between the image formed by arranging the pixel signals of the first two pixels and the image formed by arranging the pixel signals of the remaining two pixels as a phase difference, and determines the position of the lens in focus from that phase difference.

[0122] Furthermore, the second, third, fourth, and fifth embodiments, as well as their variations, can be applied to the sixth embodiment.

[0123] Thus, according to the sixth embodiment of this technology, the on-chip lenses 311 and 312 are made larger in diameter, which reduces process variations and enables PDAF.

[0124] <7. Seventh Embodiment> In the first embodiment described above, an FCG transistor and a selection transistor were arranged for each pixel, but these transistors can share a gate. The image sensor 100 in this seventh embodiment differs from the first embodiment in that multiple transistors share a gate.

[0125] Figure 18 is a circuit diagram showing one configuration example of pixels 211 and 212 in the seventh embodiment of this technology. In the seventh embodiment, two vertical signal lines 208 and 209 are wired for each row of pixels. In addition, two ADCs (not shown) are arranged in the column processing unit 130 for each row.

[0126] Furthermore, the FCG transistor 234 of pixel 211 and the FCG transistor 254 of pixel 212 share a gate. The control signal FDG is input to this gate.

[0127] Furthermore, the selection transistor 227 for pixel 211 and the selection transistor 247 for pixel 212 share a gate. The control signal SEL is input to this gate. In addition, the selection transistor 227 outputs the pixel signal to the vertical signal line 208, and the selection transistor 247 outputs the pixel signal to the vertical signal line 209.

[0128] Similarly, the FCG transistors (not shown) of pixels 213 and 214 share a gate. The control signal FCG is input to this gate. Also, the selection transistors (not shown) of pixels 213 and 214 share a gate. The control signal SEL is input to this gate.

[0129] In this figure, for the sake of clarity, the gates of FCG transistors 234 and 254 are shown separately.

[0130] However, in reality, as illustrated in Figure 19a, the gates of FCG transistors 234 and 254 are common.

[0131] Similarly, although Figure 18 shows the gates of selection transistors 227 and 247 separately, in reality, their gates are common, as illustrated in Figure 19b.

[0132] If the gates are not shared, as illustrated in Figure 6, the vertical drive unit 110 needs to supply FCG1, RST1, FDG1, TGL1, SEL1, FCG2, RST2, FDG2, TGL2, and SEL2 to two rows. In this case, 10 horizontal signal lines need to be wired to two rows to transmit these signals.

[0133] In contrast, when the gates are shared, as illustrated in Figure 18, the vertical drive unit 110 only needs to supply FCG, RST1, FDG1, TGL1, SEL, FDG2, RST2, and TGL2 to two rows. In this case, the number of horizontal signal lines wired to those two rows can be reduced to eight.

[0134] Furthermore, in Figure 18, since there are two vertical signal lines per column, the vertical drive unit 110 can drive two rows simultaneously using the selection signal SEL. Since there are two ADCs per column, the image sensor 100 can read two rows simultaneously.

[0135] Figure 20 shows an example of the transistor layout in the seventh embodiment of this technology. The FCG transistors 234 and 254 share a gate, which spans the low-sensitivity sub-pixels 230 and 250. The selection transistors 227 and 247 also share a gate, which spans the high-sensitivity sub-pixels 220 and 240.

[0136] Furthermore, the seventh embodiment can be applied to the second, third, fourth, fifth, and sixth embodiments, as well as their variations.

[0137] Thus, according to the seventh embodiment of this technology, since multiple transistors share a gate, the number of horizontal signal lines can be reduced.

[0138] <8. Eighth Embodiment> In the first embodiment described above, the floating diffusion layer and transistors were arranged for each pixel, but they can also be shared by multiple pixels. The image sensor 100 in this eighth embodiment differs from the first embodiment in that multiple pixels share the floating diffusion layer and the like.

[0139] Figure 21 is an example of a plan view of the pixel array in the eighth embodiment of this technology. The pixel arrangement in the eighth embodiment is the same as in the first embodiment, but we will focus on four pixels that differ from those in the first embodiment.

[0140] Let's consider the Gb pixel as pixel 211, the R pixel as pixel 212, the B pixel as pixel 213, and the Gr pixel as pixel 214, and focus on these. The low-sensitivity sub-pixel 230 in pixel 211 is located in the northwest, and the low-sensitivity sub-pixel 250 in pixel 212 is located in the southwest. The low-sensitivity sub-pixel 270 in pixel 213 is located in the northeast, and the low-sensitivity sub-pixel 290 in pixel 214 is located in the southeast. In this way, no low-sensitivity sub-pixel is located in the center of these four pixels. Therefore, a floating diffusion layer or the like can be placed in the center of these four pixels and shared by the four pixels.

[0141] Figure 22 is a circuit diagram showing one example configuration of pixels 211, 212, 213, and 214 in the eighth embodiment of this technology.

[0142] Pixel 211 comprises photodiodes 221 and 231, a transfer transistor 222, a capacitive element 232, a floating diffusion layer 233, and an FCG transistor 234. Pixel 212 comprises photodiodes 241 and 251, a transfer transistor 242, a capacitive element 252, a floating diffusion layer 253, and an FCG transistor 254. The connection configuration of these elements is the same as in the first embodiment.

[0143] Pixel 213 comprises photodiodes 261 and 271, a transfer transistor 262, a capacitive element 272, a floating diffusion layer 273, and an FCG transistor 274. Pixel 214 comprises photodiodes 281 and 291, a transfer transistor 282, a capacitive element 292, a floating diffusion layer 293, and an FCG transistor 294. The connection configuration of these elements is the same as in the first embodiment.

[0144] Furthermore, the four pixels share a reset transistor 223, an FDG transistor 224, a floating diffusion layer 225, amplification transistors 226-1 and 226-2, and a selection transistor 227. The connection configuration of these elements is the same as in the first embodiment, except that amplification transistors 226-1 and 226-2 are connected in parallel.

[0145] For example, nMOS transistors are used as the transistors within the four pixels mentioned above.

[0146] Furthermore, FCG transistors 234, 254, 274, and 294 are commonly connected to the connection nodes of reset transistor 223 and FDG transistor 224. Transfer transistors 222, 242, 262, and 282 are commonly connected to the floating diffusion layer 225.

[0147] During readout, the vertical drive unit 110 turns on the reset transistor 223 and the FDG transistor 224 at predetermined timings, accumulating charge in each photodiode of the high-sensitivity pixels, thereby enabling individual signal readout. Furthermore, by arranging a capacitive element and an FCG transistor in each of the low-sensitivity pixels, the signals of multiple low-sensitivity pixels can be read out individually without summing them.

[0148] As illustrated in the figure, by sharing the floating diffusion layer 225 and the like, the size of the transistor can be increased compared to when it is not shared, provided that the size of the pixels remains constant.

[0149] Although four pixels share the floating diffusion layer 225, the number of pixels shared is not limited to four; it could be two or more.

[0150] Figure 23 shows an example of a transistor layout in the eighth embodiment of this technology. FCG transistors 234, 254, 274, and 294 are arranged in the low-sensitivity sub-pixels 230, 250, 270, and 290.

[0151] Furthermore, a transfer transistor 222 and a reset transistor 223 are arranged in the high-sensitivity sub-pixel 220, and a transfer transistor 242 and an FDG transistor 224 are arranged in the high-sensitivity sub-pixel 240. A transfer transistor 262 is arranged in the high-sensitivity sub-pixel 260, and a transfer transistor 282 is arranged in the high-sensitivity sub-pixel 280.

[0152] Amplifying transistor 226-1 is positioned across high-sensitivity sub-pixels 220 and 260, and amplifying transistor 226-2 is positioned across high-sensitivity sub-pixels 240 and 280. Selecting transistor 227 is positioned across high-sensitivity sub-pixels 260 and 280. Floating diffusion layer 225 is positioned in the center of the four pixels.

[0153] Furthermore, the second, third, fourth, fifth, and sixth embodiments, as well as their variations, can be applied to the eighth embodiment.

[0154] Thus, according to the eighth embodiment of this technology, since multiple pixels share the floating diffusion layer 225 and the like, the size of the transistor can be increased.

[0155] <9. Example of using the imaging device> [Imaging device] Figure 24 is a block diagram showing an example configuration of an imaging device (camera device) 1000, which is an example of an electronic device to which this technology is applied.

[0156] As shown in Figure 24, the imaging device 1000 includes an optical system including a lens group 1001, an image sensor 1002, a DSP circuit 1003 which is a camera signal processing unit, a frame memory 1004, a display device 1005, a recording device 1006, an operating system 1007, and a power supply system 1008. The DSP circuit 1003, frame memory 1004, display device 1005, recording device 1006, operating system 1007, and power supply system 1008 are interconnected via a bus line 1009.

[0157] The lens group 1001 captures incident light (image light) from the subject and forms an image on the imaging surface of the image sensor 1002. The image sensor 1002 converts the amount of incident light formed on the imaging surface by the lens group 1001 into an electrical signal on a pixel-by-pixel basis and outputs it as a pixel signal.

[0158] The display device 1005 consists of a panel-type display device such as a liquid crystal display device or an organic EL (Electro Luminescence) display device, and displays video or still images captured by the image sensor 1002. The recording device 1006 records the video or still images captured by the image sensor 1002 onto a recording medium such as a memory card, videotape, or DVD (Digital Versatile Disk).

[0159] The control system 1007 issues operation commands for various functions of the imaging device 1000 under the user's control. The power supply system 1008 appropriately supplies various power sources to the DSP circuit 1003, frame memory 1004, display device 1005, recording device 1006, and control system 1007.

[0160] Such an imaging device 1000 can be applied to video cameras, digital still cameras, and camera modules for mobile devices such as smartphones and mobile phones. In this imaging device 1000, the image sensor 100 according to each of the above embodiments can be used as the image sensor 1002. This makes it possible to improve the image quality of the imaging device 1000.

[0161] <10. Examples of Application to Mobile Devices> The technology disclosed herein (the technology) can be applied to various products. For example, the technology disclosed herein may be implemented as a device mounted on any type of mobile device such as automobiles, electric vehicles, hybrid electric vehicles, motorcycles, bicycles, personal mobility devices, airplanes, drones, ships, and robots.

[0162] Figure 25 is a block diagram showing a schematic configuration example of a vehicle control system, which is an example of a mobile control system to which the technology described herein may be applied.

[0163] The vehicle control system 12000 comprises a plurality of electronic control units connected via a communication network 12001. In the example shown in Figure 25, the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an external information detection unit 12030, an internal information detection unit 12040, and an integrated control unit 12050. The functional configuration of the integrated control unit 12050 is shown in the figure, which includes a microcomputer 12051, an audio / image output unit 12052, and an in-vehicle network interface 12053.

[0164] The drivetrain control unit 12010 controls the operation of devices related to the vehicle's drivetrain according to various programs. For example, the drivetrain control unit 12010 functions as a control device for a drivetrain generating device that generates driving force for the vehicle, such as an internal combustion engine or a drive motor; a drivetrain transmission mechanism that transmits driving force to the wheels; a steering mechanism that adjusts the steering angle of the vehicle; and a braking device that generates braking force for the vehicle.

[0165] The body system control unit 12020 controls the operation of various devices mounted on the vehicle body according to various programs. For example, the body system control unit 12020 functions as a control device for a keyless entry system, a smart key system, a power window system, or various lamps such as headlights, reverse lights, brake lights, turn signals, or fog lights. In this case, the body system control unit 12020 may receive radio waves transmitted from a portable device that replaces a key or signals from various switches. The body system control unit 12020 receives these radio waves or signals and controls the vehicle's door lock system, power window system, lamps, etc.

[0166] The external information detection unit 12030 detects information from outside the vehicle equipped with the vehicle control system 12000. For example, an imaging unit 12031 is connected to the external information detection unit 12030. The external information detection unit 12030 causes the imaging unit 12031 to capture images of the outside of the vehicle and receives the captured images. Based on the received images, the external information detection unit 12030 may perform object detection processing such as detecting people, cars, obstacles, signs, or characters on the road surface, or distance detection processing.

[0167] The imaging unit 12031 is a light sensor that receives light and outputs an electrical signal corresponding to the amount of light received. The imaging unit 12031 can output the electrical signal as an image or as distance measurement information. The light received by the imaging unit 12031 may be visible light or invisible light such as infrared light.

[0168] The in-vehicle information detection unit 12040 detects information inside the vehicle. The in-vehicle information detection unit 12040 is connected to, for example, a driver status detection unit 12041 that detects the driver's state. The driver status detection unit 12041 includes, for example, a camera that captures images of the driver, and the in-vehicle information detection unit 12040 may calculate the driver's level of fatigue or concentration, or determine whether the driver is drowsy, based on the detection information input from the driver status detection unit 12041.

[0169] The microcomputer 12051 can calculate control target values ​​for the drive force generator, steering mechanism, or braking device based on information inside and outside the vehicle acquired by the external information detection unit 12030 or the internal information detection unit 12040, and output control commands to the drive system control unit 12010. For example, the microcomputer 12051 can perform cooperative control aimed at realizing ADAS (Advanced Driver Assistance System) functions, including collision avoidance or impact mitigation, following driving based on distance between vehicles, maintaining vehicle speed, vehicle collision warning, or vehicle lane departure warning.

[0170] Furthermore, the microcomputer 12051 can perform cooperative control for purposes such as autonomous driving, where the vehicle drives autonomously without driver intervention, by controlling the drive force generating device, steering mechanism, or braking device, etc., based on information about the vehicle's surroundings acquired by the external information detection unit 12030 or the internal information detection unit 12040.

[0171] Furthermore, the microcomputer 12051 can output control commands to the body system control unit 12020 based on external information acquired by the external information detection unit 12030. For example, the microcomputer 12051 can control the headlights according to the position of a preceding or oncoming vehicle detected by the external information detection unit 12030, and perform coordinated control aimed at reducing glare, such as switching from high beams to low beams.

[0172] The audio-image output unit 12052 transmits at least one of audio and image output signals to an output device capable of visually or audibly notifying information to the vehicle's occupants or to those outside the vehicle. In the example shown in Figure 25, the output devices include an audio speaker 12061, a display unit 12062, and an instrument panel 12063. The display unit 12062 may include, for example, at least one of an onboard display and a head-up display.

[0173] Figure 26 shows an example of the installation position of the imaging unit 12031.

[0174] In Figure 26, the imaging unit 12031 includes imaging units 12101, 12102, 12103, 12104, and 12105.

[0175] The imaging units 12101, 12102, 12103, 12104, and 12105 are installed, for example, on the front nose, side mirrors, rear bumper, back door, and the upper part of the windshield inside the vehicle 12100. The imaging unit 12101 installed on the front nose and the imaging unit 12105 installed on the upper part of the windshield inside the vehicle mainly acquire images of the front of the vehicle 12100. The imaging units 12102 and 12103 installed on the side mirrors mainly acquire images of the sides of the vehicle 12100. The imaging unit 12104 installed on the rear bumper or back door mainly acquires images of the rear of the vehicle 12100. The imaging unit 12105 installed on the upper part of the windshield inside the vehicle is mainly used for detecting preceding vehicles, pedestrians, obstacles, traffic lights, traffic signs, or lanes.

[0176] Figure 26 shows an example of the imaging range of imaging units 12101 to 12104. Imaging range 12111 indicates the imaging range of imaging unit 12101 located on the front nose, imaging ranges 12112 and 12113 indicate the imaging ranges of imaging units 12102 and 12103 located on the side mirrors, respectively, and imaging range 12114 indicates the imaging range of imaging unit 12104 located on the rear bumper or back door. For example, by superimposing the image data captured by imaging units 12101 to 12104, an overhead view image of the vehicle 12100 can be obtained.

[0177] At least one of the imaging units 12101 to 12104 may have a function for acquiring distance information. For example, at least one of the imaging units 12101 to 12104 may be a stereo camera consisting of multiple image sensors, or an image sensor having pixels for phase difference detection.

[0178] For example, the microcomputer 12051, based on distance information obtained from the imaging units 12101 to 12104, can determine the distance to each object within the imaging range 12111 to 12114 and the temporal change of this distance (relative speed to the vehicle 12100). In particular, it can extract the closest object on the vehicle 12100's path that is traveling in approximately the same direction as the vehicle 12100 at a predetermined speed (e.g., 0 km / h or more) as the preceding vehicle. Furthermore, the microcomputer 12051 can set a predetermined distance to be maintained before the preceding vehicle and perform automatic braking control (including follow-and-stop control) and automatic acceleration control (including follow-and-start control), etc. In this way, cooperative control aimed at autonomous driving, where the vehicle drives autonomously without driver intervention, can be performed.

[0179] For example, the microcomputer 12051 can use distance information obtained from imaging units 12101 to 12104 to classify and extract three-dimensional object data related to three-dimensional objects, such as motorcycles, passenger cars, large vehicles, pedestrians, utility poles, and other three-dimensional objects, and use this data for automatic obstacle avoidance. For example, the microcomputer 12051 identifies obstacles around the vehicle 12100 into obstacles that are visible to the driver of the vehicle 12100 and obstacles that are difficult to see. The microcomputer 12051 then determines the collision risk, which indicates the degree of risk of collision with each obstacle. If the collision risk is above a set value and there is a possibility of collision, the microcomputer 12051 can provide driving assistance to avoid collisions by outputting a warning to the driver via the audio speaker 12061 or the display unit 12062, or by performing forced deceleration or evasive steering via the drive system control unit 12010.

[0180] At least one of the imaging units 12101 to 12104 may be an infrared camera that detects infrared light. For example, the microcomputer 12051 can recognize pedestrians by determining whether or not pedestrians are present in the images captured by the imaging units 12101 to 12104. Such pedestrian recognition is performed, for example, by a procedure to extract feature points from the images captured by the imaging units 12101 to 12104 as infrared cameras, and a procedure to perform pattern matching on a series of feature points that indicate the contour of an object to determine whether or not it is a pedestrian. When the microcomputer 12051 determines that a pedestrian is present in the images captured by the imaging units 12101 to 12104 and recognizes a pedestrian, the audio-image output unit 12052 controls the display unit 12062 to superimpose a rectangular contour line for emphasis on the recognized pedestrian. The audio-image output unit 12052 may also control the display unit 12062 to display an icon indicating a pedestrian at a desired position.

[0181] The above describes an example of a vehicle control system to which the technology described herein may be applied. The technology described herein can be applied to, for example, the imaging unit 12031 of the configuration described above. Specifically, the image sensor 100 in Figure 1 can be applied to the imaging unit 12031. By applying the technology described herein to the imaging unit 12031, it is possible to obtain a more easily viewable image, thereby reducing driver fatigue.

[0182] The embodiments described above are merely examples of how to realize this technology, and there is a corresponding relationship between the matters in the embodiments and the inventive features in the claims. Similarly, there is a corresponding relationship between the inventive features in the claims and the matters in the embodiments of this technology that bear the same name. However, this technology is not limited to the embodiments and can be realized by making various modifications to the embodiments without departing from the gist of the technology.

[0183] The effects described herein are merely illustrative and not limited to those described herein, and other effects may also occur.

[0184] Furthermore, this technology can also take the following configurations: (1) An image sensor comprising: a pixel array section in which a plurality of pixels are arranged, each including a high-sensitivity subpixel having a sensitivity higher than a predetermined value and a low-sensitivity subpixel having a sensitivity lower than the predetermined value, and at least two of the low-sensitivity subpixels are arranged adjacent to each other; and a column processing section that performs AD conversion on the respective pixel signals of the low-sensitivity subpixels and the high-sensitivity subpixels. (2) The image sensor according to (1), wherein the high-sensitivity subpixels and the low-sensitivity subpixels are separated by a first RDTI (Rear Deep Trench Isolation), and two adjacent low-sensitivity subpixels are separated by a second RDTI. (3) The image sensor according to (2), wherein the depth of the first RDTI is different from the depth of the second RDTI. (4) The image sensor according to (2) or (3), wherein the embedding material of the first RDTI is different from the embedding material of the second RDTI. (5) The image sensor according to (1), wherein the high-sensitivity sub-pixel and the low-sensitivity sub-pixel are separated by a first FFTI (Front Full Trench Isolation), and two adjacent low-sensitivity sub-pixels are separated by a second FFTI. (6) The image sensor according to (5), wherein the width of the first FFTI is different from the width of the second FFTI. (7) The image sensor according to (5) or (6), wherein the embedding material of the first FFTI is different from the embedding material of the second FFTI. (8) The image sensor according to any one of (1) to (7), wherein, when viewed from the optical axis direction, each of the plurality of pixels and the low-sensitivity sub-pixel is rectangular, and when viewed from the optical axis direction, the high-sensitivity sub-pixel has a shape in which a part of the rectangle is cut out. (9) An image sensor according to any one of (1) to (7), wherein each of the plurality of pixels, as viewed from the optical axis direction, is a polygon with more than four sides, the high-sensitivity sub-pixel, as viewed from the optical axis direction, is shaped like a square with a part cut out, and the low-sensitivity sub-pixel, as viewed from the optical axis direction, is rhombic. (10) An image sensor according to any one of (1) to (7), wherein each of the plurality of pixels, as viewed from the optical axis direction, is a polygon with more than four sides, and the high-sensitivity sub-pixel and the low-sensitivity sub-pixel, as viewed from the optical axis direction, are rectangular.(11) The image sensor according to any one of (1) to (7), wherein each of the plurality of pixels is rectangular when viewed from the optical axis direction, the high-sensitivity sub-pixel is shaped by cutting out a part of the rectangle when viewed from the optical axis direction, and the low-sensitivity sub-pixel is a right triangle when viewed from the optical axis direction. (12) The image sensor according to any one of (1) to (11), wherein each of the plurality of pixels includes a color filter, and the color filters are arranged in a Bayer array. (13) The image sensor according to any one of (1) to (11), wherein each of the plurality of pixels includes a color filter, and the color filters are arranged in a quad-Bayer array. (14) The image sensor according to any one of (1) to (13), further comprising a first on-chip lens arranged on the low-sensitivity sub-pixel and a plurality of second on-chip lenses arranged on the high-sensitivity sub-pixel, wherein the area of ​​each of the plurality of second on-chip lenses is the same as that of the first on-chip lens. (15) The image sensor according to any one of (1) to (13), further comprising: a first on-chip lens arranged across two or more low-sensitivity sub-pixels; and a second on-chip lens arranged across two or more high-sensitivity sub-pixels, wherein the area of ​​the second on-chip lens is larger than that of the first on-chip lens. (16) The image sensor according to any one of (1) to (15), wherein the high-sensitivity sub-pixel comprises: a first photodiode; and a transfer transistor that transfers charge from the first photodiode to a first floating diffusion layer; and the low-sensitivity sub-pixel comprises: a second photodiode; a second floating diffusion layer that holds the charge generated by the second photodiode; a capacitive element inserted between the connection node of the second photodiode and the second floating diffusion layer and the power supply voltage; and a floating capacitance gate transistor that opens and closes a path between the connection node of the capacitive element and the second floating diffusion layer and a predetermined node in the high-sensitivity sub-pixel.(17) The high-sensitivity sub-pixel further comprises an amplifying transistor that outputs a voltage corresponding to the voltage of the first floating diffusion layer, and a selection transistor that outputs a pixel signal of the output voltage to a vertical signal line according to a selection signal, wherein the floating capacitance gate transistors of two adjacent low-sensitivity sub-pixels share a gate, and the selection transistors of two adjacent high-sensitivity sub-pixels share a gate, as described in (16). (18) The image sensor according to (16), wherein at least two of the plurality of pixels share the first floating diffusion layer.

[0185] 100 Image sensor 110 Vertical drive unit 120 System control unit 130 Column processing unit 140 Horizontal drive unit 150 Signal processing unit 160 Data storage unit 200 Pixel array unit 211-214 Pixels 220, 240, 260, 280 High-sensitivity sub-pixels 221, 231, 241, 251, 261, 271, 281, 291 Photodiodes 222, 242, 262, 282 Transfer transistors 223, 243 Reset transistors 224, 244 FDG transistors 225, 233, 245, 253, 273, 293 Floating diffusion layer 226, 226-1, 226-2, 246 Amplifying transistors 227, 247 Selecting transistors 230, 250, 270, 290 Low-sensitivity sub-pixels 232, 252, 272, 292 Capacitive elements 234, 254, 274, 294 FCG transistors 311, 312 On-chip lens 321 Color filter 331, 332 RDTI (Rear Deep Trench Isolation) 341, 342 FFTI (Front Full Trench Isolation) 400 RDT mask 1000 Imaging device 1001 Lens group 1002 Image sensor 1003 DSP circuit 1004 Frame memory 1005 Display device 1006 Recording device 1007 Operating system 1008 Power supply system 1009 Bus line 12031 Imaging unit

Claims

1. An image sensor comprising: a pixel array section in which a plurality of pixels are arranged, each including a high-sensitivity sub-pixel with a sensitivity higher than a predetermined value and a low-sensitivity sub-pixel with a sensitivity lower than the predetermined value, and at least two of the low-sensitivity sub-pixels are arranged adjacent to each other; and a column processing section that performs AD conversion of the respective pixel signals of the low-sensitivity sub-pixels and the high-sensitivity sub-pixels.

2. The image sensor according to claim 1, wherein the high-sensitivity sub-pixel and the low-sensitivity sub-pixel are separated by a first RDTI (Rear Deep Trench Isolation), and two adjacent low-sensitivity sub-pixels are separated by a second RDTI.

3. The image sensor according to claim 2, wherein the depth of the first RDTI is different from the depth of the second RDTI.

4. The image sensor according to claim 2, wherein the embedding material for the first RDTI is different from the embedding material for the second RDTI.

5. The image sensor according to claim 1, wherein the high-sensitivity sub-pixel and the low-sensitivity sub-pixel are separated by a first FFTI (Front Full Trench Isolation), and two adjacent low-sensitivity sub-pixels are separated by a second FFTI.

6. The image sensor according to claim 5, wherein the width of the first FFTI is different from the width of the second FFTI.

7. The image sensor according to claim 5, wherein the embedding material for the first FFTI is different from the embedding material for the second FFTI.

8. The image sensor according to claim 1, wherein each of the plurality of pixels and the low-sensitivity sub-pixels is rectangular when viewed from the optical axis direction, and the high-sensitivity sub-pixel is shaped by cutting out a part of the rectangle when viewed from the optical axis direction.

9. The image sensor according to claim 1, wherein each of the plurality of pixels, viewed from the optical axis direction, is a polygon with more than four sides, the high-sensitivity sub-pixel, viewed from the optical axis direction, is shaped like a square with a part cut out, and the low-sensitivity sub-pixel, viewed from the optical axis direction, is rhombic.

10. The image sensor according to claim 1, wherein each of the plurality of pixels, viewed from the optical axis direction, is a polygon with more than four sides, and each of the high-sensitivity sub-pixels and the low-sensitivity sub-pixels, viewed from the optical axis direction, is rectangular.

11. The image sensor according to claim 1, wherein each of the plurality of pixels is rectangular when viewed from the optical axis direction, the high-sensitivity sub-pixel is shaped by cutting out a part of the rectangle when viewed from the optical axis direction, and the low-sensitivity sub-pixel is shaped like a right triangle when viewed from the optical axis direction.

12. The image sensor according to claim 1, wherein each of the plurality of pixels includes a color filter, and the color filters are arranged in a Bayer array.

13. The image sensor according to claim 1, wherein each of the plurality of pixels includes a color filter, and the color filters are arranged in a quad Bayer array.

14. The image sensor according to claim 1, further comprising a first on-chip lens arranged in the low-sensitivity sub-pixel and a plurality of second on-chip lenses arranged in the high-sensitivity sub-pixel, wherein the area of ​​each of the plurality of second on-chip lenses is the same as that of the first on-chip lens.

15. The image sensor according to claim 1, further comprising a first on-chip lens arranged across two or more low-sensitivity sub-pixels, and a second on-chip lens arranged across two or more high-sensitivity sub-pixels, wherein the area of ​​the second on-chip lens is larger than that of the first on-chip lens.

16. The image sensor according to claim 1, wherein the high-sensitivity sub-pixel comprises a first photodiode and a transfer transistor that transfers charge from the first photodiode to a first floating diffusion layer, and the low-sensitivity sub-pixel comprises a second photodiode, a second floating diffusion layer that holds the charge generated by the second photodiode, a capacitive element inserted between the connection node of the second photodiode and the second floating diffusion layer and the power supply voltage, and a floating capacitance gate transistor that opens and closes a path between the connection node of the capacitive element and the second floating diffusion layer and a predetermined node in the high-sensitivity sub-pixel.

17. The image sensor according to claim 16, wherein the high-sensitivity sub-pixel further comprises an amplifying transistor that outputs a voltage corresponding to the voltage of the first floating diffusion layer, and a selection transistor that outputs a pixel signal of the output voltage to a vertical signal line according to a selection signal, the floating capacitance gate transistors of two adjacent low-sensitivity sub-pixels share a gate, and the selection transistors of two adjacent high-sensitivity sub-pixels share a gate.

18. The image sensor according to claim 16, wherein at least two of the plurality of pixels share the first floating diffusion layer.

Images