Storage circuit

Abstract

A store driver circuit of this storage circuit includes a first transistor and a second transistor that are cascode-connected. The gates of the first transistor and the second transistor of the store driver circuit are connected to a node of a latch circuit. The cascode connection points of the first transistor and the second transistor of the store driver circuit are connected to a magnetoresistive element. A current terminal of the first transistor or the second transistor of the store driver circuit is directly connected to a power supply voltage or a reference voltage.

Description

Memory circuit

[0001] The present disclosure relates to a memory circuit, and more particularly to a non-volatile memory circuit.

[0002] A non-volatile memory circuit that writes (stores) a bit value into a magnetoresistive element and reads (restores) a bit value from the magnetoresistive element using a change in the resistance value of the magnetoresistive element is known. For example, Patent Document 1 proposes a technique for reducing power consumption while maintaining stable writing.

[0003] Japanese Unexamined Patent Application Publication No. 2021-68488

[0004] Izumi Iida, Kenyu Seto, "Proposal and Evaluation of Logic Cell Architecture for ePFGA IP", Information Processing Society of Japan Information DA Symposium 2024, August 30, 2024, p. 278-284 Kenyu Seto, Ryota Iwasaki, Tatsuya Sasaki, Izumi Iida, "Proposal and Evaluation of Technology Mapping for Logic Cells for eFPGA IP", Information Processing Society of Japan Information DA Symposium 2024, August 30, 2024, p. 285-291

[0005] Depending on the use of the memory circuit, there are cases where the restoration frequency is higher than the storage frequency. Circuit elements related to functions other than restoration may increase the circuit area and leakage current more than necessary.

[0006] One aspect of the present disclosure is to suppress the circuit area and leakage current.

[0007] A memory circuit relating to one aspect of the present disclosure includes a latch circuit including a node for holding a bit signal, a magnetoresistive element, a store driver circuit connected between the latch circuit and the magnetoresistive element, a restore driver circuit connected between the latch circuit and the magnetoresistive element, control lines connected to the magnetoresistive element on the opposite side of the magnetoresistive element from the store driver circuit and the restore driver circuit, and a control driver circuit for controlling the voltage of the control lines, wherein the store driver circuit includes a cascode-connected first transistor and a second transistor, the gates of the first transistor and the second transistor of the store driver circuit are connected to a node of the latch circuit, the cascode connection points of the first transistor and the second transistor of the store driver circuit are connected to the magnetoresistive element, and the current terminals of the first transistor or the second transistor of the store driver circuit are directly connected to a power supply voltage or a reference voltage.

[0008] This is a diagram showing an example of the schematic configuration of the memory circuit 1 according to the embodiment. This is a diagram showing a modified version of the memory circuit 1. This is a diagram showing a modified version of the memory circuit 1. This is a diagram showing a modified version of the memory circuit 1. This is a diagram showing a modified version of the memory circuit 1. This is a diagram showing a modified version of the memory circuit 1. This is a diagram showing a modified version of the memory circuit 1. This is a diagram showing an example of the schematic configuration of the memory circuit 1A. This is a timing chart showing an example of the operation of the memory circuit 1A. This is a diagram showing a modified version of the memory circuit 1A. This is a diagram showing an example of the schematic configuration of the memory circuit 1A. This is a diagram showing a modified version of the memory circuit 1A. This is a diagram showing an example of the schematic configuration of the circuit device 100. This is a diagram showing an example of the schematic configuration of the circuit device 100. This is a diagram showing an example of the schematic configuration of the programmable AND circuit 92. This is a diagram showing an example of the truth table of the programmable AND circuit 92-1. This is a diagram showing an example of the schematic configuration of the circuit device 100. This is a diagram showing an example of the schematic configuration of the control circuit 110 for the memory circuit 1A. This is a diagram showing an example of the schematic configuration of the control circuit 110 for the memory circuit 1A. This is a diagram showing an example of the schematic configuration of the control circuit 110 for the memory circuit 1A. This figure shows an example of the control circuit 110 and the memory circuit 1A. This figure shows an example of the bit values ​​held by the memory circuit 1A. This figure shows an example of the bit values ​​held by the memory circuit 1A. This figure shows an example of the bit values ​​held by the memory circuit 1A. This figure shows an example of the bit values ​​held by the memory circuit 1A. This figure shows an example of the bit values ​​held by the memory circuit 1A. This figure shows an example of the bit values ​​held by the memory circuit 1A. This figure shows an example of the bit values ​​held by the memory circuit 1A. This figure shows an example of write control. This figure shows an example of write control. This figure shows an example of write control.

[0009] Embodiments of this disclosure will be described in detail below with reference to the drawings. In each of the following embodiments, the same elements will be denoted by the same reference numerals to avoid redundant descriptions.

[0010] This disclosure will be described in the following order of items: 1. Embodiments of memory circuits 1.1 Example of an NVFF circuit 1.2 Modifications of the NVFF circuit 1.3 Example of an NV latch circuit 1.4 Modifications of the NV latch circuit 2. Application examples to programmable logic circuits 3. Example of a control circuit 4. Summary 5. Example of a control circuit

[0011] 1. Embodiment of a Memory Circuit 1.1 Example of an NVFF Circuit Figure 1 is a diagram showing an example of the schematic configuration of a memory circuit 1 according to an embodiment. The memory circuit 1 is a non-volatile memory circuit. In the example shown in Figure 1, the memory circuit 1 is a header-type NVFF (Non-Volatile Flip-Flop) circuit.

[0012] Each element within the memory circuit 1 is supplied with a power supply voltage VDD, either directly or indirectly through other elements. Some of the power supply voltages VDD are also shown in the illustration. Separately, the power supply to the entire memory circuit 1 can also be controlled to be switched on and off, and this switching is performed, for example, by a power gate (e.g., a P-type FET) not shown.

[0013] Figure 1 illustrates some of the signals handled by the memory circuit 1, including bit signal D, bit signal Q, clock signal CK, inverted clock signal CKB, reset signal CN, power switch local signal PSL, store signal STR, inverted store signal STRB, restore signal RSTR, and control signal CTRL. The voltages of these signals switch between L (low level) and H (high level).

[0014] Bit signal D is a bit signal input to memory circuit 1 and indicates the bit value (bit data) to be stored in memory circuit 1. For example, a bit signal D at L level indicates "0", and a bit signal D at H level indicates "1".

[0015] The bit signal Q is a bit signal output by the memory circuit 1 and indicates the bit value stored in the memory circuit 1.

[0016] The clock signal CK is, as its name suggests, a clock signal. The inverted clock signal CKB is the inverted version of the clock signal CK.

[0017] The reset signal CN is used to set (reset) the bit signal Q to a low level. During a reset, the reset signal CN is set to a low level. Otherwise, the reset signal CN is set to a high level.

[0018] The power switch local signal PSL is a signal used to control the on / off state of a portion of the power supply in the memory circuit 1.

[0019] The store signal STR is a signal used to control the operation (store operation) of storing bit values ​​in the memory circuit 1. The inverted store signal STRB is the inverted version of the store signal STR.

[0020] The restore signal RSTR is a signal used to control the operation (restore operation) of reading the bit values ​​stored in the memory circuit 1.

[0021] The control signal CTRL is a signal used to control the voltage level of the control line L8, which will be described later.

[0022] In the example shown in Figure 1, the memory circuit 1 mainly includes a latch circuit 2, a latch circuit 3, a store driver circuit 4, a switch transistor 5, a restore driver circuit 6, a magnetoresistive element 7, and a control driver circuit 8. The memory circuit 1 also includes terminal T1, terminal T2, an inverter 11, a transmission gate 12, a transmission gate 13, an inverter 14, a switch transistor 15, a NOR gate 16, and a control line L8.

[0023] Transistors are either N-type FETs or P-type FETs. P-type FETs are illustrated with a white circle around the gate. The drain and source of a transistor are also called current terminals. The gate can also be called the control terminal.

[0024] In the following explanation, when a transistor is connected between two elements, it is assumed that one current terminal of the transistor is connected to one element, and the other current terminal is connected to the other element.

[0025] Terminal T1 is the terminal to which the bit signal D is input. Terminal T1 can also be called the input terminal of the memory circuit 1. Terminal T2 is the terminal to which the bit signal Q is output. Terminal T2 can also be called the output terminal of the memory circuit 1. The memory circuit 1 is configured to store the bit value indicated by the bit signal D input to terminal T1, and to output the bit signal Q indicating the stored bit value from terminal T2.

[0026] Between terminal T1 and terminal T2, the inverter 11 (also called a NOT gate), transmission gate 12, latch circuit 2, transmission gate 13, latch circuit 3, and inverter 14 are connected in this order.

[0027] The inverter 11 is connected between terminal T1 and the transmission gate 12. The inverter 11 inverts the bit signal D from terminal T1 and outputs it to the transmission gate 12. The inverter 11 connected to the input terminal T1 can also be called the input-side inverter.

[0028] The transmission gate 12 is connected between the inverter 11 and the latch circuit 2. When the transmission gate 12 is ON, it transmits the signal from the inverter 11 to the latch circuit 2. The transmission gate 12, which is located on the input side of the latch circuit 2, can also be called the input-side transmission gate.

[0029] The transmission gate 12 is supplied with a clock signal CK and an inverting clock signal CKB. The transmission gate 12 switches on and off in accordance with the rising and falling edges of the clock signal CK. Specifically, in the example shown in Figure 1, the transmission gate 12 turns on when the clock signal CK falls (the rising edge of the inverting clock signal CKB). The transmission gate 12 turns off when the clock signal CK rises (the falling edge of the inverting clock signal CKB).

[0030] The latch circuit 2 is connected between the transmission gate 12 and the transmission gate 13. The latch circuit 2 can also be called the master latch circuit in the NVFF circuit. The latch circuit 2 includes node N21, node N22, inverter 21, NAND gate 22, and transmission gate 23.

[0031] Nodes N21 and N22 are nodes for holding signals from the transmission gate 12. Node N21 corresponds to the input portion of the latch circuit 2 and is connected to the transmission gate 12. The signal from the transmission gate 12 is input to node N21. Node N22 corresponds to the output portion of the latch circuit 2 and is connected to the transmission gate 13. The signal from node N22 is output to the transmission gate 13.

[0032] The inverter 21 is connected between node N21 and node N22. The inverter 21 inverts the signal from node N21 and outputs it to node N22.

[0033] The NAND gate 22 and the transmission gate 23 are connected in this order between node N22 and node N21. The NAND gate 22 is a two-input gate. A signal from node N22 is input to one input terminal of the NAND gate 22. A reset signal CN is input to the other input terminal of the NAND gate 22. The NAND gate 22 outputs the negative logical AND signal of these two input signals to the transmission gate 23.

[0034] The transmission gate 23 is connected between node N22 and the transmission gate 23. When the transmission gate 23 is ON, it transmits the signal from the NAND gate 22 to node N21. The transmission gate 23 is supplied with a clock signal CK and an inverting clock signal CKB. The transmission gate 23 turns ON when the clock signal CK is rising. The transmission gate 23 turns OFF when the clock signal CK is falling.

[0035] The transmission gate 13 is connected between the latch circuit 2 and the latch circuit 3. When the transmission gate 13 is ON, it transmits the signal from node N22 of the latch circuit 2 to the latch circuit 3. The transmission gate 13 is supplied with a clock signal CK and an inverting clock signal CKB. The ON and OFF control of the transmission gate 13 is the same as the ON and OFF control of the transmission gate 23.

[0036] The transmission gate 13 located on the input side of the latch circuit 3 can also be called an input-side transmission gate. More specifically, the transmission gate 12 mentioned earlier can also be called a first input-side transmission gate located on the input side of latch circuit 2, one of the latch circuits 2 and 3. The transmission gate 13 can also be called a second input transmission gate located on the input side of latch circuit 3, one of the latch circuits 2 and 3.

[0037] The latch circuit 3 is connected between the transmission gate 13 and the inverter 14. The latch circuit 3 can also be called the slave latch circuit in the NVFF circuit. The latch circuit 3 includes node N31, node N32, NAND gate 31, switch transistor 31a, inverter 32, switch transistor 32a, transmission gate 33, and transistor 34.

[0038] Nodes N31 and N32 are nodes for holding signals from the transmission gate 13. Node N31 corresponds to the input portion of the latch circuit 3 and is connected to the transmission gate 13. Signals from the transmission gate 13 are input to node N31. Node N32 corresponds to the output portion of the latch circuit 3 and is connected to the inverter 14. The signal from node N32 is output to the inverter 14.

[0039] The NAND gate 31 is connected between node N31 and node N32. The NAND gate 31 is a two-input gate. A signal from node N31 is input to one input terminal of the NAND gate 31. A reset signal CN is input to the other input terminal of the NAND gate 31. The NAND gate 31 outputs the negated logical AND signal of these two input signals to node N32.

[0040] The switch transistor 31a is a P-type FET and is connected between the NAND gate 31 (power supply terminal thereof) and the power supply voltage VDD (power supply line having the same). The power switch local signal PSL is supplied to the gate of the switch transistor 31a. The on and off (conductive state and non-conductive state) of the switch transistor 31a are controlled by the power switch local signal PSL. Thereby, the power supply voltage VDD can be supplied to the NAND gate 31 or the supply thereof can be interrupted (stopped).

[0041] The inverter 32 and the transmission gate 33 are connected in this order between the node N32 and the node N31.

[0042] The inverter 32 is connected between the node N32 and the transmission gate 33. The inverter 32 inverts the signal from the node N32 and outputs it to the transmission gate 33.

[0043] The switch transistor 32a is a P-type FET and is connected between the inverter 32 and the power supply voltage VDD. The power switch local signal PSL is supplied to the gate of the switch transistor 32a, whereby the power supply voltage VDD can be supplied to the inverter 32 or the supply thereof can be interrupted.

[0044] The transmission gate 33 is connected between the inverter 32 and the node N31. When the transmission gate 33 is on, it transmits the signal from the inverter 32 to the node N31. The clock signal CK and the inverted clock signal CKB are supplied to the transmission gate 33. The control of the on and off of the transmission gate 33 is the same as the control of the on and off of the transmission gate 12.

[0045] The transistor 34 is an N-type FET and is connected in parallel with the transmission gate 33 between the inverter 32 and the node N31. The restore signal RSTR is supplied to the gate of the transistor 34. The on and off of the transistor 34 are controlled by the restore signal RSTR. By turning on the transistor 34, the transmission gate 33 is bypassed.

[0046] The inverter 14 is connected between the latch circuit 3 and the terminal T2. The inverter 14 inverts the signal from the node N32 of the latch circuit 3 and outputs it to the terminal T2. The inverter 14 connected to the output terminal T2 can also be called an output-side inverter. The terminal T2 outputs the signal from the inverter 14.

[0047] In the memory circuit 1, in particular, the nodes N31 and N32 of the latch circuit 3 are used to store or read out bit values. A store driver circuit 4, a switch transistor 5, a restore driver circuit 6, a magnetoresistive element 7, a control line L8, and a control driver circuit 8 are directly or indirectly connected to the latch circuit 3.

[0048] The store driver circuit 4 is connected between the latch circuit 3 and the magnetoresistive element 7. The store driver circuit 4 is composed of two (a pair of) store driver circuits. The first store driver circuit is referred to as the store driver circuit 4-1 and is illustrated. The second store driver circuit is referred to as the store driver circuit 4-2 and is illustrated. When not particularly distinguishing between them, it is simply called the store driver circuit 4.

[0049] The store driver circuit 4 includes a node N41, a node N42, a transistor 41, and a transistor 42.

[0050] The node N41 corresponds to the input portion of the store driver circuit 4 and is connected to the latch circuit 3. More specifically, the node N41 of the store driver circuit 4-1 is connected to the node N32 of the latch circuit 3. The node N41 of the store driver circuit 4-2 is connected to the node N31 of the latch circuit 3.

[0051] The node N42 corresponds to the output portion of the store driver circuit 4 and is connected to the magnetoresistive element 7. More specifically, the node N42 of the store driver circuit 4-1 is connected to the magnetoresistive element 7-1 described later. The node N42 of the store driver circuit 4-2 is connected to the magnetoresistive element 7-2 described later.

[0052] Transistors 41 and 42 are a first and second transistor connected in a cascode configuration to form an inverter circuit. Transistor 41 is a P-type FET. Transistor 42 is an N-type FET.

[0053] The gates of transistors 41 and 42 are connected to node N41. Therefore, the gates of transistors 41 and 42 in store driver circuit 4-1 are connected to node N32 in latch circuit 3. The gates of transistors 41 and 42 in store driver circuit 4-2 are connected to node N31 in latch circuit 3.

[0054] The cascode connection point of transistors 41 and 42 (the connection point of their respective current terminals) corresponds to node N42. Therefore, the cascode connection point of transistors 41 and 42 in the store driver circuit 4-1 is connected to the magnetoresistive element 7-1, which will be described later. The cascode connection point of transistors 41 and 42 in the store driver circuit 4-2 is connected to the magnetoresistive element 7-2, which will be described later.

[0055] The current terminals of transistor 41 or transistor 42 are directly connected to the power supply voltage VDD or the reference voltage GND (or a power line having either voltage). Direct connection means that they are connected to the power supply voltage VDD or the reference voltage GND without going through other circuit elements such as other transistors. The reference voltage GND is a voltage lower than the power supply voltage VDD, for example, the ground voltage (0V).

[0056] In the example shown in Figure 1, the current terminal on the opposite side of node N42 in transistor 41 is connected to the power supply voltage VDD via switch transistor 5. The current terminal on the opposite side of node N42 in transistor 42 is directly connected to the reference voltage GND.

[0057] The switch transistor 5 is connected between the store driver circuit 4 and the power supply voltage VDD or the reference voltage GND, more specifically between the current terminal of transistor 41 or transistor 42 of the store driver circuit 4 and the power supply voltage VDD or the reference voltage GND.

[0058] In the example shown in Figure 1, the switch transistor 5 is a P-type FET and is connected between the transistor 41 of the store driver circuit 4 and the power supply voltage VDD.

[0059] An inverting store signal STRB is supplied to the gate of the switch transistor 5, thereby controlling the on / off state of the switch transistor 5. The power supply voltage VDD can be supplied to or cut off from the store driver circuit 4. Such a switch transistor 5 can also be called a header-type switch transistor.

[0060] Switch transistor 5 consists of two (a pair) switch transistors. The first switch transistor is referred to as switch transistor 5-1 and is shown in the illustration. The second switch transistor is referred to as switch transistor 5-2 and is shown in the illustration. Unless otherwise specified, they are simply called switch transistor 5.

[0061] The restore driver circuit 6 is connected between the latch circuit 3 and the magnetoresistive element 7. The restore driver circuit 6 includes a transistor 61. The transistor 61 is an N-type FET and is connected between the latch circuit 3 and the magnetoresistive element 7.

[0062] The restore driver circuit 6 is a pair of restore driver circuits. One of the (first) restore driver circuits is referred to as restore driver circuit 6-1 and is shown in the figure. The other (second) restore driver circuit is referred to as restore driver circuit 6-2 and is shown in the figure. Unless otherwise specified, they are simply referred to as restore driver circuit 6.

[0063] Transistor 61 of restore driver circuit 6-1 is connected between node N31 of latch circuit 3 and magnetoresistive element 7-1, which will be described later. Transistor 61 of restore driver circuit 6-2 is connected between node N32 of latch circuit 3 and magnetoresistive element 7-2, which will be described later.

[0064] A restore signal RSTR is supplied to the gate of transistor 61, thereby controlling the on and off states of transistor 61.

[0065] The magnetoresistive element 7 is connected between the switch transistor 5 and the restore driver circuit 6 and the control line L8. The magnetoresistive element 7 is a pair of magnetoresistive elements. One of the (first) magnetoresistive elements is referred to as magnetoresistive element 7-1 and is shown in the figure. The other (second) magnetoresistive element is referred to as magnetoresistive element 7-2 and is shown in the figure. Unless otherwise specified, they are simply referred to as magnetoresistive element 7.

[0066] The magnetoresistive element 7 is a non-volatile memory element that switches between a low resistance state and a high resistance state. By associating these two resistance states with bit values, bit values ​​can be written (stored) to the magnetoresistive element 7. Specifically, writing to the magnetoresistive element 7 is performed so that one of the magnetoresistive elements 7-1 and 7-2 has a low resistance value and the other has a high resistance value, according to the bit value indicated by the bit signal Q input to terminal T1. An example of a magnetoresistive element 7 is an MTJ (magnetic tunnel junction) element.

[0067] The magnetoresistive element 7-1 is connected between the store driver circuit 4-1 and the restore driver circuit 6-1 and the control line L8. The connection point between the magnetoresistive element 7-1 and the store driver circuit 4-1 and the restore driver circuit 6-1 is referred to as node N7-1 and is shown in the diagram. It can also be said that the magnetoresistive element 7-1 is connected between node N7-1 and the control line L8.

[0068] The magnetoresistive element 7-2 is connected between the store driver circuit 4-2 and the restore driver circuit 6-2 and the control line L8. The connection point between the magnetoresistive element 7-2 and the store driver circuit 4-2 and the switch transistor 5-2 is referred to as node N7-2 and is shown in the diagram. It can also be said that the magnetoresistive element 7-2 is connected between node N7-2 and the control line L8.

[0069] The control line L8 is connected to the magnetoresistive element 7 on the opposite side of the magnetoresistive element 7 from the store driver circuit 4 and the switch transistor 5 (opposite to nodes N7-1 and N7-2). More specifically, the control line L8 is connected between the magnetoresistive element 7 and the control driver circuit 8.

[0070] The control driver circuit 8 is connected to the control line L8 and controls the voltage (potential) of the control line L8. The control driver circuit 8 includes node N81, node N82, transistor 81, and transistor 82.

[0071] Node N81 corresponds to the input portion of the control driver circuit 8. The control signal CTRL is supplied to node N81.

[0072] Node N82 corresponds to the output portion of the control driver circuit 8 and is connected to control line L8. The voltage at node N82 is output to control line L8.

[0073] Transistors 81 and 82 are cascode-connected to each other to form an inverter circuit. Transistor 81 is a P-type FET. Transistor 82 is an N-type FET. The gates of transistor 81 and each of transistor 82 are connected to node N81. The cascode connection point of transistors 81 and 82 (the connection point of their respective current terminals) corresponds to node N82.

[0074] In the example shown in Figure 1, the current terminal of transistor 81 opposite node N82 is connected to the power supply voltage VDD via the switch transistor 15. The current terminal of transistor 82 opposite node N82 is directly connected to the reference voltage GND.

[0075] In this example, the switch transistor 15 is a P-type FET and is connected between the control driver circuit 8 and the power supply voltage VDD. The gate of the switch transistor 15 receives a signal from the NOR gate 16, which controls the on / off state of the switch transistor 15. It can supply the power supply voltage VDD to the control driver circuit 8 or cut off its supply. Such a switch transistor 15 can also be called a header-type switch transistor.

[0076] The NOR gate 16 is a two-input gate. A store signal STR is input to one input terminal of the NOR gate 16. A restore signal RSTR is input to the other input terminal of the NOR gate 16. The NOR gate 16 outputs the negative OR signal of these two input signals to the gate of the switch transistor 15.

[0077] Furthermore, the memory circuit 1 does not need to have a verification function. In other words, the memory circuit 1 may be configured without a verification circuit. Unless otherwise specified, the memory circuit 1 shall not have a verification function.

[0078] <Example of Operation> According to the memory circuit 1 having the above configuration, the bit value indicated by the bit signal D can be written to the magnetoresistive element 7 for storage, and the bit value can be read from the magnetoresistive element 7 and output as the bit signal Q. The operation of the memory circuit 1 includes normal operation, store operation, and restore operation. These will be explained in order below. In the following explanation, the bit signal D will be assumed to be at the L level.

[0079] <Normal Operation> In normal operation, a signal corresponding to the bit signal D input to terminal T1 is held by nodes N21 and N22 of latch circuit 2, and nodes N31 and N32 of latch circuit 3.

[0080] The reset signal CN is set to a high level, and NAND gates 22 and 31 operate as inverters. The store signal STR, restore signal RSTR, and control signal CTRL are set to a low level.

[0081] A bit signal D, which is an L-level signal, is input to terminal T1. The inverter 11 inverts this bit signal D, i.e., the L-level signal, and outputs an H-level signal to the transmission gate 12.

[0082] When the clock signal CK falls, transmission gates 12 and 33 turn on, and transmission gates 23 and 13 turn off.

[0083] The transmission gate 12 transmits the H-level signal from the inverter 11 to node N21 of the latch circuit 2. Node N21 holds the H-level signal. The inverter 21 inverts the H-level signal from node N21 and outputs an L-level signal to node N22. Node N22 holds the L-level signal. The NAND gate 22 inverts the L-level signal from node N22 and outputs an H-level signal to the transmission gate 23.

[0084] When the clock signal CK falls (the inverted clock signal CKB rises), transmission gates 12 and 33 turn off, and transmission gates 13 and 23 turn on.

[0085] The transmission gate 13 transmits the low-level signal from node N22 to node N31. Node N31 holds the low-level signal. The NAND gate 31 inverts the low-level signal from node N31 and outputs a high-level signal to node N32. Node N32 holds the high-level signal.

[0086] The transmission gate 23 of the latch circuit 2 outputs the H-level signal from the NAND gate 22 to node N21. Node N21 holds the H-level signal. The inverter 21 inverts the H-level signal from node N21 and outputs the L-level signal to node N22. Node N22 holds the L-level signal.

[0087] The toggle of the clock signal CK is stopped. The same signal as bit signal D, i.e., an L-level signal in this example, is held by nodes N22 and N31. The inverted signal of that signal, i.e., an H-level signal in this example, is held by nodes N21 and N32.

[0088] <Store Operation> During the store operation, a store current flows through the magnetoresistive element 7 so that it has a resistance value corresponding to the signals held by nodes N31 and N32. The store current is a current that can switch the resistance value of the magnetoresistive element 7 between a low resistance value and a high resistance value. Here, the bit signal Q is assumed to be an L-level signal.

[0089] The store signal STR is set to high level. Switch transistor 5 turns on, and the power supply voltage VDD is supplied to the store driver circuit 4.

[0090] A high-level signal from node N32 of latch circuit 3 is input to node N41 of store driver circuit 4-1. Transistor 41 of store driver circuit 4-1 turns off, and transistor 42 turns on. Node N42 of store driver circuit 4-1 is connected to the reference voltage GND via transistor 42. Node N42 of store driver circuit 4-1 outputs the reference voltage GND to node N7-1. Node N7-1 has the reference voltage GND.

[0091] The L-level signal from node N31 of the latch circuit 3 is input to node N41 of the store driver circuit 4-2. Transistor 41 of the store driver circuit 4-2 turns on, and transistor 42 turns off. Node N42 of the store driver circuit 4-2 is connected to the power supply voltage VDD via transistor 42 and switch transistor 5-2. Node N42 of the store driver circuit 4-2 outputs the power supply voltage VDD to node N7-2. Node N7-2 has the power supply voltage VDD.

[0092] The NOR gate 16 outputs an L-level signal. The switch transistor 15 turns on.

[0093] During the store operation, the control signal CTRL is toggled once. Here, as an example, the control signal CTRL is set to L level and then H level in that order.

[0094] When the control signal CTRL is set to the L level, transistor 81 of the control driver circuit 8 turns on and transistor 82 turns off. Node N82 is connected to the power supply voltage VDD via transistor 81 and switch transistor 15. Node N82 outputs the power supply voltage VDD to control line L8. Control line L8 has the power supply voltage VDD.

[0095] As mentioned earlier, node N7-1 is connected to the reference voltage GND. A store current flows from the control line L8 to node N7-1 through the magnetoresistive element 7-1 connected between node N7-1 and the control line L8. The resistance value of the magnetoresistive element 7-1 after this store is assumed to be a low resistance value.

[0096] When the control signal CTRL is set to the H level, transistor 81 of the control driver circuit 8 turns off and transistor 82 turns on. Node N82 is connected to the reference voltage GND via transistor 82. Node N82 outputs the reference voltage GND to control line L8. Control line L8 has the reference voltage GND.

[0097] As mentioned earlier, the magnetoresistive element 7-2 has a power supply voltage VDD. A store current flows from node N7-2 to control line L8 through the magnetoresistive element 7-2, which is connected between node N7-2 and control line L8. The resistance value of the magnetoresistive element 7-2 after this store is assumed to be a high resistance value.

[0098] The store signal STR is set to L level, and the store operation ends. After that, the power supply to the entire memory circuit 1 may be cut off. Even without power supply, the resistance values ​​of magnetoresistive elements 7-1 and 7-2 are maintained.

[0099] <Restore Operation> During the restore operation, a restore current flows through the magnetoresistive element 7 so that nodes N31 and N32 retain the same signals as during the previous store operation. The restore current is a current that does not change the resistance value of the magnetoresistive element 7, and is smaller than the store current.

[0100] First, we will explain the case where power to the entire memory circuit 1 is restored after it has been cut off. The reset signal CN is set to a high level, and NAND gates 22 and 31 operate as inverters. The store signal STR is set to a low level. The restore signal RSTR is set to a high level. Transistor 34 of the latch circuit 3 is turned on, and the transmission gate 33 is bypassed. The power switch local signal PSL is set to a low level. Switch transistors 31a and 32a are turned on, and the power supply voltage VDD is supplied to NAND gate 31 and inverter 32.

[0101] The transistor 61 of the restore driver circuit 6 is turned on. Node N7-1 is connected to node N31 of the latch circuit 3 via transistor 61 of the restore driver circuit 6-1. Node N7-2 is connected to node N32 of the latch circuit 3 via transistor 61 of the restore driver circuit 6-2.

[0102] The NOR gate 16 outputs an L-level signal. The switch transistor 15 turns on.

[0103] The control signal CTRL is set to L level, turning transistor 81 of the control driver circuit 8 on and transistor 82 off. Node N82 is connected to the power supply voltage VDD via transistor 81 and switch transistor 15. Node N82 outputs the power supply voltage VDD to control line L8. Control line L8 has the power supply voltage VDD.

[0104] The potential of latch circuit 3, which is supplied with power voltage even before that point, becomes higher than the potential of control line L8. The potential of node N7-1, which is connected to node N31 of latch circuit 3, and the potential of node N7-2, which is connected to node N32, also become higher than the potential of control line L8.

[0105] A restore current flows through magnetoresistive element 7-1 from node N7-1 toward control line L8. A restore current flows through magnetoresistive element 7-2 from node N7-2 toward control line L8.

[0106] In the above case, a restore current flows in accordance with the power supply to the entire memory circuit 1. However, it is also possible to flow a restore current simply by controlling the power supply of the latch circuit 3 independently of the power supply control of the memory circuit 1. Specifically, first, the power switch local signal PSL is set to the H level. Switch transistors 31a and 32a turn off, and the supply of power voltage VDD to the NAND gate 31 and inverter 32 stops. Next, the power switch local signal PSL is set to the L level. Switch transistors 31a and 32a turn on, and the supply of power voltage VDD to the NAND gate 31 and inverter 32 begins. As mentioned earlier, by setting the reset signal CN, the store signal STR, and the restore signal RSTR, a similar restore current flows. In other words, the same operation as restoring the power supply to the entire memory circuit 1 can also be performed by controlling the power supply of only the latch circuit 3 using the power switch local signal PSL.

[0107] As the restore current flows, nodes N31 and N32 maintain potentials corresponding to the resistance values ​​of magnetoresistive elements 7-1 and 7-2. As mentioned earlier, in this example, magnetoresistive element 7-1 has a low resistance value, and magnetoresistive element 7-2 has a high resistance value. The potential of node N7-2 rises faster than the potential of node N7-1. The potential of node N32, which is connected to node N7-2, rises faster than the potential of node N31, which is connected to node N7-1.

[0108] In the latch circuit 3, the potentials of nodes N31 and N32 are fixed by a loop consisting of node N31, NAND gate 31, node N32, inverter 32, and transistor 34. Since the potential of node N32 is higher than the potential of node N31, node N32 holds the H-level signal. Node N31 holds the L-level signal. This state is the same as the state of nodes N31 and N32 during storage. In this state, the restore signal RSTR is set to L level.

[0109] The inverter 14 inverts the H-level signal from node N32 and outputs an L-level signal to terminal T2. Terminal T2 outputs a bit signal Q, which is an L-level signal. This bit signal Q is the same as the bit signal D that was input to terminal T1 during normal operation.

[0110] For example, through the above operation, the memory circuit 1 stores the bit value indicated by the bit signal Q, maintains that storage even when the power supply is cut off, and outputs the bit signal D indicating that bit value when power is supplied again.

[0111] Another example of operation besides those described above is the reset operation. When the reset signal CN is set to the L level, both NAND gate 22 and NAND gate 31 output an H level signal. In particular, when NAND gate 31 outputs an H level signal to node N32, inverter 14 inverts the H level signal from node N32 and outputs an L level signal to terminal T2. As a result, the bit signal Q is reset to the L level.

[0112] Furthermore, a restore retry operation is also possible. As mentioned earlier, in memory circuit 1, the restore operation can be performed not only by controlling the power supply of the entire memory circuit 1, but also by controlling the power supply of latch circuit 3. The restore can be performed at any timing while power is supplied to the entire memory circuit 1. The specific control is as described above.

[0113] The memory circuit 1 described above simplifies the circuit configuration for functions other than restore. Specifically, in the memory circuit 1 described above, a header-type switch transistor 5 is provided for the store driver circuit 4. The transistor 42 of the store driver circuit 4 is directly connected to the reference voltage GND without the need for other transistors. Compared to a configuration in which other transistors are connected between the store driver circuit and the power supply voltage and the reference voltage, as in Patent Document 1, the circuit configuration is simplified. This reduces the circuit area and leakage current. Furthermore, the memory circuit 1 does not need to have a verify function. The absence of a verify circuit further simplifies the circuit configuration. This further reduces the circuit area and leakage current.

[0114] 1.2 Modifications of the NVFF Circuit The configuration of the NVFF circuit is not limited to the circuit configuration shown in Figure 1 above. Several modifications will be described.

[0115] Figures 2 to 10 show modified versions of the memory circuit 1. The differences will be explained below.

[0116] In the example shown in Figure 2, the set signal SN is used instead of the reset signal CN. The set signal SN is used to set the bit signal Q to the H level. When setting, the set signal SN is set to the L level. When not setting, the set signal SN is set to the H level.

[0117] The latch circuit 2 differs from the circuit configuration in Figure 1 described earlier in that it includes a NAND gate 24 and an inverter 25 instead of the inverter 21 and NAND gate 22.

[0118] The NAND gate 24 is connected between node N21 and node N22. The NAND gate 24 is a two-input gate. A signal from node N21 is input to one input terminal of the NAND gate 24. A set signal SN is input to the other input terminal of the NAND gate 24. The NAND gate 24 outputs the negated logical AND signal of these two input signals to node N22. When the set signal SN is set to a high level, the NAND gate 24 operates as an inverter.

[0119] The inverter 25 is connected between node N22 and transmission gate 23. The inverter 25 inverts the signal from node N22 and outputs it to transmission gate 23.

[0120] The latch circuit 3 differs from the circuit configuration in Figure 1 described earlier in that it includes an inverter 35, a switch transistor 35a, a NAND gate 36, and a switch transistor 36a, instead of the NAND gate 31, a switch transistor 31a, an inverter 32, and a switch transistor 32a.

[0121] The inverter 35 is connected between node N31 and node N32. The inverter 35 inverts the signal from node N31 and outputs it to node N32.

[0122] The switch transistor 35a is a P-type FET and is connected between the inverter 35 and the power supply voltage VDD. A power switch local signal PSL is supplied to the gate of the switch transistor 35a, which allows the power supply voltage VDD to be supplied to the inverter 35 or to be cut off.

[0123] The NAND gate 36 is connected between node N32 and transmission gate 33. The NAND gate 36 is a two-input gate. A signal from node N32 is input to one input terminal of the NAND gate 36. A set signal SN is input to the other input terminal of the NAND gate 36. The NAND gate 36 outputs the negative logical AND signal of these two input signals to the transmission gate 33. When the set signal SN is set to high level, the NAND gate 36 operates as an inverter.

[0124] The switch transistor 36a is a P-type FET and is connected between the NAND gate 36 and the power supply voltage VDD. A power switch local signal PSL is supplied to the gate of the switch transistor 36a, which allows the power supply voltage VDD to be supplied to the NAND gate 36 or to be cut off.

[0125] The circuit configuration in Figure 2 also allows for normal operation, store operation, and restore operation, similar to the circuit configuration in Figure 1 described earlier. The restore operation can be performed not only by controlling the power supply of the entire memory circuit 1, but also by controlling the power supply of the latch circuit 3, and retries can be performed by controlling the power supply of the latch circuit 3. Another example of operation is the set operation. When the set signal SN is set to L level, both NAND gate 24 and NAND gate 36 output H level signals. In particular, when NAND gate 36 outputs an H level signal to transmission gate 33, transmission gate 33 transmits the H level signal from NAND gate 36 to node N31. Inverter 35 inverts the H level signal from node N31 and outputs an L level signal to node N32. Inverter 14 inverts the L level signal from node N32 and outputs an H level signal to terminal T2. As a result, the bit signal Q is set to H level.

[0126] In the examples shown in Figures 3 and 4, the memory circuit 1 is a footer-type NVFF circuit. The memory circuit 1 differs from the configurations in Figures 1 and 2 described earlier, in particular, that the switch transistor 5 is an N-type FET, the switch transistor 15 is an N-type FET, and that it includes an OR gate 16a instead of a NOR gate 16.

[0127] In this example, the current terminal of transistor 41 in the store driver circuit 4, opposite to node N42, is directly connected to the power supply voltage VDD. The current terminal of transistor 42, opposite to node N42, is connected to the reference voltage GND via switch transistor 5.

[0128] In this example, the switch transistor 5 is an N-type FET as described above, and is connected between the transistor 42 of the store driver circuit 4 and the reference voltage GND.

[0129] By controlling the on / off state of this switch transistor 5, the power supply voltage VDD can be supplied to or cut off from the store driver circuit 4. Such a switch transistor 5 can also be called a footer-type switch transistor.

[0130] The switch transistor 15 is connected between the control driver circuit 8 and the reference voltage GND. More specifically, the switch transistor 15 is connected between the current terminal on the opposite side of node N82 of transistor 82 in the control driver circuit 8 and the reference voltage GND.

[0131] The gate of the switch transistor 15 is supplied with a signal from the OR gate 16a, thereby controlling the on and off state of the switch transistor 15. The power supply voltage VDD can be supplied to the control driver circuit 8, or its supply can be cut off. Such a switch transistor 15 can also be called a footer-type switch transistor.

[0132] The OR gate 16a is a two-input gate. A store signal STR is input to one input terminal of the OR gate 16a. A restore signal RSTR is input to the other input terminal of the OR gate 16a. The OR gate 16a outputs the logical OR signal of these two input signals to the gate of the switch transistor 15.

[0133] In the circuit configuration of Figure 3, as explained earlier in Figure 1, the bit signal Q can be set to L level (reset) by setting the reset signal CN to L level. In the circuit configuration of Figure 4, as explained earlier in Figure 2, the bit signal Q can be set to H level by setting the set signal SN to L level.

[0134] According to the memory circuit 1 shown in Figures 3 and 4 above, a footer-type switch transistor 5 is provided for the store driver circuit 4. The transistor 41 of the store driver circuit 4 is directly connected to the power supply voltage VDD without going through other transistors. This simplifies the circuit configuration related to storage and suppresses circuit area and leakage current.

[0135] In the examples shown in Figures 5 to 8, the power switch local signal (PSL) is not required.

[0136] The memory circuit 1 shown in Figure 5 differs from Figure 1, which was described earlier, in that it does not include switch transistors 31a and 32a. Although not shown in the figure, the power supply voltage VDD is connected to the NAND gate 31 and inverter 32 without going through those switch transistors.

[0137] The memory circuit 1 shown in Figure 6 differs from that in Figure 2, which was described earlier, in that it does not include switch transistors 35a and 36a. Although not shown in the figure, the power supply voltage VDD is connected to the inverter 35 and NAND gate 36 without going through those switch transistors.

[0138] The memory circuit 1 shown in Figure 7 differs from that in Figure 3, which was described earlier, in that it does not include switch transistors 31a and 32a. Although not shown in the figure, the power supply voltage VDD is connected to the NAND gate 31 and inverter 32 without going through those switch transistors.

[0139] The memory circuit 1 shown in Figure 8 differs from that in Figure 4, which was described earlier, in that it does not include switch transistors 35a and 36a. Although not shown in the figure, the power supply voltage VDD is connected to the inverter 35 and NAND gate 36 without going through those switch transistors.

[0140] According to the configuration shown in Figures 5 to 8 above, the circuit configuration can be further simplified by eliminating the switch transistors 31a, 32a, 35a, and 36a.

[0141] The memory circuit 1 shown in Figures 9 and 10 differs from those in Figures 1 and 2 described earlier in that it does not include the NOR gate 16 and an inverting store signal STRB is supplied to the gate of the switch transistor 15. The operation is the same as before, so the explanation will be omitted. The absence of the NOR gate 16 allows for further simplification of the circuit configuration.

[0142] 1.3 Example of an NV latch circuit. The memory circuit is not limited to an FF (flip-flop) circuit. A memory circuit that does not have an FF function is also simply called an NV latch circuit. The memory circuit that is an NV latch circuit will be referred to as memory circuit 1A. This will be explained with reference to Figures 11 to 14.

[0143] Figure 11 shows an example of the schematic configuration of the memory circuit 1A. In the example shown in Figure 11, the memory circuit 1A is a header-type NV latch circuit.

[0144] Memory circuit 1A differs from memory circuit 1 in Figure 1, which was described earlier, in that it does not include the transmission gate 12 and latch circuit 2, a gate signal G is supplied instead of the clock signal CK, and the latch circuit 3 has a different configuration.

[0145] The inverter 11, transmission gate 13, latch circuit 3, and inverter 14 are connected between terminal T1 and terminal T2 in this order.

[0146] The transmission gate 13 is connected between the inverter 11 and the latch circuit 3. When the transmission gate 13 is ON, it transmits the signal from the inverter 11 to node N31 of the latch circuit 3.

[0147] The transmission gate 13 of the memory circuit 1A is supplied with a gate signal G and an inverting gate signal GB. The inverting gate signal GB is the inverted version of the gate signal G. The transmission gate 13 switches on and off according to the gate signal G. For example, when the gate signal G is at a high level, the transmission gate 13 turns on. When the gate signal G is at a low level, the transmission gate 13 turns off.

[0148] The latch circuit 3 differs from the configuration shown in Figure 1, which was described earlier, in that it does not include the NAND gate 31, switch transistor 31a, inverter 32, and switch transistor 32a, but does include the inverter 37. In addition, the transmission gate 33 is supplied with a gate signal G and an inverting gate signal GB in the opposite relationship to that of the transmission gate 13. When the transmission gate 13 is ON, the transmission gate 33 is OFF. When the transmission gate 13 is OFF, the transmission gate 33 is ON.

[0149] Node N32 is connected to node N31 and has the same potential as node N31.

[0150] Inverter 37 is connected between node N32 and inverter 32. This connection point is referred to as node N33 and is shown in the diagram. Due to the loop of latch circuit 3, nodes N32 and N33 hold inverted level signals relative to each other. This provides the same holding function as nodes N31 and N32 of the NVFF circuit (Figures 1 to 10) described earlier.

[0151] <Example of Operation> The memory circuit 1A having the above configuration can also store the bit value indicated by the bit signal D in the magnetoresistive element 7, just as the memory circuit 1 (Figure 1) described earlier, and can also read the bit value from the magnetoresistive element 7 and output it as a bit signal Q.

[0152] As an example, we will explain assuming that the bit signal D is at the L level. We will omit explanations of aspects that overlap with the memory circuit 1 (Figure 1) mentioned earlier.

[0153] <Normal Operation> A bit signal D, which is an L-level signal, is input to terminal T1. The inverter 11 inverts the bit signal D, i.e., the L-level signal, and outputs an H-level signal to the transmission gate 13.

[0154] When the gate signal G is set to H level, the transmission gate 13 turns on and the transmission gate 33 turns off. The transmission gate 13 transmits the H level signal from the inverter 11 to node N31 of the latch circuit 3. Nodes N31 and N32 hold the H level. The inverter 37 inverts the H level signal from node N32 and outputs an L level signal to node N33. Node N33 holds the L level signal. The inverter 32 inverts the L level signal from node N33 and outputs an H level signal to the transmission gate 33.

[0155] When the gate signal G is set to L level, transmission gate 13 turns off and transmission gate 33 turns on. Transmission gate 33 transmits an H level signal from inverter 32 to node N31.

[0156] The toggle of gate signal G is stopped. The same signal as bit signal D, i.e., an L-level signal in this example, is held by node N33. The inverted signal of that signal, i.e., an H-level signal in this example, is held by nodes N31 and N32.

[0157] <Store and Restore Operations> The store and restore operations will be explained by substituting nodes N31 and N32 of the previously described memory circuit 1 (Figure 1) with nodes N31 and N33 of this memory circuit 1A (Figure 11). Details will be omitted.

[0158] Figure 12 is a timing chart showing an example of the operation of the memory circuit 1A. Here, the bit value indicated by the H-level bit signal D is stored by the store operation and read out by the restore operation.

[0159] The bit signal D, gate signal G, bit signal Q, store signal STR, control signal CTRL, power switch signal PS, restore signal RSTR, and circuit current I are schematically shown. The power switch signal PS is a signal that controls the power supply to the entire memory circuit 1A and is supplied to the gate of the power gate (P-type FET) mentioned earlier. When the power switch signal PS is at a high level, the power supply to the entire memory circuit 1A is cut off. The circuit current I indicates the magnitude of the current flowing through the magnetoresistive element 7 and is expressed as a negative value.

[0160] During normal operation, both the store signal STR and the restore signal RSTR are set to L level. Between time t1 and time t3, the gate signal G is set to H level. The bit signal Q has the same level as the bit signal D. That is, when the bit signal D is at L level, as between time t1 and time t2, the bit signal Q is also at L level. When the bit signal D is at H level, as between time t2 and time t3, the bit signal Q is also at H level.

[0161] During the store operation, more specifically between time t4 and time t6, the store signal STR is set to a high level. During this time, the control signal CTRL is toggled once. The circuit current I changes in two stages, from time t4 to time t5 and from time t5 to time t6. This circuit current I flows as the store current. The bit value indicated by the bit signal D is written to the magnetoresistive element 7.

[0162] During the restore operation, more specifically at time t7, the power switch signal PS is set to the H level, and the restore signal RSTR is also set to the H level. In this state, the power supply to the entire memory circuit 1 is stopped. At time t8, the power switch signal PS is set to the L level, and the power supply to the entire memory circuit 1 is resumed. At the following time t9, the restore signal RSTR is set to the L level. Between time t8 and time t9, the circuit current I flows as the restore current. The value indicated by the bit signal D is read out from the magnetoresistive element 7.

[0163] As described above, the memory circuit 1A, like the memory circuit 1 (Figure 1) described earlier, simplifies the circuit configuration for functions other than restore. Specifically, the transistor 42 of the store driver circuit 4 is directly connected to the reference voltage GND without going through other transistors, etc. This reduces circuit area and leakage current. Furthermore, the memory circuit 1A does not have a verify function. The absence of a verify circuit simplifies the circuit configuration, further reducing circuit area and leakage current.

[0164] 1.4 Modified NV Latch Circuit Figures 13 and 14 show modified versions of the memory circuit 1A. In the example shown in Figure 13, the memory circuit 1A is a footer-type NV latch circuit. The memory circuit 1A differs from the configuration in Figure 11 described earlier in that the switch transistor 5 is an N-type FET, the switch transistor 15 is an N-type FET, and the NOR gate 16 is replaced with an OR gate 16a. The footer-type configuration is the same as that described earlier in Figures 3 and 4, so no further explanation will be given.

[0165] According to the memory circuit 1A shown in Figure 13 above, a footer-type switch transistor 5 is provided for the store driver circuit 4. The transistor 41 of the store driver circuit 4 is directly connected to the power supply voltage VDD without going through other transistors. This also simplifies the circuit configuration related to storage and suppresses circuit area and leakage current.

[0166] The memory circuit 1A shown in Figure 14 differs from the memory circuit 11 described earlier in that it does not include the NOR gate 16 and that an inverting store signal STRB is supplied to the gate of the switch transistor 15. Further simplification of the circuit configuration is possible.

[0167] 2. Application Examples to Programmable Logic Circuits One of the features of memory circuit 1 or memory circuit 1A described above is that it has a circuit configuration specialized for restoring rather than storing. One effective application of such a circuit is its application to programmable logic circuits. Several examples of the configuration of the circuit device will be described with reference to Figures 15 to 22. In the following, unless otherwise distinguished, memory circuit 1 and memory circuit 1A may simply be referred to as memory circuit 1. Within the bounds of consistency, memory circuit 1 and memory circuit 1A may be appropriately interpreted.

[0168] Figure 15 shows an example of the schematic configuration of the circuit device 100. The circuit device 100 is a programmable logic device (semiconductor integrated circuit), such as an FPGA (Field Programmable Gate Array). The circuit device 100 is composed of a plurality of programmable logic blocks. Each logic block includes one programmable logic circuit 9, and one logic block is schematically shown in Figure 15.

[0169] Multiple memory circuits 1 are used for one programmable logic circuit 9. The memory circuit 1 described so far corresponds to one of the multiple memory circuits 1.

[0170] Multiple memory circuits 1 store bit values ​​(configuration data) that define the logic configuration of the programmable logic circuit 9. A signal indicating that bit value is read out from the memory circuit 1 as a bit signal Q.

[0171] In the example shown in Figure 15, the logic configuration of the programmable logic circuit 9 is defined by a Look Up Table (LUT). As an example, 16 memory circuits 1 are used as a 16-bit LUT that defines the logic configuration of the programmable logic circuit 9.

[0172] To distinguish each memory circuit 1, they are referred to and illustrated as memory circuits 1-1 to 1-16. When not specifically distinguished, they are simply called memory circuit 1 or each memory circuit 1. The bit signals Q output by memory circuits 1-1 to 1-16 are referred to as bit signals Q-1 to Q-16. When not specifically distinguished, they are simply called bit signal Q or each bit signal Q.

[0173] The bit signals input to the programmable logic circuit 9 are referred to as input bit signals IN. The signals output by the programmable logic circuit 9 are referred to as output bit signals OUT. In the example shown in Figure 15, the programmable logic circuit 9 is a 4-input, 1-output logic circuit. The first input bit signal IN is referred to as input bit signal IN-1. The second input bit signal IN is referred to as input bit signal IN-2. The third input bit signal IN is referred to as input bit signal IN-3. The fourth input bit signal IN is referred to as input bit signal IN-4. When these are not specifically distinguished, they are simply referred to as input bit signals IN or each input bit signal IN.

[0174] In the example shown in Figure 15, the programmable logic circuit 9 includes multiple selectors 91. The multiple selectors 91 are connected to realize the logic configuration defined by the LUT. In this example, the multiple selectors 91 are connected in a four-stage configuration. Eight selectors 91 are arranged in the first stage, four selectors 91 in the second stage, two selectors 91 in the third stage, and one selector 91 in the fourth stage.

[0175] Each bit signal Q of each memory circuit 1 is input to the corresponding selector 91, more specifically the selector 91 located in the first stage, according to a given mapping rule. Each bit signal IN is supplied to the corresponding selector 91 according to a given mapping rule. The bit signal output by the selector 91 located in the fourth stage corresponds to the output bit signal OUT.

[0176] According to the circuit device 100 described above, multiple memory circuits 1 are used to store bit values ​​that define the logic configuration of the programmable logic circuit 9. This makes it possible to make the configuration data of the programmable logic circuit 9 non-volatile (NV). For example, even if the power to the circuit device 100 is turned off, the configuration data is maintained, so there is no need to prepare and write the configuration data again when the power is turned on next. The frequency of storing data in the memory circuits 1 is low, while the frequency of restoring data is high. The characteristics of the memory circuits 1, which are specialized for restoration, can be effectively utilized. Also, even after reading the bit signal Q of each memory circuit 1 to check the configuration, there is no need to input the configuration data again. For example, if the bit signal Q of each memory circuit 1 is read in a bucket-brigade manner, the bit signal Q of each memory circuit 1 will be overwritten, but if the memory circuits 1 are non-volatile, they will return to their original state if restored again.

[0177] The configuration of the programmable logic circuit 9 is not limited to the configuration shown in Figure 15 above. For example, the memory circuit 1 can also be applied to programmable logic circuits such as those known in Non-Patent Documents 1 and 2. This will be explained with reference to Figures 16 to 18.

[0178] Figure 16 shows an example of the schematic configuration of the circuit device 100. The programmable logic circuit 9 shown is a 4-input, 3-output logic circuit. There is some overlap with the previous explanation, but the first input bit signal IN of the four input signals IN is called input bit signal IN-1. The second input bit signal IN is called input bit signal IN-2. The third input bit signal IN is called input bit signal IN-3. The fourth input bit signal IN is called input bit signal IN-4.

[0179] The first of the three output bit signals OUT is referred to as output bit signal OUT-1. The second output bit signal OUT is referred to as output bit signal OUT-2. The third output bit signal OUT is referred to as output bit signal OUT-3. When no particular distinction is made between them, they are simply referred to as output bit signal OUT or each output bit signal OUT.

[0180] When the programmable logic circuit 9 receives input bit signals IN-1 to IN-4, it outputs output bit signals OUT-1 to OUT-3.

[0181] Eight memory circuits 1 are used for one programmable logic circuit 9. There is some overlap with the previous explanation, but the first memory circuit of the control driver circuit 8 and memory circuits 1 will be referred to as memory circuit 1-1 and illustrated. The second memory circuit will be referred to as memory circuit 1-2 and illustrated. The third memory circuit will be referred to as memory circuit 1-3 and illustrated. The fourth memory circuit will be referred to as memory circuit 1-4 and illustrated. The fifth memory circuit will be referred to as memory circuit 1-5 and illustrated. The sixth memory circuit will be referred to as memory circuit 1-6 and illustrated. The seventh memory circuit will be referred to as memory circuit 1-7 and illustrated. The eighth memory circuit will be referred to as memory circuit 1-8 and illustrated.

[0182] The bit signal Q output by memory circuit 1-1 is referred to as bit signal Q-1 (the first bit signal). The bit signal Q output by memory circuit 1-2 is referred to as bit signal Q-2 (the second bit signal). The bit signal Q output by memory circuit 1-3 is referred to as bit signal Q-3 (the third bit signal). The bit signal Q output by memory circuit 1-4 is referred to as bit signal Q-4 (the fourth bit signal). The bit signal Q output by memory circuit 1-5 is referred to as bit signal Q-5 (the fifth bit signal). The bit signal Q output by memory circuit 1-6 is referred to as bit signal Q-6 (the sixth bit signal). The bit signal Q output by memory circuit 1-7 is referred to as bit signal Q-7 (the seventh bit signal). The bit signal Q output by memory circuit 1-8 is referred to as bit signal Q-8 (the eighth bit signal).

[0183] The programmable logic circuit 9 includes three programmable AND circuits 92. Of the three programmable AND circuits 92, the first programmable AND circuit is referred to as programmable AND circuit 92-1 and is shown in the diagram. The second programmable AND circuit is referred to as programmable AND circuit 92-2 and is shown in the diagram. The third programmable AND circuit is referred to as programmable AND circuit 92-3 and is shown in the diagram. Unless otherwise specified, these are simply referred to as programmable AND circuits 92 or each programmable AND circuit 92.

[0184] The programmable AND circuit 92 is a 2-input, 1-output logic circuit. The programmable AND circuit 92-1 outputs the output bit signal OUT-1. The programmable AND circuit 92-2 outputs the output bit signal OUT-2. The programmable AND circuit 92-3 outputs the output bit signal OUT-3.

[0185] The programmable AND circuit 92-1 receives the input bit signal IN-1, the bit signal Q-1 from memory circuit 1-1, and the bit signal Q-2 from memory circuit 1-2. Furthermore, the programmable AND circuit 92-1 selectively receives either the input bit signal IN-2 or the output bit signal OUT-2 from programmable AND circuit 92-2, depending on the bit signal Q-7 from memory circuit 1-7.

[0186] The programmable AND circuit 92-2 receives the bit signal Q3 from memory circuit 1-3 and the bit signal Q4 from memory circuit 1-4. Furthermore, the programmable AND circuit 92-2 selectively receives either the input bit signal IN-2 or the output bit signal OUT-1 from programmable AND circuit 92-1, depending on the bit signal Q-7 from memory circuit 1-7. In addition, the programmable AND circuit 92-2 selectively receives either the input bit signal IN-3 or the output bit signal OUT-3 from programmable AND circuit 92-3, depending on the bit signal Q-8 from memory circuit 1-8.

[0187] The programmable AND circuit 92-3 receives the input bit signal IN-4, the bit signal Q-5 from memory circuit 1-5, and the bit signal Q-6 from memory circuit 1-6. Furthermore, the programmable AND circuit 92-3 selectively receives either the input bit signal IN-3 or the output bit signal OUT-2 from programmable AND circuit 92-2, depending on the bit signal Q-8 from memory circuit 1-8.

[0188] The programmable AND circuit 92 will be explained with reference to Figures 17 and 18.

[0189] Figure 17 shows an example of a schematic configuration of a programmable AND circuit 92. As an example, programmable AND circuit 92-1 is shown. Programmable AND circuit 92-1 is configured to satisfy the truth table in Figure 18, which will be described later. As an example of such a configuration, the programmable AND circuit 92-1 shown in Figure 17 includes an XOR gate 921 (first XOR gate), an AND gate 922, and an XOR gate 923 (second XOR gate).

[0190] The XOR gate 921 is a two-input gate. One input terminal of the XOR gate 921 is input to the corresponding input bit signal IN or the output bit signal OUT-2 of the corresponding other programmable AND circuit 92. The other input terminal is input to the bit signal Q of the corresponding memory circuit 1. Specifically, in the case of programmable AND circuit 92-1, one input terminal of the XOR gate 921 is input to the input bit signal IN-2 or the output bit signal OUT-2 of programmable AND circuit 92-2 (Figure 16). The other input terminal is input to the bit signal Q-1 of memory circuit 1-1 (Figure 16). The XOR gate 921 outputs the exclusive OR signal of these two input signals.

[0191] The AND gate 922 is a two-input gate. The corresponding input bit signal IN is input to one input terminal of the AND gate 922. The output signal of the XOR gate 921 is input to the other input terminal. Specifically, in the case of the programmable AND circuit 92-1, the input bit signal IN-1 is input to one input terminal of the AND gate 922. The output signal of the XOR gate 921 is input to the other input terminal of the AND gate 922. The AND gate 922 outputs the logical AND signal of these two input signals.

[0192] The XOR gate 923 is a two-input gate. The output signal of the AND gate 922 is input to one input terminal of the XOR gate 923. The bit signal Q of the corresponding memory circuit 1 is input to the other input terminal. Specifically, in the case of the programmable AND circuit 92-1, the output signal of the AND gate 922 is input to one input terminal of the XOR gate 923. The bit signal Q2 of the memory circuit 1-2 (Figure 16) is input to the other input terminal. The XOR gate 923 outputs the exclusive OR signal of these two input signals. The output signal of the XOR gate 923 corresponds to the output bit signal OUT-1.

[0193] Figure 18 shows an example of a truth table for the programmable AND circuit 92-1. In the truth table shown, the input bit signal IN-1 is represented as x. The input bit signal IN-2 or the output bit signal OUT-1 is represented as y.

[0194] If the bit values ​​indicated by bit signals Q-1 and Q-2 are both "0", the output bit signal OUT-1 will be the logical AND value of x and y.

[0195] If the bit value indicated by bit signal Q-1 is "0" and the bit value indicated by bit signal Q-2 is "1", then the output bit signal OUT-1 will be the inverted value of the logical AND of x and y.

[0196] If the bit value indicated by bit signal Q-1 is "1" and the bit value indicated by bit signal Q-2 is "0", then the output bit signal OUT-1 will be the logical AND of x and the inverted value of y.

[0197] When the bit values ​​indicated by bit signals Q-1 and Q-2 are both "1", the output bit signal OUT-1 is the inverted value of the logical AND of x and the inverted value of y.

[0198] Returning to Figure 16, the configuration and truth tables of programmable AND circuits 92-2 and 92-3 are the same as those of programmable AND circuit 92-1, which was explained earlier with reference to Figures 16 and 17. By applying eight memory circuits 1 to the programmable logic circuit 9, which includes these three programmable AND circuits 92, any logic configuration with four inputs and three outputs can be obtained. A logic configuration with more outputs can be realized than the configuration of Figure 15 (four inputs and one output) explained earlier. Moreover, this logic configuration can be realized with three programmable AND circuits 92, i.e., a three-stage configuration. The number of stages is one less than the configuration of Figure 15 (four-stage configuration) explained earlier, and the delay is reduced accordingly. The possibility of improving the performance of the circuit increases. Furthermore, since only eight memory circuits 1 are needed, the number of memory circuits 1 can be reduced compared to the configuration of Figure 15 (sixteen memory circuits 1) explained earlier.

[0199] 3. Examples of Control Circuits As described above, control circuits for writing bit values ​​to the memory circuit 1 (or memory circuit 1A) applied to the programmable logic circuit 9, and for reading bit values ​​from the memory circuit 1, may also be included in the circuit device 100. These will be explained with reference to Figures 19 to 22.

[0200] Figure 19 shows an example of the schematic configuration of the circuit device 100. The circuit device 100 further includes a control circuit 110.

[0201] The control circuit 110 writes the corresponding bit value to each memory circuit 1 and reads the bit value from each memory circuit 1. The signal indicating the bit value to be written to memory circuit 1 is the bit signal D, as previously explained. The signal indicating the bit value to be read from memory circuit 1 is the bit signal Q, as previously explained.

[0202] The control method by the control circuit 110 may differ between memory circuit 1, which is an NVFF (Figures 1 to 10), and memory circuit 1A, which is an NV latch circuit (Figures 11 to 14). This will be explained with reference to Figures 20 to 22.

[0203] Figure 20 shows an example of the schematic configuration of a control circuit 110 for memory circuit 1A. In this example, the control circuit 110 includes a shift register 111 and a decoder 112 (selector). The bit values ​​that define the logic configuration of the programmable logic circuit 9 are written to the corresponding memory circuit 1A via the shift register 111 and the decoder 112.

[0204] Specifically, multiple shift registers 111 are connected in a cascode configuration. Bit signals D indicating the bit values ​​to be written to the memory circuit 1A are transferred to and held in the corresponding shift registers 111. That is, multiple bit signals D corresponding to multiple memory circuits 1A are sequentially input to the first-stage shift register 111. The input bit signals D are sequentially transferred from the first-stage shift register 111 to the subsequent shift registers 111 and held in the corresponding shift registers 111.

[0205] The decoder 112 is connected between the shift register 111 and the multiple memory circuits 1A. The decoder 112 supplies the bit signals D held by each shift register 111 to the corresponding memory circuits 1A.

[0206] In this example, there are two programmable logic circuits 9 for one decoder 112, and multiple memory circuits 1A are provided for each programmable logic circuit 9. The decoder 112 selects one programmable logic circuit 9 according to a given selection signal Sel. The decoder 112 supplies the corresponding bit signal D from the bit signals D held by the shift register 111 to each of the multiple memory circuits 1A provided for the selected programmable logic circuit 9.

[0207] Furthermore, the example shift register 111 is a scan shift register, and the decoder 112 can also read the bit signal Q from the memory circuit 1A. The read bit signal Q is output via the cascode-connected shift register 111.

[0208] Figure 21 shows an example of a schematic configuration of a control circuit 110 for a memory circuit 1. Multiple memory circuits 1 are connected in a cascode configuration.

[0209] The bit values ​​that define the logic configuration of the programmable logic circuit 9 are sequentially transferred from the first-stage memory circuit 1 to the subsequent-stage memory circuit 1 of the multiple cascode-connected memory circuits 1, and stored in the corresponding memory circuits 1. That is, multiple bit signals D corresponding to the multiple memory circuits 1 are input sequentially from the first-stage memory circuit 1. The input bit signals D are sequentially transferred from the first-stage memory circuit 1 to the subsequent-stage memory circuits 1 and held by the corresponding memory circuits 1. Through a store operation, the bit values ​​indicated by the bit signals D are stored in the memory circuit 1.

[0210] The bit signal Q can also be read from memory circuit 1. The read bit signal Q is output via memory circuit 1, which is connected in cascode.

[0211] A configuration similar to that shown in Figure 21 can also be applied to the memory circuit 1A (NV latch circuit). This will be explained with reference to Figure 22.

[0212] Figure 22 shows an example of the schematic configuration of a control circuit 110 for memory circuit 1A. Multiple memory circuits 1A are connected in a cascode configuration. Gate signals G are supplied in opposite directions to adjacent memory circuits 1A in the cascode configuration. That is, the gate signal G supplied to one memory circuit 1A and the gate signal G supplied to the other memory circuit 1A are inverted signals of each other.

[0213] The bit values ​​that define the logic configuration of the programmable logic circuit 9 are sequentially transferred from the first-stage memory circuit 1A to the subsequent-stage memory circuit 1A of the multiple cascode-connected memory circuits 1A, and stored in the corresponding memory circuits 1A. That is, multiple bit signals D corresponding to the multiple memory circuits 1A are input sequentially from the first-stage memory circuit 1A. The input bit signals D are sequentially transferred from the first-stage memory circuit 1A to the subsequent-stage memory circuits 1A and held by the corresponding memory circuits 1A. Through a store operation, the bit values ​​indicated by the bit signals D are stored in the memory circuits 1A.

[0214] The bit signal Q can also be read from the memory circuit 1A. The read bit signal Q is output via the cascode-connected memory circuit 1A.

[0215] 4. The technologies described above can be identified, for example, as follows: One of the disclosed technologies is a memory circuit 1, 1A. As described with reference to Figures 1 to 11, Figure 13 and Figure 14, the memory circuits 1, 1A include a latch circuit 3 including nodes N31 and N32 for holding bit signals, a magnetoresistive element 7, a store driver circuit 4 connected between the latch circuit 3 and the magnetoresistive element 7, a restore driver circuit 6 connected between the latch circuit 3 and the magnetoresistive element 7, a control line L8 connected to the magnetoresistive element 7 on the opposite side of the magnetoresistive element 7 from the store driver circuit 4 and the restore driver circuit 6, and a control driver circuit 8 for controlling the voltage of the control line L8. The store driver circuit 4 includes cascode-connected transistors 41 (first transistor) and 42 (second transistor). The gates of transistors 41 and 42 of the store driver circuit 4 are connected to nodes N31 and N32 of the latch circuit 3. The cascode connection point of transistors 41 and 42 of the store driver circuit 4 is connected to the magnetoresistive element 7. The current terminals of transistors 41 and 42 of the store driver circuit 4 are directly connected to the power supply voltage VDD or the reference voltage GND.

[0216] According to the memory circuits 1 and 1A described above, transistor 41 or transistor 42 of the store driver circuit 4 is directly connected to the power supply voltage VDD or the reference voltage GND. Compared to a configuration in which other transistors are connected between the store driver circuit and each of the two voltages, as in Patent Document 1, the circuit configuration is simplified. This makes it possible to suppress circuit area and leakage current.

[0217] As explained with reference to Figures 1 to 11, 13 and 14, the memory circuits 1 and 1A may include a switch transistor 5 connected between the current terminal of transistor 41 or transistor 42 of the store driver circuit 4 and the power supply voltage VDD or reference voltage GND. The switch transistor 5 may be a header-type switch transistor or a footer-type switch transistor. In the case of a header-type switch transistor, as explained with reference to Figures 1, 2, 5, 6, 9 to 11, 13 and 14, the switch transistor 5 is connected between transistor 41 of the store driver circuit 4 and the power supply voltage VDD, and the current terminal of transistor 42 of the store driver circuit 4 may be directly connected to the reference voltage. In the case of a footer-type switch transistor, as explained with reference to Figures 3, 4, 7, 8 and 13, the switch transistor 5 is connected between transistor 42 of the store driver circuit 4 and the reference voltage GND, and the current terminal of transistor 41 of the store driver circuit 4 may be directly connected to the power supply voltage VDD. For example, with this configuration, transistor 41 or transistor 42 of the store driver circuit 4 can be directly connected to the power supply voltage VDD or the reference voltage GND.

[0218] As explained with reference to Figures 1 to 10, the memory circuit 1 includes a terminal T1 (input terminal) to which a bit signal D is input, an inverter 11 (input-side inverter) that inverts and outputs the signal from terminal T1, a transmission gate 12 (first input-side transmission gate) that transmits the signal from inverter 11 when it is ON, a latch circuit 2 (master latch circuit) including nodes N21 and N22 for holding the signal from transmission gate 12, a transmission gate 13 (second input-side transmission gate) that transmits the signal from node N22 of latch circuit 2 when it is ON, and the signal from transmission gate 13 The memory circuit 1 includes a latch circuit 3 (slave latch circuit) with nodes N31 and N32 for holding, an inverter 14 (output inverter) that inverts and outputs the signal from node N32 of the latch circuit 3, and a terminal T2 (output terminal) that outputs the signal from the inverter 14. The inverter 11, transmission gate 12, latch circuit 2, transmission gate 13, latch circuit 3, and inverter 14 are connected between terminal T1 and terminal T2 in this order, and both transmission gate 12 and transmission gate 13 may be switched on and off in accordance with the rising and falling edges of the clock signal CK. For example, in a memory circuit 1 which is such an NVFF circuit, the circuit area and leakage current can be suppressed.

[0219] As explained with reference to Figures 11, 13, and 14, the memory circuit 1A includes a terminal T1 (input terminal) to which a bit signal Q is input, an inverter 11 (input-side inverter) that inverts and outputs the signal from terminal T1, a transmission gate 13 (input-side transmission gate) that, when on, transmits the signal from inverter 11 to nodes N31 and N32 of the latch circuit 3, an inverter 14 (output-side inverter) that inverts and outputs the signals from nodes N31 and N32 of the latch circuit 3, and a terminal T2 (output terminal) that outputs the signal from inverter 14 (output-side inverter). The inverter 11, transmission gate 13, latch circuit 3, and inverter 14 are connected between terminal T1 and terminal T2 in this order, and the transmission gate 13 may be switched on and off according to the gate signal G. For example, even in a memory circuit 1A which is an NV latch circuit like this, the circuit area and leakage current can be suppressed.

[0220] As explained with reference to Figures 1 to 11, 13 and 14, the memory circuits 1 and 1A do not need to have a verification function. The absence of a verification circuit further simplifies the circuit configuration. Circuit area and leakage current can be further reduced.

[0221] As explained with reference to Figures 15 to 22, the memory circuits 1 and 1A are one of a plurality of memory circuits 1 and 1A, and the plurality of memory circuits 1 and 1A may store bit values ​​(configurations) that define the logic configuration of the programmable logic circuit 9. The logic configuration of the programmable logic circuit 9 can be made NV (Non-Variable). Reconfiguration after turning the power off and on is not required. Since the store frequency is low and the restore frequency is high, the features of the memory circuits 1 and 1A, which are specialized for restoration, can be effectively utilized.

[0222] As explained with reference to Figure 15, the multiple memory circuits 1, 1A may be LUTs (lookup tables) that define the logic configuration of the programmable logic circuit 9. For example, the memory circuits 1, 1A can be applied to the programmable logic circuit 9 in this manner.

[0223] As explained with reference to Figures 16 to 18, the programmable logic circuit 9, upon receiving input bit signals IN-1 (first input bit signal), IN-2 (second input bit signal), IN-3 (third input bit signal), and IN-4 (fourth input bit signal), outputs output bit signals OUT-1 (first output bit signal), OUT-2 (second output bit signal), and OUT-3 (third output bit signal). The programmable logic circuit 9 then outputs output bit signal OUT-1. The memory circuit 1 (which may also be memory circuit 1A) includes a programmable AND circuit 92-1 (first programmable AND circuit), a programmable AND circuit 92-2 (second programmable AND circuit) that outputs an output bit signal OUT-2, and a programmable AND circuit 92-3 (third programmable AND circuit) that outputs a programmable AND circuit 92-3 (third output bit signal), and the memory circuit 1 (which may also be memory circuit 1A) includes memory circuits 1-1, 1A-1 (first memory circuit) that output a bit signal Q1 (first bit signal), and memory circuits that output a bit signal Q2 (second bit signal) Memory circuits 1-2, 1A-2 (second memory circuit), memory circuits 1-3, 1A-3 (third memory circuit) that output bit signal Q-3, memory circuits 1-4, 1A-4 (fourth memory circuit) that output bit signal Q-4 (fourth bit signal), memory circuits 1-5, 1A-5 (fifth memory circuit) that output bit signal Q-5, memory circuits 1-6, 1A-6 (sixth memory circuit) that output bit signal Q-6, memory circuits 1-7, 1A-7 (seventh memory circuit) that output bit signal Q-7 (seventh bit signal), and memory circuit that outputs bit signal Q-8 (eighth bit signal) The programmable AND circuit 92-1 includes 1-8 (the eighth memory circuit), and receives input bit signal IN-1, bit signal Q-1 from memory circuits 1-1 and 1A-1, and bit signal Q-2 from memory circuits 1-2 and 1A-2 as inputs. Furthermore, depending on the bit signal Q-7 from memory circuits 1-7 and 1A-7, input bit signal IN-2 or output bit signal OUT-2 from the programmable AND circuit 92-2 is input. The programmable AND circuit 92-2 receives bit signal Q-3 from memory circuits 1-3 and 1A-3, and bit signal Q-4 from memory circuits 1-4 and 1A-4 as inputs.Furthermore, depending on the bit signal Q-7 of memory circuits 1-7 and 1A-7, the input bit signal IN-2 or the output bit signal OUT-1 of programmable AND circuit 92-1 may be input. Additionally, depending on the bit signal Q-8 of memory circuits 1-8 and 1A-8, the input bit signal IN-3 or the bit signal Q-3 of programmable AND circuit 92-3 may be input. The programmable AND circuit 92-3 receives the input bit signal IN-4, the bit signal Q-5 of memory circuits 1-5 and 1A-5, and the bit signal Q-6 of memory circuits 1-6 and 1A-6. Furthermore, depending on the bit signal Q-8 of memory circuits 1-8 and 1A-8, the input bit signal IN-3 or the output bit signal OUT-2 of programmable AND circuit 92-2 may be input. In that case, as shown in Figure 17, each programmable AND circuit 92 is a circuit with two inputs, x and y. When the two bit values ​​indicated by the two bit signals Q of the two memory circuits 1 are both "0", it outputs an output bit signal OUT indicating the logical AND value of x and y. When one of the two bit values ​​is "0" and the other is "1", it outputs an output bit signal OUT indicating the inverted value of the logical AND of x and y. When one of the two bit values ​​is "1" and the other is "0", it outputs an output bit signal OUT indicating the logical AND value of x and the inverted value of y. When both bit values ​​are "1", it may output an output bit signal OUT indicating the further inverted value of the logical AND of x and the inverted value of y. As an example of the configuration, as shown in Figure 17, the programmable AND circuit 92 includes an XOR gate 921 (first XOR gate), an AND gate 922, and an XOR gate 923 (second XOR gate). One input terminal of the XOR gate 921 receives the corresponding input bit signal IN or the output bit signal OUT of the corresponding other programmable AND circuit 92, and the other input terminal receives the bit signal Q of the corresponding memory circuits 1, 1A. One input terminal of the AND gate 922 receives the corresponding input bit signal IN, and the other input terminal receives the output signal of the XOR gate 921. One input terminal of the AND gate 922 receives the output signal of the AND gate 922, and the other input terminal receives the corresponding memory circuit 1,A bit signal Q of 1A may be input. For example, memory circuits 1 and 1A can also be applied to such a 4-input, 3-output programmable logic circuit 9.

[0224] Bit values ​​can be written to memory circuits 1 and 1A using various methods. For example, as explained with reference to Figure 20, the bit values ​​that define the logic configuration of the programmable logic circuit 9 may be written to the corresponding memory circuit 1A (NV latch circuit) via the shift register 111 and decoder 112. As explained with reference to Figure 21, the multiple memory circuits 1 (NVFF circuits) are connected in cascode, and the bit values ​​that define the logic configuration of the programmable logic circuit 9 may be transferred sequentially from the first memory circuit 1 to the subsequent memory circuits 1 of the multiple cascode-connected memory circuits 1 and written to the corresponding memory circuits 1. As explained with reference to Figure 22, the multiple memory circuits 1A are connected in a cascode configuration, and gate signals G are supplied in opposite directions to adjacent memory circuits 1A among the multiple cascode-connected memory circuits 1A. The bit values ​​that define the logic configuration of the programmable logic circuit 9 are transferred sequentially from the first-stage memory circuit 1A to the subsequent-stage memory circuits 1A of the multiple cascode-connected memory circuits 1A, and may be written to the corresponding memory circuits 1A.

[0225] The effects described in this disclosure are merely illustrative and not limited to those disclosed. Other effects may also occur.

[0226] 5. Examples of Control Circuits Further applications are possible for writing bit values ​​to the memory circuit 1A using the control circuit 110 described above. These will be explained with reference to Figures 23 to 34.

[0227] Figure 23 shows an example of a control circuit 110 and a memory circuit 1A. As previously mentioned, the bit signal D, i.e., the bit value, from the control circuit 110 is input to the first-stage memory circuit 1A, and then sequentially transferred to the subsequent memory circuits 1, where they are held. Among the multiple memory circuits 1A, the odd-numbered memory circuits 1A from the control circuit 110 are referred to as memory circuits 1Ao and are shown in the figure. The even-numbered memory circuits 1A are referred to as memory circuits 1Ae and are shown in the figure.

[0228] The gate signal G supplied to memory circuit 1Ao is referred to as gate signal Go. The gate signal G supplied to memory circuit 1Ae is referred to as gate signal Ge. Gate signals Go and Ge can be controlled independently of each other. The controlling entity for gate signals Go and Ge is not particularly limited, but in the example shown in Figure 23, it is the control circuit 110. The control circuit 110 can also control the store operation, restore operation, etc., of each memory circuit 1A. In the following, unless otherwise distinguished, memory circuits 1Ao and 1Ae will simply be referred to as memory circuit 1A.

[0229] Here, as explained earlier in Figure 11, if the memory circuit 1A does not have a transmission gate on the terminal T2 side, then two adjacent memory circuits 1A among the multiple cascode-connected memory circuits 1A will hold the same bit value. This will be explained with reference to Figures 24 to 29.

[0230] Figures 24 to 29 show examples of bit values ​​held by memory circuit 1A. Bit signals D, representing bit values ​​b1, b2, and b3, are sequentially input to the first-stage memory circuit 1A (memory circuit 1Ao) and transferred to subsequent memory circuits 1A. The bit values ​​b1, b2, and b3 held by each memory circuit 1A are also shown. The on and off states of gate signals Go and Ge represent the on and off states of the transmission gate 13 (Figure 11, etc.) of memory circuit 1A.

[0231] As shown in Figure 24, the control circuit 110 turns on the gate signal Go and off the gate signal Ge. The control circuit 110 also inputs a bit signal D, which represents the bit value b1, to the first-stage memory circuit 1A. The first-stage memory circuit 1A holds the bit signal D from the control circuit 110, i.e., the bit value b1.

[0232] As shown in Figure 25, the control circuit 110 turns off both gate signals Go and Ge. The control circuit 110 also inputs a bit signal D, which represents the bit value b2, to the first-stage memory circuit 1A. The bit values ​​held by each memory circuit 1Ao remain unchanged.

[0233] As shown in Figure 26, the control circuit 110 turns off the gate signal Go and turns on the gate signal Ge. The bit value b1 held by the first-stage memory circuit 1A is transferred to and held by the second-stage memory circuit 1A (memory circuit 1Ae). However, the first-stage memory circuit 1A also continues to hold the bit value b1.

[0234] As shown in Figure 27, the control circuit 110 turns on the gate signal Go and off the gate signal Ge. The first-stage memory circuit 1A holds the bit signal D from the control circuit 110, i.e., the bit value b2. The bit value b1 held by the second-stage memory circuit 1A is transferred to and held by the third-stage memory circuit 1A (memory circuit 1Ao). However, the second-stage memory circuit 1A also continues to hold the bit value b1.

[0235] As shown in Figure 28, the control circuit 110 turns off both gate signals Go and Ge. The control circuit 110 also inputs a bit signal D, which represents the bit value b3, to the first-stage memory circuit 1A (memory circuit 1Ao). The bit values ​​held by each memory circuit 1A remain unchanged.

[0236] As shown in Figure 29, the control circuit 110 turns off the gate signal Go and turns on the gate signal Ge. The bit value b2 held by the first-stage memory circuit 1A is transferred to and held by the second-stage memory circuit 1A. However, the first-stage memory circuit 1A also continues to hold the bit value b2. The bit value b1 held by the third-stage memory circuit 1A is transferred to and held by the fourth-stage memory circuit 1A. However, the third-stage memory circuit 1A also continues to hold the bit value b1.

[0237] The same control is performed repeatedly. As a result, two adjacent memory circuits 1A, namely adjacent memory circuits 1Ao and 1Ae, will each hold the same bit values. More specifically, the following explanation will use the example of having multiple memory circuits 1A hold bit values ​​b1 to b7.

[0238] Figure 30 shows an example of bit values ​​held by memory circuit 1A. The bit values ​​to be written to the first to seventh memory circuits 1A from the downstream side of the multiple memory circuits 1A are referred to as bit values ​​b1 to b7. The figure also shows the bit values ​​b1 to b7 held by each memory circuit 1A.

[0239] In this example, bit signals D, representing bit values ​​b1 to b7, are sequentially input to the first-stage memory circuit 1A and transferred to the subsequent memory circuits 1A. In this case, as shown in Figure 30, six memory circuit pairs (pairs of memory circuits 1Ao and 1Ae) hold bit values ​​b1 to b6, and one memory circuit 1Ao holds bit value b7. The original objective of having the first to seventh memory circuits 1A hold and write bit values ​​b1 to b7 from the subsequent side cannot be achieved immediately. It is necessary to devise a way to control the write operation by the control circuit 110.

[0240] Therefore, the control circuit 110 divides the bit signal D into two types of bit signals D: bit signals D indicating odd-numbered bit values ​​and bit signals D indicating even-numbered bit values. The control circuit 110 transfers and holds the bit signals D indicating odd-numbered bit values ​​to multiple memory circuits 1A, and then performs a store operation on the odd-numbered memory circuits 1A. The control circuit 110 also transfers and holds the bit signals D indicating even-numbered bit values ​​to multiple memory circuits 1A, and then performs a store operation on the even-numbered memory circuits 1A. Finally, the control circuit 110 performs a restore operation on all memory circuits 1A. This will be explained with reference to Figures 31 to 34.

[0241] Figures 31 to 34 show examples of write control. Similar to Figure 30 described above, bit values ​​b1 to b7 are the bit values ​​to be written to the first to seventh memory circuits 1A from the downstream side. Figure 31 shows a flowchart illustrating the write control (writing method). Figures 32 to 34 show the bit values ​​held by each memory circuit 1A.

[0242] <Bit Value Division> In step S1 of Figure 31, the multiple bit values ​​to be written to the multiple memory circuits 1A are divided into odd-numbered bit values ​​and even-numbered bit values. Here, as described above, the multiple bits are bit values ​​b1 to b7, so they are divided into bit values ​​b1, b3, b5 and b7, and bit values ​​b2, b4 and b6.

[0243] <First Write (Store)> In step S2 of Figure 31, bit signals D indicating odd-numbered bit values ​​are transferred. In step S3, odd-numbered memory circuits 1A (memory circuit 1Ao) perform a store operation. Specifically, as shown in Figure 30, the control circuit 110 sequentially inputs bit signals D indicating odd-numbered bit values, i.e., bit values ​​b1, b3, b5, and b7, to the first-stage memory circuit 1A. These bit values ​​are sequentially transferred to and held in subsequent memory circuits 1A.

[0244] The first and second memory circuits 1A from the downstream side hold bit value b1. The third and fourth memory circuits 1A hold bit value b3. The fifth and sixth memory circuits 1A hold bit value b5. The seventh memory circuit 1A holds bit value b7. In this state, the bit values ​​held by the odd-numbered memory circuits 1A (i.e., memory circuits 1Ao) are written. The first, third, fifth, and seventh memory circuits 1A from the downstream side hold and store bit values ​​b1, b3, b5, and b7.

[0245] <Second Write (Store)> In step S4 of Figure 31, bit signals D indicating even-numbered bit values ​​are transferred. In step S5, even-numbered memory circuits 1A (memory circuit 1Ae) perform a store operation. Specifically, as shown in Figure 33, the control circuit 110 inputs bit signals D indicating even-numbered bit values, i.e., bit values ​​b2, b4, and b6, to the first-stage memory circuit 1A. These bit values ​​are sequentially transferred to and held in the subsequent memory circuits 1A.

[0246] The second and third memory circuits 1A from the downstream side hold the bit value b2. The fourth and fifth memory circuits 1A hold the bit value b4. The sixth and seventh memory circuits 1A hold the bit value b6. In this state, the bit values ​​held by the even-numbered memory circuits 1A (i.e., memory circuits 1Ae) are written. The second, fourth and sixth memory circuits 1A from the downstream side now hold and store the bit values ​​b2, b4, and b6.

[0247] Through the two-stage writing process described above, bit values ​​b1 to b7 can be written to the first to seventh memory circuits 1A from the downstream side.

[0248] <Read (Restore)> In step S6 of Figure 31, all memory circuits 1A perform a restore operation. The bit values ​​written by the store operations in steps S3 and S5 are read out and held. Specifically, as shown in Figure 34, the first memory circuit 1A from the downstream side holds the bit value b1. The second memory circuit 1A holds the bit value b2. The third memory circuit 1A holds the bit value b3. The fourth memory circuit 1A holds the bit value b4. The fifth memory circuit 1A holds the bit value b5. The sixth memory circuit 1A holds the bit value b6. The seventh memory circuit 1A holds the bit value b7. The first to seventh memory circuits 1A from the downstream side hold the bit values ​​b1 to b7, thereby defining the logic configuration of the programmable logic circuit 9 (Figure 22, etc.).

[0249] In the above explanation, the example given was that in the first write operation, the odd-numbered bit values ​​are written to the odd-numbered memory circuits 1A. However, in the first write operation, the even-numbered bit values ​​may also be written to the even-numbered memory circuits 1A. In that case, in the second write operation, the odd-numbered bit values ​​will be written to the odd-numbered memory circuits 1A.

[0250] While embodiments of this disclosure have been described above, the technical scope of this disclosure is not limited to the embodiments described above, and various modifications are possible without departing from the spirit of this disclosure. Furthermore, components from different embodiments and modifications may be combined as appropriate.

[0251] Furthermore, this technology can also take the following configuration: (1) A memory circuit comprising: a latch circuit including a node for holding bit signals; a magnetoresistive element; a store driver circuit connected between the latch circuit and the magnetoresistive element; a restore driver circuit connected between the latch circuit and the magnetoresistive element; a control line connected to the magnetoresistive element on the opposite side of the magnetoresistive element from the store driver circuit and the restore driver circuit; and a control driver circuit for controlling the voltage of the control line, wherein the store driver circuit includes a cascode-connected first transistor and a second transistor, the gates of the first transistor and the second transistor of the store driver circuit are connected to the node of the latch circuit, the cascode connection points of the first transistor and the second transistor of the store driver circuit are connected to the magnetoresistive element, and the current terminals of the first transistor or the second transistor of the store driver circuit are directly connected to a power supply voltage or a reference voltage. (2) The memory circuit according to (1), further comprising a switch transistor connected between the current terminal of the first transistor or the second transistor of the store driver circuit and the power supply voltage or the reference voltage. (3) The memory circuit according to (2), wherein the switch transistor is connected between the first transistor of the store driver circuit and the power supply voltage, and the current terminal of the second transistor of the store driver circuit is directly connected to the reference voltage. (4) The memory circuit according to (2), wherein the switch transistor is connected between the second transistor of the store driver circuit and the reference voltage, and the current terminal of the first transistor of the store driver circuit is directly connected to the power supply voltage. (5) The memory circuit includes an input terminal to which a bit signal is input, an input-side inverter that inverts and outputs the signal from the input terminal, a first input-side transmission gate that transmits the signal from the input-side inverter when it is ON, and a master latch circuit including a node for holding the signal from the first input-side transmission gate.A memory circuit according to any one of (1) to (4), comprising: a second input-side transmission gate that transmits a signal from the node of the master latch circuit when it is ON; a slave latch circuit including a node for holding the signal from the second input-side transmission gate; an output-side inverter that inverts and outputs the signal from the node of the slave latch circuit; and an output terminal that outputs a signal from the output-side inverter, wherein the latch circuit is the slave latch circuit, and the input-side inverter, the first input-side transmission gate, the master latch circuit, the second input-side transmission gate, the slave latch circuit, and the output-side inverter are connected in this order between the input terminal and the output terminal, and both the first input-side transmission gate and the second input-side transmission gate switch on and off according to the rising and falling edges of the clock signal. (6) A memory circuit according to any one of (1) to (4), comprising: an input terminal into which a bit signal is input; an input-side inverter that inverts and outputs the signal from the input terminal; an input-side transmission gate that, when on, transmits the signal from the input-side inverter to the node of the latch circuit; an output-side inverter that inverts and outputs the signal from the node of the latch circuit; and an output terminal that outputs the signal from the output-side inverter, wherein the input-side inverter, the input-side transmission gate, the latch circuit, and the output-side inverter are connected in this order between the input terminal and the output terminal, and the input-side transmission gate switches on and off according to the gate signal. (7) A memory circuit according to any one of (1) to (6), which does not have a verify function. (8) A memory circuit according to any one of (1) to (7), wherein the memory circuit is one of a plurality of memory circuits, and the plurality of memory circuits store bit values ​​that define the logic configuration of a programmable logic circuit. (9) The memory circuit described in (8), wherein the plurality of memory circuits are lookup tables that define the logic configuration of the programmable logic circuit. (10)The programmable logic circuit outputs a first output bit signal, a second output bit signal, and a third output bit signal when it receives a first input bit signal, a second input bit signal, a third input bit signal, and a fourth input bit signal. The programmable logic circuit includes a first programmable AND circuit that outputs the first output bit signal, a second programmable AND circuit that outputs the second output bit signal, and a third programmable AND circuit that outputs the third output bit signal. The plurality of memory circuits include a first memory circuit that outputs the first bit signal, a second memory circuit that outputs the second bit signal, a third memory circuit that outputs the third bit signal, a fourth memory circuit that outputs the fourth bit signal, a fifth memory circuit that outputs the fifth bit signal, a sixth memory circuit that outputs the sixth bit signal, a seventh memory circuit that outputs the seventh bit signal, and an eighth memory circuit that outputs the eighth bit signal. The first programmable AND circuit receives the first input bit signal, the first bit signal of the first memory circuit, and the second bit signal of the second memory circuit as inputs, and further, selectively depending on the seventh bit signal of the seventh memory circuit, it receives the second input bit signal or the second output bit signal of the second programmable AND circuit as inputs, the second programmable AND circuit receives the third bit signal of the third memory circuit and the fourth bit signal of the fourth memory circuit as inputs, and further, selectively depending on the seventh bit signal of the seventh memory circuit, it receives the second input bit signal or the first output bit signal of the first programmable AND circuit as inputs, and further, selectively depending on the eighth bit signal of the eighth memory circuit, it receives the third input bit signal or the third output bit signal of the third programmable AND circuit as inputs,The memory circuit according to (8), wherein the third programmable AND circuit receives the fourth input bit signal, the fifth bit signal of the fifth memory circuit, and the sixth bit signal of the sixth memory circuit, and further, depending on the eighth bit signal of the eighth memory circuit, the third input bit signal or the second output bit signal of the second programmable AND circuit is input. (11) The memory circuit according to claim 10, wherein each of the first programmable AND circuit, the second programmable AND circuit, and the third programmable AND circuit is a circuit with two inputs, x and y, and outputs an output bit signal indicating the logical AND value of x and y when both bit values ​​indicated by the two bit signals of the two memory circuits are "0", outputs an output bit signal indicating the inverted value of the logical AND of x and y when one of the two bit values ​​is "0" and the other is "1", outputs an output bit signal indicating the logical AND value of x and the inverted value of y, and outputs an output bit signal indicating the inverted value of the logical AND of x and the inverted value of y when both of the two bit values ​​are "1". (12) The memory circuit according to (10) or (11), wherein each of the first programmable AND circuit, the second programmable AND circuit and the third programmable AND circuit includes a first XOR gate, an AND gate, and a second XOR gate, wherein one input terminal of the first XOR gate is input to a corresponding input bit signal or the output bit signal of the corresponding other programmable AND circuit, and the other input terminal is input to a corresponding memory circuit, the one input terminal of the AND gate is input to a corresponding input bit signal, and the other input terminal is input to the output signal of the first XOR gate, and the one input terminal of the second XOR gate is input to the output signal of the AND gate, and the other input terminal is input to a corresponding memory circuit. (13) The memory circuit includes an input terminal to which a bit signal is input, and an input-side inverter that inverts and outputs the signal from the input terminal,A memory circuit according to any one of (8) to (12), comprising: an input-side transmission gate that transmits a signal from the input-side inverter to the node of the latch circuit when it is ON; an output-side inverter that inverts and outputs the signal from the node of the latch circuit; and an output terminal that outputs a signal from the output-side inverter, wherein the input-side inverter, the input-side transmission gate, the latch circuit, and the output-side inverter are connected in this order between the input terminal and the output terminal, the input-side transmission gate switches on and off according to the gate signal, and the bit value that defines the logic configuration of the programmable logic circuit is written to the corresponding memory circuit via a shift register and a decoder. (14) The memory circuit comprises: an input terminal into which a bit signal is input; an input-side inverter that inverts and outputs the signal from the input terminal; a first input-side transmission gate that transmits the signal from the input-side inverter when it is ON; a master latch circuit including a node for holding the signal from the first input-side transmission gate; a second input-side transmission gate that transmits the signal from the node of the master latch circuit when it is ON; a slave latch circuit including a node for holding the signal from the second input-side transmission gate; an output-side inverter that inverts and outputs the signal from the node of the slave latch circuit; and an output terminal that outputs the signal from the output-side inverter, wherein the latch circuit is the slave latch circuit, and the input-side inverter, the first input-side transmission gate, the master latch circuit, the second input-side transmission gate, the slave latch circuit, and the output-side inverter are connected between the input terminal and the output terminal in this order, and both the first input-side transmission gate and the second input-side transmission gate switch on and off in accordance with the rising and falling edges of the clock signal. The memory circuit described in any of (8) to (12), wherein the plurality of memory circuits are connected in cascode, and the bit values ​​defining the logic configuration of the programmable logic circuit are transferred sequentially from the first memory circuit to the subsequent memory circuits of the plurality of cascode-connected memory circuits and written to the corresponding memory circuits. (15)The memory circuit comprises: an input terminal into which a bit signal is input; an input-side inverter that inverts and outputs the signal from the input terminal; an input-side transmission gate that, when on, transmits the signal from the input-side inverter to the node of the latch circuit; an output-side inverter that inverts and outputs the signal from the node of the latch circuit; and an output terminal that outputs the signal from the output-side inverter, wherein the input-side inverter, the input-side transmission gate, the latch circuit, and the output-side inverter are connected in this order between the input terminal and the output terminal; the input-side transmission gate switches on and off according to a gate signal; the plurality of memory circuits are cascode-connected; the gate signals are supplied in opposite directions to adjacent memory circuits among the plurality of cascode-connected memory circuits; and the bit values ​​that define the logic configuration of the programmable logic circuit are transferred sequentially from the first-stage memory circuit to the subsequent-stage memory circuits of the plurality of cascode-connected memory circuits and written to the corresponding memory circuits, as described in any of (8) to (12). (16) The memory circuit comprises: an input terminal into which a bit signal is input; an input-side inverter that inverts and outputs the signal from the input terminal; an input-side transmission gate that, when on, transmits the signal from the input-side inverter to the node of the latch circuit; an output-side inverter that inverts and outputs the signal from the node of the latch circuit; and an output terminal that outputs the signal from the output-side inverter. The input-side inverter, the input-side transmission gate, the latch circuit, and the output-side inverter are connected between the input terminal and the output terminal in this order. The input-side transmission gate switches on and off according to the gate signal. The plurality of memory circuits are connected in cascode. A plurality of bit values ​​defining the logic configuration of the programmable logic circuit are written to the plurality of memory circuits. The writing of the plurality of bit values ​​to the plurality of memory circuits is:A memory circuit according to any one of (8) to (12), which includes: sequentially transferring one of the even-numbered bit values ​​and the odd-numbered bit values ​​from the plurality of bit values ​​from the first-stage memory circuit to the subsequent-stage memory circuit and writing it to one of the odd-numbered and even-numbered memory circuits among the plurality of memory circuits; and sequentially transferring the other bit value of the even-numbered and odd-numbered bit values ​​from the plurality of bit values ​​from the first-stage memory circuit to the subsequent-stage memory circuit and writing it to the other memory circuit of the odd-numbered and even-numbered memory circuits among the plurality of memory circuits. (17) The memory circuit according to (16), wherein the sequential transfer of the bit values ​​from the first-stage memory circuit to the subsequent-stage memory circuit includes turning on the gate signal to one of the odd-numbered and even-numbered memory circuits and turning off the gate signal to the other memory circuit, and turning off the gate signal to one of the odd-numbered and even-numbered memory circuits and turning on the gate signal to the other memory circuit. (18) The memory circuit according to (16) or (17), wherein the sequential transfer of the bit values ​​from the first-stage memory circuit to the subsequent-stage memory circuit includes turning on the gate signal to one of the odd-numbered and even-numbered memory circuits and turning off the gate signal to the other memory circuit, and turning off the gate signal to both of the odd-numbered and even-numbered memory circuits and turning off the gate signal to one of the odd-numbered and even-numbered memory circuits and turning on the gate signal to the other memory circuit. (19) A memory circuit according to any one of (16) to (18), further comprising reading one of the odd-numbered bit values ​​and the even-numbered bit values ​​that have been written to one of the odd-numbered bit values ​​and the even-numbered bit values. (20) One of the even-numbered bit values ​​and the odd-numbered bit values ​​among the plurality of bit values ​​is the odd-numbered bit value, and the other bit value is the even-numbered bit value,A memory circuit according to any one of (15) to (19), wherein one of the odd-numbered memory circuits and the even-numbered memory circuits among the plurality of memory circuits is the odd-numbered memory circuit, and the other memory circuit is the even-numbered memory circuit.

[0252] 1 Memory Circuit 1A Memory Circuit 11 Inverter 12 Transmission Gate 13 Transmission Gate 14 Inverter 15 Switch Transistor 16 NOR Gate 16a OR Gate 2 Latch Circuit 21 Inverter 22 NAND Gate 23 Transmission Gate 24 NAND Gate N21 Node N22 Node 3 Latch Circuit 31 NAND Gate 32 Inverter 32a Switch Transistor 33 Transmission Gate 34 Transistor 35 Inverter 36 NAND Gate 36a Switch Transistor 37 Inverter N31 Node N32 Node N33 Node 4 Store Driver Circuit 41 Transistor 42 Transistor N41 Node N42 Node 5 Switch Transistor 6 Restore Driver Circuit 61 Transistor 7 Magnetoresistive Element N7-1 Node N7-2 Node 8 Control driver circuit 81 Transistor 82 Transistor L8 Control line N81 Node N82 Node 9 Programmable logic circuit 91 Selector 92 Programmable AND circuit 921 XOR gate 922 AND gate 923 XOR gate 100 Circuit device 110 Control circuit 111 Shift register 112 Decoder CK Clock signal CKB Inverted clock signal CTRL Control signal D Bit signal G Gate signal GB Inverted gate signal Go Gate signal Ge Gate signal GND Reference voltage IN Input bit signal OUT Output bit signal PSL Power switch local signal Q Bit signal RSTR Restore signal SN Set signal STR Store signalSTRB Inverted Store Signal Sel Selection Signal T1 Terminal T2 Terminal VDD Power Supply Voltage

Claims

1. A memory circuit comprising: a latch circuit including a node for holding a bit signal; a magnetoresistive element; a store driver circuit connected between the latch circuit and the magnetoresistive element; a restore driver circuit connected between the latch circuit and the magnetoresistive element; a control line connected to the magnetoresistive element on the opposite side of the magnetoresistive element from the store driver circuit and the restore driver circuit; and a control driver circuit for controlling the voltage of the control line, wherein the store driver circuit includes a cascode-connected first transistor and a second transistor, the gates of the first transistor and the second transistor of the store driver circuit are connected to the node of the latch circuit, the cascode connection points of the first transistor and the second transistor of the store driver circuit are connected to the magnetoresistive element, and the current terminals of the first transistor or the second transistor of the store driver circuit are directly connected to a power supply voltage or a reference voltage.

2. The memory circuit according to claim 1, further comprising a switch transistor connected between the current terminal of the first transistor or the second transistor of the store driver circuit and the power supply voltage or the reference voltage.

3. The memory circuit according to claim 2, wherein the switch transistor is connected between the first transistor of the store driver circuit and the power supply voltage, and the current terminal of the second transistor of the store driver circuit is directly connected to the reference voltage.

4. The memory circuit according to claim 2, wherein the switch transistor is connected between the second transistor of the store driver circuit and the reference voltage, and the current terminal of the first transistor of the store driver circuit is directly connected to the power supply voltage.

5. A memory circuit according to claim 1, comprising: an input terminal into which a bit signal is input; an input-side inverter that inverts and outputs the signal from the input terminal; a first input-side transmission gate that, when on, transmits the signal from the input-side inverter; a master latch circuit including a node for holding the signal from the first input-side transmission gate; a second input-side transmission gate that, when on, transmits the signal from the node of the master latch circuit; a slave latch circuit including a node for holding the signal from the second input-side transmission gate; an output-side inverter that inverts and outputs the signal from the node of the slave latch circuit; and an output terminal that outputs the signal from the output-side inverter, wherein the latch circuit is the slave latch circuit, and the input-side inverter, the first input-side transmission gate, the master latch circuit, the second input-side transmission gate, the slave latch circuit, and the output-side inverter are connected in this order between the input terminal and the output terminal, and both the first input-side transmission gate and the second input-side transmission gate switch on and off according to the rising and falling edges of the clock signal.

6. A memory circuit according to claim 1, comprising: an input terminal into which a bit signal is input; an input-side inverter that inverts and outputs the signal from the input terminal; an input-side transmission gate that, when on, transmits the signal from the input-side inverter to the node of the latch circuit; an output-side inverter that inverts and outputs the signal from the node of the latch circuit; and an output terminal that outputs the signal from the output-side inverter, wherein the input-side inverter, the input-side transmission gate, the latch circuit, and the output-side inverter are connected in this order between the input terminal and the output terminal, and the input-side transmission gate switches on and off according to a gate signal.

7. The memory circuit according to claim 1, which does not have a verify function.

8. The memory circuit according to claim 1, wherein the memory circuit is one of a plurality of memory circuits, and the plurality of memory circuits store bit values ​​that define the logic configuration of a programmable logic circuit.

9. The memory circuit according to claim 8, wherein the plurality of memory circuits are lookup tables that define the logic configuration of the programmable logic circuit.

10. The programmable logic circuit outputs a first output bit signal, a second output bit signal, and a third output bit signal when a first input bit signal, a second input bit signal, a third input bit signal, and a fourth input bit signal are input to it, and the programmable logic circuit includes a first programmable AND circuit that outputs the first output bit signal, a second programmable AND circuit that outputs the second output bit signal, and a third programmable AND circuit that outputs the third output bit signal, and the plurality of memory circuits include a first memory circuit that outputs the first bit signal, a second memory circuit that outputs the second bit signal, a third memory circuit that outputs the third bit signal, a fourth memory circuit that outputs the fourth bit signal, a fifth memory circuit that outputs the fifth bit signal, a sixth memory circuit that outputs the sixth bit signal, a seventh memory circuit that outputs the seventh bit signal, and an eighth memory circuit that outputs the eighth bit signal, The first programmable AND circuit receives the first input bit signal, the first bit signal of the first memory circuit, and the second bit signal of the second memory circuit as inputs, and further, selectively depending on the seventh bit signal of the seventh memory circuit, it receives the second input bit signal or the second output bit signal of the second programmable AND circuit as inputs, the second programmable AND circuit receives the third bit signal of the third memory circuit and the fourth bit signal of the fourth memory circuit as inputs, and further, selectively depending on the seventh bit signal of the seventh memory circuit, it receives the second input bit signal or the first output bit signal of the first programmable AND circuit as inputs, and further, selectively depending on the eighth bit signal of the eighth memory circuit, it receives the third input bit signal or the third output bit signal of the third programmable AND circuit as inputs,The memory circuit according to claim 8, wherein the third programmable AND circuit receives the fourth input bit signal, the fifth bit signal of the fifth memory circuit, and the sixth bit signal of the sixth memory circuit, and further, depending on the eighth bit signal of the eighth memory circuit, the third input bit signal or the second output bit signal of the second programmable AND circuit is input.

11. The memory circuit according to claim 10, wherein each of the first programmable AND circuit, the second programmable AND circuit, and the third programmable AND circuit is a circuit with two inputs, x and y, and outputs an output bit signal indicating the logical AND value of x and y when both bit values ​​indicated by the two bit signals of the two memory circuits are "0", outputs an output bit signal indicating the inverted value of the logical AND of x and y when one of the two bit values ​​is "0" and the other is "1", outputs an output bit signal indicating the logical AND value of x and the inverted value of y, and outputs an output bit signal indicating the inverted value of the logical AND of x and the inverted value of y when both of the two bit values ​​are "1".

12. The memory circuit according to claim 10, wherein each of the first programmable AND circuit, the second programmable AND circuit, and the third programmable AND circuit includes a first XOR gate, an AND gate, and a second XOR gate, wherein one input terminal of the first XOR gate is input to a corresponding input bit signal or the output bit signal of the corresponding other programmable AND circuit, and the other input terminal is input to a corresponding memory circuit, the one input terminal of the AND gate is input to a corresponding input bit signal, and the other input terminal is input to the output signal of the first XOR gate, and the one input terminal of the second XOR gate is input to the output signal of the AND gate, and the other input terminal is input to a corresponding memory circuit.

13. The memory circuit comprises: an input terminal into which a bit signal is input; an input-side inverter that inverts and outputs the signal from the input terminal; an input-side transmission gate that, when on, transmits the signal from the input-side inverter to the node of the latch circuit; an output-side inverter that inverts and outputs the signal from the node of the latch circuit; and an output terminal that outputs the signal from the output-side inverter, wherein the input-side inverter, the input-side transmission gate, the latch circuit, and the output-side inverter are connected in this order between the input terminal and the output terminal; the input-side transmission gate switches on and off according to a gate signal; and the bit value defining the logic configuration of the programmable logic circuit is written to the corresponding memory circuit via a shift register and a decoder, as described in claim 8.

14. The memory circuit comprises: an input terminal into which a bit signal is input; an input-side inverter that inverts and outputs the signal from the input terminal; a first input-side transmission gate that transmits the signal from the input-side inverter when it is ON; a master latch circuit including a node for holding the signal from the first input-side transmission gate; a second input-side transmission gate that transmits the signal from the node of the master latch circuit when it is ON; a slave latch circuit including a node for holding the signal from the second input-side transmission gate; an output-side inverter that inverts and outputs the signal from the node of the slave latch circuit; and an output terminal that outputs the signal from the output-side inverter, wherein the latch circuit is the slave latch circuit, and the input-side inverter, the first input-side transmission gate, the master latch circuit, the second input-side transmission gate, the slave latch circuit, and the output-side inverter are connected in this order between the input terminal and the output terminal, and both the first input-side transmission gate and the second input-side transmission gate switch on and off according to the rising and falling edges of the clock signal, and the plurality of memory circuits are cascode connected. The memory circuit according to claim 8, wherein the bit values ​​defining the logic configuration of the programmable logic circuit are sequentially transferred from the first memory circuit to the subsequent memory circuits of the plurality of cascode-connected memory circuits and written to the corresponding memory circuits.

15. The memory circuit comprises: an input terminal into which a bit signal is input; an input-side inverter that inverts and outputs the signal from the input terminal; an input-side transmission gate that, when on, transmits the signal from the input-side inverter to the node of the latch circuit; an output-side inverter that inverts and outputs the signal from the node of the latch circuit; and an output terminal that outputs the signal from the output-side inverter, wherein the input-side inverter, the input-side transmission gate, the latch circuit, and the output-side inverter are connected in this order between the input terminal and the output terminal; the input-side transmission gate switches on and off according to a gate signal; the plurality of memory circuits are cascode-connected; the gate signals are supplied in opposite directions to adjacent memory circuits among the plurality of cascode-connected memory circuits; and the bit values ​​that define the logic configuration of the programmable logic circuit are transferred sequentially from the first-stage memory circuit to the subsequent-stage memory circuits of the plurality of cascode-connected memory circuits and written to the corresponding memory circuits, as described in claim 8.

16. The memory circuit comprises: an input terminal into which a bit signal is input; an input-side inverter that inverts and outputs the signal from the input terminal; an input-side transmission gate that, when on, transmits the signal from the input-side inverter to the node of the latch circuit; an output-side inverter that inverts and outputs the signal from the node of the latch circuit; and an output terminal that outputs the signal from the output-side inverter. The input-side inverter, the input-side transmission gate, the latch circuit, and the output-side inverter are connected in this order between the input terminal and the output terminal. The input-side transmission gate switches on and off according to the gate signal. The plurality of memory circuits are connected in cascode. A plurality of bit values ​​defining the logic configuration of the programmable logic circuit are written to the plurality of memory circuits. The writing of the plurality of bit values ​​to the plurality of memory circuits is performed as follows: A memory circuit according to claim 8, comprising: sequentially transferring one of the even-numbered bit values ​​and the odd-numbered bit values ​​from the plurality of bit values ​​from the first-stage memory circuit to the subsequent-stage memory circuit and writing it to one of the odd-numbered and even-numbered memory circuits among the plurality of memory circuits; and sequentially transferring the other bit value of the even-numbered and odd-numbered bit values ​​from the plurality of bit values ​​from the first-stage memory circuit to the subsequent-stage memory circuit and writing it to the other of the odd-numbered and even-numbered memory circuits among the plurality of memory circuits.

17. The memory circuit according to claim 16, wherein sequentially transferring the bit values ​​from the first-stage memory circuit to the subsequent-stage memory circuit includes turning on the gate signal to one of the odd-numbered and even-numbered memory circuits and turning off the gate signal to the other memory circuit, and turning off the gate signal to one of the odd-numbered and even-numbered memory circuits and turning on the gate signal to the other memory circuit.

18. The memory circuit according to claim 16, wherein sequentially transferring the bit values ​​from the first-stage memory circuit to the subsequent-stage memory circuit includes: turning on the gate signal to one of the odd-numbered and even-numbered memory circuits and turning off the gate signal to the other memory circuit; turning off the gate signal to both of the odd-numbered and even-numbered memory circuits; and turning off the gate signal to one of the odd-numbered and even-numbered memory circuits and turning on the gate signal to the other memory circuit.

19. The memory circuit according to claim 16, further comprising reading out the written bit value in the memory circuit.

20. The memory circuit according to claim 16, wherein one of the even-numbered bit values ​​and the odd-numbered bit values ​​among the plurality of bit values ​​is the odd-numbered bit value, and the other bit value is the even-numbered bit value, and one of the odd-numbered memory circuits and the even-numbered memory circuits among the plurality of memory circuits is the odd-numbered memory circuit, and the other memory circuit is the even-numbered memory circuit.

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