Back contact cell and photovoltaic module

Abstract

The present application relates to the technical field of photovoltaics, and discloses a back contact cell and a photovoltaic module. Field passivation is performed on a first region and an overlapping region by means of a doping layer, and the doping layer can form a favorable electric field consistent with the induction direction of a first doped silicon layer, thereby improving charge carrier collection efficiency of the first doped silicon layer. The back contact cell comprises a semiconductor substrate, a tunneling passivation layer, a first doped silicon layer, an intrinsic silicon layer, a second doped silicon layer, and a doping layer. The tunneling passivation layer and the first doped silicon layer are sequentially stacked on the first region and the overlapping region. The intrinsic silicon layer and the second doped silicon layer are sequentially stacked on a second region, and further extend onto a first interface passivation layer and the first doped silicon layer located in the overlapping region. The doping layer is disposed within the first region and the overlapping region of the semiconductor substrate. The doping concentration of a first doping element in the doping layer having the same conductivity type as the first doped silicon layer is greater than the doping concentration of a first doping element in the second region of the semiconductor substrate.

Description

Back contact batteries and photovoltaic modules Technical Field

[0001] This application relates to the field of photovoltaic technology, and more particularly to a back contact battery and a photovoltaic module. Background Technology

[0002] A solar cell is a device that converts sunlight into electrical energy. Specifically, when a solar cell is in operation, sunlight shines on the semiconductor pn junction, forming new electron-hole pairs. Under the influence of the built-in electric field of the pn junction, photogenerated holes flow to the p-region, and photogenerated electrons flow to the n-region. When the circuit is connected, an electric current is generated. Solar cells where both the positive and negative electrodes are located on the back side of the cell are called back-contact cells. Compared to double-sided contact solar cells, the front side of a back-contact cell has no metal electrodes to block the light, resulting in higher light utilization on the light-facing side. Therefore, back-contact cells have higher short-circuit current and photoelectric conversion efficiency, making them one of the current technological directions for achieving high-efficiency crystalline silicon solar cells.

[0003] However, the passivation effect on the back side of the existing back contact battery is poor, which is not conducive to improving the conversion efficiency of the back contact battery. Summary of the Invention

[0004] The purpose of this application is to provide a back contact cell and a photovoltaic module, which passivates the first region and the overlapping region of the semiconductor substrate through a doped layer, and the doped layer can form a favorable electric field consistent with the induced direction of the first doped semiconductor layer, thereby improving the carrier collection efficiency of the first doped semiconductor layer, reducing the carrier recombination rate, and improving the conversion efficiency of the back contact cell.

[0005] To achieve the above objectives, in a first aspect, this application provides a back-contact battery, comprising: a semiconductor substrate, a tunneling passivation layer, a first doped silicon layer, an intrinsic silicon layer, a second doped silicon layer, and a doped layer. The semiconductor substrate includes a first surface and a second surface facing each other. The first surface includes alternating first and second regions, and an overlapping region located between the first and second regions. Along the thickness direction of the semiconductor substrate, the tunneling passivation layer and the first doped silicon layer are sequentially stacked on the first region and the overlapping region. Along the thickness direction of the semiconductor substrate, the intrinsic silicon layer and the second doped silicon layer are sequentially stacked on the second region. Furthermore, the stacked intrinsic silicon layer and the second doped silicon layer extend from the second region to the tunneling passivation layer and the first doped silicon layer located in the overlapping region. The conductivity type of the second doped silicon layer is opposite to that of the first doped silicon layer. The doped layer is disposed in the first region and the overlapping region of the semiconductor substrate. The doping concentration of the first doping element in the doped layer, which has the same conductivity type as the first doped silicon layer, is greater than the doping concentration of the first doping element in the second region of the semiconductor substrate. Along the direction from the first surface to the second surface, the doping concentration of the second doping element, which has the same conductivity type as the second doped silicon layer, is the same in each part of the second region of the semiconductor substrate.

[0006] In the case of the above technical solution, the back contact battery provided in this application further includes a doped layer in the first region and the overlapping region of the semiconductor substrate. This doped layer contains a first dopant element with the same conductivity type as the first doped silicon layer, and the doping concentration of the first dopant element in the doped layer is greater than that in the second region of the semiconductor substrate. At this point, the doping concentration of the first dopant element in the doped layer is higher, and the conductivity type of the first dopant element is the same as that of the first doped silicon layer. Therefore, the doped layer can be used to passivate the first region and the overlapping region of the semiconductor substrate, improving the passivation effect. Furthermore, since the conductivity type of the first dopant element in the doped layer is the same as that of the first doped silicon layer, the doped layer can form a favorable electric field consistent with the induced direction of the first doped silicon layer. The presence of this favorable electric field can repel minority carriers and attract majority carriers on the surface of the first region and the overlapping region of the semiconductor substrate, improving the carrier collection efficiency of the first doped silicon layer, further reducing the carrier recombination rate, and thus improving the conversion efficiency of the back contact battery.

[0007] Furthermore, along the direction from the first surface to the second surface, the doping concentration of the second doping element with the same conductivity type as the second doped silicon layer is the same in each portion of the second region of the semiconductor substrate. In other words, there is no inward-expanding doped layer with the same conductivity type as the second doped silicon layer in the second region of the semiconductor substrate. This prevents the doped layer from making electrical contact with an inward-expanding doped layer with an opposite conductivity type, which could lead to excessively high carrier recombination rates and a high risk of leakage, ensuring high conversion efficiency for the back contact battery. Simultaneously, it also prevents the formation of an inward-expanding doped layer in parts of the second region covered by the second doped silicon layer, thus preventing lower doping concentrations in those areas and contributing to higher burn-out resistance for the back contact battery.

[0008] As one possible implementation, the second region includes a groove. Along the direction from the second surface to the first surface, the surface height of the portion of the second doped silicon layer located at the bottom of the groove on the side facing away from the semiconductor substrate is lower than the surface height of the doped layer on the side facing away from the tunneling passivation layer.

[0009] In the above technical solution, the second region includes a groove. The presence of this groove not only indicates that after patterning the tunneling passivation layer and the first doped silicon layer formed in one layer, the portions of both located in the second region have been completely removed, improving the yield of the back contact cell, but also, because the surface height of the portion of the second doped silicon layer located at the bottom of the groove away from the semiconductor substrate is less than the surface height of the doped layer away from the tunneling passivation layer, there are no structurally aligned portions of the doped layer and the second doped silicon layer along the thickness direction of the semiconductor substrate. In other words, the presence of the groove also allows the doped layer and the first doped silicon layer to be staggered from the second doped silicon layer, which has an opposite conductivity type, along the thickness direction of the semiconductor substrate, reducing the risk of leakage between the doped layer and the second doped silicon layer, and further improving the conversion efficiency of the back contact cell. In addition, it is understood that the portion of the second doped silicon layer located at the bottom of the trench is mainly used to collect and export charge carriers. Therefore, the surface height of the portion of the second doped silicon layer located at the bottom of the trench away from the semiconductor substrate is set to be less than the surface height of the doped layer away from the tunneling passivation layer. This also helps to prevent the first doping element in the doped layer, which has the opposite conductivity type to the second doped silicon layer, from diffusing into the second doped silicon layer, thus ensuring that the second doped silicon layer has a high charge carrier collection capability for the portion at the bottom of the trench.

[0010] As one possible implementation, the width of the doped layer is greater than or equal to the width of the first doped silicon layer along the width direction of the overlapping region. In this case, the doped layer has a larger formation range, which is beneficial to improving the field passivation effect of the doped layer and further reducing the carrier recombination rate on one side of the first surface of the semiconductor substrate.

[0011] As one possible implementation, along the width direction of the overlapping region, the difference between the width of the doped layer and the width of the first doped silicon layer is greater than 0 and less than or equal to 50 μm. In this case, the width of the doped layer is approximately the same as the width of the first doped silicon layer, ensuring that the first region and the overlapping region of the semiconductor substrate have a high carrier recombination rate under the passivation effect of the doped layer. Furthermore, it is understood that the overlapping region is adjacent to the second region, and the second doped silicon layer located in the second region is mainly used to collect and extract carriers, while the conductivity type of the first dopant element in the doped layer is opposite to that of the second doped silicon layer. Based on this, when the difference between the width of the doped layer and the width of the first doped silicon layer is within the above range, it can prevent a large width of the doped layer from causing a small distance between the edge of the doped layer and the edge of the second doped silicon layer, reducing the risk of leakage between the doped silicon and the second doped silicon layer.

[0012] As one possible implementation, the second region includes a groove. Along the width direction of the overlapping region, the sides of the groove have continuously distributed first and second sub-regions, with the second sub-region being close to the first region. The surface of the first sub-region is inclined relative to the surface of the first region, and the cross-sectional area of ​​the portion of the groove corresponding to the first sub-region gradually increases along the direction from the second surface to the first surface. The surface of the second sub-region is planar. Furthermore, the doped layer extends to the region of the semiconductor substrate corresponding to the second sub-region; or, the doped layer further extends to the region of the semiconductor substrate corresponding to both the second sub-region and the portion of the first sub-region close to the second sub-region.

[0013] With the above technical solution, when the depth of the groove is fixed, the surface of the first sub-region on the side of the groove is inclined relative to the surface of the first region, and the cross-sectional area of ​​the part of the groove corresponding to the first sub-region gradually increases along the direction from the second surface to the first surface. This is beneficial to increase the lateral spacing between the doped layer and the second doped silicon layer located on the bottom of the groove, so that the edge of the doped layer only extends from the overlapping area to the second sub-region of the semiconductor substrate and the part of the first sub-region near the second sub-region, and does not extend to the bottom surface of the groove, further reducing the leakage risk between the two.

[0014] As one possible implementation, the doping concentration of the first dopant element in the doped layer gradually increases along the direction from the second surface to the first surface. In this case, a high-low junction can be formed between different regions of the doped layer along the direction from the second surface to the first surface. The built-in electric field of the high-low junction is consistent with the induced direction of the first doped silicon layer, which can further improve the carrier collection efficiency of the first doped silicon layer, further reduce the carrier recombination rate, and help improve the conversion efficiency of the back contact cell.

[0015] As one possible implementation, the doping concentration of the first doped element within the first doped silicon layer is greater than that within the doped layer. In this case, the first doped silicon layer ensures a higher field passivation effect, improving its carrier collection capability. Furthermore, a high-low junction can be formed between the first doped silicon layer and the doped layer, with the built-in electric field direction of this high-low junction aligned with the induced direction of the first doped silicon layer, further enhancing its carrier collection capability.

[0016] As one possible implementation, the doping concentration of the first doped element on the side of the doped layer closest to the first doped silicon layer is less than or equal to the doping concentration of the first doped element within the first doped silicon layer. The beneficial principle in this case is similar to the beneficial principle described above where the doping concentration of the first doped element within the first doped silicon layer is greater than the doping concentration of the first doped element within the doped layer. Furthermore, this case facilitates the formation of a high-low junction between the first doped silicon layer and the doped layer. The presence of this high-low junction helps control the magnitude of the reverse leakage current, resulting in higher conversion efficiency for the back contact battery. Simultaneously, when the doping concentration of the first doped element on the side of the doped layer closest to the first doped silicon layer is less than or equal to the doping concentration of the first doped element within the first doped silicon layer, in actual manufacturing, the doped layer can be formed during the formation of the first doped silicon layer via an inward expansion method, eliminating the need for additional manufacturing processes to form the doped layer. This simplifies the manufacturing process of the back contact battery and improves its manufacturing efficiency.

[0017] As one possible implementation, the aforementioned back contact battery further includes a transparent conductive layer. The transparent conductive layer covers the side of the first doped silicon layer and the second doped silicon layer facing away from the semiconductor substrate. Insulating trenches are provided within the transparent conductive layer to disconnect the portions of the transparent conductive layer corresponding to the first and second regions from each other. The portion of the transparent conductive layer that has the same carrier transport conductivity type as the second doped silicon layer does not overlap with the doped layer along the thickness direction of the semiconductor substrate. In this case, the transparent conductive layer has good conductivity, which can improve carrier collection efficiency. Furthermore, the absence of overlap between the first transparent conductive layer and the doped layer along the thickness direction of the semiconductor substrate prevents the first transparent conductive layer from overlapping with the doped semiconductor layer doped with a first dopant element having the opposite conductivity type to the second doped silicon layer, thus preventing an increase in leakage risk and ensuring high electrical reliability of the back contact battery.

[0018] As one possible implementation, the doping depth of the doped layer along the thickness direction of the semiconductor substrate is greater than or equal to 1 nm and less than or equal to 300 nm.

[0019] When the above technical solution is adopted, the doping depth of the doped layer is within the aforementioned range, which helps to prevent poor field passivation capability due to a shallow doping depth. Furthermore, it also prevents a high Auger recombination rate in the semiconductor substrate due to a large doping depth, thus avoiding negative impacts on passivation and ensuring a low carrier recombination rate in the first region and overlapping region of the doped layer on the semiconductor substrate. If, during the actual manufacturing process, the first dopant element in the doped layer diffuses from the first doped silicon layer into the doped layer, then the doping depth within the aforementioned range also prevents a low doping concentration of the first dopant element in the first doped silicon layer due to a large doping depth, ensuring a high carrier collection efficiency in the first doped silicon layer.

[0020] As one possible implementation, the conductivity types of the first doped silicon layer and the doped layer are the same as those of the semiconductor substrate. The second region of the semiconductor substrate does not contain a second doping element. In this case, a high-low junction can be formed between each adjacent pair of the semiconductor substrate, the doped layer, and the first doped silicon layer. Under the built-in electric field of the high-low junction, the carrier collection efficiency of the first doped silicon layer can be further improved, thereby further enhancing the conversion efficiency of the back contact cell. Furthermore, the presence of a second doping element with a conductivity type opposite to that of the doped layer within the second region of the semiconductor substrate ensures that the doped layer will not make electrical contact with the inner doped layer with a conductivity type opposite to its own, thus preventing a high risk of leakage and ensuring a high conversion efficiency for the back contact cell.

[0021] As one possible implementation, the continuous first region, overlapping region, and second region are divided into a first sub-region, a second sub-region, and a third sub-region located between the first and second sub-regions. The first sub-region corresponds to the first region and the overlapping region, and the second and third sub-regions correspond to the second region. A doped layer is also disposed in the third sub-region, and the aforementioned second doped silicon layer extends to cover at least a portion of the doped layer. In the third sub-region, the second doped silicon layer is electrically connected to the doped layer. A first transparent conductive layer covers the second doped silicon layer located in the second sub-region, and the second doped silicon layer located in the third sub-region is covered by the first transparent conductive layer extending from the second sub-region.

[0022] In the above-described technical solution, the second doped silicon layer is not only disposed on the second sub-region but also extends to cover at least a portion of the doped layer. In the third sub-region, the second doped silicon layer not only passivates the semiconductor substrate, reducing the number of surface defects in the third sub-region and improving the conversion efficiency of the back contact battery, but also electrically connects to the doped layer, forming a built-in diode with a low reverse breakdown voltage. Furthermore, a first transparent conductive layer extending from the second sub-region covers the second doped silicon layer located in the third sub-region. Based on this, when the back contact battery is blocked, the leakage current can pass through the first doped silicon layer, the doped layer, and the second doped silicon layer, then through the first transparent conductive layer extending from the second sub-region to the portion above the doped layer, and finally be discharged through the electrode in partial contact with the second sub-region corresponding to the first transparent conductive layer, reducing the risk of hot spots on the back contact battery. As can be seen from the above, the leakage current needs to be conducted between the first doped silicon layer and the second doped silicon layer through the doped layer disposed within the semiconductor substrate. Compared to the transport of reverse leakage current through doped semiconductor layers, semiconductor substrates have stronger lateral conductivity. Therefore, the back contact battery provided in this application is more conducive to the transport of reverse leakage current when it is shaded, reducing the transmission loss of reverse leakage current and improving the burn-out resistance of the back contact battery. Furthermore, the leakage current needs to flow not only through the PN junction formed by the doped layers with opposite conductivity types and the second doped silicon layer, but also through the high-low junction formed by the doped layers with the same conductivity types and the first doped silicon layer. Compared to the scheme where the leakage current only flows through the PN junction, the back contact battery provided in this application, during the shading process, is more conducive to controlling the magnitude of the reverse leakage current under the action of the two electric fields of the PN junction and the high-low junction, reducing the carrier recombination loss of the back contact battery, balancing the hot spot risk and conversion efficiency of the back contact battery, and improving the working performance of the back contact battery.

[0023] As one possible implementation, the surface of the third sub-region is recessed into the semiconductor substrate relative to the surface of the first sub-region, and the recess depth relative to the surface of the first sub-region is less than the doping depth of the doped layer.

[0024] When the above technical solution is adopted, under the same conditions, when the surface of the third sub-region is also recessed into the semiconductor substrate relative to the surface of the first sub-region, it is beneficial to reduce the height difference between the surface of the third sub-region and the bottom surface of the groove, which is beneficial to the coating of the second doped silicon layer on the sidewall of the groove and the surface of the third sub-region, improves the electrical connection performance between the second doped silicon layer and the doped layer, further reduces the hot spot risk of the back contact battery, and also helps to improve the passivation effect of the second doped silicon layer on the sidewall of the groove and the surface of the third sub-region, thereby improving the conversion efficiency of the back contact battery. Furthermore, in the actual manufacturing process, if the doped layer is formed by inward expansion during the formation of the first doped silicon layer, the doping concentration of the first doped element at the surface of the third region is relatively high. As the doping depth increases, the doping concentration of the first doped element within the doped layer decreases. Therefore, when the surface of the third region is recessed into the semiconductor substrate relative to the surface of the first region, the doping concentration of the doped layer at the surface of the third region can be reduced, which helps to reduce the leakage current between the doped layer and the second doped silicon layer, further improving the conversion efficiency of the back contact battery. At the same time, the recess depth of the third region relative to the surface of the first region into the semiconductor substrate is less than the doping depth of the doped layer, which ensures that the doped layer can be electrically connected to the second doped silicon layer at the surface of the third region, resulting in a larger leakage contact area between the doped layer and the second doped silicon layer, which is beneficial for the back contact battery to have higher resistance to burn-out.

[0025] As one possible implementation, along the distribution direction of the alternating intervals of the first and second sub-regions, the width of the third sub-region is greater than or equal to 1 nm and less than or equal to 2 μm.

[0026] With the above technical solution, the width of the third sub-region affects the size of the leakage contact area between the doped layer and the second doped silicon layer. When the ratio between the width of the second doped silicon layer extending into the third sub-region and the width of the third sub-region is constant, a larger third sub-region results in a larger leakage contact area between the doped layer and the second doped silicon layer, leading to a lower hot spot risk for the back contact battery. Conversely, a smaller third sub-region results in a smaller leakage contact area between the doped layer and the second doped silicon layer, leading to higher conversion efficiency for the back contact battery. Therefore, by controlling the width of the third sub-region, the leakage contact area and leakage current of the doped layer and the second doped silicon layer can be adjusted, improving the applicability of the back contact battery in different application scenarios. This also facilitates a balanced control of conversion efficiency and hot spot risk, ultimately improving the performance of the back contact battery.

[0027] As one possible implementation, the doping concentration of the first doped element at the surface of the doped layer corresponding to the third sub-region is less than the doping concentration of the first doped element at the surface of the doped layer corresponding to the first sub-region.

[0028] By adopting the above technical solution, it is beneficial to reduce the conductivity at the surface of the third sub-region corresponding to the doped layer, and to control the leakage current between the doped layer and the second doped silicon layer, thereby improving the conversion efficiency of the back contact cell.

[0029] As one possible implementation, the doping concentration of the first dopant element in the doped layer is greater than or equal to 8 × 10⁻⁶. 9 / cm 3 And less than or equal to 9 × 10 20 / cm 3 When using the above technical solution, the doping concentration of the first dopant element within the doped layer affects the conductivity of the doped layer. It is understood that a lower doping concentration of the first dopant element results in relatively lower conductivity of the doped layer, leading to higher reverse leakage current transmission losses, but also higher conversion efficiency of the back-contact battery. Conversely, a higher doping concentration of the first dopant element results in relatively higher conductivity of the doped layer, which is beneficial for reverse leakage current transmission, and thus lowers the hot spot risk of the back-contact battery. Therefore, by controlling the doping concentration of the first dopant element within the doped layer, the leakage current of the doped layer and the corresponding doped silicon layer can be controlled, improving the applicability of the back-contact battery in different application scenarios. This also facilitates a balance between conversion efficiency and hot spot risk, thereby improving the overall performance of the back-contact battery.

[0030] Secondly, this application provides a photovoltaic module including a back contact cell provided in the first aspect and various implementations thereof.

[0031] The beneficial effects of the second aspect and its various implementations in this application can be found in the analysis of the beneficial effects of the first aspect and its various implementations, and will not be repeated here. Attached Figure Description

[0032] The accompanying drawings, which are included to provide a further understanding of this application and form part of this application, illustrate exemplary embodiments of this application and are used to explain this application, but do not constitute an undue limitation of this application. In the drawings:

[0033] Figure 1 is a schematic diagram of the structure of the back contact battery provided in an embodiment of this application;

[0034] Figure 2 is a schematic diagram of the structure of the back contact battery provided in an embodiment of this application;

[0035] Figure 3 is a schematic diagram of the structure of the back contact battery provided in the embodiment of this application;

[0036] Figure 4 is a schematic diagram of the structure of the back contact battery provided in the embodiment of this application;

[0037] Figure 5 is a schematic diagram of the structure of the back contact battery provided in the embodiment of this application;

[0038] Figure 6 is a schematic diagram of the structure of the back contact battery provided in the embodiment of this application;

[0039] Figure 7 is a schematic diagram of the back contact battery provided in an embodiment of this application;

[0040] Figure 8 is a schematic diagram of the back contact battery provided in an embodiment of this application.

[0041] Figure 9 is a schematic diagram of the structure of the back contact battery provided in an embodiment of this application;

[0042] Figure 10 is a schematic diagram of the back contact battery provided in an embodiment of this application.

[0043] Figure 11 is a schematic diagram of the back contact battery provided in an embodiment of this application;

[0044] Figure 12 is a schematic diagram of the structure of the back contact battery provided in the embodiment of this application;

[0045] Figure 13 is a longitudinal cross-sectional view of the back contact battery provided in an embodiment of this application.

[0046] Figure 14 is a longitudinal sectional view of the back contact battery provided in an embodiment of this application.

[0047] Figure 15 is a longitudinal sectional view of the structure of the back contact battery provided in an embodiment of this application.

[0048] Figure 16 is a longitudinal sectional view of the structure of the back contact battery provided in an embodiment of this application.

[0049] Figure 17 is a longitudinal sectional view of the back contact battery provided in an embodiment of this application.

[0050] Figure 18 is a longitudinal sectional view of the structure of the back contact battery provided in an embodiment of this application.

[0051] Figure 19 is a longitudinal sectional view of the structure of the back contact battery provided in an embodiment of this application.

[0052] Figure 20 is a longitudinal sectional view of the structure of the back contact battery provided in an embodiment of this application.

[0053] Figure 21 is a longitudinal sectional view of the structure of the back contact battery provided in an embodiment of this application.

[0054] Figure 22 is a longitudinal sectional view of the structure of the back contact battery provided in the embodiment of this application.

[0055] Figure 23 is a longitudinal sectional view of the structure of the back contact battery provided in the embodiment of this application.

[0056] Figure 24 is a longitudinal sectional view of the structure of the back contact battery provided in the embodiment of this application.

[0057] Figure 25 is a longitudinal sectional view of the structure of the back contact battery provided in the embodiment of this application.

[0058] Figure 26 is a longitudinal sectional view of the structure of the back contact battery provided in an embodiment of this application.

[0059] Figure 27 is a longitudinal sectional view of the back contact battery provided in an embodiment of this application.

[0060] Reference numerals: 11 is a semiconductor substrate, 12 is a first region, 13 is a second region, 14 is an overlapping region, 15 is a tunneling passivation layer, 16 is a first doped silicon layer, 17 is an intrinsic silicon layer, 18 is a second doped silicon layer, 19 is a doped layer, 20 is a trench, 21 is a first sub-region, 22 is a second sub-region, 23 is a transparent conductive layer, 24 is an insulating trench, 25 is a surface passivation layer, 26 is an anti-reflection layer, 27 is an insulating layer, 28 is a first transparent conductive layer, 29 is a second transparent conductive layer, 30 is a first doped portion, 31 is a second doped portion, 32 is a first sub-region, 33 is a second sub-region, and 34 is a third sub-region. Detailed Implementation

[0061] The embodiments of this application will now be described with reference to the accompanying drawings. However, it should be understood that these descriptions are exemplary only and are not intended to limit the scope of this application. Furthermore, descriptions of well-known structures and technologies are omitted in the following description to avoid unnecessarily obscuring the concepts of this application.

[0062] The accompanying drawings show various structural schematic diagrams according to embodiments of this application. These drawings are not drawn to scale, and some details have been enlarged and may have been omitted for clarity. The shapes of the various regions and layers shown in the drawings, as well as their relative sizes and positional relationships, are merely exemplary and may deviate from reality due to manufacturing tolerances or technical limitations. Furthermore, those skilled in the art can design regions / layers with different shapes, sizes, and relative positions as needed.

[0063] In the context of this application, when a layer / element is referred to as being "on top of" another layer / element, the layer / element can be directly on top of the other layer / element, or there can be an intermediate layer / element between them. Furthermore, if a layer / element is "on top of" another layer / element in one orientation, then when the orientation is reversed, the layer / element can be "below" the other layer / element. To make the technical problems, technical solutions, and beneficial effects to be solved by this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of this application and are not intended to limit this application.

[0064] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, "multiple" means two or more, unless otherwise expressly specified. "Several" means one or more, unless otherwise expressly specified.

[0065] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "installation," "connection," and "joining" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.

[0066] In a first aspect, embodiments of this application provide a back-contact battery. As shown in FIG1, the back-contact battery provided in this application includes: a semiconductor substrate 11, a tunneling passivation layer 15 (the tunneling passivation layer may be or may be called a first interface passivation layer), a first doped silicon layer 16 (in this application embodiment, the doped silicon layer may be or may be called a doped semiconductor layer), an intrinsic silicon layer 17 (in this application embodiment, the intrinsic silicon layer may be or may be called a second interface passivation layer), a second doped silicon layer 18 (in this application embodiment, the doped silicon layer may be or may be called a doped semiconductor layer), and a doped layer 19 (in this application embodiment, the doped layer may also be called a doped region). The semiconductor substrate 11 includes a first surface and a second surface opposite to each other. The first surface includes an alternately spaced first region 12 and a second region 13, and an overlapping region 14 located between the first region 12 and the second region 13. Along the thickness direction of the semiconductor substrate 11, the tunneling passivation layer 15 and the first doped silicon layer 16 are sequentially stacked on the first region 12 and the overlapping region 14. Along the thickness direction of the semiconductor substrate 11, an intrinsic silicon layer 17 and a second doped silicon layer 18 are sequentially stacked on the second region 13. Furthermore, the stacked intrinsic silicon layer 17 and second doped silicon layer 18 extend from the second region 13 to the tunneling passivation layer 15 and the first doped silicon layer 16 located in the overlapping region 14. It can be understood that the overlapping region 14 can refer to the region where the tunneling passivation layer 15 and the first doped silicon layer 16, as well as the intrinsic silicon layer 17 and the second doped silicon layer 18, are simultaneously disposed. The conductivity type of the second doped silicon layer 18 is opposite to that of the first doped silicon layer 16. A doped layer 19 is disposed within the first region 12 and the overlapping region 14 of the semiconductor substrate 11.

[0067] In some embodiments, the doping concentration of the first doping element in the doped layer 19 having the same conductivity type as the first doped silicon layer 16 is greater than the doping concentration of the first doping element in the second region 13 of the semiconductor substrate 11.

[0068] In some embodiments, along the direction from the first surface to the second surface, the doping concentration of the second doped element, which has the same conductivity type as the second doped silicon layer 18, is the same in each portion of the second region 13 of the semiconductor substrate 11. The second doped silicon layer includes the second doped element. When the conductivity types of both the first doped silicon layer and the doped layer are the same as those of the semiconductor substrate, the second region of the semiconductor substrate does not contain the second doped element; or, the conductivity type of the semiconductor substrate is the same as that of the second doped silicon layer, and the doping concentration of the second doped element is the same in each portion of the second region of the semiconductor substrate along the direction from the first surface to the second surface. In this case, the doped elements of the semiconductor substrate and the second doped silicon layer may be the same; or the doped elements of the semiconductor substrate and the second doped silicon layer may be different. In this case, the second region of the semiconductor substrate does not contain the second doped element, that is, the doping concentration of the second doped element in each portion of the second region of the semiconductor substrate is 0.

[0069] As shown in Figure 1, in the back contact battery provided in this embodiment of the present application, the first surface of the semiconductor substrate 11 is not only provided with a selective contact structure composed of a tunneling passivation layer 15 and a first doped silicon layer 16, but also with a selective contact structure composed of an intrinsic silicon layer 17 and a second doped silicon layer 18. Specifically, the above-mentioned selective contact structure can not only achieve selective collection of charge carriers, but also passivate the first surface of the semiconductor substrate 11, reduce the carrier recombination rate on one side of the first surface of the semiconductor substrate 11, and improve the conversion efficiency of the back contact battery. Furthermore, the stacked intrinsic silicon layer 17 and second doped silicon layer 18 extend from the second region 13 to the tunneling passivation layer 15 and the first doped silicon layer 16 located on the overlapping region 14. At this time, there is no groove isolation between the first doped silicon layer 16 and the second doped silicon layer 18 along the distribution direction of the first region 12 and the second region 13, which can increase the area of ​​the first doped silicon layer 16 and the second doped silicon layer 18 on the first surface and improve the carrier collection efficiency. In addition, a doped layer 19 is provided in the first region 12 and the overlapping region 14 of the semiconductor substrate 11. The doped layer 19 is doped with a first doping element of the same conductivity type as the first doped silicon layer 16, and the doping concentration of the first doping element in the doped layer 19 is greater than the doping concentration of the first doping element in the second region 13 of the semiconductor substrate 11. At this time, the doping concentration of the first doping element in the doped layer 19 is high, and the conductivity type of the first doping element is the same as that of the first doped silicon layer 16. Therefore, the first region 12 and the overlapping region 14 of the semiconductor substrate 11 can be field passivated by the doped layer 19, thereby improving the passivation effect. Furthermore, the conductivity type of the first doped element in the doped layer 19 is the same as that of the first doped silicon layer 16. Therefore, the doped layer 19 can form a favorable electric field consistent with the induced direction of the first doped silicon layer 16. The presence of this favorable electric field can repel minority carriers and attract majority carriers on the surface of the first region 12 and the overlapping region 14 of the semiconductor substrate 11, thereby improving the carrier collection efficiency of the first doped silicon layer 16 and further reducing the carrier recombination rate, which is beneficial to improving the conversion efficiency of the back contact battery. Moreover, along the direction from the first surface to the second surface, the doping concentration of the second doped element with the same conductivity type as the second doped silicon layer 18 is the same in each part of the second region 13 of the semiconductor substrate 11. That is to say, there is no inner-diffusion doped layer with the same conductivity type as the second doped silicon layer 18 in the second region 13 of the semiconductor substrate 11. This can prevent the doped layer 19 from making electrical contact with the inner-diffusion doped layer (i.e., the inner-diffusion doped layer with the same conductivity type as the second doped silicon layer 18) and thus avoid a high risk of leakage, ensuring that the back contact battery has a high conversion efficiency.

[0070] In practical applications, this application does not specifically limit the material and conductivity type of the semiconductor substrate. For example, the semiconductor substrate can be a silicon substrate; or, it can be a substrate made of any semiconductor material such as a germanium-silicon substrate, a germanium substrate, or a gallium arsenide substrate. Furthermore, the semiconductor substrate can be an N-type semiconductor substrate, a P-type semiconductor substrate, or an intrinsic semiconductor substrate.

[0071] In terms of materials, the first doped silicon layer can be any semiconductor material such as silicon, germanium-silicon, germanium, or gallium arsenide. In terms of the arrangement of matter, the crystal phase of the first doped silicon layer can be amorphous, microcrystalline, nanocrystalline, single crystal, or polycrystalline.

[0072] In terms of materials, the second doped silicon layer can be any semiconductor material such as silicon, germanium-silicon, germanium, or gallium arsenide. In terms of the arrangement of matter, the crystal phase of the second doped silicon layer can be amorphous, microcrystalline, nanocrystalline, single-crystal, or polycrystalline. The specific value of the crystallinity of the second doped silicon layer can be determined based on the actual application scenario and is not specifically limited here.

[0073] Secondly, the aforementioned semiconductor substrate includes a first surface and a second surface opposite to each other. The first surface of the semiconductor substrate corresponds to the back surface or back side of the back contact battery, and the second surface of the semiconductor substrate corresponds to the light-facing surface or front side of the back contact battery. The distribution of the first region, the second region, and the overlapping region on the first surface can be determined based on the distribution of the first doped silicon layer and the second doped silicon layer formed on the first surface. Specifically, since the first doped silicon layer of the back contact battery is disposed on the first region and the overlapping region, the distribution range of the first region and the overlapping region on the first surface can be determined according to the distribution requirements of the first doped silicon layer in the actual application scenario. Since a portion of the second doped silicon layer of the back contact battery is disposed on the second region of the first surface, the distribution range of the second region on the first surface can be determined according to the distribution requirements of the second doped silicon layer on the semiconductor substrate in the actual application scenario. It can be understood that, for the first surface, all regions except the first region and the overlapping region constitute the second region.

[0074] It is understandable that the first region roughly corresponds to the first emitter region, and the second region roughly corresponds to the second emitter region. One of the first and second regions corresponds to the P region, and the other corresponds to the N region. The overlapping region corresponds to the P-N overlapping region. In this sense, the overlapping region can also be called the overlapping region.

[0075] The specific shapes of the first and second regions can be set according to actual needs. For example, the first and second regions can be distributed in alternating stripes or in an interlaced (i.e., a character-like shape) pattern.

[0076] From a surface morphology perspective, as shown in Figure 1, the first and second surfaces of the semiconductor substrate 11 can be planar. Alternatively, as shown in Figure 2, the second surface of the semiconductor substrate 11 can also be textured to improve the light-trapping effect and increase the light utilization rate of the semiconductor substrate 11. Of course, in the first surface, a portion (such as the second region) can be textured, while a portion (such as the first region) can be planar. Textured surfaces in a portion of the first surface (such as the second region) can increase the contact area between the doped silicon layer and the corresponding conductive material (such as a transparent conductive layer or a metal electrode) in that portion, which helps to reduce transmission loss.

[0077] Secondly, as shown in Figures 1 and 2, the surfaces of the first region 12 and the second region 13 on the first surface can be flush; or, as shown in Figure 3, the second region 13 can also include a groove 20 (the groove can also be called a groove structure). In this case, along the direction from the second surface to the first surface, the surface height of the second region 13 corresponding to the groove 20 is lower than the surface height of the first region 12. In this case, the presence of the groove 20 not only indicates that after patterning the tunneling passivation layer 15 and the first doped silicon layer 16 formed in the whole layer, the portions of both located in the second region 13 have been completely removed, improving the yield of the back contact battery. In addition, the presence of the groove 20 can also at least partially offset the first doped silicon layer 16 and the second doped silicon layer 18, which have opposite conductivity types, along the thickness direction of the semiconductor substrate 11, reducing the leakage risk between the first doped silicon layer 16 and the second doped silicon layer 18, which is beneficial to further improve the conversion efficiency of the back contact battery.

[0078] As for the depth of the groove, it can be set according to actual needs, and no specific limitation is made here. In addition, as shown in Figure 3, the surface of the groove 20 can be a plane; or as shown in Figure 4, the bottom surface of the groove 20 can also be a textured surface, so as to increase the contact area between the second doped silicon layer 18 formed on the second region 13 and the corresponding conductive material (transparent conductive layer 23 or metal electrode, etc.), which helps to reduce transmission loss.

[0079] It is worth noting that the groove 20 in the second region 13 may occupy only a portion of the second region 13, and the surface height of the second region 13 corresponding to the groove 20 may be lower than the surface height of the other regions in the second region 13 besides the groove 20, as described in more detail below with reference to Figures 13-27.

[0080] Specifically, as shown in Figure 3, the side surface of the groove 20 can be perpendicular to the bottom surface of the groove 20. Alternatively, as shown in Figures 4 and 5, at least a portion of the side surface of the groove 20 can be inclined relative to the bottom surface, and the cross-sectional area of ​​the bottom of the groove 20 is smaller than the cross-sectional area of ​​the opening; in this case, the entire side surface of the groove 20 can be inclined relative to the bottom surface; or, along the width direction of the overlapping region 14, the side surface of the groove 20 has a continuously distributed first sub-region 21 and a second sub-region 22, and the second sub-region 22 is close to the first region 12. The surface of the first sub-region 21 is inclined relative to the surface of the first region 12, and the cross-sectional area of ​​the portion of the groove 20 corresponding to the first sub-region 21 gradually increases along the direction from the second surface to the first surface. The surface of the second sub-region 22 is a plane, which can be parallel to the second surface or inclined relative to the second surface. Furthermore, in this case, with the depth of the groove 20 fixed, the surface of the first sub-region 21 on the side of the groove 20 is inclined relative to the surface of the first region 12, and the cross-sectional area of ​​the portion of the groove 20 corresponding to the first sub-region 21 gradually increases along the direction from the second surface to the first surface. This is beneficial to increase the lateral spacing between the doped layer 19 and the second doped silicon layer 18 located on the bottom of the groove, thereby reducing the risk of leakage between them. In addition, since the second doped silicon layer 18 is formed relatively smoothly on the inclined surface corresponding to the first sub-region 21, it is beneficial to improve the film formation quality of the second doped silicon layer 18.

[0081] Furthermore, as shown in Figure 4, along the direction from the first surface to the second surface, the doping concentration of the second doped element with the same conductivity type as the second doped silicon layer 18 is the same in each portion of the second region 13 of the semiconductor substrate 11. Specifically, the doping concentration of the second doped element in each portion of the second region 13 of the semiconductor substrate 11 can all be 0, that is, there is no second doped element in each portion of the second region 13 of the semiconductor substrate 11; or, the second doped element can also be doped in each portion of the second region 13 of the semiconductor substrate 11, but the distribution concentration of the second doped element at each position in the semiconductor substrate 11 corresponding to the second region 13 is the same. The doping concentration of the doped element in the second region 13 can be determined according to the actual application scenario, and is not specifically limited here. It should be noted that, in the actual manufacturing process, if the dopant element in the second doped silicon layer 18 diffuses through the intrinsic silicon layer 17 into the second region 13 of the semiconductor substrate 11, according to the diffusion principle, the doping concentration of the dopant element diffused from the second doped silicon layer 18 into the second region 13 of the semiconductor substrate 11 will gradually decrease along the direction from the first surface to the second surface. However, in the embodiment of this application, along the direction from the first surface to the second surface, the doping concentration of the second dopant element with the same conductivity type as the second doped silicon layer 18 is the same in each part of the second region 13 of the semiconductor substrate 11. Therefore, even if there is a second dopant element in the second region 13 of the semiconductor substrate 11, the second dopant element is not formed by the diffusion of the second doped silicon layer 18, but is the second dopant element doped by the semiconductor substrate 11 itself.

[0082] Regarding the aforementioned tunneling passivation layer and the first doped silicon layer, from a material perspective, the tunneling passivation layer can be made of any passivation material with a tunneling effect, such as silicon oxide, aluminum oxide, titanium oxide, and zinc oxide. Secondly, the aforementioned first doped silicon layer can be a doped crystalline silicon layer, and the material of this doped crystalline silicon layer can include polycrystalline silicon and / or monocrystalline silicon.

[0083] In terms of conductivity type, the first doped silicon layer can be N-type, and the second doped silicon layer can be P-type; alternatively, the first doped silicon layer can also be P-type, and the second doped silicon layer can be N-type. Optionally, when the material of the first doped silicon layer includes polycrystalline silicon, the conductivity type of the first doped silicon layer is N-type. In this case, compared to P-type doped amorphous, microcrystalline, and nanocrystalline materials (i.e., the second doped silicon layer is P-type), when the material of the first doped silicon layer is P-type polycrystalline silicon, the contact resistance between the P-type doped polycrystalline silicon material and the conductive material is higher, and the field passivation effect is poorer. Therefore, setting the conductivity type of the first doped silicon layer to N-type and the conductivity type of the second doped silicon layer to P-type can further improve the field passivation effect of the first doped silicon layer, while reducing the contact resistance between the first doped silicon layer and the conductive material, which is beneficial for improving the electrical performance of the back contact battery.

[0084] The thickness of the tunneling passivation layer and the first doped silicon layer can be set according to actual needs, and no specific limit is made here.

[0085] For example, the thickness of the tunneling passivation layer can be greater than or equal to 0.5 nm and less than or equal to 2.5 nm. For instance, the thickness of the tunneling passivation layer can be 0.5 nm, 1 nm, 1.2 nm, 1.5 nm, 1.7 nm, 2 nm, 2.2 nm, or 2.5 nm, etc. In this case, it can prevent the tunneling resistance from being too high due to a large thickness of the tunneling passivation layer, thus affecting the carrier collection efficiency of the first doped silicon layer. Furthermore, it is understood that within a certain thickness range, the thickness of the tunneling passivation layer is proportional to its diffusion blocking effect. Therefore, if, in the actual manufacturing process, at least a portion of the first doped element in the doped layer is formed by the first doped element in the first doped silicon layer diffusing through the tunneling passivation layer to the first region and overlapping region of the semiconductor substrate, then the thickness of the tunneling passivation layer within the aforementioned range can also prevent the doping concentration of the first doped element in the doped layer from being too low or too high due to excessive thickness, thus affecting the field passivation effect of the doped layer and avoiding high carrier recombination rates in the first region and overlapping region.

[0086] For example, the thickness of the first doped silicon layer can be greater than or equal to 20 nm and less than or equal to 300 nm. For instance, the thickness of the first doped silicon layer can be 20 nm, 50 nm, 80 nm, 100 nm, 120 nm, 150 nm, 180 nm, 200 nm, 220 nm, 260 nm, 280 nm, or 300 nm, etc. In this case, the thickness of the first doped silicon layer within the above range can prevent a low field passivation effect due to a small thickness, ensuring that the first doped silicon layer has a high carrier collection efficiency. Furthermore, if, during the actual manufacturing process, the first dopant element in the doped layer diffuses from the first doped silicon layer into the doped layer, then the thickness of the first doped silicon layer within the above range can also prevent a low doping concentration of the first dopant element diffused from the first doped silicon layer into the doped layer due to a small thickness. Therefore, setting the thickness of the first doped silicon layer within the above range can ensure that the doped layer has a high field passivation effect. In addition, it can prevent the large amount of consumables used for the first doped silicon layer due to its large thickness, and the problem of excessively high doping concentration of the first doped element in the doped layer, thus ensuring that the back contact battery has a high conversion efficiency.

[0087] It should be noted that the first dopant element can be of one type, such as phosphorus; or, the first dopant element can be of multiple types with the same conductivity, such as phosphorus and arsenic. The type of the first dopant element within the first doped silicon layer can be the same as or different from the type of the first dopant element within the doped layer. For example, if both the first doped silicon layer and the doped layer have an N-type conductivity, both the first doped silicon layer and the first dopant element within the doped layer can be phosphorus. As another example, if both the first doped silicon layer and the doped layer have a P-type conductivity, both the first doped silicon layer and the first dopant element within the doped layer can be boron. Yet another example, if both the first doped silicon layer and the doped layer have an N-type conductivity, the first dopant element within the first doped silicon layer can be phosphorus, while the first dopant element within the doped layer can be arsenic. It is understood that if, during the actual manufacturing process, the first dopant element in the doped layer diffuses from the first doped silicon layer into the doped layer, then the type of the first dopant element within the first doped silicon layer is the same as the type of the first dopant element within the doped layer.

[0088] Furthermore, in practical applications, the doping concentration of the first doped element on the side of the doped layer closest to the first doped silicon layer can be less than or equal to the doping concentration of the first doped element within the first doped silicon layer. In this case, the first doped silicon layer exhibits a higher field passivation effect, improving its carrier collection capability. It also facilitates the formation of a high-low junction between the first doped silicon layer and the doped layer. The presence of this high-low junction helps control the magnitude of the reverse leakage current, resulting in higher conversion efficiency for the back contact battery. Simultaneously, when the doping concentration of the first doped element on the side of the doped layer closest to the first doped silicon layer is less than or equal to the doping concentration of the first doped element within the first doped silicon layer, the doped layer can be formed during the actual manufacturing process by inward expansion when forming the first doped silicon layer. This eliminates the need for additional manufacturing processes to form the doped layer, simplifying the manufacturing process of the back contact battery and improving its manufacturing efficiency.

[0089] The doping concentration of the first doped element in the first doped silicon layer will affect its field passivation performance. When at least part of the first doped element in the doped layer is diffused from the first doped silicon layer into the doped layer, the doping concentration of the first doped element in the first doped silicon layer will also affect the doping concentration of the first doped element in the doped layer. Therefore, the doping concentration of the first doped element in the first doped silicon layer can be determined according to the field passivation effect of the first doped silicon layer and the doping concentration requirements of the first doped element in the doped layer in the actual application scenario. No specific limitation is made here.

[0090] For example, the doping concentration of the first doped element in the first doped silicon layer can be greater than or equal to 1 × 10⁻⁶. 18 / cm 3And less than or equal to 1×10 21 / cm 3 For example, the doping concentration of the first doped element in the first doped silicon layer can be 1 × 10⁻⁶. 18 / cm 3 1×10 19 / cm 3 2×10 19 / cm 3 4×10 19 / cm 3 6×10 19 / cm 3 8×10 19 / cm 3 1×10 20 / cm 3 2×10 20 / cm 3 4×10 20 / cm 3 6×10 20 / cm 3 8×10 20 / cm 3 9×10 20 / cm 3 Or 1×10 21 / cm 3 The application principle of the beneficial effect in this case is similar to that of the beneficial effect described above when the thickness of the first doped silicon layer is greater than or equal to 20 nm and less than or equal to 300 nm, and will not be repeated here.

[0091] For example, the doping concentration of the first dopant element in the doped layer can be greater than or equal to 8 × 10⁻⁶. 9 / cm 3 And less than or equal to 9 × 10 20 / cm 3 For example, the doping concentration of the first dopant element within the doped layer can be greater than or equal to 8 × 10⁻⁶. 9 / cm 3 9×10 9 / cm 3 1×10 10 / cm 3 1×10 11 / cm 3 1×10 12 / cm 3 1×10 13 / cm 3 1×10 15 / cm 3 1×10 17 / cm 3 1×1019 / cm 3 Or 9×10 20 / cm 3 The doping concentration of the first doping element in each part of the doped layer can be the same along the direction from the second surface to the first surface. Alternatively, the doping concentration of the first doping element in the doped layer can gradually increase along the direction from the second surface to the first surface. In this case, a high-low junction can be formed between different regions of the doped layer along the direction from the second surface to the first surface. The built-in electric field of this high-low junction is consistent with the induced direction of the first doped silicon layer, which can improve the carrier collection efficiency of the first doped silicon layer, further reduce the carrier recombination rate, and improve the conversion efficiency of the back contact cell. In addition, the surface of the doped layer facing away from the semiconductor substrate can have a higher doping concentration, which can increase the leakage current between the doped layer and the second doped silicon layer, further reducing the hot spot risk of the back contact cell. Specifically, the doping concentration of the first doping element in each part of the doped layer along the direction from the second surface to the first surface can be set according to the manufacturing process of the doped layer and actual needs, and is not specifically limited here.

[0092] Regarding the intrinsic silicon layer and the second doped silicon layer mentioned above, in terms of materials, the materials of the intrinsic silicon layer and / or the second doped silicon layer may include at least one of amorphous silicon, microcrystalline silicon, and nanocrystalline silicon.

[0093] In terms of formation location, as shown in Figure 4, the stacked intrinsic silicon layer 17 and second doped silicon layer 18 extend and cover the portion above the overlapping region 14, directly located on the tunneling passivation layer 15 and the first doped silicon layer 16, and in contact with the first doped silicon layer 16. Alternatively, as shown in Figure 6, the back contact battery may also include an insulating layer 27, which is located between the intrinsic silicon layer 17 and the first doped silicon layer 16 in the overlapping region 14. In this case, the insulating layer 27 will isolate the second doped silicon layer 18 from the first doped silicon layer 16 on the overlapping region 14, reducing forward leakage loss and further improving the conversion efficiency of the back contact battery. The material and thickness of the insulating layer can be determined according to the actual application scenario, and are not specifically limited here. For example, the insulating layer may include a silicon oxide layer and / or an aluminum oxide layer, etc.

[0094] Furthermore, as mentioned earlier, there is no internal doping layer corresponding to the second doped silicon layer in the second region of the semiconductor substrate. On the second region of the semiconductor substrate, the intrinsic silicon layer is located between the semiconductor substrate and the second doped silicon layer. It acts as a diffusion barrier for the dopants within the second doped silicon layer. Since the dopants within the second doped silicon layer are second dopants, the thickness of the intrinsic silicon layer not only affects its own transmission resistance but also the doping concentration of the second dopant within the semiconductor substrate (the second dopant can be of a single type, such as boron; or multiple types of the same conductivity type, such as boron and aluminum). In addition, the thickness of the second doped silicon layer and the doping concentration of its own second dopant not only affect the field passivation effect of the second doped silicon layer but may also affect whether the second dopant within the second doped silicon layer diffuses into the second region of the semiconductor substrate. Therefore, the thickness of the intrinsic silicon layer can be determined based on the requirements for transmission resistance and diffusion barrier in the actual application scenario. Furthermore, the thickness and doping concentration of the second doped silicon layer can be determined based on the requirements for field passivation effect and the diffusion requirements of the second dopant within the second doped silicon layer in the actual application scenario; no specific limitations are made here.

[0095] For example, the thickness of the intrinsic silicon layer can be greater than or equal to 5 nm and less than or equal to 20 nm. For instance, the thickness of the intrinsic silicon layer can be 5 nm, 7 nm, 9 nm, 10 nm, 12 nm, 14 nm, 16 nm, 18 nm, or 20 nm. In this case, the thickness of the intrinsic silicon layer within the above range can prevent a weak diffusion barrier effect on the dopant elements in the second doped silicon layer due to a small intrinsic silicon layer thickness. This ensures that no inward doped layer with the same conductivity type as the second doped silicon layer is formed in the second region. Furthermore, it can prevent a large transport resistance due to a large intrinsic silicon layer thickness, thus ensuring that the second doped silicon layer has a high carrier collection efficiency.

[0096] For example, the doping concentration of the second doped element in the second doped silicon layer can be greater than or equal to 1 × 10⁻⁶. 18 / cm 3 And less than or equal to 1×10 21 / cm 3 For example, the doping concentration of the second dopant element within the second doped silicon layer can be 1 × 10⁻⁶. 18 / cm 3 1×10 19 / cm 3 2×10 19 / cm 3 4×10 19 / cm 3 6×10 19 / cm3 8×10 19 / cm 3 1×10 20 / cm 3 2×10 20 / cm 3 4×10 20 / cm 3 6×10 20 / cm 3 8×10 20 / cm 3 9×10 20 / cm 3 Or 1×10 21 / cm 3 In this case, while ensuring that the second doped silicon layer has a high field passivation effect, it is necessary to prevent the high doping concentration of the second doped element in the second doped silicon layer from causing an excessive difference in doping concentration between the second doped silicon layer and the second region of the semiconductor substrate, which could easily diffuse into the second region of the semiconductor substrate and form an inner doped layer. This ensures that the doped layer will not make electrical contact with the inner doped layer, which has an opposite conductivity type, thus preventing a high risk of leakage current, and thereby ensuring that the back contact cell has a high conversion efficiency.

[0097] For example, the thickness of the second doped silicon layer can be greater than or equal to 10 nm and less than or equal to 100 nm. For instance, the thickness of the second doped silicon layer can be 10 nm, 20 nm, 40 nm, 60 nm, 80 nm, or 100 nm, etc. The application principle of the beneficial effect in this case can be referred to the previously described method where the doping concentration of the second doping element in the second doped silicon layer is greater than or equal to 1 × 10⁻⁶. 18 / cm 3 And less than or equal to 1×10 21 / cm 3 The application principle of its beneficial effects will not be elaborated here. The conductivity type of the second doped silicon layer is opposite to that of the first doped silicon layer.

[0098] For example, the sum of the thicknesses of the second doped silicon layer and the intrinsic silicon layer can be greater than or equal to 15 nm and less than or equal to 120 nm. For instance, the sum of the thicknesses of the second doped silicon layer and the intrinsic silicon layer can be 15 nm, 20 nm, 30 nm, 50 nm, 70 nm, 90 nm, 100 nm, or 120 nm, etc. The application principle of the beneficial effects in this case can refer to the application principle of the beneficial effects described above for intrinsic silicon layer thicknesses greater than or equal to 5 nm and less than or equal to 20 nm, and for second doped silicon layer thicknesses greater than or equal to 10 nm and less than or equal to 100 nm, which will not be repeated here.

[0099] Furthermore, as shown in FIG6, when the second region 13 includes a groove 20, the depth of the groove 20 affects the direct ratio between the portion of the second doped silicon layer 18 located at the bottom of the groove 20 and the doped layer 19 located in the first region 12 and the overlapping region 14 (i.e., the structural proportions that correspond exactly between the two along the direction from the second surface to the first surface or along the thickness direction of the semiconductor substrate 11). Moreover, since the conductivity type of the first doped element in the doped layer 19 is opposite to the conductivity type of the second doped silicon layer 18, the direct ratio between the portion of the second doped silicon layer 18 located at the bottom of the groove 20 and the doped layer 19 located in the first region 12 and the overlapping region 14 affects the leakage risk between them. Based on this, the depth of the groove 20 and the position between the surface height of the second doped silicon layer 18 located at the bottom of the groove 20 away from the semiconductor substrate 11 and the surface height of the doped layer 19 away from the tunneling passivation layer 15 can be determined according to the actual manufacturing process and the requirements for leakage risk between the doped layer 19 and the second doped silicon layer 18 in the actual application scenario. No specific limitation is made here.

[0100] For example, as shown in FIG7, the surface height of the portion of the second doped silicon layer 18 located at the bottom of the trench 20 away from the semiconductor substrate 11 can be lower than the surface height of the doped layer 19 away from the tunneling passivation layer 15. In this case, the doped layer 19 and the second doped silicon layer 18 located at the bottom of the trench 20 do not have structurally aligned portions along the thickness direction of the semiconductor substrate 11. In other words, the presence of the trench 20 can also offset the doped layer 19 and the first doped silicon layer 16 from the second doped silicon layer 18, which has the opposite conductivity type, along the thickness direction of the semiconductor substrate 11, reducing the leakage risk between the doped layer 19 and the second doped silicon layer 18, and further improving the conversion efficiency of the back contact cell. Additionally, it is understood that the portion of the second doped silicon layer 18 located at the bottom of the trench 20 is mainly used to collect and discharge charge carriers. Therefore, the surface height of the portion of the second doped silicon layer 18 located at the bottom of the trench 20 away from the semiconductor substrate 11 is set to be less than the surface height of the doped layer 19 away from the tunneling passivation layer 15. This also helps to prevent the first doping element in the doped layer 19, which has the opposite conductivity type to the second doped silicon layer 18, from diffusing into the second doped silicon layer 18. This ensures that the portion of the second doped silicon layer 18 corresponding to the bottom of the trench has a high charge carrier collection capability and prevents leakage between the second doped silicon layer 18 and the doped layer 19 located at the bottom of the trench, which would affect the power generation efficiency of the back contact battery.

[0101] Alternatively, as shown in Figure 6, the surface height of the portion of the second doped silicon layer 18 located at the bottom of the trench 20 away from the semiconductor substrate 11 can be lower than the surface height of the doped layer 19 near the tunneling passivation layer 15, but higher than the surface height of the doped layer 19 away from the tunneling passivation layer 15. In this case, while preventing all portions of the doped layer 19 along the thickness direction from being aligned with the portion of the second doped silicon layer 18 located at the bottom of the trench, the depth of the trench 20 can be reduced, resulting in a higher light absorption depth for the portion of the semiconductor substrate 11 corresponding to the trench 20. This improves the photoelectric conversion efficiency of the semiconductor substrate 11 and also helps to shorten the transmission path of charge carriers bypassing the deeper sidewalls of the trench 20 and being collected by the portion of the second doped silicon layer 18 located at the bottom of the trench, thus reducing transmission loss.

[0102] For example, the depth of the aforementioned groove can be greater than or equal to 300 nm and less than or equal to 15 μm. For instance, the groove depth can be 300 nm, 1 μm, 2 μm, 3 μm, 5 μm, 7 μm, 9 μm, 10 μm, 12 μm, or 15 μm, etc. In this case, the groove depth is within the aforementioned range, which helps to prevent a small spacing between the doped layer and the second doped silicon layer located at the bottom of the groove along the thickness direction of the semiconductor substrate, thus preventing a high risk of leakage. Additionally, it also prevents a large groove depth from causing a small light absorption depth in the semiconductor substrate corresponding to the groove, ensuring high photoelectric conversion efficiency of the semiconductor substrate, and thus ensuring high operating performance of the back contact battery. Furthermore, when the first dopant element in the doped layer is formed by diffusion from the first doped silicon layer to the semiconductor substrate, the groove depth being within the aforementioned range also ensures that after removing the first doped silicon layer on the second region, the groove arrangement can completely remove the doped layer formed in the second region by the first doped silicon layer, preventing the electric field of the residual doped layer in the second region from affecting the carrier collection energy of the second doped silicon layer. It should be noted that when the bottom surface of the groove is textured, the depth of the groove is the distance between the surface of the first region and the bottom of the textured structure (the side closer to the semiconductor substrate).

[0103] For example, along the direction from the second surface to the first surface, the difference between the surface height of the portion of the second doped silicon layer located at the bottom of the trench on the side facing away from the semiconductor substrate and the surface height of the doped layer on the side facing away from the tunneling passivation layer can be greater than or equal to 180 nm and less than or equal to 14.7 μm. For instance, the difference between the surface height of the portion of the second doped silicon layer located at the bottom of the trench on the side facing away from the semiconductor substrate and the surface height of the doped layer on the side facing away from the tunneling passivation layer can be 180 nm, 200 nm, 500 nm, 1 μm, 2 μm, 4 μm, 6 μm, 8 μm, 10 μm, or 14.7 μm, etc. The application principle of the beneficial effect in this case can refer to the application principle of the beneficial effect described above when the trench depth is greater than or equal to 300 nm and less than or equal to 15 μm, and will not be repeated here.

[0104] Furthermore, in practical applications, as shown in Figure 7, when the bottom surface of the aforementioned groove 20 is textured, the thickness of the second doped silicon layer 18 located on the bottom of the groove 20 can be less than the thickness of the second doped silicon layer 18 located on the overlapping region 14. In this case, the smaller thickness of the second doped silicon layer 18 located on the bottom of the groove 20 ensures good field passivation while preventing the diffusion of a large number of second doped elements into the second region 13 of the semiconductor substrate 11 due to the larger thickness of the second doped silicon layer 18 located on the bottom of the groove. This ensures that the doped layer 19 will not make electrical contact with the inner doped layer with the opposite conductivity type, thus preventing a high risk of leakage and ensuring that the back contact battery has a high conversion efficiency. In addition, the smaller thickness of the second doped silicon layer 18 located on the bottom of the groove can also increase the distance between itself and the doped layer 19 along the thickness direction of the semiconductor substrate 11, preventing the diffusion of the first doped element in the doped layer 19 into the second doped silicon layer 18, ensuring that the second doped silicon layer 18 has a high field passivation effect and carrier collection efficiency. Specifically, the difference between the thickness of the second doped silicon layer 18 located at the bottom of the groove 20 and the thickness of the second doped silicon layer 18 located in the overlapping region 14 can be set according to the size of the textured structure and actual needs, and is not specifically limited here.

[0105] Of course, the thickness of the second doped silicon layer located at the bottom of the groove can also be equal to the thickness of the second doped silicon layer located in the overlapping region.

[0106] Regarding the doped layer described above, in terms of its formation range, as mentioned earlier, the doped layer is disposed in the first region and the overlapping region of the semiconductor substrate. Specifically, along the width direction of the overlapping region, the doped layer can be disposed only in a local area of ​​the first region and the overlapping region of the semiconductor substrate; or, the doped layer can be disposed throughout the entire first region and the overlapping region; in other words, along the width direction of the overlapping region, the width of the doped layer can be greater than or equal to the width of the first doped silicon layer. In this case, the doped layer has a larger formation range, which is beneficial to improving the field passivation effect of the doped layer and further reducing the carrier recombination rate on one side of the first surface of the semiconductor substrate.

[0107] As for the difference in width between the doped layer and the first doped silicon layer, it can be determined based on the passivation treatment range of the doped layer and the requirements for leakage risk in the actual application scenario, and no specific limit is made here.

[0108] For example, along the width direction of the overlapping region, the difference between the width of the doped layer and the width of the first doped silicon layer can be greater than 0 and less than or equal to 50 μm. For instance, along the width direction of the overlapping region, the difference between the width of the doped layer and the width of the first doped silicon layer can be 5 nm, 10 nm, 50 nm, 100 nm, 150 nm, 200 nm, 300 nm, 400 nm, 500 nm, 1 μm, 1.5 μm, 2 μm, 10 μm, 20 μm, 30 μm, 40 μm, or 50 μm, etc. In this case, the width of the doped layer is approximately the same as the width of the first doped silicon layer, ensuring that the first region and the overlapping region of the semiconductor substrate have a high carrier recombination rate under the passivation effect of the doped layer. Furthermore, it is understood that the overlapping region is adjacent to the second region, and the second doped silicon layer located in the second region is mainly used to collect and extract carriers, while the conductivity type of the first dopant element in the doped layer is opposite to the conductivity type of the second doped silicon layer. Based on this, when the difference between the width of the doped layer and the width of the first doped silicon layer is within the above range, it can prevent the width of the doped layer from being too large, which would result in a small distance between the edge of the doped layer and the edge of the second doped silicon layer, thereby reducing the risk of leakage between the doped silicon and the second doped silicon layer.

[0109] Furthermore, as mentioned above, when the second region includes a groove, and the sides of the groove have continuously distributed first and second sub-regions, as shown in Figures 8 and 9, the doped layer 19 can also extend to the region corresponding to the second sub-region 22 on the side of the groove 20; or, the doped layer 19 can also extend to the region corresponding to the second sub-region 22 on the side of the groove 20 and the portion of the first sub-region 21 near the second sub-region 22. In this case, with the depth of the groove 20 fixed, the surface of the first sub-region 21 on the side of the groove 20 is inclined relative to the surface of the first region 12, and the cross-sectional area of ​​the portion of the groove 20 corresponding to the first sub-region 21 gradually increases along the direction from the second surface to the first surface. This facilitates increasing the lateral spacing between the doped layer 19 and the second doped silicon layer 18 located on the bottom of the groove, so that the edge of the doped layer 19 only extends from the overlapping region 14 to the region corresponding to the second sub-region 22 on the side of the groove 20 and the portion of the first sub-region 21 near the second sub-region 22, and does not extend to the region corresponding to the bottom surface of the groove 20, further reducing the risk of leakage between the two. At the same time, it can also increase the formation range of the doped layer 19 in the semiconductor substrate 11, improve the passivation treatment range, and further reduce the carrier recombination rate on the first side.

[0110] Furthermore, along the thickness direction of the semiconductor substrate, the doping depth of the doped layer can be determined based on the manufacturing process of the doped layer and the requirements for the passivation effect of the doped layer; no specific limitation is made here.

[0111] For example, along the thickness direction of the semiconductor substrate, the doping depth of the doped layer can be greater than or equal to 1 nm and less than or equal to 300 nm. For instance, the doping depth of the doped layer can be 1 nm, 5 nm, 10 nm, 20 nm, 40 nm, 60 nm, 80 nm, 100 nm, 120 nm, 150 nm, 180 nm, 200 nm, 260 nm, or 300 nm, etc. In this case, the doping depth of the doped layer within the above range helps to prevent poor field passivation capability due to a small doping depth. Furthermore, it also prevents a high Auger recombination rate in the semiconductor substrate due to a large doping depth, thus affecting the passivation effect and ensuring a low carrier recombination rate in the first region and overlapping region of the semiconductor substrate where the doped layer is formed. If, in the actual manufacturing process, the first dopant element in the doped layer diffuses from the first doped silicon layer into the doped layer, then the doping depth of the doped layer within the above range also prevents a low doping concentration of the first dopant element in the first doped silicon layer due to a large doping depth, ensuring a high carrier collection efficiency in the first doped silicon layer.

[0112] As for the doping concentration of the first doped element in the doped layer, it can be set according to actual needs, as long as the doping concentration of the first doped element in the doped layer is greater than the doping concentration of the first doped element in the second region of the semiconductor substrate.

[0113] For example, the doping concentration of the first dopant element in the doped layer can be less than or equal to 9 × 10⁻⁶. 20 / cm 3 And greater than or equal to 8 × 10 9 / cm 3 For example, the doping concentration of the first dopant element within the doped layer can be 8 × 10⁻⁶. 9 / cm 3 1×10 10 / cm 3 1×10 12 / cm 3 1×10 16 / cm 3 2×10 16 / cm 3 4×10 16 / cm 3 6×10 16 / cm 3 8×10 16 / cm 3 1×10 17 / cm 3 1×10 18 / cm 3 1×10 19 / cm 3 1×10 20 / cm 3 Or 9×10 20 / cm 3 In this case, it can prevent poor passivation due to a low doping concentration of the first dopant element in the doped layer. Additionally, it can prevent band dips caused by a high doping concentration of the first dopant element in the doped layer, thus preventing low carrier collection efficiency in the first doped silicon layer and ensuring high conversion efficiency of the back contact cell. If, during actual manufacturing, the first dopant element diffuses from the first doped silicon layer into the doped layer, and the doping concentration of the first dopant element in the doped layer is within the aforementioned range, it can also prevent a low doping concentration of the first dopant element in the first doped silicon layer due to a high doping concentration, ensuring high carrier collection efficiency of the first doped silicon layer.

[0114] Specifically, along the direction from the second surface to the first surface, the doping concentration of the first doped element in each region of the doped layer can be the same. Alternatively, along the direction from the second surface to the first surface, the doping concentration of the first doped element in the doped layer can gradually increase. In this case, a high-low junction can be formed between different regions of the doped layer along the direction from the second surface to the first surface. The built-in electric field of this high-low junction is consistent with the induction direction of the first doped silicon layer, which can further improve the carrier collection efficiency of the first doped silicon layer and further reduce the carrier recombination rate, thus improving the conversion efficiency of the back contact battery. It should be noted that during the detection of the doping concentration and doping depth of the doped layer, when the detection device detects that the doping concentration of the first doped element in the semiconductor substrate is 0 (or close to 0); or when it detects that the doping concentration of the first doped element in the semiconductor substrate tends to be uniform, the region where the doping concentration of the first doped element in the semiconductor substrate is 0, or where the doping concentration tends to be uniform, can be considered as the undoped layer of the semiconductor substrate. The region where the doping concentration of the first doped element in the semiconductor substrate is greater than 0, or where the doping concentration of the first doped element gradually decreases along the direction from the first surface to the second surface, is considered as the doped layer.

[0115] Furthermore, the doping concentration of the first doped element within the first doped silicon layer can be greater than that within the doped layer. In this case, a higher field passivation effect is ensured in the first doped silicon layer, improving its carrier collection capability. Moreover, a high-low junction can be formed between the first doped silicon layer and the doped layer, with the built-in electric field direction of this high-low junction aligned with the induced direction of the first doped silicon layer, further enhancing its carrier collection capability.

[0116] Alternatively, the doping concentration of the first doped element in the first doped silicon layer can be at least equal to the doping concentration of the first doped element on the side of the doped layer near the tunnel passivation layer.

[0117] As for the conductivity type of the doped layer, you can refer to the conductivity type of the first doped silicon layer, which will not be repeated here.

[0118] Optionally, the conductivity type of the first doped silicon layer and the doped layer can both be the same as the conductivity type of the semiconductor substrate. Furthermore, the second region of the semiconductor substrate does not contain a second doping element. In this case, a high-low junction can be formed between each adjacent pair of the semiconductor substrate, the doped layer, and the first doped silicon layer. Under the built-in electric field of the high-low junction, the carrier collection efficiency of the first doped silicon layer can be further improved, thereby further enhancing the conversion efficiency of the back contact cell. Since the second region of the semiconductor substrate does not contain a second doping element with a conductivity type opposite to that of the doped layer, it ensures that the doped layer will not make electrical contact with the inwardly expanding doped layer with a conductivity type opposite to its own, thus preventing a high risk of leakage. It also reduces the recombination rate of electrons and holes within the semiconductor substrate, thereby ensuring a high conversion efficiency for the back contact cell.

[0119] It should be noted that in the actual manufacturing process, the doped layer can be formed separately in the first region and overlapping region of the semiconductor substrate through diffusion or ion implantation before the formation of the tunneling passivation layer and the first doped silicon layer. In this case, the formation depth of the doped layer in the semiconductor substrate and the doping concentration of the first doped element within it can be controlled by controlling the concentration, time, and temperature of the diffusion or ion implantation. Alternatively, the doped layer can be formed simultaneously with the formation of the tunneling passivation layer and the first doped silicon layer by the diffusion of the first doped element within the first doped silicon layer into the semiconductor substrate. In this case, the formation range of the doped layer in the semiconductor substrate and the doping concentration of the first doped element within it can be controlled by controlling the thickness of the tunneling passivation layer, the thickness and doping concentration of the first doped silicon layer, as well as the time and temperature during doping of the first doped silicon layer.

[0120] Furthermore, along the direction from the first surface to the second surface, the doping concentration of the second doped element with the same conductivity type as the second doped silicon layer is the same in each part of the second region of the semiconductor substrate. This can be achieved by controlling the thickness of the intrinsic silicon layer, the thickness and doping concentration of the second doped silicon layer, and the time and temperature during doping of the second doped silicon layer, so as to avoid or prevent the second doped element in the second doped silicon layer from spreading into the second region of the semiconductor substrate.

[0121] In one example, as shown in Figures 10 and 11, the aforementioned back-contact battery may further include a transparent conductive layer 23. This transparent conductive layer 23 covers the side of the first doped silicon layer 16 and the second doped silicon layer 18 facing away from the semiconductor substrate 11 to improve carrier collection efficiency. Furthermore, the transparent conductive layer 23 has a through-hole insulating trench 24 to disconnect the portion of the transparent conductive layer 23 corresponding to the first doped silicon layer 16 from the portion corresponding to the second doped silicon layer 18, preventing short circuits. Specifically, along the width direction of the overlapping region 14, both sides of the insulating trench 24 may be located above the overlapping region 14; or, one side of the insulating trench 24 may be located above the overlapping region 14, and the other side may be located above the first region 12; or, one side of the insulating trench may be located above the overlapping region, and the other side may be located above the second region; or, one side of the insulating trench may be located above the first region, and the other side may be located above the second region.

[0122] Specifically, this application does not impose specific limitations on the material and thickness of the transparent conductive layer, as long as it can be applied to the back contact battery provided in this application. For example, the material of the transparent conductive layer may include at least one of fluorine-doped tin oxide, aluminum-doped zinc oxide, tin-doped indium oxide, tungsten-doped indium oxide, molybdenum-doped indium oxide, cerium-doped indium oxide, and indium hydroxide. The thickness of the transparent conductive layer may be greater than or equal to 10 nm and less than or equal to 200 nm. The surface of the transparent conductive layer covering the groove on the side facing away from the semiconductor substrate may be flush with, or higher than or lower than, the side of the doped layer facing away from the tunneling passivation layer.

[0123] Regarding the width of the insulating trench, as shown in Figure 10, when both sides of the insulating trench 24 are located above the overlapping region 14, the etching amount required to open the insulating trench 24 into the transparent conductive layer 23 is smaller, which is beneficial to improving etching capacity. Furthermore, in this case, if the second doped silicon layer 18 on the overlapping region 14 can be electrically contacted with the first doped silicon layer 16 through the intrinsic silicon layer 17, and the second doped silicon layer 18 on the overlapping region 14 is covered with a transparent conductive layer 23 extending from the second region 13, a reverse leakage structure can be formed, reducing the risk of hot spots in the back contact battery. As shown in Figure 11, when one side of the insulating trench 24 can be located above the overlapping region 14, and the other side can be located above the second region 13, although the etching amount required to open the insulating trench 24 is larger, the insulating trench 24 can completely isolate the portions of the transparent conductive layer 23 corresponding to the second region 13 and those corresponding to the first region 12, significantly reducing the risk of leakage and improving the conversion efficiency of the back contact battery. As can be seen from the above, the insulating groove 24 has different effects with different widths. The width of the insulating groove 24 can be set according to the needs of different application scenarios, thereby improving the applicability of the back contact battery provided in this application embodiment in different application scenarios.

[0124] Furthermore, as shown in Figures 11 and 12, when the back contact battery also includes a transparent conductive layer 23, the portion of the transparent conductive layer 23 with the same carrier conductivity type as the second doped silicon layer 18 does not overlap with the doped layer 19 along the thickness direction of the semiconductor substrate 11. In this case, the transparent conductive layer 23 has good conductivity, which can improve the carrier collection efficiency. Additionally, the absence of overlap between the portion of the transparent conductive layer 23 with the second doped silicon layer 18 and the doped layer 19 along the thickness direction of the semiconductor substrate 11 prevents the portion of the transparent conductive layer 23 with the same carrier conductivity type as the second doped silicon layer 18 from overlapping with the doped layer 19, which is doped with a first dopant element with a conductivity type opposite to that of the second doped silicon layer 18, thus preventing an increase in leakage risk and ensuring high electrical reliability of the back contact battery.

[0125] In some cases, as shown in FIG12, the back contact battery provided in this application embodiment may further include a surface passivation layer 25 and an antireflection layer 26 sequentially stacked on the second surface along the thickness direction of the semiconductor substrate 11, so as to reduce the carrier recombination rate on the second surface side and facilitate more light to enter the semiconductor substrate 11 from the second surface side, thereby further improving the conversion efficiency of the back contact battery provided in this application embodiment. In this application embodiment, the material and thickness of the surface passivation layer 25 and the antireflection layer 26 are not specifically limited.

[0126] For example, the surface passivation layer may include at least one of a silicon oxide layer, an aluminum oxide layer, and an intrinsic silicon layer.

[0127] For example, the antireflection layer may include a silicon nitride layer and / or a silicon oxynitride layer.

[0128] In realizing the concept of this application, it was also discovered that by appropriately setting various layers on the semiconductor substrate, the risk of hot spots in the back contact battery can be reduced and the burn-out resistance of the back contact battery can be improved.

[0129] During actual use, back-contact solar cells may be obstructed by objects such as bird droppings, leaves, and dust. This obstruction can cause the cells to overheat and develop hot spots. If the temperature of these hot spots exceeds a certain threshold, it can lead to problems such as photovoltaic module delamination, backsheet burning, and glass shattering, ultimately rendering the entire solar cell unusable. In severe cases, it can even pose a fire risk.

[0130] Referring to Figures 13-27, a back-contact battery is provided in some embodiments of this application. For ease of description of embodiments related to reducing the risk of hot spots in back-contact batteries, the concepts of a first sub-region, a second sub-region, and a third sub-region are introduced herein. The concepts of a first region, an overlapping region, and a second region have been described above. On a first surface of a semiconductor substrate, a continuous first region, an overlapping region, and a second region are divided into a first sub-region, a second sub-region, and a third sub-region located between the first sub-region and the second sub-region. The first sub-region corresponds to the aforementioned first region and optionally the aforementioned overlapping region, while the second and third sub-regions correspond to the aforementioned second region.

[0131] As shown in Figure 13, the back contact battery includes: a semiconductor substrate 11, a first doped silicon layer 16, a second doped silicon layer 18, and a first transparent conductive layer 28. The first transparent conductive layer 28 corresponds to the transparent conductive layer 23 overlying the second doped silicon layer 18 described above with reference to Figures 10-12. The semiconductor substrate 11 includes a first surface and a second surface opposite to each other. The first surface includes alternating first sub-regions 32 and second sub-regions 33, and a third sub-region 34 located between the first sub-regions 32 and 33. The first doped silicon layer 16 is disposed on the first sub-region 32. The doping element in the first doped silicon layer 16 is a first doping element. A doped layer 19 is disposed within the first sub-region 32 and the third sub-region 34 of the semiconductor substrate 11.

[0132] In some embodiments, the doping concentration of the first dopant element in the doped layer 19 is greater than the doping concentration of the first dopant element in the second sub-region 33 of the semiconductor substrate 11. A second doped silicon layer 18 is disposed in the second sub-region 33 and extends to cover at least a portion of the doped layer 19. The second doped silicon layer 18 has the opposite conductivity type to the first doped silicon layer 16.

[0133] In some embodiments, in the third region 34, the second doped silicon layer 18 is electrically connected to the doped layer 19. A first transparent conductive layer 28 covers the second doped silicon layer 18 located in the second region 33, and the second doped silicon layer 18 located in the third region 34 is covered by the first transparent conductive layer 28 extending from the second region 33.

[0134] It is worth noting that the embodiments described with reference to Figures 13-27 can be used in conjunction with the embodiments with reference to Figures 1-12, or both can be used alone. As described above, on the first surface of the semiconductor substrate, a continuous first region, an overlapping region, and a second region are divided into a first sub-region, a second sub-region, and a third sub-region located between the first sub-region and the second sub-region. The first sub-region corresponds to the aforementioned first region and the optional overlapping region, and the second and third sub-regions correspond to the aforementioned second region. In the case where the embodiments described with reference to Figures 13-27 can be used alone with the embodiments with reference to Figures 1-12, the overlapping regions may not exist in the embodiments described with reference to Figures 13-27, that is, there may not be a region where the tunneling passivation layer 15 and the first doped silicon layer 16, the intrinsic silicon layer 17, and the second doped silicon layer 18 are simultaneously provided. For example, there are no overlapping regions in Figures 13-18, and there is a gap between the first doped silicon layer 16 and the second doped silicon layer 18.

[0135] With the above technical solution, when the back contact battery is in operation, the first and second doped silicon layers with opposite conductivity types can effectively shunt and collect charge carriers, which is beneficial for forming photocurrent. The first transparent conductive layer covering the second doped silicon layer has high conductivity, which can promptly export the charge carriers collected by the second doped silicon layer, reducing the carrier recombination rate and improving the conversion efficiency of the back contact battery. Furthermore, as shown in Figure 13, the back contact battery also includes a doped layer 19 disposed in the first sub-region 32 and the third sub-region 34 of the semiconductor substrate 11. Since the first doped silicon layer 16 is disposed on the first sub-region 32, the portion of the doped layer 19 located in the third sub-region 34 can be exposed outside the first doped silicon layer 16. Furthermore, the doping concentration of the first doped element in the doped layer 19 is greater than that of the first doped element in the second sub-region 33 of the semiconductor substrate 11. Therefore, the doping concentration of the first doped element in the doped layer 19 is higher, and the doped element in the first doped silicon layer 16 is also the first doped element. Consequently, the doped layer 19 and the first doped silicon layer 16 have the same conductivity type, while the doped layer 19 and the second doped silicon layer 18 have opposite conductivity types. Additionally, the second doped silicon layer 18 is not only disposed on the second sub-region 33 but also extends to cover at least a portion of the doped layer 19. In the third sub-region 34, the second doped silicon layer 18 not only passivates the semiconductor substrate 11, reducing the number of surface defects in the third sub-region 34 and improving the conversion efficiency of the back contact battery, but it is also electrically connected to the doped layer 19, forming a built-in diode with a low reverse breakdown voltage. Furthermore, a first transparent conductive layer 28 extending from the second sub-region 33 covers the second doped silicon layer 18 located in the third sub-region 34. Based on this, when the back contact battery is blocked, the leakage current can pass through the first doped silicon layer 16, the doped layer 19, and the second doped silicon layer 18, then through the first transparent conductive layer 28, extending from the second sub-region 33 to cover the portion above the doped layer 19, and finally being discharged through the electrode that partially contacts the second sub-region 33 corresponding to the first transparent conductive layer 28, reducing the risk of hot spots on the back contact battery. As can be seen from the above, the leakage current needs to be conducted between the first doped silicon layer 16 and the second doped silicon layer 18 through the doped layer 19 disposed within the semiconductor substrate 11. Compared to transmission through the doped semiconductor layer, the semiconductor substrate 11 has stronger lateral conductivity. Therefore, the back contact battery provided in this embodiment is more conducive to the transmission of reverse leakage current when blocked, reducing reverse leakage current transmission loss and improving the back contact battery's resistance to burn-out. Furthermore, the leakage current not only needs to flow through the PN junction formed by the doped layer 19 and the second doped silicon layer 18 with opposite conductivity types, but also needs to flow through the high-low junction formed by the doped layer 19 and the first doped silicon layer 16 with the same conductivity type.Compared with the scheme where leakage current only flows through the PN junction, the back contact battery provided in this application embodiment, during the process of being shielded, is more conducive to controlling the magnitude of reverse leakage current under the action of two electric fields of the PN junction and the high and low junctions, reducing the carrier recombination loss of the back contact battery, balancing the hot spot risk and conversion efficiency of the back contact battery, and improving the working performance of the back contact battery.

[0136] The preceding text has described the materials and conductivity types of the semiconductor substrate, as well as the methods for determining the extent of the first, second, and overlapping regions. Regarding the third sub-region, its extent is determined after the extents of the first, overlapping, and second regions on the first surface are established. Along the alternating distribution direction of the first and second sub-regions, i.e., along the width direction of the third sub-region, the width of the third sub-region affects the size of the leakage contact area between the doped layer and the second doped silicon layer. Specifically, when the ratio between the width of the second doped silicon layer extending into the third sub-region and the width of the third sub-region is constant, a larger width of the third sub-region results in a larger leakage contact area between the doped layer and the second doped silicon layer, leading to a lower hot spot risk for the back contact battery. Conversely, a smaller width of the third sub-region results in a smaller leakage contact area between the doped layer and the second doped silicon layer, leading to a higher conversion efficiency for the back contact battery. Based on this, the width of the third sub-region can be determined according to the requirements for hot spot risk and conversion efficiency of the back contact battery in actual application scenarios; no specific limitations are made here.

[0137] For example, along the distribution direction of the alternation interval between the first and second sub-regions, that is, along the width direction of the third sub-region, the width of the third sub-region can be greater than or equal to 1 nm and less than or equal to 2 μm. For example, the width of the third sub-region can be 1 nm, 10 nm, 50 nm, 100 nm, 200 nm, 300 nm, 400 nm, 500 nm, 800 nm, 1 μm, 1.2 μm, 1.5 μm, 1.8 μm, or 2 μm, etc. In this scenario, if there are few obstructions such as sand and dust in the installation environment of the back contact battery, the width of the third sub-region can be set to a smaller range. This results in a smaller area of ​​the doped layer exposed in the third sub-region, which helps reduce the leakage contact area between the doped layer and the second doped silicon layer, thus improving the conversion efficiency of the back contact battery. Conversely, if there are many obstructions such as sand and dust in the installation environment, the width of the third sub-region can be set to a larger range. This results in a larger area of ​​the doped layer exposed on the surface of the third sub-region, which helps increase the leakage contact area between the doped layer and the second doped silicon layer, further improving the burn-out resistance of the back contact battery. Therefore, by controlling the width of the third sub-region, the leakage contact area and leakage current of the doped layer and the second doped silicon layer can be adjusted, improving the applicability of the back contact battery in different application scenarios. Simultaneously, it facilitates a balance between the conversion efficiency and hot spot risk of the back contact battery, thereby improving its performance.

[0138] Secondly, as shown in FIG13, on one side of the first surface of the semiconductor substrate 11, the surface of the second sub-region 33 can be flush with the surface of the third sub-region 34. In this case, the portion of the second doped silicon layer 18 extending from the second sub-region 33 will only make electrical contact with the surface of the doped layer 19 at the surface of the third sub-region 34. Alternatively, as shown in FIG15, the surface of the second sub-region 33 can also be recessed into the semiconductor substrate 11 relative to the surface of the third sub-region 34 to form a groove 20; and the portion of the second doped silicon layer 18 corresponding to the second sub-region 33 is located within the groove 20. In this case, at least a portion of the doped layer 19 near the sidewall of the second sub-region 33 can be exposed through the groove 20. In this case, when the second doped silicon layer 18 extends sequentially from the bottom surface of the groove 20 to cover the sidewalls of the groove 20 and the surface of the third sub-region 34, the second doped silicon layer 18 can not only be electrically connected to the doped layer 19 at the surface of the third sub-region 34 along the thickness direction of the semiconductor substrate 11, but also be electrically connected at at least a portion of the sidewalls of the groove 20. This is beneficial for increasing the leakage contact area and leakage current between the second doped silicon layer 18 and the doped layer 19, further reducing the risk of hot spots in the back contact battery. Simultaneously, in the actual manufacturing process, if the doped layer 19 is formed by inward expansion during the formation of the first doped silicon layer 16, then forming the groove 20 in the second sub-region 33 can also remove at least a portion of the doped layer 19 formed in the second sub-region 33 during the formation of the first doped silicon layer 16, reducing carrier recombination between the doped layer 19 and the second doped silicon layer 18 in the second sub-region 33, thus improving the conversion efficiency of the back contact battery.

[0139] When the depth of the recess 20 indented into the semiconductor substrate 11 relative to the surface of the first sub-region 32 is greater than the doping depth of the doped layer 19 along the thickness direction of the semiconductor substrate 11, all portions of the sidewall of the doped layer 19 near the second sub-region 33 along the thickness direction of the semiconductor substrate 11 can be exposed through the recess 20. This further increases the leakage contact area and leakage current between the second doped silicon layer 18 and the doped layer 19, further reducing the risk of hot spots in the back contact battery. Furthermore, in actual manufacturing, if the doped layer 19 is formed by inward expansion during the formation of the first doped silicon layer 16, then when the depth of the recess 20 indented into the semiconductor substrate 11 relative to the surface of the first sub-region 32 is greater than the doping depth of the doped layer 19, it indicates that the doped layer 19 formed in the second sub-region 33 has been completely removed. This reduces carrier recombination in the second sub-region 33, resulting in a higher carrier collection efficiency for the second doped silicon layer 18 located in the second sub-region 33, which is beneficial for improving the conversion efficiency of the back contact battery.

[0140] Alternatively, along the thickness direction of the semiconductor substrate, the depth to which the groove is recessed into the semiconductor substrate relative to the surface of the first region can be less than or equal to the doping depth of the doped layer. As mentioned earlier, the recess depth of the groove not only affects the area of ​​the sidewalls of the doped layer near the second region that can be exposed, thus affecting the hot spot risk and conversion efficiency of the back contact battery, but also, when the doped layer is formed by inward expansion during the formation of the first doped silicon layer, the recess depth of the groove also affects the doping concentration of the first dopant element in the second region of the semiconductor substrate and the carrier recombination rate of the back contact battery. Based on this, the specific recess depth of the groove can be determined according to the doping depth of the doped layer in the actual application scenario and the requirements for the hot spot risk and conversion efficiency of the back contact battery, and is not specifically limited here.

[0141] For example, the height difference between the bottom surface of the groove and the surface of the third sub-region can be greater than or equal to 200 nm and less than or equal to 20 μm. For instance, the height difference between the bottom surface of the groove and the surface of the third sub-region can be 200 nm, 300 nm, 500 nm, 800 nm, 1 μm, 2 μm, 5 μm, 8 μm, 10 μm, 15 μm, or 20 μm, etc. In this case, the height difference between the bottom surface of the groove and the surface of the third sub-region is within the aforementioned range. This helps prevent a small groove depth due to a small height difference, which would result in a small exposed area of ​​the doped layer near the sidewall of the second region. This allows for a relatively large leakage contact area between the second doped silicon layer and the doped layer at the sidewall of the groove, reducing the risk of hot spots. Secondly, if the doped layer is formed by inward expansion during the formation of the first doped silicon layer, it also prevents a small removal amount of the doped layer formed in the second region when the groove is created, further reducing carrier recombination between the doped layer and the second doped silicon layer in the second region, thus improving the conversion efficiency of the back contact cell. Furthermore, it also helps prevent a large groove depth due to a large height difference, allowing the portion of the semiconductor substrate corresponding to the second region to have a larger light absorption depth, further improving the conversion efficiency of the back contact cell.

[0142] Regarding the surface height of the first and third sub-regions in the first surface, as shown in Figure 16, the surface of the third sub-region 34 can be flush with the surface of the first sub-region 32. Alternatively, as shown in Figure 17, the surface of the third sub-region 34 can also be recessed into the semiconductor substrate 11 relative to the surface of the first sub-region 32, and the recess depth relative to the surface of the first sub-region 32 is less than the doping depth of the doped layer 19. In this case, under the same conditions, when the surface of the third sub-region 34 is also recessed into the semiconductor substrate 11 relative to the surface of the first sub-region 32, it is beneficial to reduce the height difference between the surface of the third sub-region 34 and the bottom surface of the groove 20, which is beneficial to the coverage of the second doped silicon layer 18 on the sidewall of the groove 20 and the surface of the third sub-region 34, improving the electrical connection performance between the second doped silicon layer 18 and the doped layer 19, further reducing the hot spot risk of the back contact battery, and also improving the passivation effect of the second doped silicon layer 18 on the sidewall of the groove 20 and the surface of the third sub-region 34, thereby improving the conversion efficiency of the back contact battery. Furthermore, in the actual manufacturing process, if the doped layer 19 is formed by inward expansion during the formation of the first doped silicon layer 16, the doping concentration of the first doped element at the surface of the third region 34 of the doped layer 19 is relatively high. As the doping depth increases, the doping concentration of the first doped element in the doped layer 19 will decrease. Therefore, when the surface of the third region 34 is recessed into the semiconductor substrate 11 relative to the surface of the first region 32, the doping concentration of the doped layer 19 at the surface of the third region 34 can be reduced, which is beneficial to reducing the leakage current between the doped layer 19 and the second doped silicon layer 18, and further improving the conversion efficiency of the back contact battery. At the same time, the recess depth of the surface of the third region 34 into the semiconductor substrate 11 relative to the surface of the first region 32 is less than the doping depth of the doped layer 19, which can ensure that the doped layer 19 can be electrically connected to the second doped silicon layer 18 at the surface of the third region 34, so that the doped layer 19 and the second doped silicon layer 18 have a large leakage contact area, which is beneficial to the back contact battery having a high resistance to burn-out.

[0143] For example, the height difference between the surface of the third sub-region and the surface of the first sub-region can be greater than or equal to 10 nm and less than or equal to 2 μm. The height difference between the surface of the third sub-region and the surface of the first sub-region can be 10 nm, 50 nm, 100 nm, 300 nm, 500 nm, 800 nm, 1 μm, 1.2 μm, 1.4 μm, 1.5 μm, 1.8 μm, or 2 μm, etc. In this case, when the height difference between the surface of the third sub-region and the surface of the first sub-region is within the above range, it can prevent a large height difference between the surface of the third sub-region and the bottom surface of the groove due to a small height difference, which would lead to poor formation quality of the second doped silicon layer on the sidewall of the groove and the surface of the third sub-region. This improves the electrical connection performance between the second doped silicon layer and the doped layer, further reduces the risk of hot spots on the back contact battery, and also helps to improve the passivation effect of the second doped silicon layer on the sidewall of the groove and the surface of the third sub-region. Furthermore, this also prevents the doping depth of the doped layer in the third region from being too shallow due to the large height difference, thus reducing the transmission loss of leakage current at the doped layer. Additionally, in actual manufacturing, if the doped layer is formed by inward expansion during the formation of the first doped silicon layer, then, all other things being equal, the greater the height difference between the surface of the third region and the surface of the first region, the shallower the doping depth of the doped layer in the third region, and the lower its doping concentration at the surface of the third region. This, in turn, affects the magnitude of the leakage current between the doped layer and the second doped silicon layer in the third region. Based on this, depending on the requirements of different practical application scenarios, if there are few obstructions such as sand and dust in the installation environment of the back contact battery, the aforementioned height difference can be set within a larger range. This results in a lower doping concentration of the doped layer at the surface of the third region, which helps reduce the leakage current of the doped layer and the second doped silicon layer, thus promoting higher conversion efficiency of the back contact battery. Conversely, if there are many obstructions such as sand and dust in the installation environment, the aforementioned height difference can be set within a smaller range. This results in a higher doping concentration of the doped layer at the surface of the third region, which helps increase the leakage current of the doped layer and the second doped silicon layer, further improving the burn-out resistance of the back contact battery. In summary, by controlling the height difference between the surface of the third region and the surface of the first region, the leakage current of the doped layer and the second doped silicon layer can be controlled, improving the applicability of the back contact battery in different application scenarios.

[0144] Regarding the doping concentration of the first dopant element in the portion of the doped layer located within the third sub-region, it is understandable that the doping concentration of the first dopant element at the surface of the doped layer corresponding to the third sub-region affects the conductivity of the doped layer. It is understood that a lower doping concentration of the first dopant element at the surface of the doped layer corresponding to the third sub-region results in relatively lower conductivity of the doped layer, leading to higher reverse leakage current transmission losses, but at the same time, higher conversion efficiency of the back contact battery. Conversely, a higher doping concentration of the first dopant element at the surface of the doped layer corresponding to the third sub-region results in relatively higher conductivity of the doped layer, which is beneficial for reverse leakage current transmission, and at this time, the risk of hot spots on the back contact battery is lower. Furthermore, as shown in Figure 17, in the actual manufacturing process, when the first dopant element in the doped layer 19 is diffused into the doped layer 19 from the first dopant element in the first doped silicon layer 16, whether the second sub-region 33 has a groove 20 and the size of the groove 20's recess depth will also affect the doping concentration of the first dopant element at the surface of the doped layer 19 corresponding to the third sub-region 34. Therefore, the doping concentration of the first dopant element at the surface of the doped layer 19 corresponding to the third sub-region 34 can be determined according to the recess depth of the groove 20 in the actual application scenario and the requirements for hot spot risk and conversion efficiency of the back contact battery. No specific limitation is made here.

[0145] For example, the doping concentration of the first dopant element at the surface of the doped layer corresponding to the third sub-region can be less than the doping concentration of the first dopant element at the surface of the doped layer corresponding to the first sub-region. In this case, it is beneficial to reduce the conduction characteristics at the surface of the doped layer corresponding to the third sub-region, and to control the leakage current between the doped layer and the second doped silicon layer, thereby improving the conversion efficiency of the back contact cell. Alternatively, the doping concentration of the first dopant element at the surface of the doped layer corresponding to the third sub-region can also be equal to the doping concentration of the first dopant element at the surface of the doped layer corresponding to the first sub-region.

[0146] For example, the doping concentration of the first dopant element at the surface of the doped layer corresponding to the third sub-region can be greater than or equal to 8 × 10⁻⁶. 9 / cm 3 And less than or equal to 9 × 10 20 / cm 3 For example, the doping concentration of the first dopant element at the surface of the third sub-region of the doped layer can be 8 × 10⁻⁶. 9 / cm 3 9×10 9 / cm 3 1×10 10 / cm 3 1×10 11 / cm 3 1×10 12 / cm 3 1×10 13 / cm 3 1×10 15 / cm 3 1×10 17 / cm 3 1×10 19 / cm 3 Or 9×10 20 / cm 3 In this case, if there are few obstructions such as sand and dust in the installation environment of the back contact battery, the doping concentration of the first dopant element at the surface of the doped layer corresponding to the third sub-region can be set within a smaller range. This results in relatively low conductivity of the doped layer at the surface of the third sub-region, which helps to reduce the leakage current of the doped layer and the second doped silicon layer, thus improving the conversion efficiency of the back contact battery. Conversely, if there are many obstructions such as sand and dust in the installation environment of the back contact battery, the doping concentration of the first dopant element at the surface of the doped layer corresponding to the third sub-region can be set within a larger range. This results in relatively high conductivity of the doped layer at the surface of the third sub-region, which helps to increase the leakage current of the doped layer and the second doped silicon layer, further improving the burn-out resistance of the back contact battery. Therefore, by controlling the doping concentration of the first dopant element at the surface of the doped layer corresponding to the third sub-region, the leakage current of the doped layer and the second doped silicon layer can be controlled, improving the applicability of the back contact battery in different application scenarios. Simultaneously, it facilitates a balance between the conversion efficiency and hot spot risk of the back contact battery, improving its overall performance.

[0147] As mentioned above, the doping concentration of the second doped element can be the same in each portion of the second region of the semiconductor substrate along the direction from the first surface to the second surface. In this case, there is no inward doped layer with the same conductivity type as the second doped silicon layer in the second region of the semiconductor substrate. This not only prevents the doped layer from making electrical contact with the inward doped layer with the opposite conductivity type, which would lead to an excessively high carrier recombination rate and thus benefit the back contact battery to have a higher conversion efficiency, but also prevents the doping concentration of the doped layer in the third region from being low due to the inward doped layer also forming in the portion of the second doped silicon layer covering the third region. This would benefit the back contact battery to have a higher resistance to burn-out.

[0148] In terms of the formation range, as shown in Figures 17 and 18, the edge of the second doped silicon layer 18 extending from the second sub-region 33 can be located within the third sub-region 34. At this time, in the third sub-region 34, the second doped silicon layer 18 can cover only a part of the doped layer 19 or cover the entire doped layer 19.

[0149] Alternatively, as shown in Figure 19, the second doped silicon layer 18 extending from the second sub-region 33 can also extend into the first sub-region 32. In this case, in the first sub-region 32, the second doped silicon layer 18 can be electrically connected to the first doped silicon layer 16 to increase the leakage contact area and further reduce the risk of hot spots on the back contact battery. The extension width of the second doped silicon layer 18 within the first sub-region 32 can be set according to actual needs and is not specifically limited here. Alternatively, as shown in Figure 20, the back contact battery can also include an insulating layer 27, which is disposed between the first doped silicon layer 16 and the second doped silicon layer 18 located in the first sub-region 32. This insulating layer can electrically insulate the two layers, which helps control the size of the leakage contact area and allows the back contact battery to have higher conversion efficiency. The material and thickness of the insulating layer 27 can be set according to actual needs and are not specifically limited here. For example, the material of the insulating layer 27 can include at least one of silicon oxide, silicon nitride, or aluminum oxide.

[0150] In terms of the formation range, the formation range of the first transparent conductive layer can be determined based on the formation range of the second doped silicon layer and the requirements for hot spot risk and conversion efficiency of the back contact battery in actual application scenarios. No specific limitation is made here.

[0151] For example, as shown in Figures 17 and 18, when the edge of the second doped silicon layer 18 extending from the second sub-region 33 is located within the third sub-region 34, the edge of the first transparent conductive layer 28 extending from the second sub-region 33 is also located within the third sub-region 34. In this case, in the third sub-region 34, the edge of the first transparent conductive layer 28 can be flush with the edge of the second doped silicon layer 18; or, the edge of the first transparent conductive layer 28 can be recessed inward relative to the edge of the second doped silicon layer 18 along the direction from the first sub-region 32 to the second sub-region 33. The distance of this recess can be determined according to the requirements of hot spot risk and conversion efficiency of the back contact battery in the actual scenario, and is not specifically limited here.

[0152] For example, as shown in Figures 19, 20, and 21, when the second doped silicon layer 18 extending from the second sub-region 33 continues to extend into the first sub-region 32, the edge of the first transparent conductive layer 28 extending from the second sub-region 33 can be located within the third sub-region 34. In this case, in the third sub-region 34, the first transparent conductive layer 28 can cover only a portion of the doped layer 19, or it can cover the entire doped layer 19.

[0153] Alternatively, as shown in Figures 22 and 23, when the second doped silicon layer 18 extending from the second sub-region 33 continues to extend into the first sub-region 32, the first transparent conductive layer 28 extending from the second sub-region 33 can also continue to extend into the first sub-region 32, and in the first sub-region 32, the first transparent conductive layer 28 extending from the second sub-region 33 is located on the second doped silicon layer 18. In this case, in the first sub-region 32, the edge of the first transparent conductive layer 28 can be flush with the edge of the second doped silicon layer 18; or, the edge of the first transparent conductive layer 28 can also be recessed inward relative to the edge of the second doped silicon layer 18 along the direction from the first sub-region 32 to the third sub-region 34. The distance of this recess can be determined according to the requirements of hot spot risk and conversion efficiency of the back contact battery in the actual scenario, and is not specifically limited here. As shown in Figure 24, when both the second doped silicon layer 18 extending from the second sub-region 33 and the first transparent conductive layer 28 extending from the second sub-region 33 continue to extend into the first sub-region 32, the back contact battery may also include the aforementioned insulating layer 27, in order to control the size of the leakage contact area and enable the back contact battery to have a higher conversion efficiency; at this time, the extension width of the second doped silicon layer 18 and the first transparent conductive layer 28 on the first sub-region 32 can be determined according to actual manufacturing requirements, and is not specifically limited here.

[0154] It is worth noting that, as shown in Figures 17 to 24, there are multiple instances of the edge positioning of the second doped silicon layer 18 extending from the second sub-region 33 and the first transparent conductive layer 28 extending from the second sub-region 33. This helps to reduce the difficulty of the manufacturing process and also allows the extension coverage of the second doped silicon layer 18 and the first transparent conductive layer 28 to be determined according to the requirements of different actual application scenarios (e.g., when the edges of the second doped silicon layer 18 and the first transparent conductive layer 28 extending from the second sub-region 33 are both located within the third sub-region 34, the leakage between the first doped silicon layer 16, the doped layer 19, and the second doped silicon layer 18 is...). The current is relatively small. However, when the second doped silicon layer 18 extending from the second sub-region 33 and the first transparent conductive layer 28 extending from the second sub-region 33 both continue to extend into the first sub-region 32, and when the first transparent conductive layer 28 extending from the second sub-region 33 is located on the second doped silicon layer 18 in the first sub-region 32, it is beneficial to increase the leakage current between the first doped silicon layer 16, the doped layer 19 and the second doped silicon layer 18, thereby realizing the control of the leakage current between the first doped silicon layer 16, the doped layer 19 and the second doped silicon layer 18, realizing the balanced control of the conversion efficiency and hot spot risk of the back contact battery, and improving the working performance of the back contact battery.

[0155] Alternatively, the first doped silicon layer can be in direct ohmic contact with the corresponding electrode; or, as shown in FIG25, the back contact battery may further include a second transparent conductive layer 29, which covers the first doped silicon layer 16. The second transparent conductive layer 29 corresponds to the transparent conductive layer 23 covering the first doped silicon layer 16 described above with reference to FIGS. 10-12. The second transparent conductive layer 29 and the first transparent conductive layer 28 are physically insulated. In this case, the presence of the second transparent conductive layer 29 can reduce the contact barrier between the first doped silicon layer 16 and the corresponding electrode, and reduce the carrier transport loss between the first doped silicon layer 16 and the corresponding electrode. The material and thickness of the second transparent conductive layer 29 can refer to the material and thickness of the first transparent conductive layer 28 described above, and will not be repeated here. In practical applications, the materials of the first transparent conductive layer 28 and the second transparent conductive layer 29 may be the same or different. The first transparent conductive layer 28 and the second transparent conductive layer 29 may be integrally continuous, that is, they are formed simultaneously using the same manufacturing process; or, the first transparent conductive layer 28 and the second transparent conductive layer 29 may be formed separately in different operation steps.

[0156] In the case where the edges of the second doped silicon layer extending from the second region and the first transparent conductive layer extending from the second region are both located within the first sub-region, and the back contact cell also includes the second transparent conductive layer, as shown in FIG25, the second transparent conductive layer 29 may only cover the first doped silicon layer 16, and the edge of the second transparent conductive layer 29 near the third sub-region 34 and the second doped silicon layer 18 may be spaced apart along the arrangement direction of the first sub-region 32 and the second sub-region 33. Alternatively, as shown in FIG26, the second transparent conductive layer 29 may also extend onto the second doped silicon layer 18, the portion of the second doped silicon layer 18 located on the first sub-region 32 is continuously distributed, and the edge of the second transparent conductive layer 29 near the third sub-region 34 and the first transparent conductive layer 28 are spaced apart along the arrangement direction of the first sub-region 32 and the second sub-region 33. Alternatively, as shown in Figure 27, a through insulating trench 24 is provided in the second doped silicon layer 18 located in the first sub-region 32. The insulating trench 24 divides the second doped silicon layer 18 located in the first sub-region 32 into a first doped portion 30 and a second doped portion 31. The second doped portion 31 is closer to the second sub-region 33 than the first doped portion 30, and the second transparent conductive layer 29 extends to the first doped portion 30.

[0157] It is worth noting that when the edges of the second doped silicon layer extending from the second region and the first transparent conductive layer extending from the second region are both located within the first sub-region, a larger leakage contact area can be achieved between the second doped silicon layer and the doped layer, reducing the risk of hot spots in the back contact battery. Furthermore, the second doped silicon layer located in the first sub-region has a through-hole insulating trench to ensure physical insulation between the second and first transparent conductive layers, preventing short circuits. The second transparent conductive layer also extends away from the first doped portion of the second region, ensuring a large coverage area on the first doped silicon layer, which facilitates carrier collection and conduction, further improving the conversion efficiency of the back contact battery. The width of the insulating trench can be set according to actual needs and is not specifically limited here.

[0158] Although various embodiments have been described above with reference to the accompanying drawings, this does not mean that the features in the various embodiments cannot be used advantageously in combination. For example, possible combinations may be as follows:

[0159] In some embodiments, this application also provides a back contact battery, comprising: a semiconductor substrate, a tunneling passivation layer, a first doped silicon layer, an intrinsic silicon layer, a second doped silicon layer, a doped layer, and a first transparent conductive layer. The semiconductor substrate includes opposing first and second surfaces. The first surface includes alternating first and second regions, and an overlapping region located between the first and second regions. Along the thickness direction of the semiconductor substrate, the tunneling passivation layer and the first doped silicon layer are sequentially stacked on the first region and the overlapping region. Along the thickness direction of the semiconductor substrate, the intrinsic silicon layer and the second doped silicon layer are sequentially stacked on the second region. Furthermore, the stacked intrinsic silicon layer and the second doped silicon layer extend from the second region to the tunneling passivation layer and the first doped silicon layer located in the overlapping region. The conductivity type of the second doped silicon layer is opposite to that of the first doped silicon layer. The doped layer is disposed in the first region and the overlapping region of the semiconductor substrate. The doping concentration of the first doping element in the doped layer, which has the same conductivity type as the first doped silicon layer, is greater than the doping concentration of the first doping element in the second region of the semiconductor substrate. Along the direction from the first surface to the second surface, the doping concentration of the second doping element, which has the same conductivity type as the second doped silicon layer, is the same in each portion of the second region of the semiconductor substrate. The continuous first region, overlapping region, and second region are divided into a first sub-region, a second sub-region, and a third sub-region located between the first and second sub-regions. The first sub-region corresponds to the first region and the overlapping region, and the second and third sub-regions correspond to the second region. A doped layer is also disposed in the third sub-region, and the second doped silicon layer extends to cover at least a portion of the doped layer. In the third sub-region, the second doped silicon layer is electrically connected to the doped layer. A first transparent conductive layer covers the second doped silicon layer located in the second sub-region, and the second doped silicon layer located in the third sub-region is covered by the first transparent conductive layer extending from the second sub-region.

[0160] In the above technical solution, a doped layer is further disposed in the first region and the overlapping region of the semiconductor substrate. This doped layer contains a first dopant element with the same conductivity type as the first doped silicon layer, and the doping concentration of the first dopant element in the doped layer is greater than that of the first dopant element in the second region of the semiconductor substrate. At this point, the doping concentration of the first dopant element in the doped layer is high, and the conductivity type of the first dopant element is the same as that of the first doped silicon layer. Therefore, the doped layer can be used to passivate the first region and the overlapping region of the semiconductor substrate, improving the passivation effect. Furthermore, since the conductivity type of the first dopant element in the doped layer is the same as that of the first doped silicon layer, the doped layer can form a favorable electric field consistent with the induced direction of the first doped silicon layer. The presence of this favorable electric field can repel minority carriers and attract majority carriers on the surface of the first region and the overlapping region of the semiconductor substrate, improving the carrier collection efficiency of the first doped silicon layer, further reducing the carrier recombination rate, and thus improving the conversion efficiency of the back contact battery. Furthermore, a doped layer is also disposed in the third sub-region. Since the first doped silicon layer is disposed on the first sub-region, the portion of the doped layer located in the third sub-region can be exposed outside the first doped silicon layer. Additionally, the aforementioned second doped silicon layer is not only disposed on the second sub-region but also extends to cover at least a portion of the doped layer. In the third sub-region, the second doped silicon layer not only passivates the semiconductor substrate, reducing the number of surface defects in the third sub-region and improving the conversion efficiency of the back contact cell, but also electrically connects to the doped layer, forming a built-in diode with a low reverse breakdown voltage. Moreover, a first transparent conductive layer extending from the second sub-region covers the second doped silicon layer located in the third sub-region. This first transparent conductive layer covering the second doped silicon layer has high conductivity, allowing it to promptly export the carriers collected by the second doped silicon layer, reducing the carrier recombination rate and improving the conversion efficiency of the back contact cell. When the back contact battery is blocked, the leakage current can pass through the first doped silicon layer, the second doped silicon layer, and then through the first transparent conductive layer, extending from the second sub-region to cover the portion above the doped layer. Finally, it is discharged through the electrode in partial contact with the second sub-region corresponding to the first transparent conductive layer, reducing the risk of hot spots on the back contact battery. As can be seen from the above, the leakage current needs to be conducted between the first and second doped silicon layers through the doped layer disposed within the semiconductor substrate. Compared to transmission through the doped semiconductor layer, the semiconductor substrate has stronger lateral conductivity. Therefore, the back contact battery provided in this application is more conducive to the transmission of reverse leakage current when blocked, reducing reverse leakage current transmission losses and improving the back contact battery's resistance to burn-out. Furthermore, the leakage current not only needs to flow through the PN junction formed by the doped layer and the second doped silicon layer with opposite conductivity types, but also needs to flow through the high-low junction formed by the doped layer and the first doped silicon layer with the same conductivity type.Compared with the scheme where leakage current only flows through the PN junction, the back contact battery provided in this application, under the action of two electric fields of the PN junction and the high and low junctions during the shielding process, is more conducive to controlling the magnitude of the reverse leakage current, reducing the carrier recombination loss of the back contact battery, balancing the hot spot risk and conversion efficiency of the back contact battery, and improving the working performance of the back contact battery.

[0161] Furthermore, along the direction from the first surface to the second surface, the doping concentration of the second doping element with the same conductivity type as the second doped silicon layer is the same in each part of the second region of the semiconductor substrate. In other words, there is no inner doping layer with the same conductivity type as the second doped silicon layer in the second region of the semiconductor substrate. This can prevent the doped layer and the inner doping layer with the opposite conductivity type from making electrical contact, which would lead to excessively high carrier recombination rate and high leakage risk, thus ensuring that the back contact battery has high conversion efficiency.

[0162] Based on this, as one possible implementation, the second region includes a groove. Along the direction from the second surface to the first surface, the surface height of the portion of the second doped silicon layer located at the bottom of the groove on the side facing away from the semiconductor substrate is lower than the surface height of the doped layer on the side facing away from the tunneling passivation layer. The beneficial effects in this case can be referred to the preceding description, and will not be repeated here.

[0163] As one possible implementation, the width of the doped layer is greater than or equal to the width of the first doped silicon layer along the width direction of the overlapping region. The beneficial effects of this approach are described above and will not be repeated here.

[0164] As one possible implementation, the second region includes a groove. Along the width direction of the overlapping region, the sides of the groove have continuously distributed first and second sub-regions, with the second sub-region close to the first region. The surface of the first sub-region is inclined relative to the surface of the first region, and the cross-sectional area of ​​the portion of the groove corresponding to the first sub-region gradually increases along the direction from the second surface to the first surface. The surface of the second sub-region is planar. Furthermore, the doped layer extends to the region of the semiconductor substrate corresponding to the second sub-region; or, the doped layer further extends to the region of the semiconductor substrate corresponding to the second sub-region and the portion of the first sub-region close to the second sub-region. The beneficial effects in this case can be referred to the preceding description, and will not be repeated here.

[0165] As one possible implementation, the doping concentration of the first dopant element in the doped layer gradually increases along the direction from the second surface to the first surface. The beneficial effects of this approach are described above and will not be repeated here.

[0166] As one possible implementation, the doping concentration of the first dopant element within the first doped silicon layer is greater than the doping concentration of the first dopant element within the doped layer. The beneficial effects of this approach are as described above and will not be repeated here.

[0167] As one possible implementation, the doping concentration of the first dopant element on the side of the doped layer closest to the first doped silicon layer is less than or equal to the doping concentration of the first dopant element within the first doped silicon layer. The beneficial effects of this approach are described above and will not be repeated here.

[0168] As one possible implementation, the aforementioned back-contact battery further includes a transparent conductive layer. This transparent conductive layer covers the sides of the first and second doped silicon layers facing away from the semiconductor substrate. The transparent conductive layer covering the second doped silicon layer is the first transparent conductive layer. Insulating trenches are provided within the transparent conductive layer to disconnect the portions of the transparent conductive layer corresponding to the first and second regions from each other. The portion of the transparent conductive layer that carries the same type of charge carrier conductivity as the second doped silicon layer does not overlap with the doped layer along the thickness direction of the semiconductor substrate. The beneficial effects of this configuration can be referred to the preceding description and will not be repeated here.

[0169] As one possible implementation, the surface of the third sub-region is recessed into the semiconductor substrate relative to the surface of the first sub-region, and the recess depth relative to the surface of the first sub-region is less than the doping depth of the doped layer. The beneficial effects of this approach are described above and will not be repeated here.

[0170] As one possible implementation, the doping concentration of the first dopant element at the surface of the doped layer corresponding to the third sub-region is less than the doping concentration of the first dopant element at the surface of the doped layer corresponding to the first sub-region. The beneficial effects of this approach are described above and will not be repeated here.

[0171] Secondly, embodiments of this application provide a photovoltaic module, which includes a back contact battery provided in the first aspect and various implementations thereof. The photovoltaic module also includes a glass cover plate disposed on the light-facing side of the back contact battery and a back plate disposed on the back-facing side of the back contact battery.

[0172] The beneficial effects of the second aspect and its various implementations in the embodiments of this application can be found by referring to the analysis of the beneficial effects of the first aspect and its various implementations, and will not be repeated here.

[0173] In the above description, the technical details of the patterning and etching of each layer are not described in detail. However, those skilled in the art should understand that layers and regions of the desired shape can be formed using various technical means. Furthermore, to form the same structure, those skilled in the art can also design methods that are not entirely the same as those described above. Additionally, although various embodiments have been described above, this does not mean that the features in the various embodiments cannot be used advantageously in combination.

[0174] The embodiments of this application have been described above. However, these embodiments are merely for clarity and are not intended to limit the scope of this application. The scope of this application is defined by the appended claims and their equivalents. Various substitutions and modifications can be made by those skilled in the art without departing from the scope of this application, and all such substitutions and modifications should fall within the scope of this application.

Claims

1. A back-contact battery, comprising: A semiconductor substrate, the semiconductor substrate including a first surface and a second surface opposite to each other; the first surface including an alternately spaced first region and a second region, and an overlapping region located between the first region and the second region; Along the thickness direction of the semiconductor substrate, a tunneling passivation layer and a first doped silicon layer are sequentially stacked on the first region and the overlapping region; An intrinsic silicon layer and a second doped silicon layer are sequentially stacked on the second region along the thickness direction of the semiconductor substrate; the stacked intrinsic silicon layer and the second doped silicon layer also extend from the second region to the tunneling passivation layer and the first doped silicon layer located in the overlapping region; the conductivity type of the second doped silicon layer is opposite to that of the first doped silicon layer. A doped layer is disposed in the first region and the overlapping region of the semiconductor substrate; the doping concentration of the first doping element in the doped layer having the same conductivity type as the first doped silicon layer is greater than the doping concentration of the first doping element in the second region of the semiconductor substrate; along the direction from the first surface to the second surface, the doping concentration of the second doping element having the same conductivity type as the second doped silicon layer is the same in each part of the second region of the semiconductor substrate.

2. The back contact battery according to claim 1, wherein, The second region includes a groove; along the direction from the second surface to the first surface, the surface height of the portion of the second doped silicon layer located at the bottom of the groove on the side facing away from the semiconductor substrate is lower than the surface height of the doped layer on the side facing away from the tunneling passivation layer.

3. The back contact battery according to claim 2, wherein, Along the direction from the second surface to the first surface, the difference between the surface height of the portion of the second doped silicon layer located at the bottom of the groove away from the semiconductor substrate and the surface height of the doped layer away from the tunneling passivation layer is greater than or equal to 180 nm and less than or equal to 14.7 μm.

4. The back contact battery according to claim 2, wherein, The depth of the groove is greater than or equal to 300 nm and less than or equal to 15 μm.

5. The back contact battery according to claim 1, wherein, Along the width direction of the overlapping region, the width of the doped layer is greater than or equal to the width of the first doped silicon layer; And / or, along the width direction of the overlapping region, the difference between the width of the doped layer and the width of the first doped silicon layer is greater than 0 and less than or equal to 50 μm.

6. The back contact battery according to claim 1, wherein, The second region includes a groove; along the width direction of the overlapping region, the side of the groove has a continuously distributed first sub-region and a second sub-region, and the second sub-region is close to the first region; the surface of the first sub-region is inclined relative to the surface of the first region, and the cross-sectional area of ​​the portion of the groove corresponding to the first sub-region gradually increases along the direction from the second surface to the first surface; the surface of the second sub-region is planar. The doped layer also extends to the region of the semiconductor substrate corresponding to the second sub-region; or, the doped layer also extends to the region of the semiconductor substrate corresponding to the second sub-region and a portion of the first sub-region near the second sub-region.

7. The back contact battery according to claim 1, wherein, Along the direction from the second surface to the first surface, the doping concentration of the first dopant element in the doped layer gradually increases.

8. The back contact battery according to claim 1, wherein, The doping concentration of the first doped element in the first doped silicon layer is greater than the doping concentration of the first doped element in the doped layer.

9. The back contact battery according to claim 1, wherein, The back contact battery further includes a transparent conductive layer; the transparent conductive layer covers the side of the first doped silicon layer and the second doped silicon layer that is away from the semiconductor substrate; The transparent conductive layer has insulating grooves to disconnect the portions of the transparent conductive layer corresponding to the first region and the second region from each other; The portion of the transparent conductive layer that carries the same type of charge carriers as the second doped silicon layer does not overlap with the doped layer along the thickness direction of the semiconductor substrate.

10. The back contact battery according to claim 1, wherein, Along the thickness direction of the semiconductor substrate, the doping depth of the doped layer is greater than or equal to 1 nm and less than or equal to 300 nm.

11. The back contact battery according to claim 1, wherein, The doping concentration of the first dopant element within the doped layer is less than or equal to 9 × 10⁻⁶. 20 / cm 3 And greater than or equal to 8 × 10 9 / cm 3 .

12. The back contact battery according to claim 1, wherein, The thickness of the first doped silicon layer is greater than or equal to 20 nm and less than or equal to 300 nm; And / or, the doping concentration of the first doped element in the first doped silicon layer is greater than or equal to 1 × 10⁻⁶. 18 / cm 3 And less than or equal to 1×10 21 / cm 3 .

13. The back contact battery according to claim 1, wherein, The sum of the thicknesses of the second doped silicon layer and the intrinsic silicon layer is greater than or equal to 15 nm and less than or equal to 120 nm; And / or, the doping concentration of the second doped element in the second doped silicon layer is greater than or equal to 1 × 10⁻⁶. 18 / cm 3 And less than or equal to 1×10 21 / cm 3 .

14. The back contact battery according to claim 1, wherein, The conductivity type of both the first doped silicon layer and the doped layer is the same as that of the semiconductor substrate; the second region of the semiconductor substrate does not contain the second doping element; And / or, the conductivity type of the doped layer and the first doped silicon layer is N-type, and the conductivity type of the second doped silicon layer is P-type.

15. The back contact battery according to claim 1, wherein, The second region includes a groove; the bottom surface of the groove is textured, and the thickness of the second doped silicon layer on the bottom of the groove is less than the thickness of the second doped silicon layer in the overlapping region.

16. The back contact battery according to claim 1, wherein, The continuous first region, the overlapping region, and the second region are divided into a first sub-region, a second sub-region, and a third sub-region located between the first sub-region and the second sub-region. The first sub-region corresponds to the first region and the overlapping region, and the second sub-region and the third sub-region correspond to the second region. The doped layer is also disposed in the third sub-region, and the second doped silicon layer extends to cover at least a portion of the doped layer. In the third sub-region, the second doped silicon layer is electrically connected to the doped layer; The back contact battery further includes: a first transparent conductive layer covering the second doped silicon layer located in the second sub-region, and the first transparent conductive layer extending from the second sub-region covering the second doped silicon layer located in the third sub-region.

17. The back contact battery according to claim 16, wherein, The surface of the third sub-region is recessed into the semiconductor substrate relative to the surface of the first sub-region, and the recess depth relative to the surface of the first sub-region is less than the depth of the doped layer.

18. The back contact battery according to claim 16, wherein, The doping concentration of the first doped element at the surface of the doped layer corresponding to the third sub-region is less than the doping concentration of the first doped element at the surface of the doped layer corresponding to the first sub-region.

19. The back contact battery according to claim 16, wherein, The doping concentration of the first doped element on the side of the doped layer closest to the first doped silicon layer is less than or equal to the doping concentration of the first doped element in the first doped silicon layer. And / or, the doping concentration of the first dopant element in the doped layer is greater than or equal to 8 × 10⁻⁶. 9 / cm 3 And less than or equal to 9 × 10 20 / cm 3 .

20. A photovoltaic module comprising a back contact cell as described in any one of claims 1 to 19.

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